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at91: add kernel support for sama7g5 soc
[openwrt/staging/wigyori.git] / target / linux / at91 / patches-5.10 / 180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch
1 From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001
2 From: Eugen Hristev <eugen.hristev@microchip.com>
3 Date: Tue, 13 Apr 2021 12:57:22 +0200
4 Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into
5 product specific code
6
7 The list of input and output formats has to be product specific.
8 Move this list into the product specific code.
9 Have pointers to these arrays inside the device struct.
10
11 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
12 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
13 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
14 ---
15 drivers/media/platform/atmel/atmel-isc-base.c | 167 ++----------------
16 drivers/media/platform/atmel/atmel-isc.h | 12 +-
17 .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++
18 3 files changed, 165 insertions(+), 150 deletions(-)
19
20 diff --git a/drivers/media/platform/atmel/atmel-isc-base.c b/drivers/media/platform/atmel/atmel-isc-base.c
21 index 67c16ca17672..90a62d43fdb1 100644
22 --- a/drivers/media/platform/atmel/atmel-isc-base.c
23 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
24 @@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 0644);
25 MODULE_PARM_DESC(sensor_preferred,
26 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
27
28 -/* This is a list of the formats that the ISC can *output* */
29 -const struct isc_format controller_formats[] = {
30 - {
31 - .fourcc = V4L2_PIX_FMT_ARGB444,
32 - },
33 - {
34 - .fourcc = V4L2_PIX_FMT_ARGB555,
35 - },
36 - {
37 - .fourcc = V4L2_PIX_FMT_RGB565,
38 - },
39 - {
40 - .fourcc = V4L2_PIX_FMT_ABGR32,
41 - },
42 - {
43 - .fourcc = V4L2_PIX_FMT_XBGR32,
44 - },
45 - {
46 - .fourcc = V4L2_PIX_FMT_YUV420,
47 - },
48 - {
49 - .fourcc = V4L2_PIX_FMT_YUYV,
50 - },
51 - {
52 - .fourcc = V4L2_PIX_FMT_YUV422P,
53 - },
54 - {
55 - .fourcc = V4L2_PIX_FMT_GREY,
56 - },
57 - {
58 - .fourcc = V4L2_PIX_FMT_Y10,
59 - },
60 -};
61 -
62 -/* This is a list of formats that the ISC can receive as *input* */
63 -struct isc_format formats_list[] = {
64 - {
65 - .fourcc = V4L2_PIX_FMT_SBGGR8,
66 - .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
67 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
68 - .cfa_baycfg = ISC_BAY_CFG_BGBG,
69 - },
70 - {
71 - .fourcc = V4L2_PIX_FMT_SGBRG8,
72 - .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
73 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
74 - .cfa_baycfg = ISC_BAY_CFG_GBGB,
75 - },
76 - {
77 - .fourcc = V4L2_PIX_FMT_SGRBG8,
78 - .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
79 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
80 - .cfa_baycfg = ISC_BAY_CFG_GRGR,
81 - },
82 - {
83 - .fourcc = V4L2_PIX_FMT_SRGGB8,
84 - .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
85 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
86 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
87 - },
88 - {
89 - .fourcc = V4L2_PIX_FMT_SBGGR10,
90 - .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
91 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
92 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
93 - },
94 - {
95 - .fourcc = V4L2_PIX_FMT_SGBRG10,
96 - .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
97 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
98 - .cfa_baycfg = ISC_BAY_CFG_GBGB,
99 - },
100 - {
101 - .fourcc = V4L2_PIX_FMT_SGRBG10,
102 - .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
103 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
104 - .cfa_baycfg = ISC_BAY_CFG_GRGR,
105 - },
106 - {
107 - .fourcc = V4L2_PIX_FMT_SRGGB10,
108 - .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
109 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
110 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
111 - },
112 - {
113 - .fourcc = V4L2_PIX_FMT_SBGGR12,
114 - .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
115 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
116 - .cfa_baycfg = ISC_BAY_CFG_BGBG,
117 - },
118 - {
119 - .fourcc = V4L2_PIX_FMT_SGBRG12,
120 - .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
121 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
122 - .cfa_baycfg = ISC_BAY_CFG_GBGB,
123 - },
124 - {
125 - .fourcc = V4L2_PIX_FMT_SGRBG12,
126 - .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
127 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
128 - .cfa_baycfg = ISC_BAY_CFG_GRGR,
129 - },
130 - {
131 - .fourcc = V4L2_PIX_FMT_SRGGB12,
132 - .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
133 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
134 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
135 - },
136 - {
137 - .fourcc = V4L2_PIX_FMT_GREY,
138 - .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
139 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
140 - },
141 - {
142 - .fourcc = V4L2_PIX_FMT_YUYV,
143 - .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
144 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
145 - },
146 - {
147 - .fourcc = V4L2_PIX_FMT_RGB565,
148 - .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
149 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
150 - },
151 - {
152 - .fourcc = V4L2_PIX_FMT_Y10,
153 - .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
154 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
155 - },
156 -
157 -};
158 -
159 #define ISC_IS_FORMAT_RAW(mbus_code) \
160 (((mbus_code) & 0xf000) == 0x3000)
161
162 @@ -919,24 +788,25 @@ static int isc_querycap(struct file *file, void *priv,
163 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
164 struct v4l2_fmtdesc *f)
165 {
166 + struct isc_device *isc = video_drvdata(file);
167 u32 index = f->index;
168 u32 i, supported_index;
169
170 - if (index < ARRAY_SIZE(controller_formats)) {
171 - f->pixelformat = controller_formats[index].fourcc;
172 + if (index < isc->controller_formats_size) {
173 + f->pixelformat = isc->controller_formats[index].fourcc;
174 return 0;
175 }
176
177 - index -= ARRAY_SIZE(controller_formats);
178 + index -= isc->controller_formats_size;
179
180 supported_index = 0;
181
182 - for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
183 - if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
184 - !formats_list[i].sd_support)
185 + for (i = 0; i < isc->formats_list_size; i++) {
186 + if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
187 + !isc->formats_list[i].sd_support)
188 continue;
189 if (supported_index == index) {
190 - f->pixelformat = formats_list[i].fourcc;
191 + f->pixelformat = isc->formats_list[i].fourcc;
192 return 0;
193 }
194 supported_index++;
195 @@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct file *file, void *fh,
196 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
197 ret = 0;
198
199 - for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
200 - if (controller_formats[i].fourcc == fsize->pixel_format)
201 + for (i = 0; i < isc->controller_formats_size; i++)
202 + if (isc->controller_formats[i].fourcc == fsize->pixel_format)
203 ret = 0;
204
205 if (ret)
206 @@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struct file *file, void *fh,
207 if (isc->user_formats[i]->fourcc == fival->pixel_format)
208 ret = 0;
209
210 - for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
211 - if (controller_formats[i].fourcc == fival->pixel_format)
212 + for (i = 0; i < isc->controller_formats_size; i++)
213 + if (isc->controller_formats[i].fourcc == fival->pixel_format)
214 ret = 0;
215
216 if (ret)
217 @@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2_async_notifier *notifier,
218 v4l2_ctrl_handler_free(&isc->ctrls.handler);
219 }
220
221 -static struct isc_format *find_format_by_code(unsigned int code, int *index)
222 +static struct isc_format *find_format_by_code(struct isc_device *isc,
223 + unsigned int code, int *index)
224 {
225 - struct isc_format *fmt = &formats_list[0];
226 + struct isc_format *fmt = &isc->formats_list[0];
227 unsigned int i;
228
229 - for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
230 + for (i = 0; i < isc->formats_list_size; i++) {
231 if (fmt->mbus_code == code) {
232 *index = i;
233 return fmt;
234 @@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_device *isc)
235 struct isc_format *fmt;
236 struct v4l2_subdev *subdev = isc->current_subdev->sd;
237 unsigned int num_fmts, i, j;
238 - u32 list_size = ARRAY_SIZE(formats_list);
239 + u32 list_size = isc->formats_list_size;
240 struct v4l2_subdev_mbus_code_enum mbus_code = {
241 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
242 };
243 @@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_device *isc)
244 NULL, &mbus_code)) {
245 mbus_code.index++;
246
247 - fmt = find_format_by_code(mbus_code.code, &i);
248 + fmt = find_format_by_code(isc, mbus_code.code, &i);
249 if (!fmt) {
250 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
251 mbus_code.code);
252 @@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_device *isc)
253 if (!isc->user_formats)
254 return -ENOMEM;
255
256 - fmt = &formats_list[0];
257 + fmt = &isc->formats_list[0];
258 for (i = 0, j = 0; i < list_size; i++) {
259 if (fmt->sd_support)
260 isc->user_formats[j++] = fmt;
261 diff --git a/drivers/media/platform/atmel/atmel-isc.h b/drivers/media/platform/atmel/atmel-isc.h
262 index 24006327c5e4..b34737c09a5b 100644
263 --- a/drivers/media/platform/atmel/atmel-isc.h
264 +++ b/drivers/media/platform/atmel/atmel-isc.h
265 @@ -236,6 +236,12 @@ struct isc_reg_offsets {
266 * specific v4l2 controls.
267 *
268 * @offsets: struct holding the product specific register offsets
269 + * @controller_formats: pointer to the array of possible formats that the
270 + * controller can output
271 + * @formats_list: pointer to the array of possible formats that can
272 + * be used as an input to the controller
273 + * @controller_formats_size: size of controller_formats array
274 + * @formats_list_size: size of formats_list array
275 */
276 struct isc_device {
277 struct regmap *regmap;
278 @@ -317,10 +323,12 @@ struct isc_device {
279 };
280
281 struct isc_reg_offsets offsets;
282 + const struct isc_format *controller_formats;
283 + struct isc_format *formats_list;
284 + u32 controller_formats_size;
285 + u32 formats_list_size;
286 };
287
288 -extern struct isc_format formats_list[];
289 -extern const struct isc_format controller_formats[];
290 extern const struct regmap_config isc_regmap_config;
291 extern const struct v4l2_async_notifier_operations isc_async_ops;
292
293 diff --git a/drivers/media/platform/atmel/atmel-sama5d2-isc.c b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
294 index 86704a1a24b9..b8c1b57ed820 100644
295 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
296 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
297 @@ -54,6 +54,137 @@
298
299 #define ISC_CLK_MAX_DIV 255
300
301 +/* This is a list of the formats that the ISC can *output* */
302 +static const struct isc_format sama5d2_controller_formats[] = {
303 + {
304 + .fourcc = V4L2_PIX_FMT_ARGB444,
305 + },
306 + {
307 + .fourcc = V4L2_PIX_FMT_ARGB555,
308 + },
309 + {
310 + .fourcc = V4L2_PIX_FMT_RGB565,
311 + },
312 + {
313 + .fourcc = V4L2_PIX_FMT_ABGR32,
314 + },
315 + {
316 + .fourcc = V4L2_PIX_FMT_XBGR32,
317 + },
318 + {
319 + .fourcc = V4L2_PIX_FMT_YUV420,
320 + },
321 + {
322 + .fourcc = V4L2_PIX_FMT_YUYV,
323 + },
324 + {
325 + .fourcc = V4L2_PIX_FMT_YUV422P,
326 + },
327 + {
328 + .fourcc = V4L2_PIX_FMT_GREY,
329 + },
330 + {
331 + .fourcc = V4L2_PIX_FMT_Y10,
332 + },
333 +};
334 +
335 +/* This is a list of formats that the ISC can receive as *input* */
336 +static struct isc_format sama5d2_formats_list[] = {
337 + {
338 + .fourcc = V4L2_PIX_FMT_SBGGR8,
339 + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
340 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
341 + .cfa_baycfg = ISC_BAY_CFG_BGBG,
342 + },
343 + {
344 + .fourcc = V4L2_PIX_FMT_SGBRG8,
345 + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
346 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
347 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
348 + },
349 + {
350 + .fourcc = V4L2_PIX_FMT_SGRBG8,
351 + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
352 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
353 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
354 + },
355 + {
356 + .fourcc = V4L2_PIX_FMT_SRGGB8,
357 + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
358 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
359 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
360 + },
361 + {
362 + .fourcc = V4L2_PIX_FMT_SBGGR10,
363 + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
364 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
365 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
366 + },
367 + {
368 + .fourcc = V4L2_PIX_FMT_SGBRG10,
369 + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
370 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
371 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
372 + },
373 + {
374 + .fourcc = V4L2_PIX_FMT_SGRBG10,
375 + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
376 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
377 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
378 + },
379 + {
380 + .fourcc = V4L2_PIX_FMT_SRGGB10,
381 + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
382 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
383 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
384 + },
385 + {
386 + .fourcc = V4L2_PIX_FMT_SBGGR12,
387 + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
388 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
389 + .cfa_baycfg = ISC_BAY_CFG_BGBG,
390 + },
391 + {
392 + .fourcc = V4L2_PIX_FMT_SGBRG12,
393 + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
394 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
395 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
396 + },
397 + {
398 + .fourcc = V4L2_PIX_FMT_SGRBG12,
399 + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
400 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
401 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
402 + },
403 + {
404 + .fourcc = V4L2_PIX_FMT_SRGGB12,
405 + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
406 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
407 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
408 + },
409 + {
410 + .fourcc = V4L2_PIX_FMT_GREY,
411 + .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
412 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
413 + },
414 + {
415 + .fourcc = V4L2_PIX_FMT_YUYV,
416 + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
417 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
418 + },
419 + {
420 + .fourcc = V4L2_PIX_FMT_RGB565,
421 + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
422 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
423 + },
424 + {
425 + .fourcc = V4L2_PIX_FMT_Y10,
426 + .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
427 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
428 + },
429 +
430 +};
431 +
432 static void isc_sama5d2_config_csc(struct isc_device *isc)
433 {
434 struct regmap *regmap = isc->regmap;
435 @@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platform_device *pdev)
436 isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
437 isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;
438
439 + isc->controller_formats = sama5d2_controller_formats;
440 + isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats);
441 + isc->formats_list = sama5d2_formats_list;
442 + isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list);
443 +
444 /* sama5d2-isc - 8 bits per beat */
445 isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
446
447 --
448 2.32.0
449
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