target/linux/brcm2708/patches-4.19/950-0190-media-tc358743-Increase-FIFO-level-to-374.patch

   1 From 74cfa3689511a7befa86ab18ff4d4d9662472c08 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.org>
   3 Date: Wed, 31 Oct 2018 14:56:59 +0000
   4 Subject: [PATCH 190/703] media: tc358743: Increase FIFO level to 374.
   5
   6 The existing fixed value of 16 worked for UYVY 720P60 over
   7 2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888
   8 1080P60 needs 6 lanes at 594MHz).
   9 It doesn't allow for lower resolutions to work as the FIFO
  10 underflows.
  11
  12 374 is required for 1080P24-30 UYVY over 2 lanes @ 972Mbit/s, but
  13 >374 means that the FIFO underflows on 1080P50 UYVY over 2 lanes
  14 @ 972Mbit/s.
  15
  16 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.org>
  17 ---
  18  drivers/media/i2c/tc358743.c | 2 +-
  19  1 file changed, 1 insertion(+), 1 deletion(-)
  20
  21 --- a/drivers/media/i2c/tc358743.c
  22 +++ b/drivers/media/i2c/tc358743.c
  23 @@ -1946,7 +1946,7 @@ static int tc358743_probe_of(struct tc35
  24         state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
  25         state->pdata.enable_hdcp = false;
  26         /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
  27 -       state->pdata.fifo_level = 16;
  28 +       state->pdata.fifo_level = 374;
  29         /*
  30          * The PLL input clock is obtained by dividing refclk by pll_prd.
  31          * It must be between 6 MHz and 40 MHz, lower frequency is better.