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kernel: add linux 5.10 support
[openwrt/staging/wigyori.git] / target / linux / generic / pending-5.10 / 770-15-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Sun, 11 Oct 2020 22:23:08 +0200
3 Subject: [PATCH] ethernet: mediatek: mtk_eth_soc: add support for
4 initializing the PPE
5
6 The PPE (packet processing engine) is used to offload NAT/routed or even
7 bridged flows. This patch brings up the PPE and uses it to get a packet
8 hash. It also contains some functionality that will be used to bring up
9 flow offloading.
10
11 Signed-off-by: Felix Fietkau <nbd@nbd.name>
12 ---
13 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.c
14 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.h
15 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
16 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_regs.h
17
18 --- a/drivers/net/ethernet/mediatek/Makefile
19 +++ b/drivers/net/ethernet/mediatek/Makefile
20 @@ -4,5 +4,5 @@
21 #
22
23 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
24 -mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
25 +mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o
26 obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
27 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
28 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
29 @@ -2284,12 +2284,17 @@ static int mtk_open(struct net_device *d
30
31 /* we run 2 netdevs on the same dma ring so we only bring it up once */
32 if (!refcount_read(&eth->dma_refcnt)) {
33 - int err = mtk_start_dma(eth);
34 + u32 gdm_config = MTK_GDMA_TO_PDMA;
35 + int err;
36
37 + err = mtk_start_dma(eth);
38 if (err)
39 return err;
40
41 - mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
42 + if (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)
43 + gdm_config = MTK_GDMA_TO_PPE;
44 +
45 + mtk_gdm_config(eth, gdm_config);
46
47 napi_enable(&eth->tx_napi);
48 napi_enable(&eth->rx_napi);
49 @@ -2359,6 +2364,9 @@ static int mtk_stop(struct net_device *d
50
51 mtk_dma_free(eth);
52
53 + if (eth->soc->offload_version)
54 + mtk_ppe_stop(&eth->ppe);
55 +
56 return 0;
57 }
58
59 @@ -3148,6 +3156,13 @@ static int mtk_probe(struct platform_dev
60 goto err_free_dev;
61 }
62
63 + if (eth->soc->offload_version) {
64 + err = mtk_ppe_init(&eth->ppe, eth->dev,
65 + eth->base + MTK_ETH_PPE_BASE, 2);
66 + if (err)
67 + goto err_free_dev;
68 + }
69 +
70 for (i = 0; i < MTK_MAX_DEVS; i++) {
71 if (!eth->netdev[i])
72 continue;
73 @@ -3222,6 +3237,7 @@ static const struct mtk_soc_data mt7621_
74 .hw_features = MTK_HW_FEATURES,
75 .required_clks = MT7621_CLKS_BITMAP,
76 .required_pctl = false,
77 + .offload_version = 2,
78 };
79
80 static const struct mtk_soc_data mt7622_data = {
81 @@ -3230,6 +3246,7 @@ static const struct mtk_soc_data mt7622_
82 .hw_features = MTK_HW_FEATURES,
83 .required_clks = MT7622_CLKS_BITMAP,
84 .required_pctl = false,
85 + .offload_version = 2,
86 };
87
88 static const struct mtk_soc_data mt7623_data = {
89 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
90 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
91 @@ -16,6 +16,7 @@
92 #include <linux/refcount.h>
93 #include <linux/phylink.h>
94 #include <linux/dim.h>
95 +#include "mtk_ppe.h"
96
97 #define MTK_QDMA_PAGE_SIZE 2048
98 #define MTK_MAX_RX_LENGTH 1536
99 @@ -87,6 +88,7 @@
100 #define MTK_GDMA_TCS_EN BIT(21)
101 #define MTK_GDMA_UCS_EN BIT(20)
102 #define MTK_GDMA_TO_PDMA 0x0
103 +#define MTK_GDMA_TO_PPE 0x4444
104 #define MTK_GDMA_DROP_ALL 0x7777
105
106 /* Unicast Filter MAC Address Register - Low */
107 @@ -308,6 +310,12 @@
108 #define RX_DMA_VID(_x) ((_x) & 0xfff)
109
110 /* QDMA descriptor rxd4 */
111 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
112 +#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
113 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
114 +#define MTK_RXD4_ALG GENMASK(31, 22)
115 +
116 +/* QDMA descriptor rxd4 */
117 #define RX_DMA_L4_VALID BIT(24)
118 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
119 #define RX_DMA_FPORT_SHIFT 19
120 @@ -807,6 +815,7 @@ struct mtk_soc_data {
121 u32 caps;
122 u32 required_clks;
123 bool required_pctl;
124 + u8 offload_version;
125 netdev_features_t hw_features;
126 };
127
128 @@ -918,6 +927,8 @@ struct mtk_eth {
129 u32 tx_int_status_reg;
130 u32 rx_dma_l4_valid;
131 int ip_align;
132 +
133 + struct mtk_ppe ppe;
134 };
135
136 /* struct mtk_mac - the structure that holds the info about the MACs of the
137 --- /dev/null
138 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
139 @@ -0,0 +1,511 @@
140 +// SPDX-License-Identifier: GPL-2.0-only
141 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
142 +
143 +#include <linux/kernel.h>
144 +#include <linux/jiffies.h>
145 +#include <linux/delay.h>
146 +#include <linux/io.h>
147 +#include <linux/etherdevice.h>
148 +#include <linux/platform_device.h>
149 +#include "mtk_ppe.h"
150 +#include "mtk_ppe_regs.h"
151 +
152 +static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)
153 +{
154 + writel(val, ppe->base + reg);
155 +}
156 +
157 +static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg)
158 +{
159 + return readl(ppe->base + reg);
160 +}
161 +
162 +static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set)
163 +{
164 + u32 val;
165 +
166 + val = ppe_r32(ppe, reg);
167 + val &= ~mask;
168 + val |= set;
169 + ppe_w32(ppe, reg, val);
170 +
171 + return val;
172 +}
173 +
174 +static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val)
175 +{
176 + return ppe_m32(ppe, reg, 0, val);
177 +}
178 +
179 +static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val)
180 +{
181 + return ppe_m32(ppe, reg, val, 0);
182 +}
183 +
184 +static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)
185 +{
186 + unsigned long timeout = jiffies + HZ;
187 +
188 + while (time_is_before_jiffies(timeout)) {
189 + if (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY))
190 + return 0;
191 +
192 + usleep_range(10, 20);
193 + }
194 +
195 + dev_err(ppe->dev, "PPE table busy");
196 +
197 + return -ETIMEDOUT;
198 +}
199 +
200 +static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
201 +{
202 + ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
203 + ppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
204 +}
205 +
206 +static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)
207 +{
208 + mtk_ppe_cache_clear(ppe);
209 +
210 + ppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN,
211 + enable * MTK_PPE_CACHE_CTL_EN);
212 +}
213 +
214 +static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
215 +{
216 + u32 hv1, hv2, hv3;
217 + u32 hash;
218 +
219 + switch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {
220 + case MTK_PPE_PKT_TYPE_BRIDGE:
221 + hv1 = e->bridge.src_mac_lo;
222 + hv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);
223 + hv2 = e->bridge.src_mac_hi >> 16;
224 + hv2 ^= e->bridge.dest_mac_lo;
225 + hv3 = e->bridge.dest_mac_hi;
226 + break;
227 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
228 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
229 + hv1 = e->ipv4.orig.ports;
230 + hv2 = e->ipv4.orig.dest_ip;
231 + hv3 = e->ipv4.orig.src_ip;
232 + break;
233 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
234 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
235 + hv1 = e->ipv6.src_ip[3] ^ e->ipv6.dest_ip[3];
236 + hv1 ^= e->ipv6.ports;
237 +
238 + hv2 = e->ipv6.src_ip[2] ^ e->ipv6.dest_ip[2];
239 + hv2 ^= e->ipv6.dest_ip[0];
240 +
241 + hv3 = e->ipv6.src_ip[1] ^ e->ipv6.dest_ip[1];
242 + hv3 ^= e->ipv6.src_ip[0];
243 + break;
244 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
245 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
246 + default:
247 + WARN_ON_ONCE(1);
248 + return MTK_PPE_HASH_MASK;
249 + }
250 +
251 + hash = (hv1 & hv2) | ((~hv1) & hv3);
252 + hash = (hash >> 24) | ((hash & 0xffffff) << 8);
253 + hash ^= hv1 ^ hv2 ^ hv3;
254 + hash ^= hash >> 16;
255 + hash <<= 1;
256 + hash &= MTK_PPE_ENTRIES - 1;
257 +
258 + return hash;
259 +}
260 +
261 +static inline struct mtk_foe_mac_info *
262 +mtk_foe_entry_l2(struct mtk_foe_entry *entry)
263 +{
264 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
265 +
266 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
267 + return &entry->ipv6.l2;
268 +
269 + return &entry->ipv4.l2;
270 +}
271 +
272 +static inline u32 *
273 +mtk_foe_entry_ib2(struct mtk_foe_entry *entry)
274 +{
275 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
276 +
277 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
278 + return &entry->ipv6.ib2;
279 +
280 + return &entry->ipv4.ib2;
281 +}
282 +
283 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
284 + u8 pse_port, u8 *src_mac, u8 *dest_mac)
285 +{
286 + struct mtk_foe_mac_info *l2;
287 + u32 ports_pad, val;
288 +
289 + memset(entry, 0, sizeof(*entry));
290 +
291 + val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
292 + FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE, type) |
293 + FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
294 + MTK_FOE_IB1_BIND_TTL |
295 + MTK_FOE_IB1_BIND_CACHE;
296 + entry->ib1 = val;
297 +
298 + val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
299 + FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) |
300 + FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port);
301 +
302 + if (is_multicast_ether_addr(dest_mac))
303 + val |= MTK_FOE_IB2_MULTICAST;
304 +
305 + ports_pad = 0xa5a5a500 | (l4proto & 0xff);
306 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
307 + entry->ipv4.orig.ports = ports_pad;
308 + if (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
309 + entry->ipv6.ports = ports_pad;
310 +
311 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
312 + entry->ipv6.ib2 = val;
313 + l2 = &entry->ipv6.l2;
314 + } else {
315 + entry->ipv4.ib2 = val;
316 + l2 = &entry->ipv4.l2;
317 + }
318 +
319 + l2->dest_mac_hi = get_unaligned_be32(dest_mac);
320 + l2->dest_mac_lo = get_unaligned_be16(dest_mac + 4);
321 + l2->src_mac_hi = get_unaligned_be32(src_mac);
322 + l2->src_mac_lo = get_unaligned_be16(src_mac + 4);
323 +
324 + if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
325 + l2->etype = ETH_P_IPV6;
326 + else
327 + l2->etype = ETH_P_IP;
328 +
329 + return 0;
330 +}
331 +
332 +int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port)
333 +{
334 + u32 *ib2 = mtk_foe_entry_ib2(entry);
335 + u32 val;
336 +
337 + val = *ib2;
338 + val &= ~MTK_FOE_IB2_DEST_PORT;
339 + val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT, port);
340 + *ib2 = val;
341 +
342 + return 0;
343 +}
344 +
345 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool egress,
346 + __be32 src_addr, __be16 src_port,
347 + __be32 dest_addr, __be16 dest_port)
348 +{
349 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
350 + struct mtk_ipv4_tuple *t;
351 +
352 + switch (type) {
353 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
354 + if (egress) {
355 + t = &entry->ipv4.new;
356 + break;
357 + }
358 + fallthrough;
359 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
360 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
361 + t = &entry->ipv4.orig;
362 + break;
363 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
364 + entry->ipv6_6rd.tunnel_src_ip = be32_to_cpu(src_addr);
365 + entry->ipv6_6rd.tunnel_dest_ip = be32_to_cpu(dest_addr);
366 + return 0;
367 + default:
368 + WARN_ON_ONCE(1);
369 + return -EINVAL;
370 + }
371 +
372 + t->src_ip = be32_to_cpu(src_addr);
373 + t->dest_ip = be32_to_cpu(dest_addr);
374 +
375 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
376 + return 0;
377 +
378 + t->src_port = be16_to_cpu(src_port);
379 + t->dest_port = be16_to_cpu(dest_port);
380 +
381 + return 0;
382 +}
383 +
384 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
385 + __be32 *src_addr, __be16 src_port,
386 + __be32 *dest_addr, __be16 dest_port)
387 +{
388 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
389 + u32 *src, *dest;
390 + int i;
391 +
392 + switch (type) {
393 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
394 + src = entry->dslite.tunnel_src_ip;
395 + dest = entry->dslite.tunnel_dest_ip;
396 + break;
397 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
398 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
399 + entry->ipv6.src_port = be16_to_cpu(src_port);
400 + entry->ipv6.dest_port = be16_to_cpu(dest_port);
401 + fallthrough;
402 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
403 + src = entry->ipv6.src_ip;
404 + dest = entry->ipv6.dest_ip;
405 + break;
406 + default:
407 + WARN_ON_ONCE(1);
408 + return -EINVAL;
409 + };
410 +
411 + for (i = 0; i < 4; i++)
412 + src[i] = be32_to_cpu(src_addr[i]);
413 + for (i = 0; i < 4; i++)
414 + dest[i] = be32_to_cpu(dest_addr[i]);
415 +
416 + return 0;
417 +}
418 +
419 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port)
420 +{
421 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
422 +
423 + l2->etype = BIT(port);
424 +
425 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER))
426 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
427 + else
428 + l2->etype |= BIT(8);
429 +
430 + entry->ib1 &= ~MTK_FOE_IB1_BIND_VLAN_TAG;
431 +
432 + return 0;
433 +}
434 +
435 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid)
436 +{
437 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
438 +
439 + switch (FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, entry->ib1)) {
440 + case 0:
441 + entry->ib1 |= MTK_FOE_IB1_BIND_VLAN_TAG |
442 + FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
443 + l2->vlan1 = vid;
444 + return 0;
445 + case 1:
446 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) {
447 + l2->vlan1 = vid;
448 + l2->etype |= BIT(8);
449 + } else {
450 + l2->vlan2 = vid;
451 + entry->ib1 += FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
452 + }
453 + return 0;
454 + default:
455 + return -ENOSPC;
456 + }
457 +}
458 +
459 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)
460 +{
461 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
462 +
463 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER) ||
464 + (entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG))
465 + l2->etype = ETH_P_PPP_SES;
466 +
467 + entry->ib1 |= MTK_FOE_IB1_BIND_PPPOE;
468 + l2->pppoe_id = sid;
469 +
470 + return 0;
471 +}
472 +
473 +static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)
474 +{
475 + return !(entry->ib1 & MTK_FOE_IB1_STATIC) &&
476 + FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;
477 +}
478 +
479 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
480 + u16 timestamp)
481 +{
482 + struct mtk_foe_entry *hwe;
483 + u32 hash;
484 +
485 + timestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;
486 + entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;
487 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);
488 +
489 + hash = mtk_ppe_hash_entry(entry);
490 + hwe = &ppe->foe_table[hash];
491 + if (!mtk_foe_entry_usable(hwe)) {
492 + hwe++;
493 + hash++;
494 +
495 + if (!mtk_foe_entry_usable(hwe))
496 + return -ENOSPC;
497 + }
498 +
499 + memcpy(&hwe->data, &entry->data, sizeof(hwe->data));
500 + wmb();
501 + hwe->ib1 = entry->ib1;
502 +
503 + dma_wmb();
504 +
505 + mtk_ppe_cache_clear(ppe);
506 +
507 + return hash;
508 +}
509 +
510 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
511 + int version)
512 +{
513 + struct mtk_foe_entry *foe;
514 +
515 + /* need to allocate a separate device, since it PPE DMA access is
516 + * not coherent.
517 + */
518 + ppe->base = base;
519 + ppe->dev = dev;
520 + ppe->version = version;
521 +
522 + foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),
523 + &ppe->foe_phys, GFP_KERNEL);
524 + if (!foe)
525 + return -ENOMEM;
526 +
527 + ppe->foe_table = foe;
528 +
529 + mtk_ppe_debugfs_init(ppe);
530 +
531 + return 0;
532 +}
533 +
534 +static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)
535 +{
536 + static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };
537 + int i, k;
538 +
539 + memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table));
540 +
541 + if (!IS_ENABLED(CONFIG_SOC_MT7621))
542 + return;
543 +
544 + /* skip all entries that cross the 1024 byte boundary */
545 + for (i = 0; i < MTK_PPE_ENTRIES; i += 128)
546 + for (k = 0; k < ARRAY_SIZE(skip); k++)
547 + ppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC;
548 +}
549 +
550 +int mtk_ppe_start(struct mtk_ppe *ppe)
551 +{
552 + u32 val;
553 +
554 + mtk_ppe_init_foe_table(ppe);
555 + ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
556 +
557 + val = MTK_PPE_TB_CFG_ENTRY_80B |
558 + MTK_PPE_TB_CFG_AGE_NON_L4 |
559 + MTK_PPE_TB_CFG_AGE_UNBIND |
560 + MTK_PPE_TB_CFG_AGE_TCP |
561 + MTK_PPE_TB_CFG_AGE_UDP |
562 + MTK_PPE_TB_CFG_AGE_TCP_FIN |
563 + FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
564 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) |
565 + FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE,
566 + MTK_PPE_KEEPALIVE_DISABLE) |
567 + FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) |
568 + FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE,
569 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
570 + FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
571 + MTK_PPE_ENTRIES_SHIFT);
572 + ppe_w32(ppe, MTK_PPE_TB_CFG, val);
573 +
574 + ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
575 + MTK_PPE_IP_PROTO_CHK_IPV4 | MTK_PPE_IP_PROTO_CHK_IPV6);
576 +
577 + mtk_ppe_cache_enable(ppe, true);
578 +
579 + val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG |
580 + MTK_PPE_FLOW_CFG_IP4_UDP_FRAG |
581 + MTK_PPE_FLOW_CFG_IP6_3T_ROUTE |
582 + MTK_PPE_FLOW_CFG_IP6_5T_ROUTE |
583 + MTK_PPE_FLOW_CFG_IP6_6RD |
584 + MTK_PPE_FLOW_CFG_IP4_NAT |
585 + MTK_PPE_FLOW_CFG_IP4_NAPT |
586 + MTK_PPE_FLOW_CFG_IP4_DSLITE |
587 + MTK_PPE_FLOW_CFG_L2_BRIDGE |
588 + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
589 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, val);
590 +
591 + val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) |
592 + FIELD_PREP(MTK_PPE_UNBIND_AGE_DELTA, 3);
593 + ppe_w32(ppe, MTK_PPE_UNBIND_AGE, val);
594 +
595 + val = FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_UDP, 12) |
596 + FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_NON_L4, 1);
597 + ppe_w32(ppe, MTK_PPE_BIND_AGE0, val);
598 +
599 + val = FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP_FIN, 1) |
600 + FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP, 7);
601 + ppe_w32(ppe, MTK_PPE_BIND_AGE1, val);
602 +
603 + val = MTK_PPE_BIND_LIMIT0_QUARTER | MTK_PPE_BIND_LIMIT0_HALF;
604 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val);
605 +
606 + val = MTK_PPE_BIND_LIMIT1_FULL |
607 + FIELD_PREP(MTK_PPE_BIND_LIMIT1_NON_L4, 1);
608 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val);
609 +
610 + val = FIELD_PREP(MTK_PPE_BIND_RATE_BIND, 30) |
611 + FIELD_PREP(MTK_PPE_BIND_RATE_PREBIND, 1);
612 + ppe_w32(ppe, MTK_PPE_BIND_RATE, val);
613 +
614 + /* enable PPE */
615 + val = MTK_PPE_GLO_CFG_EN |
616 + MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |
617 + MTK_PPE_GLO_CFG_IP4_CS_DROP |
618 + MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;
619 + ppe_w32(ppe, MTK_PPE_GLO_CFG, val);
620 +
621 + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
622 +
623 + return 0;
624 +}
625 +
626 +int mtk_ppe_stop(struct mtk_ppe *ppe)
627 +{
628 + u32 val;
629 + int i;
630 +
631 + for (i = 0; i < MTK_PPE_ENTRIES; i++)
632 + ppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE,
633 + MTK_FOE_STATE_INVALID);
634 +
635 + mtk_ppe_cache_enable(ppe, false);
636 +
637 + /* disable offload engine */
638 + ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);
639 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);
640 +
641 + /* disable aging */
642 + val = MTK_PPE_TB_CFG_AGE_NON_L4 |
643 + MTK_PPE_TB_CFG_AGE_UNBIND |
644 + MTK_PPE_TB_CFG_AGE_TCP |
645 + MTK_PPE_TB_CFG_AGE_UDP |
646 + MTK_PPE_TB_CFG_AGE_TCP_FIN;
647 + ppe_clear(ppe, MTK_PPE_TB_CFG, val);
648 +
649 + return mtk_ppe_wait_busy(ppe);
650 +}
651 --- /dev/null
652 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
653 @@ -0,0 +1,287 @@
654 +// SPDX-License-Identifier: GPL-2.0-only
655 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
656 +
657 +#ifndef __MTK_PPE_H
658 +#define __MTK_PPE_H
659 +
660 +#include <linux/kernel.h>
661 +#include <linux/bitfield.h>
662 +
663 +#define MTK_ETH_PPE_BASE 0xc00
664 +
665 +#define MTK_PPE_ENTRIES_SHIFT 3
666 +#define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT)
667 +#define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1)
668 +
669 +#define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
670 +#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)
671 +#define MTK_FOE_IB1_UNBIND_PREBIND BIT(24)
672 +
673 +#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)
674 +#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15)
675 +#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16)
676 +#define MTK_FOE_IB1_BIND_PPPOE BIT(19)
677 +#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20)
678 +#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21)
679 +#define MTK_FOE_IB1_BIND_CACHE BIT(22)
680 +#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23)
681 +#define MTK_FOE_IB1_BIND_TTL BIT(24)
682 +
683 +#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25)
684 +#define MTK_FOE_IB1_STATE GENMASK(29, 28)
685 +#define MTK_FOE_IB1_UDP BIT(30)
686 +#define MTK_FOE_IB1_STATIC BIT(31)
687 +
688 +enum {
689 + MTK_PPE_PKT_TYPE_IPV4_HNAPT = 0,
690 + MTK_PPE_PKT_TYPE_IPV4_ROUTE = 1,
691 + MTK_PPE_PKT_TYPE_BRIDGE = 2,
692 + MTK_PPE_PKT_TYPE_IPV4_DSLITE = 3,
693 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
694 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
695 + MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
696 +};
697 +
698 +#define MTK_FOE_IB2_QID GENMASK(3, 0)
699 +#define MTK_FOE_IB2_PSE_QOS BIT(4)
700 +#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)
701 +#define MTK_FOE_IB2_MULTICAST BIT(8)
702 +
703 +#define MTK_FOE_IB2_WHNAT_QID2 GENMASK(13, 12)
704 +#define MTK_FOE_IB2_WHNAT_DEVIDX BIT(16)
705 +#define MTK_FOE_IB2_WHNAT_NAT BIT(17)
706 +
707 +#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12)
708 +
709 +#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18)
710 +
711 +#define MTK_FOE_IB2_DSCP GENMASK(31, 24)
712 +
713 +#define MTK_FOE_VLAN2_WHNAT_BSS GEMMASK(5, 0)
714 +#define MTK_FOE_VLAN2_WHNAT_WCID GENMASK(13, 6)
715 +#define MTK_FOE_VLAN2_WHNAT_RING GENMASK(15, 14)
716 +
717 +enum {
718 + MTK_FOE_STATE_INVALID,
719 + MTK_FOE_STATE_UNBIND,
720 + MTK_FOE_STATE_BIND,
721 + MTK_FOE_STATE_FIN
722 +};
723 +
724 +struct mtk_foe_mac_info {
725 + u16 vlan1;
726 + u16 etype;
727 +
728 + u32 dest_mac_hi;
729 +
730 + u16 vlan2;
731 + u16 dest_mac_lo;
732 +
733 + u32 src_mac_hi;
734 +
735 + u16 pppoe_id;
736 + u16 src_mac_lo;
737 +};
738 +
739 +struct mtk_foe_bridge {
740 + u32 dest_mac_hi;
741 +
742 + u16 src_mac_lo;
743 + u16 dest_mac_lo;
744 +
745 + u32 src_mac_hi;
746 +
747 + u32 ib2;
748 +
749 + u32 _rsv[5];
750 +
751 + u32 udf_tsid;
752 + struct mtk_foe_mac_info l2;
753 +};
754 +
755 +struct mtk_ipv4_tuple {
756 + u32 src_ip;
757 + u32 dest_ip;
758 + union {
759 + struct {
760 + u16 dest_port;
761 + u16 src_port;
762 + };
763 + struct {
764 + u8 protocol;
765 + u8 _pad[3]; /* fill with 0xa5a5a5 */
766 + };
767 + u32 ports;
768 + };
769 +};
770 +
771 +struct mtk_foe_ipv4 {
772 + struct mtk_ipv4_tuple orig;
773 +
774 + u32 ib2;
775 +
776 + struct mtk_ipv4_tuple new;
777 +
778 + u16 timestamp;
779 + u16 _rsv0[3];
780 +
781 + u32 udf_tsid;
782 +
783 + struct mtk_foe_mac_info l2;
784 +};
785 +
786 +struct mtk_foe_ipv4_dslite {
787 + struct mtk_ipv4_tuple ip4;
788 +
789 + u32 tunnel_src_ip[4];
790 + u32 tunnel_dest_ip[4];
791 +
792 + u8 flow_label[3];
793 + u8 priority;
794 +
795 + u32 udf_tsid;
796 +
797 + u32 ib2;
798 +
799 + struct mtk_foe_mac_info l2;
800 +};
801 +
802 +struct mtk_foe_ipv6 {
803 + u32 src_ip[4];
804 + u32 dest_ip[4];
805 +
806 + union {
807 + struct {
808 + u8 protocol;
809 + u8 _pad[3]; /* fill with 0xa5a5a5 */
810 + }; /* 3-tuple */
811 + struct {
812 + u16 dest_port;
813 + u16 src_port;
814 + }; /* 5-tuple */
815 + u32 ports;
816 + };
817 +
818 + u32 _rsv[3];
819 +
820 + u32 udf;
821 +
822 + u32 ib2;
823 + struct mtk_foe_mac_info l2;
824 +};
825 +
826 +struct mtk_foe_ipv6_6rd {
827 + u32 src_ip[4];
828 + u32 dest_ip[4];
829 + u16 dest_port;
830 + u16 src_port;
831 +
832 + u32 tunnel_src_ip;
833 + u32 tunnel_dest_ip;
834 +
835 + u16 hdr_csum;
836 + u8 dscp;
837 + u8 ttl;
838 +
839 + u8 flag;
840 + u8 pad;
841 + u8 per_flow_6rd_id;
842 + u8 pad2;
843 +
844 + u32 ib2;
845 + struct mtk_foe_mac_info l2;
846 +};
847 +
848 +struct mtk_foe_entry {
849 + u32 ib1;
850 +
851 + union {
852 + struct mtk_foe_bridge bridge;
853 + struct mtk_foe_ipv4 ipv4;
854 + struct mtk_foe_ipv4_dslite dslite;
855 + struct mtk_foe_ipv6 ipv6;
856 + struct mtk_foe_ipv6_6rd ipv6_6rd;
857 + u32 data[19];
858 + };
859 +};
860 +
861 +enum {
862 + MTK_PPE_CPU_REASON_TTL_EXCEEDED = 0x02,
863 + MTK_PPE_CPU_REASON_OPTION_HEADER = 0x03,
864 + MTK_PPE_CPU_REASON_NO_FLOW = 0x07,
865 + MTK_PPE_CPU_REASON_IPV4_FRAG = 0x08,
866 + MTK_PPE_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
867 + MTK_PPE_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
868 + MTK_PPE_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
869 + MTK_PPE_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
870 + MTK_PPE_CPU_REASON_UN_HIT = 0x0d,
871 + MTK_PPE_CPU_REASON_HIT_UNBIND = 0x0e,
872 + MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
873 + MTK_PPE_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
874 + MTK_PPE_CPU_REASON_HIT_TTL_1 = 0x11,
875 + MTK_PPE_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
876 + MTK_PPE_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
877 + MTK_PPE_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
878 + MTK_PPE_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
879 + MTK_PPE_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
880 + MTK_PPE_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
881 + MTK_PPE_CPU_REASON_MULTICAST_TO_CPU = 0x18,
882 + MTK_PPE_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
883 + MTK_PPE_CPU_REASON_HIT_PRE_BIND = 0x1a,
884 + MTK_PPE_CPU_REASON_PACKET_SAMPLING = 0x1b,
885 + MTK_PPE_CPU_REASON_EXCEED_MTU = 0x1c,
886 + MTK_PPE_CPU_REASON_PPE_BYPASS = 0x1e,
887 + MTK_PPE_CPU_REASON_INVALID = 0x1f,
888 +};
889 +
890 +struct mtk_ppe {
891 + struct device *dev;
892 + void __iomem *base;
893 + int version;
894 +
895 + struct mtk_foe_entry *foe_table;
896 + dma_addr_t foe_phys;
897 +
898 + void *acct_table;
899 +};
900 +
901 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
902 + int version);
903 +int mtk_ppe_start(struct mtk_ppe *ppe);
904 +int mtk_ppe_stop(struct mtk_ppe *ppe);
905 +
906 +static inline void
907 +mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)
908 +{
909 + ppe->foe_table[hash].ib1 = 0;
910 + dma_wmb();
911 +}
912 +
913 +static inline int
914 +mtk_foe_entry_timestamp(struct mtk_ppe *ppe, u16 hash)
915 +{
916 + u32 ib1 = READ_ONCE(ppe->foe_table[hash].ib1);
917 +
918 + if (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND)
919 + return -1;
920 +
921 + return FIELD_GET(MTK_FOE_IB1_BIND_TIMESTAMP, ib1);
922 +}
923 +
924 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
925 + u8 pse_port, u8 *src_mac, u8 *dest_mac);
926 +int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port);
927 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool orig,
928 + __be32 src_addr, __be16 src_port,
929 + __be32 dest_addr, __be16 dest_port);
930 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
931 + __be32 *src_addr, __be16 src_port,
932 + __be32 *dest_addr, __be16 dest_port);
933 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);
934 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);
935 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);
936 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
937 + u16 timestamp);
938 +int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);
939 +
940 +#endif
941 --- /dev/null
942 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
943 @@ -0,0 +1,217 @@
944 +// SPDX-License-Identifier: GPL-2.0-only
945 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
946 +
947 +#include <linux/kernel.h>
948 +#include <linux/debugfs.h>
949 +#include "mtk_eth_soc.h"
950 +
951 +struct mtk_flow_addr_info
952 +{
953 + void *src, *dest;
954 + u16 *src_port, *dest_port;
955 + bool ipv6;
956 +};
957 +
958 +static const char *mtk_foe_entry_state_str(int state)
959 +{
960 + static const char * const state_str[] = {
961 + [MTK_FOE_STATE_INVALID] = "INV",
962 + [MTK_FOE_STATE_UNBIND] = "UNB",
963 + [MTK_FOE_STATE_BIND] = "BND",
964 + [MTK_FOE_STATE_FIN] = "FIN",
965 + };
966 +
967 + if (state >= ARRAY_SIZE(state_str) || !state_str[state])
968 + return "UNK";
969 +
970 + return state_str[state];
971 +}
972 +
973 +static const char *mtk_foe_pkt_type_str(int type)
974 +{
975 + static const char * const type_str[] = {
976 + [MTK_PPE_PKT_TYPE_IPV4_HNAPT] = "IPv4 5T",
977 + [MTK_PPE_PKT_TYPE_IPV4_ROUTE] = "IPv4 3T",
978 + [MTK_PPE_PKT_TYPE_BRIDGE] = "L2",
979 + [MTK_PPE_PKT_TYPE_IPV4_DSLITE] = "DS-LITE",
980 + [MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = "IPv6 3T",
981 + [MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = "IPv6 5T",
982 + [MTK_PPE_PKT_TYPE_IPV6_6RD] = "6RD",
983 + };
984 +
985 + if (type >= ARRAY_SIZE(type_str) || !type_str[type])
986 + return "UNKNOWN";
987 +
988 + return type_str[type];
989 +}
990 +
991 +static void
992 +mtk_print_addr(struct seq_file *m, u32 *addr, bool ipv6)
993 +{
994 + u32 n_addr[4];
995 + int i;
996 +
997 + if (!ipv6) {
998 + seq_printf(m, "%pI4h", addr);
999 + return;
1000 + }
1001 +
1002 + for (i = 0; i < ARRAY_SIZE(n_addr); i++)
1003 + n_addr[i] = htonl(addr[i]);
1004 + seq_printf(m, "%pI6", n_addr);
1005 +}
1006 +
1007 +static void
1008 +mtk_print_addr_info(struct seq_file *m, struct mtk_flow_addr_info *ai)
1009 +{
1010 + mtk_print_addr(m, ai->src, ai->ipv6);
1011 + if (ai->src_port)
1012 + seq_printf(m, ":%d", *ai->src_port);
1013 + seq_printf(m, "->");
1014 + mtk_print_addr(m, ai->dest, ai->ipv6);
1015 + if (ai->dest_port)
1016 + seq_printf(m, ":%d", *ai->dest_port);
1017 +}
1018 +
1019 +static int
1020 +mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)
1021 +{
1022 + struct mtk_ppe *ppe = m->private;
1023 + int i, count;
1024 +
1025 + for (i = 0, count = 0; i < MTK_PPE_ENTRIES; i++) {
1026 + struct mtk_foe_entry *entry = &ppe->foe_table[i];
1027 + struct mtk_foe_mac_info *l2;
1028 + struct mtk_flow_addr_info ai = {};
1029 + unsigned char h_source[ETH_ALEN];
1030 + unsigned char h_dest[ETH_ALEN];
1031 + int type, state;
1032 + u32 ib2;
1033 +
1034 +
1035 + state = FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1);
1036 + if (!state)
1037 + continue;
1038 +
1039 + if (bind && state != MTK_FOE_STATE_BIND)
1040 + continue;
1041 +
1042 + type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
1043 + seq_printf(m, "%05x %s %7s", i,
1044 + mtk_foe_entry_state_str(state),
1045 + mtk_foe_pkt_type_str(type));
1046 +
1047 + switch (type) {
1048 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
1049 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
1050 + ai.src_port = &entry->ipv4.orig.src_port;
1051 + ai.dest_port = &entry->ipv4.orig.dest_port;
1052 + fallthrough;
1053 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
1054 + ai.src = &entry->ipv4.orig.src_ip;
1055 + ai.dest = &entry->ipv4.orig.dest_ip;
1056 + break;
1057 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
1058 + ai.src_port = &entry->ipv6.src_port;
1059 + ai.dest_port = &entry->ipv6.dest_port;
1060 + fallthrough;
1061 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
1062 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
1063 + ai.src = &entry->ipv6.src_ip;
1064 + ai.dest = &entry->ipv6.dest_ip;
1065 + ai.ipv6 = true;
1066 + break;
1067 + }
1068 +
1069 + seq_printf(m, " orig=");
1070 + mtk_print_addr_info(m, &ai);
1071 +
1072 + switch (type) {
1073 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
1074 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
1075 + ai.src_port = &entry->ipv4.new.src_port;
1076 + ai.dest_port = &entry->ipv4.new.dest_port;
1077 + fallthrough;
1078 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
1079 + ai.src = &entry->ipv4.new.src_ip;
1080 + ai.dest = &entry->ipv4.new.dest_ip;
1081 + seq_printf(m, " new=");
1082 + mtk_print_addr_info(m, &ai);
1083 + break;
1084 + }
1085 +
1086 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
1087 + l2 = &entry->ipv6.l2;
1088 + ib2 = entry->ipv6.ib2;
1089 + } else {
1090 + l2 = &entry->ipv4.l2;
1091 + ib2 = entry->ipv4.ib2;
1092 + }
1093 +
1094 + *((__be32 *)h_source) = htonl(l2->src_mac_hi);
1095 + *((__be16 *)&h_source[4]) = htons(l2->src_mac_lo);
1096 + *((__be32 *)h_dest) = htonl(l2->dest_mac_hi);
1097 + *((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);
1098 +
1099 + seq_printf(m, " eth=%pM->%pM etype=%04x"
1100 + " vlan=%d,%d ib1=%08x ib2=%08x\n",
1101 + h_source, h_dest, ntohs(l2->etype),
1102 + l2->vlan1, l2->vlan2, entry->ib1, ib2);
1103 + }
1104 +
1105 + return 0;
1106 +}
1107 +
1108 +static int
1109 +mtk_ppe_debugfs_foe_show_all(struct seq_file *m, void *private)
1110 +{
1111 + return mtk_ppe_debugfs_foe_show(m, private, false);
1112 +}
1113 +
1114 +static int
1115 +mtk_ppe_debugfs_foe_show_bind(struct seq_file *m, void *private)
1116 +{
1117 + return mtk_ppe_debugfs_foe_show(m, private, true);
1118 +}
1119 +
1120 +static int
1121 +mtk_ppe_debugfs_foe_open_all(struct inode *inode, struct file *file)
1122 +{
1123 + return single_open(file, mtk_ppe_debugfs_foe_show_all,
1124 + inode->i_private);
1125 +}
1126 +
1127 +static int
1128 +mtk_ppe_debugfs_foe_open_bind(struct inode *inode, struct file *file)
1129 +{
1130 + return single_open(file, mtk_ppe_debugfs_foe_show_bind,
1131 + inode->i_private);
1132 +}
1133 +
1134 +int mtk_ppe_debugfs_init(struct mtk_ppe *ppe)
1135 +{
1136 + static const struct file_operations fops_all = {
1137 + .open = mtk_ppe_debugfs_foe_open_all,
1138 + .read = seq_read,
1139 + .llseek = seq_lseek,
1140 + .release = single_release,
1141 + };
1142 +
1143 + static const struct file_operations fops_bind = {
1144 + .open = mtk_ppe_debugfs_foe_open_bind,
1145 + .read = seq_read,
1146 + .llseek = seq_lseek,
1147 + .release = single_release,
1148 + };
1149 +
1150 + struct dentry *root;
1151 +
1152 + root = debugfs_create_dir("mtk_ppe", NULL);
1153 + if (!root)
1154 + return -ENOMEM;
1155 +
1156 + debugfs_create_file("entries", S_IRUGO, root, ppe, &fops_all);
1157 + debugfs_create_file("bind", S_IRUGO, root, ppe, &fops_bind);
1158 +
1159 + return 0;
1160 +}
1161 --- /dev/null
1162 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
1163 @@ -0,0 +1,144 @@
1164 +// SPDX-License-Identifier: GPL-2.0-only
1165 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
1166 +
1167 +#ifndef __MTK_PPE_REGS_H
1168 +#define __MTK_PPE_REGS_H
1169 +
1170 +#define MTK_PPE_GLO_CFG 0x200
1171 +#define MTK_PPE_GLO_CFG_EN BIT(0)
1172 +#define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
1173 +#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
1174 +#define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
1175 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
1176 +#define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
1177 +#define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
1178 +#define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
1179 +#define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
1180 +#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9)
1181 +#define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10)
1182 +#define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11)
1183 +#define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12)
1184 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
1185 +
1186 +#define MTK_PPE_FLOW_CFG 0x204
1187 +#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6)
1188 +#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7)
1189 +#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8)
1190 +#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9)
1191 +#define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10)
1192 +#define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12)
1193 +#define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13)
1194 +#define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14)
1195 +#define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15)
1196 +#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16)
1197 +#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17)
1198 +#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18)
1199 +#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19)
1200 +#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20)
1201 +
1202 +#define MTK_PPE_IP_PROTO_CHK 0x208
1203 +#define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
1204 +#define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16)
1205 +
1206 +#define MTK_PPE_TB_CFG 0x21c
1207 +#define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
1208 +#define MTK_PPE_TB_CFG_ENTRY_80B BIT(3)
1209 +#define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4)
1210 +#define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6)
1211 +#define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7)
1212 +#define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8)
1213 +#define MTK_PPE_TB_CFG_AGE_TCP BIT(9)
1214 +#define MTK_PPE_TB_CFG_AGE_UDP BIT(10)
1215 +#define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11)
1216 +#define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)
1217 +#define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14)
1218 +#define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16)
1219 +#define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18)
1220 +
1221 +enum {
1222 + MTK_PPE_SCAN_MODE_DISABLED,
1223 + MTK_PPE_SCAN_MODE_CHECK_AGE,
1224 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE,
1225 +};
1226 +
1227 +enum {
1228 + MTK_PPE_KEEPALIVE_DISABLE,
1229 + MTK_PPE_KEEPALIVE_UNICAST_CPU,
1230 + MTK_PPE_KEEPALIVE_DUP_CPU = 3,
1231 +};
1232 +
1233 +enum {
1234 + MTK_PPE_SEARCH_MISS_ACTION_DROP,
1235 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2,
1236 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3,
1237 +};
1238 +
1239 +#define MTK_PPE_TB_BASE 0x220
1240 +
1241 +#define MTK_PPE_TB_USED 0x224
1242 +#define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
1243 +
1244 +#define MTK_PPE_BIND_RATE 0x228
1245 +#define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0)
1246 +#define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16)
1247 +
1248 +#define MTK_PPE_BIND_LIMIT0 0x22c
1249 +#define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)
1250 +#define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16)
1251 +
1252 +#define MTK_PPE_BIND_LIMIT1 0x230
1253 +#define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)
1254 +#define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16)
1255 +
1256 +#define MTK_PPE_KEEPALIVE 0x234
1257 +#define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0)
1258 +#define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16)
1259 +#define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24)
1260 +
1261 +#define MTK_PPE_UNBIND_AGE 0x238
1262 +#define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16)
1263 +#define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0)
1264 +
1265 +#define MTK_PPE_BIND_AGE0 0x23c
1266 +#define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)
1267 +#define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)
1268 +
1269 +#define MTK_PPE_BIND_AGE1 0x240
1270 +#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)
1271 +#define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)
1272 +
1273 +#define MTK_PPE_HASH_SEED 0x244
1274 +
1275 +#define MTK_PPE_DEFAULT_CPU_PORT 0x248
1276 +#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4))
1277 +
1278 +#define MTK_PPE_MTU_DROP 0x308
1279 +
1280 +#define MTK_PPE_VLAN_MTU0 0x30c
1281 +#define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)
1282 +#define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16)
1283 +
1284 +#define MTK_PPE_VLAN_MTU1 0x310
1285 +#define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)
1286 +#define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16)
1287 +
1288 +#define MTK_PPE_VPM_TPID 0x318
1289 +
1290 +#define MTK_PPE_CACHE_CTL 0x320
1291 +#define MTK_PPE_CACHE_CTL_EN BIT(0)
1292 +#define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4)
1293 +#define MTK_PPE_CACHE_CTL_REQ BIT(8)
1294 +#define MTK_PPE_CACHE_CTL_CLEAR BIT(9)
1295 +#define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12)
1296 +
1297 +#define MTK_PPE_MIB_CFG 0x334
1298 +#define MTK_PPE_MIB_CFG_EN BIT(0)
1299 +#define MTK_PPE_MIB_CFG_RD_CLR BIT(1)
1300 +
1301 +#define MTK_PPE_MIB_TB_BASE 0x338
1302 +
1303 +#define MTK_PPE_MIB_CACHE_CTL 0x350
1304 +#define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
1305 +#define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
1306 +
1307 +#endif
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