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ipq40xx: add support for AVM FRITZ!Repeater 3000
[openwrt/staging/wigyori.git] / target / linux / ipq40xx / patches-4.14 / 078-ARM-dts-ipq4019-Add-a-few-peripheral-nodes.patch
1 From 187519403273f0599c848d20eca9acce8b1807a5 Mon Sep 17 00:00:00 2001
2 From: Sricharan R <sricharan@codeaurora.org>
3 Date: Fri, 25 May 2018 11:41:12 +0530
4 Subject: [PATCH] ARM: dts: ipq4019: Add a few peripheral nodes
5
6 Now with the driver updates for some peripherals being there,
7 add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
8 peripheral support.
9
10 Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
11 Signed-off-by: Sricharan R <sricharan@codeaurora.org>
12 Signed-off-by: Andy Gross <andy.gross@linaro.org>
13 ---
14 arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
15 arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
16 2 files changed, 146 insertions(+), 12 deletions(-)
17
18 --- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
19 +++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
20 @@ -61,7 +61,7 @@
21 status = "ok";
22 };
23
24 - spi_0: spi@78b5000 {
25 + spi@78b5000 {
26 pinctrl-0 = <&spi_0_pins>;
27 pinctrl-names = "default";
28 status = "ok";
29 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
30 +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
31 @@ -24,8 +24,10 @@
32 interrupt-parent = <&intc>;
33
34 aliases {
35 - spi0 = &spi_0;
36 - i2c0 = &i2c_0;
37 + spi0 = &blsp1_spi1;
38 + spi1 = &blsp1_spi2;
39 + i2c0 = &blsp1_i2c3;
40 + i2c1 = &blsp1_i2c4;
41 };
42
43 cpus {
44 @@ -132,6 +134,12 @@
45 };
46 };
47
48 + firmware {
49 + scm {
50 + compatible = "qcom,scm-ipq4019";
51 + };
52 + };
53 +
54 timer {
55 compatible = "arm,armv7-timer";
56 interrupts = <1 2 0xf08>,
57 @@ -177,13 +185,13 @@
58 #gpio-cells = <2>;
59 interrupt-controller;
60 #interrupt-cells = <2>;
61 - interrupts = <0 208 0>;
62 + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
63 };
64
65 blsp_dma: dma@7884000 {
66 compatible = "qcom,bam-v1.7.0";
67 reg = <0x07884000 0x23000>;
68 - interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
69 + interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
70 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
71 clock-names = "bam_clk";
72 #dma-cells = <1>;
73 @@ -191,7 +199,7 @@
74 status = "disabled";
75 };
76
77 - spi_0: spi@78b5000 {
78 + blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
79 compatible = "qcom,spi-qup-v2.2.1";
80 reg = <0x78b5000 0x600>;
81 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
82 @@ -200,10 +208,26 @@
83 clock-names = "core", "iface";
84 #address-cells = <1>;
85 #size-cells = <0>;
86 + dmas = <&blsp_dma 5>, <&blsp_dma 4>;
87 + dma-names = "rx", "tx";
88 + status = "disabled";
89 + };
90 +
91 + blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
92 + compatible = "qcom,spi-qup-v2.2.1";
93 + reg = <0x78b6000 0x600>;
94 + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
95 + clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
96 + <&gcc GCC_BLSP1_AHB_CLK>;
97 + clock-names = "core", "iface";
98 + #address-cells = <1>;
99 + #size-cells = <0>;
100 + dmas = <&blsp_dma 7>, <&blsp_dma 6>;
101 + dma-names = "rx", "tx";
102 status = "disabled";
103 };
104
105 - i2c_0: i2c@78b7000 {
106 + blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
107 compatible = "qcom,i2c-qup-v2.2.1";
108 reg = <0x78b7000 0x600>;
109 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
110 @@ -212,14 +236,29 @@
111 clock-names = "iface", "core";
112 #address-cells = <1>;
113 #size-cells = <0>;
114 + dmas = <&blsp_dma 9>, <&blsp_dma 8>;
115 + dma-names = "rx", "tx";
116 status = "disabled";
117 };
118
119 + blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
120 + compatible = "qcom,i2c-qup-v2.2.1";
121 + reg = <0x78b8000 0x600>;
122 + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
123 + clocks = <&gcc GCC_BLSP1_AHB_CLK>,
124 + <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
125 + clock-names = "iface", "core";
126 + #address-cells = <1>;
127 + #size-cells = <0>;
128 + dmas = <&blsp_dma 11>, <&blsp_dma 10>;
129 + dma-names = "rx", "tx";
130 + status = "disabled";
131 + };
132
133 cryptobam: dma@8e04000 {
134 compatible = "qcom,bam-v1.7.0";
135 reg = <0x08e04000 0x20000>;
136 - interrupts = <GIC_SPI 207 0>;
137 + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
138 clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
139 clock-names = "bam_clk";
140 #dma-cells = <1>;
141 @@ -293,7 +332,7 @@
142 serial@78af000 {
143 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
144 reg = <0x78af000 0x200>;
145 - interrupts = <0 107 0>;
146 + interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
147 status = "disabled";
148 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
149 <&gcc GCC_BLSP1_AHB_CLK>;
150 @@ -305,7 +344,7 @@
151 serial@78b0000 {
152 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
153 reg = <0x78b0000 0x200>;
154 - interrupts = <0 108 0>;
155 + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
156 status = "disabled";
157 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
158 <&gcc GCC_BLSP1_AHB_CLK>;
159 @@ -327,6 +366,101 @@
160 reg = <0x4ab000 0x4>;
161 };
162
163 + pcie0: pci@40000000 {
164 + compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
165 + reg = <0x40000000 0xf1d
166 + 0x40000f20 0xa8
167 + 0x80000 0x2000
168 + 0x40100000 0x1000>;
169 + reg-names = "dbi", "elbi", "parf", "config";
170 + device_type = "pci";
171 + linux,pci-domain = <0>;
172 + bus-range = <0x00 0xff>;
173 + num-lanes = <1>;
174 + #address-cells = <3>;
175 + #size-cells = <2>;
176 +
177 + ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
178 + 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
179 +
180 + interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
181 + interrupt-names = "msi";
182 + #interrupt-cells = <1>;
183 + interrupt-map-mask = <0 0 0 0x7>;
184 + interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
185 + <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
186 + <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
187 + <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
188 + clocks = <&gcc GCC_PCIE_AHB_CLK>,
189 + <&gcc GCC_PCIE_AXI_M_CLK>,
190 + <&gcc GCC_PCIE_AXI_S_CLK>;
191 + clock-names = "aux",
192 + "master_bus",
193 + "slave_bus";
194 +
195 + resets = <&gcc PCIE_AXI_M_ARES>,
196 + <&gcc PCIE_AXI_S_ARES>,
197 + <&gcc PCIE_PIPE_ARES>,
198 + <&gcc PCIE_AXI_M_VMIDMT_ARES>,
199 + <&gcc PCIE_AXI_S_XPU_ARES>,
200 + <&gcc PCIE_PARF_XPU_ARES>,
201 + <&gcc PCIE_PHY_ARES>,
202 + <&gcc PCIE_AXI_M_STICKY_ARES>,
203 + <&gcc PCIE_PIPE_STICKY_ARES>,
204 + <&gcc PCIE_PWR_ARES>,
205 + <&gcc PCIE_AHB_ARES>,
206 + <&gcc PCIE_PHY_AHB_ARES>;
207 + reset-names = "axi_m",
208 + "axi_s",
209 + "pipe",
210 + "axi_m_vmid",
211 + "axi_s_xpu",
212 + "parf",
213 + "phy",
214 + "axi_m_sticky",
215 + "pipe_sticky",
216 + "pwr",
217 + "ahb",
218 + "phy_ahb";
219 +
220 + status = "disabled";
221 + };
222 +
223 + qpic_bam: dma@7984000 {
224 + compatible = "qcom,bam-v1.7.0";
225 + reg = <0x7984000 0x1a000>;
226 + interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
227 + clocks = <&gcc GCC_QPIC_CLK>;
228 + clock-names = "bam_clk";
229 + #dma-cells = <1>;
230 + qcom,ee = <0>;
231 + status = "disabled";
232 + };
233 +
234 + nand: qpic-nand@79b0000 {
235 + compatible = "qcom,ipq4019-nand";
236 + reg = <0x79b0000 0x1000>;
237 + #address-cells = <1>;
238 + #size-cells = <0>;
239 + clocks = <&gcc GCC_QPIC_CLK>,
240 + <&gcc GCC_QPIC_AHB_CLK>;
241 + clock-names = "core", "aon";
242 +
243 + dmas = <&qpic_bam 0>,
244 + <&qpic_bam 1>,
245 + <&qpic_bam 2>;
246 + dma-names = "tx", "rx", "cmd";
247 + status = "disabled";
248 +
249 + nand@0 {
250 + reg = <0>;
251 +
252 + nand-ecc-strength = <4>;
253 + nand-ecc-step-size = <512>;
254 + nand-bus-width = <8>;
255 + };
256 + };
257 +
258 wifi0: wifi@a000000 {
259 compatible = "qcom,ipq4019-wifi";
260 reg = <0xa000000 0x200000>;
261 @@ -360,7 +494,7 @@
262 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
263 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
264 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
265 - <GIC_SPI 168 IRQ_TYPE_NONE>;
266 + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
267 interrupt-names = "msi0", "msi1", "msi2", "msi3",
268 "msi4", "msi5", "msi6", "msi7",
269 "msi8", "msi9", "msi10", "msi11",
270 @@ -402,7 +536,7 @@
271 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
272 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
273 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
274 - <GIC_SPI 169 IRQ_TYPE_NONE>;
275 + <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
276 interrupt-names = "msi0", "msi1", "msi2", "msi3",
277 "msi4", "msi5", "msi6", "msi7",
278 "msi8", "msi9", "msi10", "msi11",
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