target/linux/ipq807x/files/arch/arm64/boot/dts/qcom/ipq8072-haze.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 /dts-v1/;
   4
   5 #include "ipq8074.dtsi"
   6 #include "ipq8074-hk-cpu.dtsi"
   7 #include "ipq8074-ess.dtsi"
   8 #include <dt-bindings/gpio/gpio.h>
   9 #include <dt-bindings/input/input.h>
  10 #include <dt-bindings/leds/common.h>
  11
  12 / {
  13         model = "prpl Foundation Haze";
  14         compatible = "prpl,haze", "qcom,ipq8074";
  15
  16         aliases {
  17                 serial0 = &blsp1_uart5;
  18                 /* Aliases are required by U-Boot to patch MAC addresses */
  19                 ethernet0 = &dp6_syn;
  20                 ethernet1 = &dp4;
  21                 ethernet2 = &dp3;
  22                 ethernet3 = &dp2;
  23                 label-mac-device = &dp6_syn;
  24         };
  25
  26         chosen {
  27                 stdout-path = "serial0:115200n8";
  28         };
  29
  30         keys {
  31                 compatible = "gpio-keys";
  32                 pinctrl-0 = <&button_pins>;
  33                 pinctrl-names = "default";
  34
  35                 wps-button {
  36                         label = "wps";
  37                         gpios = <&tlmm 42 GPIO_ACTIVE_LOW>;
  38                         linux,code = <KEY_WPS_BUTTON>;
  39                 };
  40
  41                 reset-button {
  42                         label = "reset";
  43                         gpios = <&tlmm 44 GPIO_ACTIVE_LOW>;
  44                         linux,code = <KEY_RESTART>;
  45                 };
  46         };
  47 };
  48
  49 &tlmm {
  50         mdio_pins: mdio-state {
  51                 mdc-pins {
  52                         pins = "gpio68";
  53                         function = "mdc";
  54                         drive-strength = <8>;
  55                         bias-pull-up;
  56                 };
  57
  58                 mdio-pins {
  59                         pins = "gpio69";
  60                         function = "mdio";
  61                         drive-strength = <8>;
  62                         bias-pull-up;
  63                 };
  64         };
  65
  66         button_pins: button-state {
  67                 wps-pins {
  68                         pins = "gpio42";
  69                         function = "gpio";
  70                         drive-strength = <8>;
  71                         bias-pull-up;
  72                 };
  73
  74                 rst-pins {
  75                         pins = "gpio44";
  76                         function = "gpio";
  77                         drive-strength = <8>;
  78                         bias-pull-up;
  79                 };
  80         };
  81 };
  82
  83 &blsp1_uart5 {
  84         status = "okay";
  85 };
  86
  87 &prng {
  88         status = "okay";
  89 };
  90
  91 &ssphy_0 {
  92         status = "okay";
  93 };
  94
  95 &qusb_phy_0 {
  96         status = "okay";
  97 };
  98
  99 &ssphy_1 {
 100         status = "okay";
 101 };
 102
 103 &qusb_phy_1 {
 104         status = "okay";
 105 };
 106
 107 &usb_0 {
 108         status = "okay";
 109 };
 110
 111 &usb_1 {
 112         status = "okay";
 113 };
 114
 115 &cryptobam {
 116         status = "okay";
 117 };
 118
 119 &crypto {
 120         status = "okay";
 121 };
 122
 123 &qpic_bam {
 124         status = "okay";
 125 };
 126
 127 &blsp1_spi1 { /* BLSP1 QUP1 */
 128         pinctrl-0 = <&spi_0_pins>;
 129         pinctrl-names = "default";
 130         cs-gpios = <0>;
 131         status = "okay";
 132
 133         flash@0 {
 134                 #address-cells = <1>;
 135                 #size-cells = <1>;
 136                 reg = <0>;
 137                 compatible = "jedec,spi-nor";
 138                 spi-max-frequency = <50000000>;
 139
 140                 partitions {
 141                         compatible = "qcom,smem-part";
 142                 };
 143         };
 144 };
 145
 146 &mdio {
 147         status = "okay";
 148
 149         pinctrl-0 = <&mdio_pins>;
 150         pinctrl-names = "default";
 151         reset-gpios = <&tlmm 22 GPIO_ACTIVE_LOW>;
 152
 153         qca8075_1: ethernet-phy@0 {
 154                 compatible = "ethernet-phy-ieee802.3-c22";
 155                 reg = <0>;
 156         };
 157
 158         qca8075_2: ethernet-phy@1 {
 159                 compatible = "ethernet-phy-ieee802.3-c22";
 160                 reg = <1>;
 161         };
 162
 163         qca8075_3: ethernet-phy@2 {
 164                 compatible = "ethernet-phy-ieee802.3-c22";
 165                 reg = <2>;
 166         };
 167
 168         qca8075_4: ethernet-phy@3 {
 169                 compatible = "ethernet-phy-ieee802.3-c22";
 170                 reg = <3>;
 171         };
 172
 173         aqr113c: ethernet-phy@5 {
 174                 compatible ="ethernet-phy-ieee802.3-c45";
 175                 reg = <8>;
 176                 reset-gpios = <&tlmm 43 GPIO_ACTIVE_LOW>;
 177         };
 178 };
 179
 180 &sdhc_1 {
 181         status = "okay";
 182
 183         vqmmc-supply = <&l11>;
 184 };
 185
 186 &switch {
 187         status = "okay";
 188
 189         switch_cpu_bmp = <0x1>;  /* cpu port bitmap */
 190         switch_lan_bmp = <0x1e>; /* lan port bitmap */
 191         switch_wan_bmp = <0x60>; /* wan port bitmap */
 192         switch_mac_mode = <0x0>; /* mac mode for uniphy instance0*/
 193         switch_mac_mode1 = <0xe>; /* mac mode for uniphy instance1*/
 194         switch_mac_mode2 = <0xd>; /* mac mode for uniphy instance2*/
 195         bm_tick_mode = <0>; /* bm tick mode */
 196         tm_tick_mode = <0>; /* tm tick mode */
 197
 198         qcom,port_phyinfo {
 199                 port@0 {
 200                         port_id = <1>;
 201                         phy_address = <0>;
 202                 };
 203                 port@1 {
 204                         port_id = <2>;
 205                         phy_address = <1>;
 206                 };
 207                 port@2 {
 208                         port_id = <3>;
 209                         phy_address = <2>;
 210                 };
 211                 port@3 {
 212                         port_id = <4>;
 213                         phy_address = <3>;
 214                 };
 215                 port@4 {
 216                         port_id = <6>;
 217                         phy_address = <8>;
 218                         compatible = "ethernet-phy-ieee802.3-c45";
 219                         ethernet-phy-ieee802.3-c45;
 220                 };
 221         };
 222 };
 223
 224 &edma {
 225         status = "okay";
 226 };
 227
 228 /* Dummy LAN port */
 229 &dp1 {
 230         status = "disabled";
 231         phy-handle = <&qca8075_1>;
 232         label = "lan4";
 233 };
 234
 235 &dp2 {
 236         status = "okay";
 237         phy-handle = <&qca8075_2>;
 238         label = "lan3";
 239 };
 240
 241 &dp3 {
 242         status = "okay";
 243         phy-handle = <&qca8075_3>;
 244         label = "lan2";
 245 };
 246
 247 &dp4 {
 248         status = "okay";
 249         phy-handle = <&qca8075_4>;
 250         label = "lan1";
 251 };
 252
 253 &dp6_syn {
 254         status = "okay";
 255         qcom,mactype = <1>;
 256         phy-handle = <&aqr113c>;
 257         label = "wan";
 258 };
 259
 260 &pcie_qmp0 {
 261         status = "okay";
 262 };
 263
 264 &pcie0 {
 265         status = "okay";
 266
 267         perst-gpio = <&tlmm 58 GPIO_ACTIVE_LOW>;
 268
 269         bridge@0,0 {
 270                 reg = <0x00020000 0 0 0 0>;
 271                 #address-cells = <3>;
 272                 #size-cells = <2>;
 273                 ranges;
 274         };
 275 };
 276
 277 &pcie_qmp1 {
 278         status = "okay";
 279 };
 280
 281 &pcie1 {
 282         status = "okay";
 283
 284         perst-gpio = <&tlmm 61 GPIO_ACTIVE_LOW>;
 285
 286         bridge@1,0 {
 287                 reg = <0x00010000 0 0 0 0>;
 288                 #address-cells = <3>;
 289                 #size-cells = <2>;
 290                 ranges;
 291
 292                 wifi@1,0 {
 293                         status = "okay";
 294
 295                         /* ath11k has no DT compatible for PCI cards */
 296                         compatible = "pci17cb,1104";
 297                         reg = <0x00010000 0 0 0 0>;
 298
 299                         qcom,ath11k-calibration-variant = "prpl-Haze";
 300                 };
 301         };
 302 };
 303
 304 &wifi {
 305         status = "okay";
 306
 307         qcom,ath11k-calibration-variant = "prpl-Haze";
 308 };