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[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 302-dts-0082-arm64-dts-lx2160a-add-tmu-device-node.patch
1 From f6233242d21bb4cb973a7dfc61dcfbf6d9a5d22b Mon Sep 17 00:00:00 2001
2 From: Yuantian Tang <andy.tang@nxp.com>
3 Date: Mon, 2 Sep 2019 17:45:19 +0800
4 Subject: [PATCH] arm64: dts: lx2160a: add tmu device node
5
6 Add the TMU (Thermal Monitoring Unit) device node to enable
7 TMU feature.
8
9 Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
10 ---
11 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++++++++++++++++++++----
12 1 file changed, 92 insertions(+), 16 deletions(-)
13
14 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
15 +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
16 @@ -6,6 +6,7 @@
17
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
20 +#include <dt-bindings/thermal/thermal.h>
21
22 /memreserve/ 0x80000000 0x00010000;
23
24 @@ -24,7 +25,7 @@
25 #size-cells = <0>;
26
27 // 8 clusters having 2 Cortex-A72 cores each
28 - cpu@0 {
29 + cpu0: cpu@0 {
30 device_type = "cpu";
31 compatible = "arm,cortex-a72";
32 enable-method = "psci";
33 @@ -38,9 +39,10 @@
34 i-cache-sets = <192>;
35 next-level-cache = <&cluster0_l2>;
36 cpu-idle-states = <&cpu_pw15>;
37 + #cooling-cells = <2>;
38 };
39
40 - cpu@1 {
41 + cpu1: cpu@1 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a72";
44 enable-method = "psci";
45 @@ -54,9 +56,10 @@
46 i-cache-sets = <192>;
47 next-level-cache = <&cluster0_l2>;
48 cpu-idle-states = <&cpu_pw15>;
49 + #cooling-cells = <2>;
50 };
51
52 - cpu@100 {
53 + cpu100: cpu@100 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a72";
56 enable-method = "psci";
57 @@ -70,9 +73,10 @@
58 i-cache-sets = <192>;
59 next-level-cache = <&cluster1_l2>;
60 cpu-idle-states = <&cpu_pw15>;
61 + #cooling-cells = <2>;
62 };
63
64 - cpu@101 {
65 + cpu101: cpu@101 {
66 device_type = "cpu";
67 compatible = "arm,cortex-a72";
68 enable-method = "psci";
69 @@ -86,9 +90,10 @@
70 i-cache-sets = <192>;
71 next-level-cache = <&cluster1_l2>;
72 cpu-idle-states = <&cpu_pw15>;
73 + #cooling-cells = <2>;
74 };
75
76 - cpu@200 {
77 + cpu200: cpu@200 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a72";
80 enable-method = "psci";
81 @@ -102,9 +107,10 @@
82 i-cache-sets = <192>;
83 next-level-cache = <&cluster2_l2>;
84 cpu-idle-states = <&cpu_pw15>;
85 + #cooling-cells = <2>;
86 };
87
88 - cpu@201 {
89 + cpu201: cpu@201 {
90 device_type = "cpu";
91 compatible = "arm,cortex-a72";
92 enable-method = "psci";
93 @@ -118,9 +124,10 @@
94 i-cache-sets = <192>;
95 next-level-cache = <&cluster2_l2>;
96 cpu-idle-states = <&cpu_pw15>;
97 + #cooling-cells = <2>;
98 };
99
100 - cpu@300 {
101 + cpu300: cpu@300 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a72";
104 enable-method = "psci";
105 @@ -134,9 +141,10 @@
106 i-cache-sets = <192>;
107 next-level-cache = <&cluster3_l2>;
108 cpu-idle-states = <&cpu_pw15>;
109 + #cooling-cells = <2>;
110 };
111
112 - cpu@301 {
113 + cpu301: cpu@301 {
114 device_type = "cpu";
115 compatible = "arm,cortex-a72";
116 enable-method = "psci";
117 @@ -150,9 +158,10 @@
118 i-cache-sets = <192>;
119 next-level-cache = <&cluster3_l2>;
120 cpu-idle-states = <&cpu_pw15>;
121 + #cooling-cells = <2>;
122 };
123
124 - cpu@400 {
125 + cpu400: cpu@400 {
126 device_type = "cpu";
127 compatible = "arm,cortex-a72";
128 enable-method = "psci";
129 @@ -166,9 +175,10 @@
130 i-cache-sets = <192>;
131 next-level-cache = <&cluster4_l2>;
132 cpu-idle-states = <&cpu_pw15>;
133 + #cooling-cells = <2>;
134 };
135
136 - cpu@401 {
137 + cpu401: cpu@401 {
138 device_type = "cpu";
139 compatible = "arm,cortex-a72";
140 enable-method = "psci";
141 @@ -182,9 +192,10 @@
142 i-cache-sets = <192>;
143 next-level-cache = <&cluster4_l2>;
144 cpu-idle-states = <&cpu_pw15>;
145 + #cooling-cells = <2>;
146 };
147
148 - cpu@500 {
149 + cpu500: cpu@500 {
150 device_type = "cpu";
151 compatible = "arm,cortex-a72";
152 enable-method = "psci";
153 @@ -198,9 +209,10 @@
154 i-cache-sets = <192>;
155 next-level-cache = <&cluster5_l2>;
156 cpu-idle-states = <&cpu_pw15>;
157 + #cooling-cells = <2>;
158 };
159
160 - cpu@501 {
161 + cpu501: cpu@501 {
162 device_type = "cpu";
163 compatible = "arm,cortex-a72";
164 enable-method = "psci";
165 @@ -214,9 +226,10 @@
166 i-cache-sets = <192>;
167 next-level-cache = <&cluster5_l2>;
168 cpu-idle-states = <&cpu_pw15>;
169 + #cooling-cells = <2>;
170 };
171
172 - cpu@600 {
173 + cpu600: cpu@600 {
174 device_type = "cpu";
175 compatible = "arm,cortex-a72";
176 enable-method = "psci";
177 @@ -230,9 +243,10 @@
178 i-cache-sets = <192>;
179 next-level-cache = <&cluster6_l2>;
180 cpu-idle-states = <&cpu_pw15>;
181 + #cooling-cells = <2>;
182 };
183
184 - cpu@601 {
185 + cpu601: cpu@601 {
186 device_type = "cpu";
187 compatible = "arm,cortex-a72";
188 enable-method = "psci";
189 @@ -246,9 +260,10 @@
190 i-cache-sets = <192>;
191 next-level-cache = <&cluster6_l2>;
192 cpu-idle-states = <&cpu_pw15>;
193 + #cooling-cells = <2>;
194 };
195
196 - cpu@700 {
197 + cpu700: cpu@700 {
198 device_type = "cpu";
199 compatible = "arm,cortex-a72";
200 enable-method = "psci";
201 @@ -262,9 +277,10 @@
202 i-cache-sets = <192>;
203 next-level-cache = <&cluster7_l2>;
204 cpu-idle-states = <&cpu_pw15>;
205 + #cooling-cells = <2>;
206 };
207
208 - cpu@701 {
209 + cpu701: cpu@701 {
210 device_type = "cpu";
211 compatible = "arm,cortex-a72";
212 enable-method = "psci";
213 @@ -278,6 +294,7 @@
214 i-cache-sets = <192>;
215 next-level-cache = <&cluster7_l2>;
216 cpu-idle-states = <&cpu_pw15>;
217 + #cooling-cells = <2>;
218 };
219
220 cluster0_l2: l2-cache0 {
221 @@ -422,6 +439,51 @@
222 clock-output-names = "sysclk";
223 };
224
225 + thermal-zones {
226 + core_thermal1: core-thermal1 {
227 + polling-delay-passive = <1000>;
228 + polling-delay = <5000>;
229 + thermal-sensors = <&tmu 0>;
230 +
231 + trips {
232 + core_cluster_alert: core-cluster-alert {
233 + temperature = <85000>;
234 + hysteresis = <2000>;
235 + type = "passive";
236 + };
237 +
238 + core_cluster_crit: core-cluster-crit {
239 + temperature = <95000>;
240 + hysteresis = <2000>;
241 + type = "critical";
242 + };
243 + };
244 +
245 + cooling-maps {
246 + map0 {
247 + trip = <&core_cluster_alert>;
248 + cooling-device =
249 + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
250 + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
251 + <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
252 + <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
253 + <&cpu200 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
254 + <&cpu201 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
255 + <&cpu300 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
256 + <&cpu301 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
257 + <&cpu400 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
258 + <&cpu401 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
259 + <&cpu500 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
260 + <&cpu501 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
261 + <&cpu600 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
262 + <&cpu601 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
263 + <&cpu700 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
264 + <&cpu701 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
265 + };
266 + };
267 + };
268 + };
269 +
270 soc {
271 compatible = "simple-bus";
272 #address-cells = <2>;
273 @@ -689,6 +751,20 @@
274 status = "disabled";
275 };
276
277 + tmu: tmu@1f80000 {
278 + compatible = "fsl,qoriq-tmu";
279 + reg = <0x0 0x1f80000 0x0 0x10000>;
280 + interrupts = <0 23 0x4>;
281 + fsl,tmu-range = <0x800000E6 0x8001017D>;
282 + fsl,tmu-calibration =
283 + /* Calibration data group 1 */
284 + <0x00000000 0x00000035
285 + /* Calibration data group 2 */
286 + 0x00010001 0x00000154>;
287 + little-endian;
288 + #thermal-sensor-cells = <1>;
289 + };
290 +
291 uart0: serial@21c0000 {
292 compatible = "arm,sbsa-uart","arm,pl011";
293 reg = <0x0 0x21c0000 0x0 0x1000>;
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