target/linux/layerscape/patches-5.4/801-audio-0033-MLK-13946-3-ASoC-fsl_sai-fix-the-xMR-setting.patch

   1 From 9d00118e0ac420d3bf6e266a0fbfd28135cbadb8 Mon Sep 17 00:00:00 2001
   2 From: Shengjiu Wang <shengjiu.wang@nxp.com>
   3 Date: Thu, 12 Oct 2017 14:01:19 +0800
   4 Subject: [PATCH] MLK-13946-3: ASoC: fsl_sai: fix the xMR setting
   5
   6 When there is multi data line enabled, the xMR setting is
   7 wrong if according to the channel number. which should
   8 according to the slot number
   9
  10 Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
  11 ---
  12  sound/soc/fsl/fsl_sai.c | 28 ++++++++++++++++++++++++++--
  13  sound/soc/fsl/fsl_sai.h | 12 ++++++++++++
  14  2 files changed, 38 insertions(+), 2 deletions(-)
  15
  16 --- a/sound/soc/fsl/fsl_sai.c
  17 +++ b/sound/soc/fsl/fsl_sai.c
  18 @@ -80,7 +80,7 @@ static struct fsl_sai_soc_data fsl_sai_i
  19
  20  static struct fsl_sai_soc_data fsl_sai_imx8qm = {
  21         .imx = true,
  22 -       .dataline = 0x3,
  23 +       .dataline = 0xf,
  24         .fifos = 1,
  25         .fifo_depth = 64,
  26         .flags = 0,
  27 @@ -571,7 +571,7 @@ static int fsl_sai_hw_params(struct snd_
  28         regmap_update_bits(sai->regmap, FSL_SAI_xCR5(tx, offset),
  29                            FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  30                            FSL_SAI_CR5_FBT_MASK, val_cr5);
  31 -       regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << channels) - 1));
  32 +       regmap_write(sai->regmap, FSL_SAI_xMR(tx), ~0UL - ((1 << slots) - 1));
  33
  34         return 0;
  35  }
  36 @@ -858,11 +858,23 @@ static bool fsl_sai_readable_reg(struct
  37         switch (reg) {
  38         case FSL_SAI_TFR0:
  39         case FSL_SAI_TFR1:
  40 +       case FSL_SAI_TFR2:
  41 +       case FSL_SAI_TFR3:
  42 +       case FSL_SAI_TFR4:
  43 +       case FSL_SAI_TFR5:
  44 +       case FSL_SAI_TFR6:
  45 +       case FSL_SAI_TFR7:
  46         case FSL_SAI_TMR:
  47         case FSL_SAI_RDR0:
  48         case FSL_SAI_RDR1:
  49         case FSL_SAI_RFR0:
  50         case FSL_SAI_RFR1:
  51 +       case FSL_SAI_RFR2:
  52 +       case FSL_SAI_RFR3:
  53 +       case FSL_SAI_RFR4:
  54 +       case FSL_SAI_RFR5:
  55 +       case FSL_SAI_RFR6:
  56 +       case FSL_SAI_RFR7:
  57         case FSL_SAI_RMR:
  58                 return true;
  59         default:
  60 @@ -881,8 +893,20 @@ static bool fsl_sai_volatile_reg(struct
  61         switch (reg) {
  62         case FSL_SAI_TFR0:
  63         case FSL_SAI_TFR1:
  64 +       case FSL_SAI_TFR2:
  65 +       case FSL_SAI_TFR3:
  66 +       case FSL_SAI_TFR4:
  67 +       case FSL_SAI_TFR5:
  68 +       case FSL_SAI_TFR6:
  69 +       case FSL_SAI_TFR7:
  70         case FSL_SAI_RFR0:
  71         case FSL_SAI_RFR1:
  72 +       case FSL_SAI_RFR2:
  73 +       case FSL_SAI_RFR3:
  74 +       case FSL_SAI_RFR4:
  75 +       case FSL_SAI_RFR5:
  76 +       case FSL_SAI_RFR6:
  77 +       case FSL_SAI_RFR7:
  78         case FSL_SAI_RDR0:
  79         case FSL_SAI_RDR1:
  80                 return true;
  81 --- a/sound/soc/fsl/fsl_sai.h
  82 +++ b/sound/soc/fsl/fsl_sai.h
  83 @@ -24,6 +24,12 @@
  84  #define FSL_SAI_TDR1    0x24 /* SAI Transmit Data */
  85  #define FSL_SAI_TFR0    0x40 /* SAI Transmit FIFO */
  86  #define FSL_SAI_TFR1    0x44 /* SAI Transmit FIFO */
  87 +#define FSL_SAI_TFR2    0x48 /* SAI Transmit FIFO */
  88 +#define FSL_SAI_TFR3    0x4C /* SAI Transmit FIFO */
  89 +#define FSL_SAI_TFR4    0x50 /* SAI Transmit FIFO */
  90 +#define FSL_SAI_TFR5    0x54 /* SAI Transmit FIFO */
  91 +#define FSL_SAI_TFR6    0x58 /* SAI Transmit FIFO */
  92 +#define FSL_SAI_TFR7    0x5C /* SAI Transmit FIFO */
  93  #define FSL_SAI_TFR    0x40 /* SAI Transmit FIFO */
  94  #define FSL_SAI_TMR    0x60 /* SAI Transmit Mask */
  95  #define FSL_SAI_RCSR(offset) (0x80 + offset) /* SAI Receive Control */
  96 @@ -36,6 +42,12 @@
  97  #define FSL_SAI_RDR1    0xa4 /* SAI Receive Data */
  98  #define FSL_SAI_RFR0    0xc0 /* SAI Receive FIFO */
  99  #define FSL_SAI_RFR1    0xc4 /* SAI Receive FIFO */
 100 +#define FSL_SAI_RFR2    0xc8 /* SAI Receive FIFO */
 101 +#define FSL_SAI_RFR3    0xcc /* SAI Receive FIFO */
 102 +#define FSL_SAI_RFR4    0xd0 /* SAI Receive FIFO */
 103 +#define FSL_SAI_RFR5    0xd4 /* SAI Receive FIFO */
 104 +#define FSL_SAI_RFR6    0xd8 /* SAI Receive FIFO */
 105 +#define FSL_SAI_RFR7    0xdc /* SAI Receive FIFO */
 106  #define FSL_SAI_RMR    0xe0 /* SAI Receive Mask */
 107
 108  #define FSL_SAI_xCSR(tx, off)  (tx ? FSL_SAI_TCSR(off) : FSL_SAI_RCSR(off))