target/linux/layerscape/patches-5.4/806-dma-0006-MLK-15014-dma-fsl-edma-v3-clear-DONE-before-E_SG-ena.patch

   1 From 03691bf3038250def574c78576a8be39133923fd Mon Sep 17 00:00:00 2001
   2 From: Robin Gong <yibin.gong@nxp.com>
   3 Date: Tue, 6 Jun 2017 16:56:49 +0800
   4 Subject: [PATCH] MLK-15014 dma: fsl-edma-v3: clear DONE before E_SG enabled
   5
   6 Below described in RM, otherwise, channel error status(CHa_ES)
   7 may be triggered:
   8 The user must clear the CHa_CSR[DONE] bit before writing the
   9 TCDa_CSR[MAJORELINK] or TCDa_CSR[ESG] bits.
  10
  11 Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  12 (cherry picked from commit c4164d0a15306174056c6ff423ba2408dd901fcf)
  13 ---
  14  drivers/dma/fsl-edma-v3.c | 5 +++++
  15  1 file changed, 5 insertions(+)
  16
  17 --- a/drivers/dma/fsl-edma-v3.c
  18 +++ b/drivers/dma/fsl-edma-v3.c
  19 @@ -421,6 +421,11 @@ static void fsl_edma3_set_tcd_regs(struc
  20
  21         writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA);
  22
  23 +       /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */
  24 +       if ((EDMA_TCD_CSR_E_SG | le16_to_cpu(tcd->csr)) &&
  25 +               EDMA_CH_CSR_DONE | readl(addr + EDMA_CH_CSR))
  26 +               writel(EDMA_CH_CSR_DONE, addr + EDMA_CH_CSR);
  27 +
  28         writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR);
  29  }
  30