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layerscape: add patches-5.4
[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 812-pcie-0016-PCI-mobiveil-Add-the-EP-driver-support.patch
1 From 21d86ac5a6c0ede443676cb455e988adcc0e3762 Mon Sep 17 00:00:00 2001
2 From: Xiaowei Bao <xiaowei.bao@nxp.com>
3 Date: Sat, 5 Jan 2019 16:06:43 +0800
4 Subject: [PATCH] PCI: mobiveil: Add the EP driver support
5
6 Add the EP driver support for Mobiveil base on endpoint framework.
7
8 Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
9 [Zhiqiang: Correct the Copyright]
10 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
11 ---
12 MAINTAINERS | 1 +
13 drivers/pci/controller/mobiveil/Kconfig | 5 +
14 drivers/pci/controller/mobiveil/Makefile | 1 +
15 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c | 568 +++++++++++++++++++++
16 drivers/pci/controller/mobiveil/pcie-mobiveil.c | 99 +++-
17 drivers/pci/controller/mobiveil/pcie-mobiveil.h | 68 +++
18 6 files changed, 734 insertions(+), 8 deletions(-)
19 create mode 100644 drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
20
21 --- a/MAINTAINERS
22 +++ b/MAINTAINERS
23 @@ -12499,6 +12499,7 @@ F: drivers/ntb/hw/mscc/
24 PCI DRIVER FOR MOBIVEIL PCIE IP
25 M: Karthikeyan Mitran <m.karthikeyan@mobiveil.co.in>
26 M: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
27 +M: Xiaowei Bao <xiaowei.bao@nxp.com>
28 L: linux-pci@vger.kernel.org
29 S: Supported
30 F: Documentation/devicetree/bindings/pci/mobiveil-pcie.txt
31 --- a/drivers/pci/controller/mobiveil/Kconfig
32 +++ b/drivers/pci/controller/mobiveil/Kconfig
33 @@ -11,6 +11,11 @@ config PCIE_MOBIVEIL_HOST
34 depends on PCI_MSI_IRQ_DOMAIN
35 select PCIE_MOBIVEIL
36
37 +config PCIE_MOBIVEIL_EP
38 + bool
39 + depends on PCI_ENDPOINT
40 + select PCIE_MOBIVEIL
41 +
42 config PCIE_MOBIVEIL_PLAT
43 bool "Mobiveil AXI PCIe controller"
44 depends on ARCH_ZYNQMP || COMPILE_TEST
45 --- a/drivers/pci/controller/mobiveil/Makefile
46 +++ b/drivers/pci/controller/mobiveil/Makefile
47 @@ -1,5 +1,6 @@
48 # SPDX-License-Identifier: GPL-2.0
49 obj-$(CONFIG_PCIE_MOBIVEIL) += pcie-mobiveil.o
50 obj-$(CONFIG_PCIE_MOBIVEIL_HOST) += pcie-mobiveil-host.o
51 +obj-$(CONFIG_PCIE_MOBIVEIL_EP) += pcie-mobiveil-ep.o
52 obj-$(CONFIG_PCIE_MOBIVEIL_PLAT) += pcie-mobiveil-plat.o
53 obj-$(CONFIG_PCIE_LAYERSCAPE_GEN4) += pcie-layerscape-gen4.o
54 --- /dev/null
55 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil-ep.c
56 @@ -0,0 +1,568 @@
57 +// SPDX-License-Identifier: GPL-2.0
58 +/*
59 + * Mobiveil PCIe Endpoint controller driver
60 + *
61 + * Copyright 2019 NXP
62 + * Author: Xiaowei Bao <xiaowei.bao@nxp.com>
63 + */
64 +
65 +#include <linux/of.h>
66 +#include <linux/pci-epc.h>
67 +#include <linux/pci-epf.h>
68 +#include <linux/platform_device.h>
69 +#include "pcie-mobiveil.h"
70 +
71 +static void mobiveil_pcie_ep_func_select(struct mobiveil_pcie *pcie, u8 func_no)
72 +{
73 + u32 func_num;
74 +
75 + /*
76 + * select to access the config space of func_no by setting func_no
77 + * to FUNC_SEL_SHIFT bit of PAB_CTRL register.
78 + */
79 + func_num = csr_readl(pcie, PAB_CTRL);
80 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
81 + func_num |= (func_no & FUNC_SEL_MASK) << FUNC_SEL_SHIFT;
82 + csr_writel(pcie, func_num, PAB_CTRL);
83 +}
84 +
85 +static void mobiveil_pcie_ep_func_deselect(struct mobiveil_pcie *pcie)
86 +{
87 + u32 func_num;
88 +
89 + /*
90 + * clear the FUNC_SEL_SHIFT bits when access other registers except
91 + * config space register.
92 + */
93 + func_num = csr_readl(pcie, PAB_CTRL);
94 + func_num &= ~(FUNC_SEL_MASK << FUNC_SEL_SHIFT);
95 + csr_writel(pcie, func_num, PAB_CTRL);
96 +}
97 +
98 +static void __mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
99 +{
100 + csr_writel(pcie, bar, GPEX_BAR_SELECT);
101 + csr_writel(pcie, 0, GPEX_BAR_SIZE_LDW);
102 + csr_writel(pcie, 0, GPEX_BAR_SIZE_UDW);
103 +}
104 +
105 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pcie, u8 bar)
106 +{
107 + __mobiveil_pcie_ep_reset_bar(pcie, bar);
108 +}
109 +
110 +static u8 __mobiveil_pcie_ep_find_next_cap(struct mobiveil_pcie *pcie,
111 + u8 func_no, u8 cap_ptr, u8 cap)
112 +{
113 + u8 cap_id, next_cap_ptr;
114 + u16 reg;
115 +
116 + if (!cap_ptr)
117 + return 0;
118 +
119 + mobiveil_pcie_ep_func_select(pcie, func_no);
120 +
121 + reg = csr_readw(pcie, cap_ptr);
122 + cap_id = (reg & 0x00ff);
123 +
124 + mobiveil_pcie_ep_func_deselect(pcie);
125 +
126 + if (cap_id > PCI_CAP_ID_MAX)
127 + return 0;
128 +
129 + if (cap_id == cap)
130 + return cap_ptr;
131 +
132 + next_cap_ptr = (reg & 0xff00) >> 8;
133 + return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
134 + next_cap_ptr, cap);
135 +}
136 +
137 +static u8 mobiveil_pcie_ep_find_capability(struct mobiveil_pcie_ep *ep,
138 + u8 func_no, u8 cap)
139 +{
140 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
141 + u8 next_cap_ptr;
142 + u16 reg;
143 +
144 + mobiveil_pcie_ep_func_select(pcie, func_no);
145 +
146 + reg = csr_readw(pcie, PCI_CAPABILITY_LIST);
147 + next_cap_ptr = (reg & 0x00ff);
148 +
149 + mobiveil_pcie_ep_func_deselect(pcie);
150 +
151 + return __mobiveil_pcie_ep_find_next_cap(pcie, func_no,
152 + next_cap_ptr, cap);
153 +}
154 +
155 +static int mobiveil_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
156 + struct pci_epf_header *hdr)
157 +{
158 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
159 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
160 +
161 + mobiveil_pcie_ep_func_select(pcie, func_no);
162 +
163 + csr_writew(pcie, hdr->vendorid, PCI_VENDOR_ID);
164 + csr_writew(pcie, hdr->deviceid, PCI_DEVICE_ID);
165 + csr_writeb(pcie, hdr->revid, PCI_REVISION_ID);
166 + csr_writeb(pcie, hdr->progif_code, PCI_CLASS_PROG);
167 + csr_writew(pcie, hdr->subclass_code | hdr->baseclass_code << 8,
168 + PCI_CLASS_DEVICE);
169 + csr_writeb(pcie, hdr->cache_line_size, PCI_CACHE_LINE_SIZE);
170 + csr_writew(pcie, hdr->subsys_vendor_id, PCI_SUBSYSTEM_VENDOR_ID);
171 + csr_writew(pcie, hdr->subsys_id, PCI_SUBSYSTEM_ID);
172 + csr_writeb(pcie, hdr->interrupt_pin, PCI_INTERRUPT_PIN);
173 +
174 + mobiveil_pcie_ep_func_deselect(pcie);
175 +
176 + return 0;
177 +}
178 +
179 +static void mobiveil_pcie_ep_inbound_win(struct mobiveil_pcie_ep *ep,
180 + u8 func_no, enum pci_barno bar,
181 + dma_addr_t cpu_addr)
182 +{
183 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
184 +
185 + program_ib_windows_ep(pcie, func_no, bar, cpu_addr);
186 +}
187 +
188 +static int mobiveil_pcie_ep_outbound_win(struct mobiveil_pcie_ep *ep,
189 + phys_addr_t phys_addr,
190 + u64 pci_addr, u8 func_no,
191 + size_t size)
192 +{
193 + u32 free_win;
194 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
195 +
196 + free_win = find_first_zero_bit(ep->apio_wins_map, ep->apio_wins);
197 + if (free_win >= ep->apio_wins) {
198 + dev_err(&pcie->pdev->dev, "No free outbound window\n");
199 + return -EINVAL;
200 + }
201 +
202 + program_ob_windows_ep(pcie, func_no, free_win, phys_addr,
203 + pci_addr, MEM_WINDOW_TYPE, size);
204 +
205 + set_bit(free_win, ep->apio_wins_map);
206 + ep->apio_addr[free_win] = phys_addr;
207 +
208 + return 0;
209 +}
210 +
211 +static void mobiveil_pcie_ep_clear_bar(struct pci_epc *epc, u8 func_no,
212 + struct pci_epf_bar *epf_bar)
213 +{
214 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
215 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
216 + enum pci_barno bar = epf_bar->barno;
217 +
218 + if (bar < ep->bar_num) {
219 + __mobiveil_pcie_ep_reset_bar(pcie, func_no * ep->bar_num + bar);
220 +
221 + mobiveil_pcie_disable_ib_win_ep(pcie, func_no, bar);
222 + }
223 +}
224 +
225 +static int mobiveil_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no,
226 + struct pci_epf_bar *epf_bar)
227 +{
228 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
229 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
230 + enum pci_barno bar = epf_bar->barno;
231 + size_t size = epf_bar->size;
232 +
233 + if (bar < ep->bar_num) {
234 + mobiveil_pcie_ep_inbound_win(ep, func_no, bar,
235 + epf_bar->phys_addr);
236 +
237 + csr_writel(pcie, func_no * ep->bar_num + bar,
238 + GPEX_BAR_SELECT);
239 + csr_writel(pcie, lower_32_bits(~(size - 1)),
240 + GPEX_BAR_SIZE_LDW);
241 + csr_writel(pcie, upper_32_bits(~(size - 1)),
242 + GPEX_BAR_SIZE_UDW);
243 + }
244 +
245 + return 0;
246 +}
247 +
248 +static int mobiveil_pcie_find_index(struct mobiveil_pcie_ep *ep,
249 + phys_addr_t addr,
250 + u32 *atu_index)
251 +{
252 + u32 index;
253 +
254 + for (index = 0; index < ep->apio_wins; index++) {
255 + if (ep->apio_addr[index] != addr)
256 + continue;
257 + *atu_index = index;
258 + return 0;
259 + }
260 +
261 + return -EINVAL;
262 +}
263 +
264 +static void mobiveil_pcie_ep_unmap_addr(struct pci_epc *epc, u8 func_no,
265 + phys_addr_t addr)
266 +{
267 + int ret;
268 + u32 atu_index;
269 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
270 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
271 +
272 + ret = mobiveil_pcie_find_index(ep, addr, &atu_index);
273 + if (ret < 0)
274 + return;
275 +
276 + mobiveil_pcie_disable_ob_win(pcie, atu_index);
277 + clear_bit(atu_index, ep->apio_wins_map);
278 +}
279 +
280 +static int mobiveil_pcie_ep_map_addr(struct pci_epc *epc, u8 func_no,
281 + phys_addr_t addr,
282 + u64 pci_addr, size_t size)
283 +{
284 + int ret;
285 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
286 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
287 +
288 + ret = mobiveil_pcie_ep_outbound_win(ep, addr, pci_addr, func_no, size);
289 + if (ret) {
290 + dev_err(&pcie->pdev->dev, "Failed to enable address\n");
291 + return ret;
292 + }
293 +
294 + return 0;
295 +}
296 +
297 +static int mobiveil_pcie_ep_get_msi(struct pci_epc *epc, u8 func_no)
298 +{
299 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
300 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
301 + u32 val, reg;
302 + u8 msi_cap;
303 +
304 + msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
305 + PCI_CAP_ID_MSI);
306 + if (!msi_cap)
307 + return -EINVAL;
308 +
309 + mobiveil_pcie_ep_func_select(pcie, func_no);
310 +
311 + reg = msi_cap + PCI_MSI_FLAGS;
312 + val = csr_readw(pcie, reg);
313 +
314 + mobiveil_pcie_ep_func_deselect(pcie);
315 +
316 + if (!(val & PCI_MSI_FLAGS_ENABLE))
317 + return -EINVAL;
318 +
319 + val = (val & PCI_MSI_FLAGS_QSIZE) >> 4;
320 +
321 + return val;
322 +}
323 +
324 +static int mobiveil_pcie_ep_set_msi(struct pci_epc *epc,
325 + u8 func_no, u8 interrupts)
326 +{
327 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
328 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
329 + u32 val, reg;
330 + u8 msi_cap;
331 +
332 + msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
333 + PCI_CAP_ID_MSI);
334 + if (!msi_cap)
335 + return -EINVAL;
336 +
337 + mobiveil_pcie_ep_func_select(pcie, func_no);
338 +
339 + reg = msi_cap + PCI_MSI_FLAGS;
340 + val = csr_readw(pcie, reg);
341 + val &= ~PCI_MSI_FLAGS_QMASK;
342 + val |= (interrupts << 1) & PCI_MSI_FLAGS_QMASK;
343 + csr_writew(pcie, val, reg);
344 +
345 + mobiveil_pcie_ep_func_deselect(pcie);
346 +
347 + return 0;
348 +}
349 +
350 +static int mobiveil_pcie_ep_get_msix(struct pci_epc *epc, u8 func_no)
351 +{
352 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
353 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
354 + u32 val, reg;
355 + u8 msix_cap;
356 +
357 + msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
358 + PCI_CAP_ID_MSIX);
359 + if (!msix_cap)
360 + return -EINVAL;
361 +
362 + mobiveil_pcie_ep_func_select(pcie, func_no);
363 +
364 + reg = msix_cap + PCI_MSIX_FLAGS;
365 + val = csr_readw(pcie, reg);
366 +
367 + mobiveil_pcie_ep_func_deselect(pcie);
368 +
369 + if (!(val & PCI_MSIX_FLAGS_ENABLE))
370 + return -EINVAL;
371 +
372 + val &= PCI_MSIX_FLAGS_QSIZE;
373 +
374 + return val;
375 +}
376 +
377 +static int mobiveil_pcie_ep_set_msix(struct pci_epc *epc, u8 func_no,
378 + u16 interrupts)
379 +{
380 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
381 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
382 + u32 val, reg;
383 + u8 msix_cap;
384 +
385 + msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
386 + PCI_CAP_ID_MSIX);
387 + if (!msix_cap)
388 + return -EINVAL;
389 +
390 + mobiveil_pcie_ep_func_select(pcie, func_no);
391 +
392 + reg = msix_cap + PCI_MSIX_FLAGS;
393 + val = csr_readw(pcie, reg);
394 + val &= ~PCI_MSIX_FLAGS_QSIZE;
395 + val |= interrupts;
396 + csr_writew(pcie, val, reg);
397 +
398 + mobiveil_pcie_ep_func_deselect(pcie);
399 +
400 + return 0;
401 +}
402 +
403 +static int mobiveil_pcie_ep_raise_irq(struct pci_epc *epc, u8 func_no,
404 + enum pci_epc_irq_type type,
405 + u16 interrupt_num)
406 +{
407 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
408 +
409 + if (!ep->ops->raise_irq)
410 + return -EINVAL;
411 +
412 + return ep->ops->raise_irq(ep, func_no, type, interrupt_num);
413 +}
414 +
415 +static const struct pci_epc_features*
416 +mobiveil_pcie_ep_get_features(struct pci_epc *epc, u8 func_no)
417 +{
418 + struct mobiveil_pcie_ep *ep = epc_get_drvdata(epc);
419 +
420 + if (!ep->ops->get_features)
421 + return NULL;
422 +
423 + return ep->ops->get_features(ep);
424 +}
425 +
426 +static const struct pci_epc_ops epc_ops = {
427 + .write_header = mobiveil_pcie_ep_write_header,
428 + .set_bar = mobiveil_pcie_ep_set_bar,
429 + .clear_bar = mobiveil_pcie_ep_clear_bar,
430 + .map_addr = mobiveil_pcie_ep_map_addr,
431 + .unmap_addr = mobiveil_pcie_ep_unmap_addr,
432 + .set_msi = mobiveil_pcie_ep_set_msi,
433 + .get_msi = mobiveil_pcie_ep_get_msi,
434 + .set_msix = mobiveil_pcie_ep_set_msix,
435 + .get_msix = mobiveil_pcie_ep_get_msix,
436 + .raise_irq = mobiveil_pcie_ep_raise_irq,
437 + .get_features = mobiveil_pcie_ep_get_features,
438 +};
439 +
440 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no)
441 +{
442 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
443 +
444 + dev_err(&pcie->pdev->dev, "EP cannot trigger legacy IRQs\n");
445 +
446 + return -EINVAL;
447 +}
448 +
449 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
450 + u8 interrupt_num)
451 +{
452 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
453 + struct pci_epc *epc = ep->epc;
454 + u16 msg_ctrl, msg_data;
455 + u32 msg_addr_lower, msg_addr_upper, reg;
456 + u64 msg_addr;
457 + bool has_upper;
458 + int ret;
459 + u8 msi_cap;
460 +
461 + msi_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
462 + PCI_CAP_ID_MSI);
463 + if (!msi_cap)
464 + return -EINVAL;
465 +
466 + mobiveil_pcie_ep_func_select(pcie, func_no);
467 +
468 + reg = msi_cap + PCI_MSI_FLAGS;
469 + msg_ctrl = csr_readw(pcie, reg);
470 + has_upper = !!(msg_ctrl & PCI_MSI_FLAGS_64BIT);
471 + reg = msi_cap + PCI_MSI_ADDRESS_LO;
472 + msg_addr_lower = csr_readl(pcie, reg);
473 + if (has_upper) {
474 + reg = msi_cap + PCI_MSI_ADDRESS_HI;
475 + msg_addr_upper = csr_readl(pcie, reg);
476 + reg = msi_cap + PCI_MSI_DATA_64;
477 + msg_data = csr_readw(pcie, reg);
478 + } else {
479 + msg_addr_upper = 0;
480 + reg = msi_cap + PCI_MSI_DATA_32;
481 + msg_data = csr_readw(pcie, reg);
482 + }
483 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
484 +
485 + mobiveil_pcie_ep_func_deselect(pcie);
486 +
487 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
488 + msg_addr, epc->mem->page_size);
489 + if (ret)
490 + return ret;
491 +
492 + writel(msg_data | (interrupt_num - 1), ep->msi_mem);
493 +
494 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
495 +
496 + return 0;
497 +}
498 +
499 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
500 + u16 interrupt_num)
501 +{
502 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
503 + struct pci_epc *epc = ep->epc;
504 + u32 msg_addr_upper, msg_addr_lower;
505 + u32 msg_data;
506 + u64 msg_addr;
507 + u8 msix_cap;
508 + int ret;
509 +
510 + msix_cap = mobiveil_pcie_ep_find_capability(ep, func_no,
511 + PCI_CAP_ID_MSIX);
512 + if (!msix_cap)
513 + return -EINVAL;
514 +
515 + mobiveil_pcie_ep_func_deselect(pcie);
516 +
517 + msg_addr_lower = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
518 + PCI_MSIX_ENTRY_LOWER_ADDR +
519 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
520 + msg_addr_upper = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
521 + PCI_MSIX_ENTRY_UPPER_ADDR +
522 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
523 + msg_addr = ((u64) msg_addr_upper) << 32 | msg_addr_lower;
524 + msg_data = csr_readl(pcie, PAB_MSIX_TABLE_PBA_ACCESS +
525 + PCI_MSIX_ENTRY_DATA +
526 + (interrupt_num - 1) * PCI_MSIX_ENTRY_SIZE);
527 +
528 + ret = mobiveil_pcie_ep_map_addr(epc, func_no, ep->msi_mem_phys,
529 + msg_addr, epc->mem->page_size);
530 + if (ret)
531 + return ret;
532 +
533 + writel(msg_data, ep->msi_mem);
534 +
535 + mobiveil_pcie_ep_unmap_addr(epc, func_no, ep->msi_mem_phys);
536 +
537 + return 0;
538 +}
539 +
540 +void mobiveil_pcie_ep_exit(struct mobiveil_pcie_ep *ep)
541 +{
542 + struct pci_epc *epc = ep->epc;
543 +
544 + pci_epc_mem_free_addr(epc, ep->msi_mem_phys, ep->msi_mem,
545 + epc->mem->page_size);
546 +
547 + pci_epc_mem_exit(epc);
548 +}
549 +
550 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep)
551 +{
552 + int ret;
553 + void *addr;
554 + struct pci_epc *epc;
555 + struct mobiveil_pcie *pcie = to_mobiveil_pcie_from_ep(ep);
556 + struct device *dev = &pcie->pdev->dev;
557 + struct device_node *np = dev->of_node;
558 +
559 + if (!pcie->csr_axi_slave_base) {
560 + dev_err(dev, "csr_base is not populated\n");
561 + return -EINVAL;
562 + }
563 +
564 + ret = of_property_read_u32(np, "apio-wins", &ep->apio_wins);
565 + if (ret < 0) {
566 + dev_err(dev, "Unable to read apio-wins property\n");
567 + return ret;
568 + }
569 +
570 + if (ep->apio_wins > MAX_IATU_OUT) {
571 + dev_err(dev, "Invalid apio-wins\n");
572 + return -EINVAL;
573 + }
574 + ep->apio_wins_map = devm_kcalloc(dev,
575 + BITS_TO_LONGS(ep->apio_wins),
576 + sizeof(long),
577 + GFP_KERNEL);
578 + if (!ep->apio_wins_map)
579 + return -ENOMEM;
580 +
581 + addr = devm_kcalloc(dev, ep->apio_wins, sizeof(phys_addr_t),
582 + GFP_KERNEL);
583 + if (!addr)
584 + return -ENOMEM;
585 +
586 + ep->apio_addr = addr;
587 +
588 + mobiveil_pcie_enable_bridge_pio(pcie);
589 + mobiveil_pcie_enable_engine_apio(pcie);
590 + mobiveil_pcie_enable_engine_ppio(pcie);
591 + mobiveil_pcie_enable_msi_ep(pcie);
592 +
593 + epc = devm_pci_epc_create(dev, &epc_ops);
594 + if (IS_ERR(epc)) {
595 + dev_err(dev, "Failed to create epc device\n");
596 + return PTR_ERR(epc);
597 + }
598 +
599 + ep->epc = epc;
600 + epc_set_drvdata(epc, ep);
601 +
602 + ret = of_property_read_u8(np, "max-functions", &epc->max_functions);
603 + if (ret < 0)
604 + epc->max_functions = 1;
605 +
606 + if (ep->ops->ep_init)
607 + ep->ops->ep_init(ep);
608 +
609 + ret = __pci_epc_mem_init(epc, ep->phys_base, ep->addr_size,
610 + ep->page_size);
611 + if (ret < 0) {
612 + dev_err(dev, "Failed to initialize address space\n");
613 + return ret;
614 + }
615 +
616 + ep->msi_mem = pci_epc_mem_alloc_addr(epc, &ep->msi_mem_phys,
617 + epc->mem->page_size);
618 + if (!ep->msi_mem) {
619 + dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
620 + return -ENOMEM;
621 + }
622 +
623 + return 0;
624 +}
625 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c
626 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c
627 @@ -168,18 +168,12 @@ void program_ib_windows(struct mobiveil_
628 /*
629 * routine to program the outbound windows
630 */
631 -void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
632 - u64 pci_addr, u32 type, u64 size)
633 +void __program_ob_windows(struct mobiveil_pcie *pcie, u8 func_no, int win_num,
634 + u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
635 {
636 u32 value;
637 u64 size64 = ~(size - 1);
638
639 - if (win_num >= pcie->apio_wins) {
640 - dev_err(&pcie->pdev->dev,
641 - "ERROR: max outbound windows reached !\n");
642 - return;
643 - }
644 -
645 /*
646 * program Enable Bit to 1, Type Bit to (00) base 2, AXI Window Size Bit
647 * to 4 KB in PAB_AXI_AMAP_CTRL register
648 @@ -192,6 +186,7 @@ void program_ob_windows(struct mobiveil_
649
650 csr_writel(pcie, upper_32_bits(size64), PAB_EXT_AXI_AMAP_SIZE(win_num));
651
652 + csr_writel(pcie, func_no, PAB_AXI_AMAP_PCI_HDR_PARAM(win_num));
653 /*
654 * program AXI window base with appropriate value in
655 * PAB_AXI_AMAP_AXI_WIN0 register
656 @@ -205,10 +200,98 @@ void program_ob_windows(struct mobiveil_
657 PAB_AXI_AMAP_PEX_WIN_L(win_num));
658 csr_writel(pcie, upper_32_bits(pci_addr),
659 PAB_AXI_AMAP_PEX_WIN_H(win_num));
660 +}
661 +
662 +void program_ob_windows(struct mobiveil_pcie *pcie, int win_num, u64 cpu_addr,
663 + u64 pci_addr, u32 type, u64 size)
664 +{
665 + if (win_num >= pcie->apio_wins) {
666 + dev_err(&pcie->pdev->dev,
667 + "ERROR: max outbound windows reached !\n");
668 + return;
669 + }
670 +
671 + __program_ob_windows(pcie, 0, win_num, cpu_addr,
672 + pci_addr, type, size);
673
674 pcie->ob_wins_configured++;
675 }
676
677 +void program_ob_windows_ep(struct mobiveil_pcie *pcie, u8 func_no, int win_num,
678 + u64 cpu_addr, u64 pci_addr, u32 type, u64 size)
679 +{
680 + if (size & (size - 1))
681 + size = 1 << (1 + ilog2(size));
682 +
683 + __program_ob_windows(pcie, func_no, win_num, cpu_addr,
684 + pci_addr, type, size);
685 +}
686 +
687 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
688 + int bar, u64 phys)
689 +{
690 + csr_writel(pcie, upper_32_bits(phys),
691 + PAB_EXT_PEX_BAR_AMAP(func_no, bar));
692 + csr_writel(pcie, lower_32_bits(phys) | PEX_BAR_AMAP_EN,
693 + PAB_PEX_BAR_AMAP(func_no, bar));
694 +}
695 +
696 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pcie,
697 + u8 func_no, u8 bar)
698 +{
699 + u32 val;
700 +
701 + val = csr_readl(pcie, PAB_PEX_BAR_AMAP(func_no, bar));
702 + val &= ~(1 << 0);
703 + csr_writel(pcie, val, PAB_PEX_BAR_AMAP(func_no, bar));
704 +}
705 +
706 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num)
707 +{
708 + u32 val;
709 +
710 + val = csr_readl(pcie, PAB_AXI_AMAP_CTRL(win_num));
711 + val &= ~(1 << WIN_ENABLE_SHIFT);
712 + csr_writel(pcie, val, PAB_AXI_AMAP_CTRL(win_num));
713 +}
714 +
715 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pcie)
716 +{
717 + u32 val;
718 +
719 + val = csr_readl(pcie, PAB_CTRL);
720 + val |= 1 << AMBA_PIO_ENABLE_SHIFT;
721 + val |= 1 << PEX_PIO_ENABLE_SHIFT;
722 + csr_writel(pcie, val, PAB_CTRL);
723 +}
724 +
725 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pcie)
726 +{
727 + u32 val;
728 +
729 + val = csr_readl(pcie, PAB_AXI_PIO_CTRL);
730 + val |= APIO_EN_MASK;
731 + csr_writel(pcie, val, PAB_AXI_PIO_CTRL);
732 +}
733 +
734 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pcie)
735 +{
736 + u32 val;
737 +
738 + val = csr_readl(pcie, PAB_PEX_PIO_CTRL);
739 + val |= 1 << PIO_ENABLE_SHIFT;
740 + csr_writel(pcie, val, PAB_PEX_PIO_CTRL);
741 +}
742 +
743 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pcie)
744 +{
745 + u32 val;
746 +
747 + val = csr_readl(pcie, PAB_INTP_AMBA_MISC_ENB);
748 + val |= PAB_INTP_PAMR;
749 + csr_writel(pcie, val, PAB_INTP_AMBA_MISC_ENB);
750 +}
751 +
752 int mobiveil_bringup_link(struct mobiveil_pcie *pcie)
753 {
754 int retries;
755 --- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h
756 +++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h
757 @@ -15,8 +15,12 @@
758 #include <linux/pci.h>
759 #include <linux/irq.h>
760 #include <linux/msi.h>
761 +#include <linux/pci-epc.h>
762 +#include <linux/pci-epf.h>
763 +
764 #include "../../pci.h"
765
766 +#define MAX_IATU_OUT 256
767 /* register offsets and bit positions */
768
769 /*
770 @@ -42,6 +46,9 @@
771 #define PAGE_SEL_MASK 0x3f
772 #define PAGE_LO_MASK 0x3ff
773 #define PAGE_SEL_OFFSET_SHIFT 10
774 +#define FUNC_SEL_SHIFT 19
775 +#define FUNC_SEL_MASK 0x1ff
776 +#define MSI_SW_CTRL_EN BIT(29)
777
778 #define PAB_ACTIVITY_STAT 0x81c
779
780 @@ -52,6 +59,7 @@
781 #define PIO_ENABLE_SHIFT 0
782
783 #define PAB_INTP_AMBA_MISC_ENB 0x0b0c
784 +#define PAB_INTP_PAMR BIT(0)
785 #define PAB_INTP_AMBA_MISC_STAT 0x0b1c
786 #define PAB_INTP_RESET BIT(1)
787 #define PAB_INTP_MSI BIT(3)
788 @@ -72,6 +80,8 @@
789 #define WIN_TYPE_MASK 0x3
790 #define WIN_SIZE_MASK 0xfffffc00
791
792 +#define PAB_AXI_AMAP_PCI_HDR_PARAM(win) PAB_EXT_REG_ADDR(0x5ba0, win)
793 +
794 #define PAB_EXT_AXI_AMAP_SIZE(win) PAB_EXT_REG_ADDR(0xbaf0, win)
795
796 #define PAB_EXT_AXI_AMAP_AXI_WIN(win) PAB_EXT_REG_ADDR(0x80a0, win)
797 @@ -101,6 +111,18 @@
798 #define PAB_PEX_AMAP_PEX_WIN_L(win) PAB_REG_ADDR(0x4ba8, win)
799 #define PAB_PEX_AMAP_PEX_WIN_H(win) PAB_REG_ADDR(0x4bac, win)
800
801 +/* PPIO WINs EP mode */
802 +#define PAB_PEX_BAR_AMAP(func, bar) (0x1ba0 + 0x20 * func + 4 * bar)
803 +#define PAB_EXT_PEX_BAR_AMAP(func, bar) (0x84a0 + 0x20 * func + 4 * bar)
804 +#define PEX_BAR_AMAP_EN BIT(0)
805 +
806 +#define PAB_MSIX_TABLE_PBA_ACCESS 0xD000
807 +
808 +#define GPEX_BAR_ENABLE 0x4D4
809 +#define GPEX_BAR_SIZE_LDW 0x4D8
810 +#define GPEX_BAR_SIZE_UDW 0x4DC
811 +#define GPEX_BAR_SELECT 0x4E0
812 +
813 /* starting offset of INTX bits in status register */
814 #define PAB_INTX_START 5
815
816 @@ -138,6 +160,7 @@
817 ((off >> PAGE_SEL_OFFSET_SHIFT) & PAGE_SEL_MASK)
818
819 struct mobiveil_pcie;
820 +struct mobiveil_pcie_ep;
821
822 struct mobiveil_msi { /* MSI information */
823 struct mutex lock; /* protect bitmap variable */
824 @@ -170,6 +193,28 @@ struct mobiveil_pab_ops {
825 int (*host_init)(struct mobiveil_pcie *pcie);
826 };
827
828 +struct mobiveil_pcie_ep_ops {
829 + void (*ep_init)(struct mobiveil_pcie_ep *ep);
830 + int (*raise_irq)(struct mobiveil_pcie_ep *ep, u8 func_no,
831 + enum pci_epc_irq_type type, u16 interrupt_num);
832 + const struct pci_epc_features* (*get_features)
833 + (struct mobiveil_pcie_ep *ep);
834 +};
835 +
836 +struct mobiveil_pcie_ep {
837 + struct pci_epc *epc;
838 + const struct mobiveil_pcie_ep_ops *ops;
839 + phys_addr_t phys_base;
840 + size_t addr_size;
841 + size_t page_size;
842 + phys_addr_t *apio_addr;
843 + unsigned long *apio_wins_map;
844 + u32 apio_wins;
845 + void __iomem *msi_mem;
846 + phys_addr_t msi_mem_phys;
847 + u8 bar_num;
848 +};
849 +
850 struct mobiveil_pcie {
851 struct platform_device *pdev;
852 struct list_head *resources;
853 @@ -183,8 +228,12 @@ struct mobiveil_pcie {
854 const struct mobiveil_pab_ops *ops;
855 struct root_port rp;
856 struct pci_host_bridge *bridge;
857 + struct mobiveil_pcie_ep ep;
858 };
859
860 +#define to_mobiveil_pcie_from_ep(endpoint) \
861 + container_of((endpoint), struct mobiveil_pcie, ep)
862 +
863 int mobiveil_pcie_host_probe(struct mobiveil_pcie *pcie);
864 int mobiveil_host_init(struct mobiveil_pcie *pcie, bool reinit);
865 bool mobiveil_pcie_link_up(struct mobiveil_pcie *pcie);
866 @@ -226,4 +275,23 @@ static inline void csr_writeb(struct mob
867 csr_write(pcie, val, off, 0x1);
868 }
869
870 +void program_ib_windows_ep(struct mobiveil_pcie *pcie, u8 func_no,
871 + int bar, u64 phys);
872 +void program_ob_windows_ep(struct mobiveil_pcie *pcie, u8 func_num, int win_num,
873 + u64 cpu_addr, u64 pci_addr, u32 type, u64 size);
874 +void mobiveil_pcie_disable_ib_win_ep(struct mobiveil_pcie *pci,
875 + u8 func_no, u8 bar);
876 +void mobiveil_pcie_disable_ob_win(struct mobiveil_pcie *pcie, int win_num);
877 +int mobiveil_pcie_ep_init(struct mobiveil_pcie_ep *ep);
878 +int mobiveil_pcie_ep_raise_legacy_irq(struct mobiveil_pcie_ep *ep, u8 func_no);
879 +int mobiveil_pcie_ep_raise_msi_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
880 + u8 interrupt_num);
881 +int mobiveil_pcie_ep_raise_msix_irq(struct mobiveil_pcie_ep *ep, u8 func_no,
882 + u16 interrupt_num);
883 +void mobiveil_pcie_ep_reset_bar(struct mobiveil_pcie *pci, u8 bar);
884 +u8 mobiveil_pcie_ep_get_bar_num(struct mobiveil_pcie_ep *ep, u8 func_no);
885 +void mobiveil_pcie_enable_bridge_pio(struct mobiveil_pcie *pci);
886 +void mobiveil_pcie_enable_engine_apio(struct mobiveil_pcie *pci);
887 +void mobiveil_pcie_enable_engine_ppio(struct mobiveil_pcie *pci);
888 +void mobiveil_pcie_enable_msi_ep(struct mobiveil_pcie *pci);
889 #endif /* _PCIE_MOBIVEIL_H */
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