target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch

   1 From d0ff7a1bcfe886cab1a237895b08ac51ecfe10e7 Mon Sep 17 00:00:00 2001
   2 From: Tim Harvey <tharvey@gateworks.com>
   3 Date: Wed, 10 Apr 2019 08:00:47 -0700
   4 Subject: [PATCH 04/12] PCI: add quirk for Gateworks PLX PEX860x switch with
   5  GPIO PERST#
   6
   7 Gateworks boards use PLX PEX860x switches where downstream ports
   8 have their PERST# driven from the PEX GPIO.
   9
  10 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
  11 ---
  12  drivers/pci/quirks.c | 32 ++++++++++++++++++++++++++++++++
  13  1 file changed, 32 insertions(+)
  14
  15 diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
  16 index 419dda6..40e2ddb 100644
  17 --- a/drivers/pci/quirks.c
  18 +++ b/drivers/pci/quirks.c
  19 @@ -26,6 +26,7 @@
  20  #include <linux/ktime.h>
  21  #include <linux/mm.h>
  22  #include <linux/nvme.h>
  23 +#include <linux/of.h>
  24  #include <linux/platform_data/x86/apple.h>
  25  #include <linux/pm_runtime.h>
  26  #include <linux/switchtec.h>
  27 @@ -5216,3 +5217,34 @@ static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev)
  28  DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1,
  29                               PCI_CLASS_DISPLAY_VGA, 8,
  30                               quirk_reset_lenovo_thinkpad_p50_nvgpu);
  31 +
  32 +#ifdef CONFIG_PCI_HOST_THUNDER_PEM
  33 +/*
  34 + * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High
  35 + * as they are used for slots1-7 PERST#
  36 + */
  37 +static void newport_pciesw_early_fixup(struct pci_dev *dev)
  38 +{
  39 +       u32 dw;
  40 +
  41 +       if (!of_machine_is_compatible("gw,newport"))
  42 +               return;
  43 +
  44 +       if (dev->devfn != 0)
  45 +               return;
  46 +
  47 +       dev_info(&dev->dev, "de-asserting PERST#\n");
  48 +       pci_read_config_dword(dev, 0x62c, &dw);
  49 +       dw |= 0xaaa8; /* GPIO1-7 outputs */
  50 +       pci_write_config_dword(dev, 0x62c, dw);
  51 +
  52 +       pci_read_config_dword(dev, 0x644, &dw);
  53 +       dw |= 0xfe;   /* GPIO1-7 output high */
  54 +       pci_write_config_dword(dev, 0x644, dw);
  55 +
  56 +       msleep(100);
  57 +}
  58 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, newport_pciesw_early_fixup);
  59 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, newport_pciesw_early_fixup);
  60 +DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, newport_pciesw_early_fixup);
  61 +#endif /* CONFIG_PCI_HOST_THUNDER_PEM */
  62 --
  63 2.7.4
  64