target/linux/ramips/dts/rt3052_planex_mzk-wdpr.dts

   1 #include "rt3050.dtsi"
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4
   5 / {
   6         compatible = "planex,mzk-wdpr", "ralink,rt3052-soc";
   7         model = "Planex MZK-WDPR";
   8
   9         chosen {
  10                 bootargs = "console=ttyS0,115200";
  11         };
  12
  13         flash@1f000000 {
  14                 compatible = "cfi-flash";
  15                 reg = <0x1f000000 0x800000>;
  16
  17                 bank-width = <2>;
  18                 device-width = <2>;
  19
  20                 partitions {
  21                         compatible = "fixed-partitions";
  22                         #address-cells = <1>;
  23                         #size-cells = <1>;
  24
  25                         partition@0 {
  26                                 label = "u-boot";
  27                                 reg = <0x0 0x30000>;
  28                                 read-only;
  29                         };
  30
  31                         partition@30000 {
  32                                 label = "u-boot-env";
  33                                 reg = <0x30000 0x10000>;
  34                                 read-only;
  35                         };
  36
  37                         factory: partition@40000 {
  38                                 label = "factory";
  39                                 reg = <0x40000 0x10000>;
  40                                 read-only;
  41                         };
  42
  43                         partition@7f0000 {
  44                                 label = "Data3G";
  45                                 reg = <0x7f0000 0x10000>;
  46                                 read-only;
  47                         };
  48
  49                         partition@50000 {
  50                                 compatible = "denx,uimage";
  51                                 label = "firmware";
  52                                 reg = <0x50000 0x680000>;
  53                         };
  54                 };
  55         };
  56
  57         gpio-export {
  58                 compatible = "gpio-export";
  59
  60                 lcd_ctrl1 {
  61                         gpio-export,name = "lcd_ctrl1";
  62                         gpio-export,output = <0>;
  63                         gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
  64                 };
  65         };
  66 };
  67
  68 &state_default {
  69         gpio {
  70                 groups = "spi", "i2c", "jtag", "rgmii", "mdio", "uartf";
  71                 function = "gpio";
  72         };
  73 };
  74
  75 &ethernet {
  76         nvmem-cells = <&macaddr_factory_28>;
  77         nvmem-cell-names = "mac-address";
  78 };
  79
  80 &esw {
  81         mediatek,portmap = <0x2f>;
  82 };
  83
  84 &wmac {
  85         ralink,mtd-eeprom = <&factory 0x0>;
  86 };
  87
  88 &otg {
  89         status = "okay";
  90 };
  91
  92 &factory {
  93         compatible = "nvmem-cells";
  94         #address-cells = <1>;
  95         #size-cells = <1>;
  96
  97         macaddr_factory_28: macaddr@28 {
  98                 reg = <0x28 0x6>;
  99         };
 100 };