target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.c

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #include <linux/module.h>
  16 #include <linux/mii.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/of_device.h>
  21 #include <linux/of_irq.h>
  22
  23 #include <ralink_regs.h>
  24
  25 #include "mtk_eth_soc.h"
  26 #include "gsw_mt7620.h"
  27
  28 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg)
  29 {
  30         iowrite32(val, gsw->base + reg);
  31 }
  32
  33 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg)
  34 {
  35         return ioread32(gsw->base + reg);
  36 }
  37
  38 static irqreturn_t gsw_interrupt_mt7620(int irq, void *_priv)
  39 {
  40         struct fe_priv *priv = (struct fe_priv *)_priv;
  41         struct mt7620_gsw *gsw = (struct mt7620_gsw *)priv->soc->swpriv;
  42         u32 status;
  43         int i, max = (gsw->port4 == PORT4_EPHY) ? (4) : (3);
  44
  45         status = mtk_switch_r32(gsw, GSW_REG_ISR);
  46         if (status & PORT_IRQ_ST_CHG)
  47                 for (i = 0; i <= max; i++) {
  48                         u32 status = mtk_switch_r32(gsw, GSW_REG_PORT_STATUS(i));
  49                         int link = status & 0x1;
  50
  51                         if (link != priv->link[i])
  52                                 mt7620_print_link_state(priv, i, link,
  53                                                         (status >> 2) & 3,
  54                                                         (status & 0x2));
  55
  56                         priv->link[i] = link;
  57                 }
  58         mt7620_handle_carrier(priv);
  59         mtk_switch_w32(gsw, status, GSW_REG_ISR);
  60
  61         return IRQ_HANDLED;
  62 }
  63
  64 static int mt7620_mdio_mode(struct device_node *eth_node)
  65 {
  66         struct device_node *phy_node, *mdiobus_node;
  67         const __be32 *id;
  68         int ret = 0;
  69
  70         mdiobus_node = of_get_child_by_name(eth_node, "mdio-bus");
  71
  72         if (mdiobus_node) {
  73                 if (of_property_read_bool(mdiobus_node, "mediatek,mdio-mode"))
  74                         ret = 1;
  75
  76                 for_each_child_of_node(mdiobus_node, phy_node) {
  77                         id = of_get_property(phy_node, "reg", NULL);
  78                         if (id && (be32_to_cpu(*id) == 0x1f))
  79                                 ret = 1;
  80                 }
  81
  82                 of_node_put(mdiobus_node);
  83         }
  84
  85         return ret;
  86 }
  87
  88 static void mt7620_hw_init(struct mt7620_gsw *gsw, int mdio_mode)
  89 {
  90         u32 i;
  91         u32 val;
  92         u32 is_BGA = (rt_sysc_r32(0x0c) >> 16) & 1;
  93
  94         rt_sysc_w32(rt_sysc_r32(SYSC_REG_CFG1) | BIT(8), SYSC_REG_CFG1);
  95         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_CKGCR) & ~(0x3 << 4), GSW_REG_CKGCR);
  96
  97         /* Enable MIB stats */
  98         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_MIB_CNT_EN) | (1 << 1), GSW_REG_MIB_CNT_EN);
  99
 100         if (mdio_mode) {
 101                 u32 val;
 102
 103                 /* turn off ephy and set phy base addr to 12 */
 104                 mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
 105                         (0x1f << 24) | (0xc << 16),
 106                         GSW_REG_GPC1);
 107
 108                 /* set MT7530 central align */
 109                 val = mt7530_mdio_r32(gsw, 0x7830);
 110                 val &= ~BIT(0);
 111                 val |= BIT(1);
 112                 mt7530_mdio_w32(gsw, 0x7830, val);
 113
 114                 val = mt7530_mdio_r32(gsw, 0x7a40);
 115                 val &= ~BIT(30);
 116                 mt7530_mdio_w32(gsw, 0x7a40, val);
 117
 118                 mt7530_mdio_w32(gsw, 0x7a78, 0x855);
 119         } else {
 120
 121                 if (gsw->ephy_base) {
 122                         /* set phy base addr to ephy_base */
 123                         mtk_switch_w32(gsw, mtk_switch_r32(gsw, GSW_REG_GPC1) |
 124                                 (gsw->ephy_base << 16),
 125                                 GSW_REG_GPC1);
 126                         fe_reset(BIT(24)); /* Resets the Ethernet PHY block. */
 127                 }
 128
 129                 /* global page 4 */
 130                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x4000);
 131
 132                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x7444);
 133                 if (is_BGA)
 134                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0114);
 135                 else
 136                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 19, 0x0117);
 137
 138                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x10cf);
 139                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x6212);
 140                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0777);
 141                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 29, 0x4000);
 142                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 28, 0xc077);
 143                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0000);
 144
 145                 /* global page 3 */
 146                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x3000);
 147                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0x4838);
 148
 149                 /* global page 2 */
 150                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x2000);
 151                 if (is_BGA) {
 152                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0515);
 153                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0053);
 154                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
 155                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aaf);
 156                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x0fad);
 157                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fc1);
 158                 } else {
 159                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 21, 0x0517);
 160                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 22, 0x0fd2);
 161                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 23, 0x00bf);
 162                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 24, 0x0aab);
 163                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 25, 0x00ae);
 164                         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 26, 0x0fff);
 165                 }
 166                 /* global page 1 */
 167                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x1000);
 168                 _mt7620_mii_write(gsw, gsw->ephy_base + 1, 17, 0xe7f8);
 169
 170                 /* turn on all PHYs */
 171                 for (i = 0; i <= 4; i++) {
 172                         val = _mt7620_mii_read(gsw, gsw->ephy_base + i, MII_BMCR);
 173                         val &= ~BMCR_PDOWN;
 174                         val |= BMCR_ANRESTART | BMCR_ANENABLE | BMCR_SPEED100;
 175                         _mt7620_mii_write(gsw, gsw->ephy_base + i, MII_BMCR, val);
 176                 }
 177         }
 178
 179         /* global page 0 */
 180         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0x8000);
 181         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 30, 0xa000);
 182         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 30, 0xa000);
 183         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 30, 0xa000);
 184         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 30, 0xa000);
 185
 186         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 4, 0x05e1);
 187         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 4, 0x05e1);
 188         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 4, 0x05e1);
 189         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 4, 0x05e1);
 190
 191         /* global page 2 */
 192         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 31, 0xa000);
 193         _mt7620_mii_write(gsw, gsw->ephy_base + 0, 16, 0x1111);
 194         _mt7620_mii_write(gsw, gsw->ephy_base + 1, 16, 0x1010);
 195         _mt7620_mii_write(gsw, gsw->ephy_base + 2, 16, 0x1515);
 196         _mt7620_mii_write(gsw, gsw->ephy_base + 3, 16, 0x0f0f);
 197
 198         /* CPU Port6 Force Link 1G, FC ON */
 199         mtk_switch_w32(gsw, 0x5e33b, GSW_REG_PORT_PMCR(6));
 200
 201         /* Set Port 6 as CPU Port */
 202         mtk_switch_w32(gsw, 0x7f7f7fe0, 0x0010);
 203
 204         /* setup port 4 */
 205         if (gsw->port4 == PORT4_EPHY) {
 206                 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 207
 208                 val |= 3 << 14;
 209                 rt_sysc_w32(val, SYSC_REG_CFG1);
 210                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 30, 0xa000);
 211                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 4, 0x05e1);
 212                 _mt7620_mii_write(gsw, gsw->ephy_base + 4, 16, 0x1313);
 213                 pr_info("gsw: setting port4 to ephy mode\n");
 214         } else if (!mdio_mode) {
 215                 u32 val = rt_sysc_r32(SYSC_REG_CFG1);
 216
 217                 val &= ~(3 << 14);
 218                 rt_sysc_w32(val, SYSC_REG_CFG1);
 219                 pr_info("gsw: setting port4 to gmac mode\n");
 220         }
 221 }
 222
 223 static const struct of_device_id mediatek_gsw_match[] = {
 224         { .compatible = "mediatek,mt7620-gsw" },
 225         {},
 226 };
 227 MODULE_DEVICE_TABLE(of, mediatek_gsw_match);
 228
 229 int mtk_gsw_init(struct fe_priv *priv)
 230 {
 231         struct device_node *np = priv->switch_np;
 232         struct platform_device *pdev = of_find_device_by_node(np);
 233         struct mt7620_gsw *gsw;
 234
 235         if (!pdev)
 236                 return -ENODEV;
 237
 238         if (!of_device_is_compatible(np, mediatek_gsw_match->compatible))
 239                 return -EINVAL;
 240
 241         gsw = platform_get_drvdata(pdev);
 242         priv->soc->swpriv = gsw;
 243
 244         mt7620_hw_init(gsw, mt7620_mdio_mode(priv->dev->of_node));
 245
 246         if (gsw->irq) {
 247                 request_irq(gsw->irq, gsw_interrupt_mt7620, 0,
 248                             "gsw", priv);
 249                 mtk_switch_w32(gsw, ~PORT_IRQ_ST_CHG, GSW_REG_IMR);
 250         }
 251
 252         return 0;
 253 }
 254
 255 static int mt7620_gsw_probe(struct platform_device *pdev)
 256 {
 257         struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 258         const char *port4 = NULL;
 259         struct mt7620_gsw *gsw;
 260         struct device_node *np = pdev->dev.of_node;
 261         u16 val;
 262
 263         gsw = devm_kzalloc(&pdev->dev, sizeof(struct mt7620_gsw), GFP_KERNEL);
 264         if (!gsw)
 265                 return -ENOMEM;
 266
 267         gsw->base = devm_ioremap_resource(&pdev->dev, res);
 268         if (IS_ERR(gsw->base))
 269                 return PTR_ERR(gsw->base);
 270
 271         gsw->dev = &pdev->dev;
 272
 273         of_property_read_string(np, "mediatek,port4", &port4);
 274         if (port4 && !strcmp(port4, "ephy"))
 275                 gsw->port4 = PORT4_EPHY;
 276         else if (port4 && !strcmp(port4, "gmac"))
 277                 gsw->port4 = PORT4_EXT;
 278         else
 279                 gsw->port4 = PORT4_EPHY;
 280
 281         if (of_property_read_u16(np, "mediatek,ephy-base-address", &val) == 0)
 282                 gsw->ephy_base = val;
 283         else
 284                 gsw->ephy_base = 0;
 285
 286         gsw->irq = platform_get_irq(pdev, 0);
 287
 288         platform_set_drvdata(pdev, gsw);
 289
 290         return 0;
 291 }
 292
 293 static int mt7620_gsw_remove(struct platform_device *pdev)
 294 {
 295         platform_set_drvdata(pdev, NULL);
 296
 297         return 0;
 298 }
 299
 300 static struct platform_driver gsw_driver = {
 301         .probe = mt7620_gsw_probe,
 302         .remove = mt7620_gsw_remove,
 303         .driver = {
 304                 .name = "mt7620-gsw",
 305                 .owner = THIS_MODULE,
 306                 .of_match_table = mediatek_gsw_match,
 307         },
 308 };
 309
 310 module_platform_driver(gsw_driver);
 311
 312 MODULE_LICENSE("GPL");
 313 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
 314 MODULE_DESCRIPTION("GBit switch driver for Mediatek MT7620 SoC");
 315 MODULE_VERSION(MTK_FE_DRV_VERSION);