target/linux/ramips/files/drivers/net/ethernet/ralink/gsw_mt7620.h

   1 /*   This program is free software; you can redistribute it and/or modify
   2  *   it under the terms of the GNU General Public License as published by
   3  *   the Free Software Foundation; version 2 of the License
   4  *
   5  *   This program is distributed in the hope that it will be useful,
   6  *   but WITHOUT ANY WARRANTY; without even the implied warranty of
   7  *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   8  *   GNU General Public License for more details.
   9  *
  10  *   Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
  11  *   Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
  12  *   Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
  13  */
  14
  15 #ifndef _RALINK_GSW_MT7620_H__
  16 #define _RALINK_GSW_MT7620_H__
  17
  18 #define GSW_REG_PHY_TIMEOUT     (5 * HZ)
  19
  20 #define MT7620A_GSW_REG_PIAC    0x7004
  21
  22 #define GSW_NUM_VLANS           16
  23 #define GSW_NUM_VIDS            4096
  24 #define GSW_NUM_PORTS           7
  25 #define GSW_PORT6               6
  26
  27 #define GSW_MDIO_ACCESS         BIT(31)
  28 #define GSW_MDIO_READ           BIT(19)
  29 #define GSW_MDIO_WRITE          BIT(18)
  30 #define GSW_MDIO_START          BIT(16)
  31 #define GSW_MDIO_ADDR_SHIFT     20
  32 #define GSW_MDIO_REG_SHIFT      25
  33
  34 #define GSW_REG_MIB_CNT_EN      0x4000
  35
  36 #define GSW_REG_PORT_PMCR(x)    (0x3000 + (x * 0x100))
  37 #define GSW_REG_PORT_STATUS(x)  (0x3008 + (x * 0x100))
  38 #define GSW_REG_SMACCR0         0x3fE4
  39 #define GSW_REG_SMACCR1         0x3fE8
  40 #define GSW_REG_CKGCR           0x3ff0
  41
  42 #define GSW_REG_IMR             0x7008
  43 #define GSW_REG_ISR             0x700c
  44 #define GSW_REG_GPC1            0x7014
  45 #define GSW_REG_GPC2            0x701c
  46
  47 #define GSW_REG_GPCx_TXDELAY    BIT(3)
  48 #define GSW_REG_GPCx_RXDELAY    BIT(2)
  49
  50 #define GSW_REG_MAC_P0_MCR      0x100
  51 #define GSW_REG_MAC_P1_MCR      0x200
  52
  53 // Global MAC control register
  54 #define GSW_REG_GMACCR          0x30E0
  55
  56 #define SYSC_REG_CHIP_REV_ID    0x0c
  57 #define SYSC_REG_CFG1           0x14
  58 #define PCIE_RC_MODE            BIT(8)
  59 #define SYSC_PAD_RGMII2_MDIO    0x58
  60 #define SYSC_GPIO_MODE          0x60
  61
  62 #define PORT_IRQ_ST_CHG         0x7f
  63
  64 #define ESW_PHY_POLLING         0x7000
  65
  66 #define PMCR_IPG                BIT(18)
  67 #define PMCR_MAC_MODE           BIT(16)
  68 #define PMCR_FORCE              BIT(15)
  69 #define PMCR_TX_EN              BIT(14)
  70 #define PMCR_RX_EN              BIT(13)
  71 #define PMCR_BACKOFF            BIT(9)
  72 #define PMCR_BACKPRES           BIT(8)
  73 #define PMCR_RX_FC              BIT(5)
  74 #define PMCR_TX_FC              BIT(4)
  75 #define PMCR_SPEED(_x)          (_x << 2)
  76 #define PMCR_DUPLEX             BIT(1)
  77 #define PMCR_LINK               BIT(0)
  78
  79 #define PHY_AN_EN               BIT(31)
  80 #define PHY_PRE_EN              BIT(30)
  81 #define PMY_MDC_CONF(_x)        ((_x & 0x3f) << 24)
  82
  83
  84 enum {
  85         /* Global attributes. */
  86         GSW_ATTR_ENABLE_VLAN,
  87         /* Port attributes. */
  88         GSW_ATTR_PORT_UNTAG,
  89 };
  90
  91 struct mt7620_gsw {
  92         struct device           *dev;
  93         void __iomem            *base;
  94         int                     irq;
  95         bool                    ephy_disable;
  96         bool                    port4_ephy;
  97         unsigned long int       autopoll;
  98         u16                     ephy_base;
  99 };
 100
 101 void mtk_switch_w32(struct mt7620_gsw *gsw, u32 val, unsigned reg);
 102 u32 mtk_switch_r32(struct mt7620_gsw *gsw, unsigned reg);
 103 int mtk_gsw_init(struct fe_priv *priv);
 104
 105 int mt7620_mdio_write(struct mii_bus *bus, int phy_addr, int phy_reg, u16 val);
 106 int mt7620_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg);
 107 void mt7620_mdio_link_adjust(struct fe_priv *priv, int port);
 108 int mt7620_has_carrier(struct fe_priv *priv);
 109 void mt7620_print_link_state(struct fe_priv *priv, int port, int link,
 110                              int speed, int duplex);
 111
 112 void mt7530_mdio_w32(struct mt7620_gsw *gsw, u32 reg, u32 val);
 113 u32 mt7530_mdio_r32(struct mt7620_gsw *gsw, u32 reg);
 114
 115 u32 _mt7620_mii_write(struct mt7620_gsw *gsw, u32 phy_addr,
 116                              u32 phy_register, u32 write_data);
 117 u32 _mt7620_mii_read(struct mt7620_gsw *gsw, int phy_addr, int phy_reg);
 118 void mt7620_handle_carrier(struct fe_priv *priv);
 119
 120 #endif