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[openwrt/staging/wigyori.git] / target / linux / ramips / files / drivers / net / ethernet / ralink / mtk_eth_soc.h
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2015 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2015 Felix Fietkau <nbd@nbd.name>
12 * Copyright (C) 2013-2015 Michael Lee <igvtee@gmail.com>
13 */
14
15 #ifndef FE_ETH_H
16 #define FE_ETH_H
17
18 #include <linux/mii.h>
19 #include <linux/interrupt.h>
20 #include <linux/netdevice.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/phy.h>
23 #include <linux/ethtool.h>
24 #include <linux/version.h>
25
26 enum fe_reg {
27 FE_REG_PDMA_GLO_CFG = 0,
28 FE_REG_PDMA_RST_CFG,
29 FE_REG_DLY_INT_CFG,
30 FE_REG_TX_BASE_PTR0,
31 FE_REG_TX_MAX_CNT0,
32 FE_REG_TX_CTX_IDX0,
33 FE_REG_TX_DTX_IDX0,
34 FE_REG_RX_BASE_PTR0,
35 FE_REG_RX_MAX_CNT0,
36 FE_REG_RX_CALC_IDX0,
37 FE_REG_RX_DRX_IDX0,
38 FE_REG_FE_INT_ENABLE,
39 FE_REG_FE_INT_STATUS,
40 FE_REG_FE_DMA_VID_BASE,
41 FE_REG_FE_COUNTER_BASE,
42 FE_REG_FE_RST_GL,
43 FE_REG_FE_INT_STATUS2,
44 FE_REG_COUNT
45 };
46
47 enum fe_work_flag {
48 FE_FLAG_RESET_PENDING,
49 FE_FLAG_MAX
50 };
51
52 #define MTK_FE_DRV_VERSION "0.2"
53
54 /* power of 2 to let NEXT_TX_DESP_IDX work */
55 #define NUM_DMA_DESC BIT(10)
56 #define MAX_DMA_DESC 0xfff
57
58 #define FE_DELAY_EN_INT 0x80
59 #define FE_DELAY_MAX_INT 0x04
60 #define FE_DELAY_MAX_TOUT 0x04
61 #define FE_DELAY_TIME 20
62 #define FE_DELAY_CHAN (((FE_DELAY_EN_INT | FE_DELAY_MAX_INT) << 8) | \
63 FE_DELAY_MAX_TOUT)
64 #define FE_DELAY_INIT ((FE_DELAY_CHAN << 16) | FE_DELAY_CHAN)
65 #define FE_PSE_FQFC_CFG_INIT 0x80504000
66 #define FE_PSE_FQFC_CFG_256Q 0xff908000
67
68 /* interrupt bits */
69 #define FE_CNT_PPE_AF BIT(31)
70 #define FE_CNT_GDM_AF BIT(29)
71 #define FE_PSE_P2_FC BIT(26)
72 #define FE_PSE_BUF_DROP BIT(24)
73 #define FE_GDM_OTHER_DROP BIT(23)
74 #define FE_PSE_P1_FC BIT(22)
75 #define FE_PSE_P0_FC BIT(21)
76 #define FE_PSE_FQ_EMPTY BIT(20)
77 #define FE_GE1_STA_CHG BIT(18)
78 #define FE_TX_COHERENT BIT(17)
79 #define FE_RX_COHERENT BIT(16)
80 #define FE_TX_DONE_INT3 BIT(11)
81 #define FE_TX_DONE_INT2 BIT(10)
82 #define FE_TX_DONE_INT1 BIT(9)
83 #define FE_TX_DONE_INT0 BIT(8)
84 #define FE_RX_DONE_INT0 BIT(2)
85 #define FE_TX_DLY_INT BIT(1)
86 #define FE_RX_DLY_INT BIT(0)
87
88 #define FE_RX_DONE_INT FE_RX_DONE_INT0
89 #define FE_TX_DONE_INT (FE_TX_DONE_INT0 | FE_TX_DONE_INT1 | \
90 FE_TX_DONE_INT2 | FE_TX_DONE_INT3)
91
92 #define RT5350_RX_DLY_INT BIT(30)
93 #define RT5350_TX_DLY_INT BIT(28)
94 #define RT5350_RX_DONE_INT1 BIT(17)
95 #define RT5350_RX_DONE_INT0 BIT(16)
96 #define RT5350_TX_DONE_INT3 BIT(3)
97 #define RT5350_TX_DONE_INT2 BIT(2)
98 #define RT5350_TX_DONE_INT1 BIT(1)
99 #define RT5350_TX_DONE_INT0 BIT(0)
100
101 #define RT5350_RX_DONE_INT (RT5350_RX_DONE_INT0 | RT5350_RX_DONE_INT1)
102 #define RT5350_TX_DONE_INT (RT5350_TX_DONE_INT0 | RT5350_TX_DONE_INT1 | \
103 RT5350_TX_DONE_INT2 | RT5350_TX_DONE_INT3)
104
105 /* registers */
106 #define FE_FE_OFFSET 0x0000
107 #define FE_GDMA_OFFSET 0x0020
108 #define FE_PSE_OFFSET 0x0040
109 #define FE_GDMA2_OFFSET 0x0060
110 #define FE_CDMA_OFFSET 0x0080
111 #define FE_DMA_VID0 0x00a8
112 #define FE_PDMA_OFFSET 0x0100
113 #define FE_PPE_OFFSET 0x0200
114 #define FE_CMTABLE_OFFSET 0x0400
115 #define FE_POLICYTABLE_OFFSET 0x1000
116
117 #define RT5350_PDMA_OFFSET 0x0800
118 #define RT5350_SDM_OFFSET 0x0c00
119
120 #define FE_MDIO_ACCESS (FE_FE_OFFSET + 0x00)
121 #define FE_MDIO_CFG (FE_FE_OFFSET + 0x04)
122 #define FE_FE_GLO_CFG (FE_FE_OFFSET + 0x08)
123 #define FE_FE_RST_GL (FE_FE_OFFSET + 0x0C)
124 #define FE_FE_INT_STATUS (FE_FE_OFFSET + 0x10)
125 #define FE_FE_INT_ENABLE (FE_FE_OFFSET + 0x14)
126 #define FE_MDIO_CFG2 (FE_FE_OFFSET + 0x18)
127 #define FE_FOC_TS_T (FE_FE_OFFSET + 0x1C)
128
129 #define FE_GDMA1_FWD_CFG (FE_GDMA_OFFSET + 0x00)
130 #define FE_GDMA1_SCH_CFG (FE_GDMA_OFFSET + 0x04)
131 #define FE_GDMA1_SHPR_CFG (FE_GDMA_OFFSET + 0x08)
132 #define FE_GDMA1_MAC_ADRL (FE_GDMA_OFFSET + 0x0C)
133 #define FE_GDMA1_MAC_ADRH (FE_GDMA_OFFSET + 0x10)
134
135 #define FE_GDMA2_FWD_CFG (FE_GDMA2_OFFSET + 0x00)
136 #define FE_GDMA2_SCH_CFG (FE_GDMA2_OFFSET + 0x04)
137 #define FE_GDMA2_SHPR_CFG (FE_GDMA2_OFFSET + 0x08)
138 #define FE_GDMA2_MAC_ADRL (FE_GDMA2_OFFSET + 0x0C)
139 #define FE_GDMA2_MAC_ADRH (FE_GDMA2_OFFSET + 0x10)
140
141 #define FE_PSE_FQ_CFG (FE_PSE_OFFSET + 0x00)
142 #define FE_CDMA_FC_CFG (FE_PSE_OFFSET + 0x04)
143 #define FE_GDMA1_FC_CFG (FE_PSE_OFFSET + 0x08)
144 #define FE_GDMA2_FC_CFG (FE_PSE_OFFSET + 0x0C)
145
146 #define FE_CDMA_CSG_CFG (FE_CDMA_OFFSET + 0x00)
147 #define FE_CDMA_SCH_CFG (FE_CDMA_OFFSET + 0x04)
148
149 #ifdef CONFIG_SOC_MT7621
150 #define MT7620A_GDMA_OFFSET 0x0500
151 #else
152 #define MT7620A_GDMA_OFFSET 0x0600
153 #endif
154 #define MT7620A_GDMA1_FWD_CFG (MT7620A_GDMA_OFFSET + 0x00)
155 #define MT7620A_FE_GDMA1_SCH_CFG (MT7620A_GDMA_OFFSET + 0x04)
156 #define MT7620A_FE_GDMA1_SHPR_CFG (MT7620A_GDMA_OFFSET + 0x08)
157 #define MT7620A_FE_GDMA1_MAC_ADRL (MT7620A_GDMA_OFFSET + 0x0C)
158 #define MT7620A_FE_GDMA1_MAC_ADRH (MT7620A_GDMA_OFFSET + 0x10)
159
160 #define MT7620A_RESET_EPHY BIT(24)
161
162 #define RT5350_TX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x00)
163 #define RT5350_TX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x04)
164 #define RT5350_TX_CTX_IDX0 (RT5350_PDMA_OFFSET + 0x08)
165 #define RT5350_TX_DTX_IDX0 (RT5350_PDMA_OFFSET + 0x0C)
166 #define RT5350_TX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x10)
167 #define RT5350_TX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x14)
168 #define RT5350_TX_CTX_IDX1 (RT5350_PDMA_OFFSET + 0x18)
169 #define RT5350_TX_DTX_IDX1 (RT5350_PDMA_OFFSET + 0x1C)
170 #define RT5350_TX_BASE_PTR2 (RT5350_PDMA_OFFSET + 0x20)
171 #define RT5350_TX_MAX_CNT2 (RT5350_PDMA_OFFSET + 0x24)
172 #define RT5350_TX_CTX_IDX2 (RT5350_PDMA_OFFSET + 0x28)
173 #define RT5350_TX_DTX_IDX2 (RT5350_PDMA_OFFSET + 0x2C)
174 #define RT5350_TX_BASE_PTR3 (RT5350_PDMA_OFFSET + 0x30)
175 #define RT5350_TX_MAX_CNT3 (RT5350_PDMA_OFFSET + 0x34)
176 #define RT5350_TX_CTX_IDX3 (RT5350_PDMA_OFFSET + 0x38)
177 #define RT5350_TX_DTX_IDX3 (RT5350_PDMA_OFFSET + 0x3C)
178 #define RT5350_RX_BASE_PTR0 (RT5350_PDMA_OFFSET + 0x100)
179 #define RT5350_RX_MAX_CNT0 (RT5350_PDMA_OFFSET + 0x104)
180 #define RT5350_RX_CALC_IDX0 (RT5350_PDMA_OFFSET + 0x108)
181 #define RT5350_RX_DRX_IDX0 (RT5350_PDMA_OFFSET + 0x10C)
182 #define RT5350_RX_BASE_PTR1 (RT5350_PDMA_OFFSET + 0x110)
183 #define RT5350_RX_MAX_CNT1 (RT5350_PDMA_OFFSET + 0x114)
184 #define RT5350_RX_CALC_IDX1 (RT5350_PDMA_OFFSET + 0x118)
185 #define RT5350_RX_DRX_IDX1 (RT5350_PDMA_OFFSET + 0x11C)
186 #define RT5350_PDMA_GLO_CFG (RT5350_PDMA_OFFSET + 0x204)
187 #define RT5350_PDMA_RST_CFG (RT5350_PDMA_OFFSET + 0x208)
188 #define RT5350_DLY_INT_CFG (RT5350_PDMA_OFFSET + 0x20c)
189 #define RT5350_FE_INT_STATUS (RT5350_PDMA_OFFSET + 0x220)
190 #define RT5350_FE_INT_ENABLE (RT5350_PDMA_OFFSET + 0x228)
191 #define RT5350_PDMA_SCH_CFG (RT5350_PDMA_OFFSET + 0x280)
192
193 #define FE_PDMA_GLO_CFG (FE_PDMA_OFFSET + 0x00)
194 #define FE_PDMA_RST_CFG (FE_PDMA_OFFSET + 0x04)
195 #define FE_PDMA_SCH_CFG (FE_PDMA_OFFSET + 0x08)
196 #define FE_DLY_INT_CFG (FE_PDMA_OFFSET + 0x0C)
197 #define FE_TX_BASE_PTR0 (FE_PDMA_OFFSET + 0x10)
198 #define FE_TX_MAX_CNT0 (FE_PDMA_OFFSET + 0x14)
199 #define FE_TX_CTX_IDX0 (FE_PDMA_OFFSET + 0x18)
200 #define FE_TX_DTX_IDX0 (FE_PDMA_OFFSET + 0x1C)
201 #define FE_TX_BASE_PTR1 (FE_PDMA_OFFSET + 0x20)
202 #define FE_TX_MAX_CNT1 (FE_PDMA_OFFSET + 0x24)
203 #define FE_TX_CTX_IDX1 (FE_PDMA_OFFSET + 0x28)
204 #define FE_TX_DTX_IDX1 (FE_PDMA_OFFSET + 0x2C)
205 #define FE_RX_BASE_PTR0 (FE_PDMA_OFFSET + 0x30)
206 #define FE_RX_MAX_CNT0 (FE_PDMA_OFFSET + 0x34)
207 #define FE_RX_CALC_IDX0 (FE_PDMA_OFFSET + 0x38)
208 #define FE_RX_DRX_IDX0 (FE_PDMA_OFFSET + 0x3C)
209 #define FE_TX_BASE_PTR2 (FE_PDMA_OFFSET + 0x40)
210 #define FE_TX_MAX_CNT2 (FE_PDMA_OFFSET + 0x44)
211 #define FE_TX_CTX_IDX2 (FE_PDMA_OFFSET + 0x48)
212 #define FE_TX_DTX_IDX2 (FE_PDMA_OFFSET + 0x4C)
213 #define FE_TX_BASE_PTR3 (FE_PDMA_OFFSET + 0x50)
214 #define FE_TX_MAX_CNT3 (FE_PDMA_OFFSET + 0x54)
215 #define FE_TX_CTX_IDX3 (FE_PDMA_OFFSET + 0x58)
216 #define FE_TX_DTX_IDX3 (FE_PDMA_OFFSET + 0x5C)
217 #define FE_RX_BASE_PTR1 (FE_PDMA_OFFSET + 0x60)
218 #define FE_RX_MAX_CNT1 (FE_PDMA_OFFSET + 0x64)
219 #define FE_RX_CALC_IDX1 (FE_PDMA_OFFSET + 0x68)
220 #define FE_RX_DRX_IDX1 (FE_PDMA_OFFSET + 0x6C)
221
222 /* Switch DMA configuration */
223 #define RT5350_SDM_CFG (RT5350_SDM_OFFSET + 0x00)
224 #define RT5350_SDM_RRING (RT5350_SDM_OFFSET + 0x04)
225 #define RT5350_SDM_TRING (RT5350_SDM_OFFSET + 0x08)
226 #define RT5350_SDM_MAC_ADRL (RT5350_SDM_OFFSET + 0x0C)
227 #define RT5350_SDM_MAC_ADRH (RT5350_SDM_OFFSET + 0x10)
228 #define RT5350_SDM_TPCNT (RT5350_SDM_OFFSET + 0x100)
229 #define RT5350_SDM_TBCNT (RT5350_SDM_OFFSET + 0x104)
230 #define RT5350_SDM_RPCNT (RT5350_SDM_OFFSET + 0x108)
231 #define RT5350_SDM_RBCNT (RT5350_SDM_OFFSET + 0x10C)
232 #define RT5350_SDM_CS_ERR (RT5350_SDM_OFFSET + 0x110)
233
234 #define RT5350_SDM_ICS_EN BIT(16)
235 #define RT5350_SDM_TCS_EN BIT(17)
236 #define RT5350_SDM_UCS_EN BIT(18)
237
238 /* MDIO_CFG register bits */
239 #define FE_MDIO_CFG_AUTO_POLL_EN BIT(29)
240 #define FE_MDIO_CFG_GP1_BP_EN BIT(16)
241 #define FE_MDIO_CFG_GP1_FRC_EN BIT(15)
242 #define FE_MDIO_CFG_GP1_SPEED_10 (0 << 13)
243 #define FE_MDIO_CFG_GP1_SPEED_100 (1 << 13)
244 #define FE_MDIO_CFG_GP1_SPEED_1000 (2 << 13)
245 #define FE_MDIO_CFG_GP1_DUPLEX BIT(12)
246 #define FE_MDIO_CFG_GP1_FC_TX BIT(11)
247 #define FE_MDIO_CFG_GP1_FC_RX BIT(10)
248 #define FE_MDIO_CFG_GP1_LNK_DWN BIT(9)
249 #define FE_MDIO_CFG_GP1_AN_FAIL BIT(8)
250 #define FE_MDIO_CFG_MDC_CLK_DIV_1 (0 << 6)
251 #define FE_MDIO_CFG_MDC_CLK_DIV_2 (1 << 6)
252 #define FE_MDIO_CFG_MDC_CLK_DIV_4 (2 << 6)
253 #define FE_MDIO_CFG_MDC_CLK_DIV_8 (3 << 6)
254 #define FE_MDIO_CFG_TURBO_MII_FREQ BIT(5)
255 #define FE_MDIO_CFG_TURBO_MII_MODE BIT(4)
256 #define FE_MDIO_CFG_RX_CLK_SKEW_0 (0 << 2)
257 #define FE_MDIO_CFG_RX_CLK_SKEW_200 (1 << 2)
258 #define FE_MDIO_CFG_RX_CLK_SKEW_400 (2 << 2)
259 #define FE_MDIO_CFG_RX_CLK_SKEW_INV (3 << 2)
260 #define FE_MDIO_CFG_TX_CLK_SKEW_0 0
261 #define FE_MDIO_CFG_TX_CLK_SKEW_200 1
262 #define FE_MDIO_CFG_TX_CLK_SKEW_400 2
263 #define FE_MDIO_CFG_TX_CLK_SKEW_INV 3
264
265 /* uni-cast port */
266 #define FE_GDM1_JMB_LEN_MASK 0xf
267 #define FE_GDM1_JMB_LEN_SHIFT 28
268 #define FE_GDM1_ICS_EN BIT(22)
269 #define FE_GDM1_TCS_EN BIT(21)
270 #define FE_GDM1_UCS_EN BIT(20)
271 #define FE_GDM1_JMB_EN BIT(19)
272 #define FE_GDM1_STRPCRC BIT(16)
273 #define FE_GDM1_UFRC_P_CPU (0 << 12)
274 #define FE_GDM1_UFRC_P_GDMA1 (1 << 12)
275 #define FE_GDM1_UFRC_P_PPE (6 << 12)
276
277 /* checksums */
278 #define FE_ICS_GEN_EN BIT(2)
279 #define FE_UCS_GEN_EN BIT(1)
280 #define FE_TCS_GEN_EN BIT(0)
281
282 /* dma ring */
283 #define FE_PST_DRX_IDX0 BIT(16)
284 #define FE_PST_DTX_IDX3 BIT(3)
285 #define FE_PST_DTX_IDX2 BIT(2)
286 #define FE_PST_DTX_IDX1 BIT(1)
287 #define FE_PST_DTX_IDX0 BIT(0)
288
289 #define FE_RX_2B_OFFSET BIT(31)
290 #define FE_TX_WB_DDONE BIT(6)
291 #define FE_RX_DMA_BUSY BIT(3)
292 #define FE_TX_DMA_BUSY BIT(1)
293 #define FE_RX_DMA_EN BIT(2)
294 #define FE_TX_DMA_EN BIT(0)
295
296 #define FE_PDMA_SIZE_4DWORDS (0 << 4)
297 #define FE_PDMA_SIZE_8DWORDS (1 << 4)
298 #define FE_PDMA_SIZE_16DWORDS (2 << 4)
299
300 #define FE_US_CYC_CNT_MASK 0xff
301 #define FE_US_CYC_CNT_SHIFT 0x8
302 #define FE_US_CYC_CNT_DIVISOR 1000000
303
304 /* rxd2 */
305 #define RX_DMA_DONE BIT(31)
306 #define RX_DMA_LSO BIT(30)
307 #define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
308 #define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
309 #define RX_DMA_TAG BIT(15)
310 /* rxd3 */
311 #define RX_DMA_TPID(_x) (((_x) >> 16) & 0xffff)
312 #define RX_DMA_VID(_x) ((_x) & 0xffff)
313 /* rxd4 */
314 #define RX_DMA_L4VALID BIT(30)
315
316 struct fe_rx_dma {
317 unsigned int rxd1;
318 unsigned int rxd2;
319 unsigned int rxd3;
320 unsigned int rxd4;
321 } __packed __aligned(4);
322
323 #define TX_DMA_BUF_LEN 0x3fff
324 #define TX_DMA_PLEN0_MASK (TX_DMA_BUF_LEN << 16)
325 #define TX_DMA_PLEN0(_x) (((_x) & TX_DMA_BUF_LEN) << 16)
326 #define TX_DMA_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
327 #define TX_DMA_GET_PLEN0(_x) (((_x) >> 16) & TX_DMA_BUF_LEN)
328 #define TX_DMA_GET_PLEN1(_x) ((_x) & TX_DMA_BUF_LEN)
329 #define TX_DMA_LS1 BIT(14)
330 #define TX_DMA_LS0 BIT(30)
331 #define TX_DMA_DONE BIT(31)
332
333 #define TX_DMA_INS_VLAN_MT7621 BIT(16)
334 #define TX_DMA_INS_VLAN BIT(7)
335 #define TX_DMA_INS_PPPOE BIT(12)
336 #define TX_DMA_QN(_x) ((_x) << 16)
337 #define TX_DMA_PN(_x) ((_x) << 24)
338 #define TX_DMA_QN_MASK TX_DMA_QN(0x7)
339 #define TX_DMA_PN_MASK TX_DMA_PN(0x7)
340 #define TX_DMA_UDF BIT(20)
341 #define TX_DMA_CHKSUM (0x7 << 29)
342 #define TX_DMA_TSO BIT(28)
343
344 /* frame engine counters */
345 #define FE_PPE_AC_BCNT0 (FE_CMTABLE_OFFSET + 0x00)
346 #define FE_GDMA1_TX_GBCNT (FE_CMTABLE_OFFSET + 0x300)
347 #define FE_GDMA2_TX_GBCNT (FE_GDMA1_TX_GBCNT + 0x40)
348
349 /* phy device flags */
350 #define FE_PHY_FLAG_PORT BIT(0)
351 #define FE_PHY_FLAG_ATTACH BIT(1)
352
353 struct fe_tx_dma {
354 unsigned int txd1;
355 unsigned int txd2;
356 unsigned int txd3;
357 unsigned int txd4;
358 } __packed __aligned(4);
359
360 struct fe_priv;
361
362 struct fe_phy {
363 /* make sure that phy operations are atomic */
364 spinlock_t lock;
365
366 struct phy_device *phy[8];
367 struct device_node *phy_node[8];
368 const __be32 *phy_fixed[8];
369 int duplex[8];
370 int speed[8];
371 int tx_fc[8];
372 int rx_fc[8];
373 int (*connect)(struct fe_priv *priv);
374 void (*disconnect)(struct fe_priv *priv);
375 void (*start)(struct fe_priv *priv);
376 void (*stop)(struct fe_priv *priv);
377 };
378
379 struct fe_soc_data {
380 const u16 *reg_table;
381
382 void (*init_data)(struct fe_soc_data *data, struct net_device *netdev);
383 void (*set_mac)(struct fe_priv *priv, unsigned char *mac);
384 int (*fwd_config)(struct fe_priv *priv);
385 void (*tx_dma)(struct fe_tx_dma *txd);
386 int (*switch_init)(struct fe_priv *priv);
387 int (*switch_config)(struct fe_priv *priv);
388 void (*port_init)(struct fe_priv *priv, struct device_node *port);
389 int (*has_carrier)(struct fe_priv *priv);
390 int (*mdio_init)(struct fe_priv *priv);
391 void (*mdio_cleanup)(struct fe_priv *priv);
392 int (*mdio_write)(struct mii_bus *bus, int phy_addr, int phy_reg,
393 u16 val);
394 int (*mdio_read)(struct mii_bus *bus, int phy_addr, int phy_reg);
395 void (*mdio_adjust_link)(struct fe_priv *priv, int port);
396
397 void *swpriv;
398 u32 pdma_glo_cfg;
399 u32 rx_int;
400 u32 tx_int;
401 u32 status_int;
402 u32 checksum_bit;
403 };
404
405 #define FE_FLAG_PADDING_64B BIT(0)
406 #define FE_FLAG_PADDING_BUG BIT(1)
407 #define FE_FLAG_JUMBO_FRAME BIT(2)
408 #define FE_FLAG_RX_2B_OFFSET BIT(3)
409 #define FE_FLAG_RX_SG_DMA BIT(4)
410 #define FE_FLAG_NAPI_WEIGHT BIT(6)
411 #define FE_FLAG_CALIBRATE_CLK BIT(7)
412 #define FE_FLAG_HAS_SWITCH BIT(8)
413
414 #define FE_STAT_REG_DECLARE \
415 _FE(tx_bytes) \
416 _FE(tx_packets) \
417 _FE(tx_skip) \
418 _FE(tx_collisions) \
419 _FE(rx_bytes) \
420 _FE(rx_packets) \
421 _FE(rx_overflow) \
422 _FE(rx_fcs_errors) \
423 _FE(rx_short_errors) \
424 _FE(rx_long_errors) \
425 _FE(rx_checksum_errors) \
426 _FE(rx_flow_control_packets)
427
428 struct fe_hw_stats {
429 /* make sure that stats operations are atomic */
430 spinlock_t stats_lock;
431
432 struct u64_stats_sync syncp;
433 #define _FE(x) u64 x;
434 FE_STAT_REG_DECLARE
435 #undef _FE
436 };
437
438 struct fe_tx_buf {
439 struct sk_buff *skb;
440 DEFINE_DMA_UNMAP_ADDR(dma_addr0);
441 DEFINE_DMA_UNMAP_ADDR(dma_addr1);
442 u16 dma_len0;
443 u16 dma_len1;
444 };
445
446 struct fe_tx_ring {
447 struct fe_tx_dma *tx_dma;
448 struct fe_tx_buf *tx_buf;
449 dma_addr_t tx_phys;
450 u16 tx_ring_size;
451 u16 tx_free_idx;
452 u16 tx_next_idx;
453 u16 tx_thresh;
454 };
455
456 struct fe_rx_ring {
457 struct page_frag_cache frag_cache;
458 struct fe_rx_dma *rx_dma;
459 u8 **rx_data;
460 dma_addr_t rx_phys;
461 u16 rx_ring_size;
462 u16 frag_size;
463 u16 rx_buf_size;
464 u16 rx_calc_idx;
465 };
466
467 struct fe_priv {
468 /* make sure that register operations are atomic */
469 spinlock_t page_lock;
470
471 struct fe_soc_data *soc;
472 struct net_device *netdev;
473 struct device_node *switch_np;
474 u32 msg_enable;
475 u32 flags;
476
477 struct device *dev;
478 unsigned long sysclk;
479
480 struct fe_rx_ring rx_ring;
481 struct napi_struct rx_napi;
482
483 struct fe_tx_ring tx_ring;
484
485 struct fe_phy *phy;
486 struct mii_bus *mii_bus;
487 struct phy_device *phy_dev;
488 u32 phy_flags;
489
490 int link[8];
491
492 struct fe_hw_stats *hw_stats;
493 unsigned long vlan_map;
494 struct work_struct pending_work;
495 DECLARE_BITMAP(pending_flags, FE_FLAG_MAX);
496
497 struct reset_control *resets;
498 struct mtk_foe_entry *foe_table;
499 dma_addr_t foe_table_phys;
500 struct flow_offload __rcu **foe_flow_table;
501 };
502
503 extern const struct of_device_id of_fe_match[];
504
505 void fe_w32(u32 val, unsigned reg);
506 void fe_m32(struct fe_priv *priv, u32 clear, u32 set, unsigned reg);
507 u32 fe_r32(unsigned reg);
508
509 int fe_set_clock_cycle(struct fe_priv *priv);
510 void fe_csum_config(struct fe_priv *priv);
511 void fe_stats_update(struct fe_priv *priv);
512 void fe_fwd_config(struct fe_priv *priv);
513 void fe_reg_w32(u32 val, enum fe_reg reg);
514 u32 fe_reg_r32(enum fe_reg reg);
515
516 void fe_reset(u32 reset_bits);
517
518 static inline void *priv_netdev(struct fe_priv *priv)
519 {
520 return (char *)priv - ALIGN(sizeof(struct net_device), NETDEV_ALIGN);
521 }
522
523
524 #endif /* FE_ETH_H */
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