target/linux/ramips/patches-3.10/0006-GPIO-MIPS-ralink-add-gpio-driver-for-ralink-SoC.patch

   1 From 55833373cf527dc94bc6c63b68d0f39591667a5d Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Sun, 28 Jul 2013 14:00:25 +0200
   4 Subject: [PATCH 06/25] GPIO: MIPS: ralink: add gpio driver for ralink SoC
   5
   6 Add gpio driver for Ralink SoC. This driver makes the gpio core on
   7 RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 Cc: linux-mips@linux-mips.org
  11 Cc: linux-gpio@vger.kernel.org
  12 ---
  13  arch/mips/Kconfig                        |    1 +
  14  arch/mips/include/asm/mach-ralink/gpio.h |   24 +++
  15  drivers/gpio/Kconfig                     |    6 +
  16  drivers/gpio/Makefile                    |    1 +
  17  drivers/gpio/gpio-ralink.c               |  337 ++++++++++++++++++++++++++++++
  18  5 files changed, 369 insertions(+)
  19  create mode 100644 arch/mips/include/asm/mach-ralink/gpio.h
  20  create mode 100644 drivers/gpio/gpio-ralink.c
  21
  22 Index: linux-3.10.9/arch/mips/Kconfig
  23 ===================================================================
  24 --- linux-3.10.9.orig/arch/mips/Kconfig 2013-08-26 17:48:27.481164281 +0200
  25 +++ linux-3.10.9/arch/mips/Kconfig      2013-08-27 23:15:40.751965869 +0200
  26 @@ -444,6 +444,7 @@
  27         select SYS_HAS_EARLY_PRINTK
  28         select HAVE_MACH_CLKDEV
  29         select CLKDEV_LOOKUP
  30 +       select ARCH_REQUIRE_GPIOLIB
  31
  32  config SGI_IP22
  33         bool "SGI IP22 (Indy/Indigo2)"
  34 Index: linux-3.10.9/arch/mips/include/asm/mach-ralink/gpio.h
  35 ===================================================================
  36 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  37 +++ linux-3.10.9/arch/mips/include/asm/mach-ralink/gpio.h       2013-08-26 17:48:30.941164428 +0200
  38 @@ -0,0 +1,24 @@
  39 +/*
  40 + *  Ralink SoC GPIO API support
  41 + *
  42 + *  Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
  43 + *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
  44 + *
  45 + *  This program is free software; you can redistribute it and/or modify it
  46 + *  under the terms of the GNU General Public License version 2 as published
  47 + *  by the Free Software Foundation.
  48 + *
  49 + */
  50 +
  51 +#ifndef __ASM_MACH_RALINK_GPIO_H
  52 +#define __ASM_MACH_RALINK_GPIO_H
  53 +
  54 +#define ARCH_NR_GPIOS  128
  55 +#include <asm-generic/gpio.h>
  56 +
  57 +#define gpio_get_value __gpio_get_value
  58 +#define gpio_set_value __gpio_set_value
  59 +#define gpio_cansleep  __gpio_cansleep
  60 +#define gpio_to_irq    __gpio_to_irq
  61 +
  62 +#endif /* __ASM_MACH_RALINK_GPIO_H */
  63 Index: linux-3.10.9/drivers/gpio/Kconfig
  64 ===================================================================
  65 --- linux-3.10.9.orig/drivers/gpio/Kconfig      2013-08-21 00:40:47.000000000 +0200
  66 +++ linux-3.10.9/drivers/gpio/Kconfig   2013-08-26 17:48:30.941164428 +0200
  67 @@ -209,6 +209,12 @@
  68         help
  69           Say yes here to support GPIO on Renesas R-Car SoCs.
  70
  71 +config GPIO_RALINK
  72 +       bool "Ralink GPIO Support"
  73 +       depends on RALINK
  74 +       help
  75 +         Say yes here to support the Ralink SoC GPIO device
  76 +
  77  config GPIO_SPEAR_SPICS
  78         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
  79         depends on PLAT_SPEAR
  80 Index: linux-3.10.9/drivers/gpio/Makefile
  81 ===================================================================
  82 --- linux-3.10.9.orig/drivers/gpio/Makefile     2013-08-21 00:40:47.000000000 +0200
  83 +++ linux-3.10.9/drivers/gpio/Makefile  2013-08-26 17:48:30.941164428 +0200
  84 @@ -56,6 +56,7 @@
  85  obj-$(CONFIG_GPIO_PCH)         += gpio-pch.o
  86  obj-$(CONFIG_GPIO_PL061)       += gpio-pl061.o
  87  obj-$(CONFIG_GPIO_PXA)         += gpio-pxa.o
  88 +obj-$(CONFIG_GPIO_RALINK)      += gpio-ralink.o
  89  obj-$(CONFIG_GPIO_RC5T583)     += gpio-rc5t583.o
  90  obj-$(CONFIG_GPIO_RDC321X)     += gpio-rdc321x.o
  91  obj-$(CONFIG_GPIO_RCAR)                += gpio-rcar.o
  92 Index: linux-3.10.9/drivers/gpio/gpio-ralink.c
  93 ===================================================================
  94 --- /dev/null   1970-01-01 00:00:00.000000000 +0000
  95 +++ linux-3.10.9/drivers/gpio/gpio-ralink.c     2013-08-27 22:37:34.999868257 +0200
  96 @@ -0,0 +1,345 @@
  97 +/*
  98 + * This program is free software; you can redistribute it and/or modify it
  99 + * under the terms of the GNU General Public License version 2 as published
 100 + * by the Free Software Foundation.
 101 + *
 102 + * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
 103 + * Copyright (C) 2013 John Crispin <blogic@openwrt.org>
 104 + */
 105 +
 106 +#include <linux/module.h>
 107 +#include <linux/io.h>
 108 +#include <linux/gpio.h>
 109 +#include <linux/spinlock.h>
 110 +#include <linux/platform_device.h>
 111 +#include <linux/of_irq.h>
 112 +#include <linux/irqdomain.h>
 113 +#include <linux/interrupt.h>
 114 +
 115 +enum ralink_gpio_reg {
 116 +       GPIO_REG_INT = 0,
 117 +       GPIO_REG_EDGE,
 118 +       GPIO_REG_RENA,
 119 +       GPIO_REG_FENA,
 120 +       GPIO_REG_DATA,
 121 +       GPIO_REG_DIR,
 122 +       GPIO_REG_POL,
 123 +       GPIO_REG_SET,
 124 +       GPIO_REG_RESET,
 125 +       GPIO_REG_TOGGLE,
 126 +       GPIO_REG_MAX
 127 +};
 128 +
 129 +struct ralink_gpio_chip {
 130 +       struct gpio_chip chip;
 131 +       u8 regs[GPIO_REG_MAX];
 132 +
 133 +       spinlock_t lock;
 134 +       void __iomem *membase;
 135 +       struct irq_domain *domain;
 136 +       int irq;
 137 +
 138 +       u32 rising;
 139 +       u32 falling;
 140 +};
 141 +
 142 +#define MAP_MAX        4
 143 +static struct irq_domain *irq_map[MAP_MAX];
 144 +static int irq_map_count;
 145 +static atomic_t irq_refcount = ATOMIC_INIT(0);
 146 +
 147 +static inline struct ralink_gpio_chip *to_ralink_gpio(struct gpio_chip *chip)
 148 +{
 149 +       struct ralink_gpio_chip *rg;
 150 +
 151 +       rg = container_of(chip, struct ralink_gpio_chip, chip);
 152 +
 153 +       return rg;
 154 +}
 155 +
 156 +static inline void rt_gpio_w32(struct ralink_gpio_chip *rg, u8 reg, u32 val)
 157 +{
 158 +       iowrite32(val, rg->membase + rg->regs[reg]);
 159 +}
 160 +
 161 +static inline u32 rt_gpio_r32(struct ralink_gpio_chip *rg, u8 reg)
 162 +{
 163 +       return ioread32(rg->membase + rg->regs[reg]);
 164 +}
 165 +
 166 +static void ralink_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 167 +{
 168 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 169 +
 170 +       rt_gpio_w32(rg, (value) ? GPIO_REG_SET : GPIO_REG_RESET, BIT(offset));
 171 +}
 172 +
 173 +static int ralink_gpio_get(struct gpio_chip *chip, unsigned offset)
 174 +{
 175 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 176 +
 177 +       return !!(rt_gpio_r32(rg, GPIO_REG_DATA) & BIT(offset));
 178 +}
 179 +
 180 +static int ralink_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 181 +{
 182 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 183 +       unsigned long flags;
 184 +       u32 t;
 185 +
 186 +       spin_lock_irqsave(&rg->lock, flags);
 187 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 188 +       t &= ~BIT(offset);
 189 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 190 +       spin_unlock_irqrestore(&rg->lock, flags);
 191 +
 192 +       return 0;
 193 +}
 194 +
 195 +static int ralink_gpio_direction_output(struct gpio_chip *chip,
 196 +                                       unsigned offset, int value)
 197 +{
 198 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 199 +       unsigned long flags;
 200 +       u32 t;
 201 +
 202 +       spin_lock_irqsave(&rg->lock, flags);
 203 +       ralink_gpio_set(chip, offset, value);
 204 +       t = rt_gpio_r32(rg, GPIO_REG_DIR);
 205 +       t |= BIT(offset);
 206 +       rt_gpio_w32(rg, GPIO_REG_DIR, t);
 207 +       spin_unlock_irqrestore(&rg->lock, flags);
 208 +
 209 +       return 0;
 210 +}
 211 +
 212 +static int ralink_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
 213 +{
 214 +       struct ralink_gpio_chip *rg = to_ralink_gpio(chip);
 215 +
 216 +       if (rg->irq < 1)
 217 +               return -1;
 218 +
 219 +       return irq_create_mapping(rg->domain, pin);
 220 +}
 221 +
 222 +static void ralink_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 223 +{
 224 +       int i;
 225 +
 226 +       for (i = 0; i < irq_map_count; i++) {
 227 +               struct irq_domain *domain = irq_map[i];
 228 +               struct ralink_gpio_chip *rg;
 229 +               unsigned long pending;
 230 +               int bit;
 231 +
 232 +               rg = (struct ralink_gpio_chip *) domain->host_data;
 233 +               pending = rt_gpio_r32(rg, GPIO_REG_INT);
 234 +
 235 +               for_each_set_bit(bit, &pending, rg->chip.ngpio) {
 236 +                       u32 map = irq_find_mapping(domain, bit);
 237 +                       generic_handle_irq(map);
 238 +                       rt_gpio_w32(rg, GPIO_REG_INT, BIT(bit));
 239 +               }
 240 +       }
 241 +}
 242 +
 243 +static void ralink_gpio_irq_unmask(struct irq_data *d)
 244 +{
 245 +       struct ralink_gpio_chip *rg;
 246 +       unsigned long flags;
 247 +       u32 val;
 248 +
 249 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 250 +       val = rt_gpio_r32(rg, GPIO_REG_RENA);
 251 +
 252 +       spin_lock_irqsave(&rg->lock, flags);
 253 +       rt_gpio_w32(rg, GPIO_REG_RENA, val | (BIT(d->hwirq) & rg->rising));
 254 +       rt_gpio_w32(rg, GPIO_REG_FENA, val | (BIT(d->hwirq) & rg->falling));
 255 +       spin_unlock_irqrestore(&rg->lock, flags);
 256 +}
 257 +
 258 +static void ralink_gpio_irq_mask(struct irq_data *d)
 259 +{
 260 +       struct ralink_gpio_chip *rg;
 261 +       unsigned long flags;
 262 +       u32 val;
 263 +
 264 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 265 +       val = rt_gpio_r32(rg, GPIO_REG_RENA);
 266 +
 267 +       spin_lock_irqsave(&rg->lock, flags);
 268 +       rt_gpio_w32(rg, GPIO_REG_FENA, val & ~BIT(d->hwirq));
 269 +       rt_gpio_w32(rg, GPIO_REG_RENA, val & ~BIT(d->hwirq));
 270 +       spin_unlock_irqrestore(&rg->lock, flags);
 271 +}
 272 +
 273 +static int ralink_gpio_irq_type(struct irq_data *d, unsigned int type)
 274 +{
 275 +       struct ralink_gpio_chip *rg;
 276 +       u32 mask = BIT(d->hwirq);
 277 +
 278 +       rg = (struct ralink_gpio_chip *) d->domain->host_data;
 279 +
 280 +       if (type == IRQ_TYPE_PROBE) {
 281 +               if ((rg->rising | rg->falling) & mask)
 282 +                       return 0;
 283 +
 284 +               type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_RISING;
 285 +       }
 286 +
 287 +       if (type & IRQ_TYPE_EDGE_RISING)
 288 +               rg->rising |= mask;
 289 +       else
 290 +               rg->rising &= mask;
 291 +
 292 +       if (type & IRQ_TYPE_EDGE_RISING)
 293 +               rg->falling |= mask;
 294 +       else
 295 +               rg->falling &= mask;
 296 +
 297 +       return 0;
 298 +}
 299 +
 300 +static struct irq_chip ralink_gpio_irq_chip = {
 301 +       .name           = "GPIO",
 302 +       .irq_unmask     = ralink_gpio_irq_unmask,
 303 +       .irq_mask       = ralink_gpio_irq_mask,
 304 +       .irq_mask_ack   = ralink_gpio_irq_mask,
 305 +       .irq_set_type   = ralink_gpio_irq_type,
 306 +};
 307 +
 308 +static int gpio_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
 309 +{
 310 +       irq_set_chip_and_handler(irq, &ralink_gpio_irq_chip, handle_level_irq);
 311 +       irq_set_handler_data(irq, d);
 312 +
 313 +       return 0;
 314 +}
 315 +
 316 +static const struct irq_domain_ops irq_domain_ops = {
 317 +       .xlate = irq_domain_xlate_onecell,
 318 +       .map = gpio_map,
 319 +};
 320 +
 321 +static void ralink_gpio_irq_init(struct device_node *np,
 322 +                                struct ralink_gpio_chip *rg)
 323 +{
 324 +       if (irq_map_count >= MAP_MAX)
 325 +               return;
 326 +
 327 +       rg->irq = irq_of_parse_and_map(np, 0);
 328 +       if (!rg->irq)
 329 +               return;
 330 +
 331 +       rg->domain = irq_domain_add_linear(np, rg->chip.ngpio,
 332 +                                          &irq_domain_ops, rg);
 333 +       if (!rg->domain) {
 334 +               dev_err(rg->chip.dev, "irq_domain_add_linear failed\n");
 335 +               return;
 336 +       }
 337 +
 338 +       irq_map[irq_map_count++] = rg->domain;
 339 +
 340 +       rt_gpio_w32(rg, GPIO_REG_RENA, 0x0);
 341 +       rt_gpio_w32(rg, GPIO_REG_FENA, 0x0);
 342 +
 343 +       if (!atomic_read(&irq_refcount))
 344 +               irq_set_chained_handler(rg->irq, ralink_gpio_irq_handler);
 345 +       atomic_inc(&irq_refcount);
 346 +
 347 +       dev_info(rg->chip.dev, "registering %d irq handlers\n", rg->chip.ngpio);
 348 +}
 349 +
 350 +static int ralink_gpio_request(struct gpio_chip *chip, unsigned offset)
 351 +{
 352 +       int gpio = chip->base + offset;
 353 +
 354 +       return pinctrl_request_gpio(gpio);
 355 +}
 356 +
 357 +static int ralink_gpio_probe(struct platform_device *pdev)
 358 +{
 359 +       struct device_node *np = pdev->dev.of_node;
 360 +       struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 361 +       struct ralink_gpio_chip *rg;
 362 +       const __be32 *ngpio, *gpiobase;
 363 +
 364 +       if (!res) {
 365 +               dev_err(&pdev->dev, "failed to find resource\n");
 366 +               return -ENOMEM;
 367 +       }
 368 +
 369 +       rg = devm_kzalloc(&pdev->dev,
 370 +                       sizeof(struct ralink_gpio_chip), GFP_KERNEL);
 371 +       if (!rg)
 372 +               return -ENOMEM;
 373 +
 374 +       rg->membase = devm_request_and_ioremap(&pdev->dev, res);
 375 +       if (!rg->membase) {
 376 +               dev_err(&pdev->dev, "cannot remap I/O memory region\n");
 377 +               return -ENOMEM;
 378 +       }
 379 +
 380 +       if (of_property_read_u8_array(np, "ralink,register-map",
 381 +                       rg->regs, GPIO_REG_MAX)) {
 382 +               dev_err(&pdev->dev, "failed to read register definition\n");
 383 +               return -EINVAL;
 384 +       }
 385 +
 386 +       ngpio = of_get_property(np, "ralink,num-gpios", NULL);
 387 +       if (!ngpio) {
 388 +               dev_err(&pdev->dev, "failed to read number of pins\n");
 389 +               return -EINVAL;
 390 +       }
 391 +
 392 +       gpiobase = of_get_property(np, "ralink,gpio-base", NULL);
 393 +       if (gpiobase)
 394 +               rg->chip.base = be32_to_cpu(*gpiobase);
 395 +       else
 396 +               rg->chip.base = -1;
 397 +
 398 +       spin_lock_init(&rg->lock);
 399 +
 400 +       rg->chip.dev = &pdev->dev;
 401 +       rg->chip.label = dev_name(&pdev->dev);
 402 +       rg->chip.of_node = np;
 403 +       rg->chip.ngpio = be32_to_cpu(*ngpio);
 404 +       rg->chip.direction_input = ralink_gpio_direction_input;
 405 +       rg->chip.direction_output = ralink_gpio_direction_output;
 406 +       rg->chip.get = ralink_gpio_get;
 407 +       rg->chip.set = ralink_gpio_set;
 408 +       rg->chip.request = ralink_gpio_request;
 409 +       rg->chip.to_irq = ralink_gpio_to_irq;
 410 +
 411 +       /* set polarity to low for all lines */
 412 +       rt_gpio_w32(rg, GPIO_REG_POL, 0);
 413 +
 414 +       dev_info(&pdev->dev, "registering %d gpios\n", rg->chip.ngpio);
 415 +
 416 +       ralink_gpio_irq_init(np, rg);
 417 +
 418 +       return gpiochip_add(&rg->chip);
 419 +}
 420 +
 421 +static const struct of_device_id ralink_gpio_match[] = {
 422 +       { .compatible = "ralink,rt2880-gpio" },
 423 +       {},
 424 +};
 425 +MODULE_DEVICE_TABLE(of, ralink_gpio_match);
 426 +
 427 +static struct platform_driver ralink_gpio_driver = {
 428 +       .probe = ralink_gpio_probe,
 429 +       .driver = {
 430 +               .name = "rt2880_gpio",
 431 +               .owner = THIS_MODULE,
 432 +               .of_match_table = ralink_gpio_match,
 433 +       },
 434 +};
 435 +
 436 +static int __init ralink_gpio_init(void)
 437 +{
 438 +       return platform_driver_register(&ralink_gpio_driver);
 439 +}
 440 +
 441 +subsys_initcall(ralink_gpio_init);