target/linux/ramips/patches-5.10/320-MIPS-add-support-for-buggy-MT7621S-core-detection.patch

   1 From 6decd1aad15f56b169217789630a0098b496de0e Mon Sep 17 00:00:00 2001
   2 From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
   3 Date: Wed, 7 Apr 2021 13:07:38 -0700
   4 Subject: [PATCH] MIPS: add support for buggy MT7621S core detection
   5
   6 Most MT7621 SoCs have 2 cores, which is detected and supported properly
   7 by CPS.
   8
   9 Unfortunately, MT7621 SoC has a less common S variant with only one core.
  10 On MT7621S, GCR_CONFIG still reports 2 cores, which leads to hangs when
  11 starting SMP. CPULAUNCH registers can be used in that case to detect the
  12 absence of the second core and override the GCR_CONFIG PCORES field.
  13
  14 Rework a long-standing OpenWrt patch to override the value of
  15 mips_cps_numcores on single-core MT7621 systems.
  16
  17 Tested on a dual-core MT7621 device (Ubiquiti ER-X) and a single-core
  18 MT7621 device (Netgear R6220).
  19
  20 Original 4.14 OpenWrt patch:
  21 Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=commitdiff;h=4cdbc90a376dd0555201c1434a2081e055e9ceb7
  22 Current 5.10 OpenWrt patch:
  23 Link: https://git.openwrt.org/?p=openwrt/openwrt.git;a=blob;f=target/linux/ramips/patches-5.10/320-mt7621-core-detect-hack.patch;h=c63f0f4c1ec742e24d8480e80553863744b58f6a;hb=10267e17299806f9885d086147878f6c492cb904
  24
  25 Suggested-by: Felix Fietkau <nbd@nbd.name>
  26 Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
  27 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  28 ---
  29  arch/mips/include/asm/mips-cps.h | 23 ++++++++++++++++++++++-
  30  1 file changed, 22 insertions(+), 1 deletion(-)
  31
  32 --- a/arch/mips/include/asm/mips-cps.h
  33 +++ b/arch/mips/include/asm/mips-cps.h
  34 @@ -10,6 +10,8 @@
  35  #include <linux/io.h>
  36  #include <linux/types.h>
  37
  38 +#include <asm/mips-boards/launch.h>
  39 +
  40  extern unsigned long __cps_access_bad_size(void)
  41         __compiletime_error("Bad size for CPS accessor");
  42
  43 @@ -165,11 +167,30 @@ static inline uint64_t mips_cps_cluster_
  44   */
  45  static inline unsigned int mips_cps_numcores(unsigned int cluster)
  46  {
  47 +       unsigned int ncores;
  48 +
  49         if (!mips_cm_present())
  50                 return 0;
  51
  52         /* Add one before masking to handle 0xff indicating no cores */
  53 -       return (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
  54 +       ncores = (mips_cps_cluster_config(cluster) + 1) & CM_GCR_CONFIG_PCORES;
  55 +
  56 +       if (IS_ENABLED(CONFIG_SOC_MT7621)) {
  57 +               struct cpulaunch *launch;
  58 +
  59 +               /*
  60 +                * Ralink MT7621S SoC is single core, but the GCR_CONFIG method
  61 +                * always reports 2 cores. Check the second core's LAUNCH_FREADY
  62 +                * flag to detect if the second core is missing. This method
  63 +                * only works before the core has been started.
  64 +                */
  65 +               launch = (struct cpulaunch *)CKSEG0ADDR(CPULAUNCH);
  66 +               launch += 2; /* MT7621 has 2 VPEs per core */
  67 +               if (!(launch->flags & LAUNCH_FREADY))
  68 +                       ncores = 1;
  69 +       }
  70 +
  71 +       return ncores;
  72  }
  73
  74  /**