81482dde1090de59dc82ab0562345782c973d872
[openwrt/staging/wigyori.git] / target / linux / realtek / dts-5.10 / rtl8382_zyxel_gs1900-24-v1.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later
2
3 #include "rtl8380_zyxel_gs1900.dtsi"
4
5 / {
6 compatible = "zyxel,gs1900-24-v1", "realtek,rtl838x-soc";
7 model = "ZyXEL GS1900-24 v1";
8
9 memory@0 {
10 reg = <0x0 0x4000000>;
11 };
12
13 /* i2c of the left SFP cage: port 25 */
14 i2c0: i2c-gpio-0 {
15 compatible = "i2c-gpio";
16 sda-gpios = <&gpio1 24 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
17 scl-gpios = <&gpio1 25 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
18 i2c-gpio,delay-us = <2>;
19 #address-cells = <1>;
20 #size-cells = <0>;
21 };
22
23 sfp0: sfp-p25 {
24 compatible = "sff,sfp";
25 i2c-bus = <&i2c0>;
26 los-gpio = <&gpio1 27 GPIO_ACTIVE_HIGH>;
27 tx-fault-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
28 mod-def0-gpio = <&gpio1 26 GPIO_ACTIVE_LOW>;
29 tx-disable-gpio = <&gpio1 23 GPIO_ACTIVE_HIGH>;
30 };
31
32 /* i2c of the right SFP cage: port 26 */
33 i2c1: i2c-gpio-1 {
34 compatible = "i2c-gpio";
35 sda-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
36 scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
37 i2c-gpio,delay-us = <2>;
38 #address-cells = <1>;
39 #size-cells = <0>;
40 };
41
42 sfp1: sfp-p26 {
43 compatible = "sff,sfp";
44 i2c-bus = <&i2c1>;
45 los-gpio = <&gpio1 33 GPIO_ACTIVE_HIGH>;
46 tx-fault-gpio = <&gpio1 28 GPIO_ACTIVE_HIGH>;
47 mod-def0-gpio = <&gpio1 32 GPIO_ACTIVE_LOW>;
48 tx-disable-gpio = <&gpio1 29 GPIO_ACTIVE_HIGH>;
49 };
50 };
51
52 &uart1 {
53 status = "okay";
54 };
55
56 &mdio {
57 EXTERNAL_PHY(0)
58 EXTERNAL_PHY(1)
59 EXTERNAL_PHY(2)
60 EXTERNAL_PHY(3)
61 EXTERNAL_PHY(4)
62 EXTERNAL_PHY(5)
63 EXTERNAL_PHY(6)
64 EXTERNAL_PHY(7)
65
66 EXTERNAL_PHY(16)
67 EXTERNAL_PHY(17)
68 EXTERNAL_PHY(18)
69 EXTERNAL_PHY(19)
70 EXTERNAL_PHY(20)
71 EXTERNAL_PHY(21)
72 EXTERNAL_PHY(22)
73 EXTERNAL_PHY(23)
74
75 INTERNAL_PHY(24)
76 INTERNAL_PHY(26)
77 };
78
79 &switch0 {
80 ports {
81 SWITCH_PORT(0, 1, qsgmii)
82 SWITCH_PORT(1, 2, qsgmii)
83 SWITCH_PORT(2, 3, qsgmii)
84 SWITCH_PORT(3, 4, qsgmii)
85 SWITCH_PORT(4, 5, qsgmii)
86 SWITCH_PORT(5, 6, qsgmii)
87 SWITCH_PORT(6, 7, qsgmii)
88 SWITCH_PORT(7, 8, qsgmii)
89
90 SWITCH_PORT(8, 9, internal)
91 SWITCH_PORT(9, 10, internal)
92 SWITCH_PORT(10, 11, internal)
93 SWITCH_PORT(11, 12, internal)
94 SWITCH_PORT(12, 13, internal)
95 SWITCH_PORT(13, 14, internal)
96 SWITCH_PORT(14, 15, internal)
97 SWITCH_PORT(15, 16, internal)
98
99 SWITCH_PORT(16, 17, qsgmii)
100 SWITCH_PORT(17, 18, qsgmii)
101 SWITCH_PORT(18, 19, qsgmii)
102 SWITCH_PORT(19, 20, qsgmii)
103 SWITCH_PORT(20, 21, qsgmii)
104 SWITCH_PORT(21, 22, qsgmii)
105 SWITCH_PORT(22, 23, qsgmii)
106 SWITCH_PORT(23, 24, qsgmii)
107
108 port@24 {
109 reg = <24>;
110 label = "lan25";
111 phy-mode = "1000base-x";
112 managed = "in-band-status";
113 sfp = <&sfp0>;
114 };
115
116 port@26 {
117 reg = <26>;
118 label = "lan26";
119 phy-mode = "1000base-x";
120 managed = "in-band-status";
121 sfp = <&sfp1>;
122 };
123 };
124 };
125
126 &gpio1 {
127 /delete-node/ poe_enable;
128 };