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realtek: Improve MAC config handling for all SoCs
[openwrt/staging/wigyori.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / dsa.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <net/dsa.h>
4 #include <linux/if_bridge.h>
5
6 #include <asm/mach-rtl838x/mach-rtl83xx.h>
7 #include "rtl83xx.h"
8
9
10 extern struct rtl83xx_soc_info soc_info;
11
12
13 static void rtl83xx_init_stats(struct rtl838x_switch_priv *priv)
14 {
15 mutex_lock(&priv->reg_mutex);
16
17 /* Enable statistics module: all counters plus debug.
18 * On RTL839x all counters are enabled by default
19 */
20 if (priv->family_id == RTL8380_FAMILY_ID)
21 sw_w32_mask(0, 3, RTL838X_STAT_CTRL);
22
23 /* Reset statistics counters */
24 sw_w32_mask(0, 1, priv->r->stat_rst);
25
26 mutex_unlock(&priv->reg_mutex);
27 }
28
29 static void rtl83xx_enable_phy_polling(struct rtl838x_switch_priv *priv)
30 {
31 int i;
32 u64 v = 0;
33
34 msleep(1000);
35 /* Enable all ports with a PHY, including the SFP-ports */
36 for (i = 0; i < priv->cpu_port; i++) {
37 if (priv->ports[i].phy)
38 v |= BIT_ULL(i);
39 }
40
41 pr_info("%s: %16llx\n", __func__, v);
42 priv->r->set_port_reg_le(v, priv->r->smi_poll_ctrl);
43
44 /* PHY update complete, there is no global PHY polling enable bit on the 9300 */
45 if (priv->family_id == RTL8390_FAMILY_ID)
46 sw_w32_mask(0, BIT(7), RTL839X_SMI_GLB_CTRL);
47 else if(priv->family_id == RTL9300_FAMILY_ID)
48 sw_w32_mask(0, 0x8000, RTL838X_SMI_GLB_CTRL);
49 }
50
51 const struct rtl83xx_mib_desc rtl83xx_mib[] = {
52 MIB_DESC(2, 0xf8, "ifInOctets"),
53 MIB_DESC(2, 0xf0, "ifOutOctets"),
54 MIB_DESC(1, 0xec, "dot1dTpPortInDiscards"),
55 MIB_DESC(1, 0xe8, "ifInUcastPkts"),
56 MIB_DESC(1, 0xe4, "ifInMulticastPkts"),
57 MIB_DESC(1, 0xe0, "ifInBroadcastPkts"),
58 MIB_DESC(1, 0xdc, "ifOutUcastPkts"),
59 MIB_DESC(1, 0xd8, "ifOutMulticastPkts"),
60 MIB_DESC(1, 0xd4, "ifOutBroadcastPkts"),
61 MIB_DESC(1, 0xd0, "ifOutDiscards"),
62 MIB_DESC(1, 0xcc, ".3SingleCollisionFrames"),
63 MIB_DESC(1, 0xc8, ".3MultipleCollisionFrames"),
64 MIB_DESC(1, 0xc4, ".3DeferredTransmissions"),
65 MIB_DESC(1, 0xc0, ".3LateCollisions"),
66 MIB_DESC(1, 0xbc, ".3ExcessiveCollisions"),
67 MIB_DESC(1, 0xb8, ".3SymbolErrors"),
68 MIB_DESC(1, 0xb4, ".3ControlInUnknownOpcodes"),
69 MIB_DESC(1, 0xb0, ".3InPauseFrames"),
70 MIB_DESC(1, 0xac, ".3OutPauseFrames"),
71 MIB_DESC(1, 0xa8, "DropEvents"),
72 MIB_DESC(1, 0xa4, "tx_BroadcastPkts"),
73 MIB_DESC(1, 0xa0, "tx_MulticastPkts"),
74 MIB_DESC(1, 0x9c, "CRCAlignErrors"),
75 MIB_DESC(1, 0x98, "tx_UndersizePkts"),
76 MIB_DESC(1, 0x94, "rx_UndersizePkts"),
77 MIB_DESC(1, 0x90, "rx_UndersizedropPkts"),
78 MIB_DESC(1, 0x8c, "tx_OversizePkts"),
79 MIB_DESC(1, 0x88, "rx_OversizePkts"),
80 MIB_DESC(1, 0x84, "Fragments"),
81 MIB_DESC(1, 0x80, "Jabbers"),
82 MIB_DESC(1, 0x7c, "Collisions"),
83 MIB_DESC(1, 0x78, "tx_Pkts64Octets"),
84 MIB_DESC(1, 0x74, "rx_Pkts64Octets"),
85 MIB_DESC(1, 0x70, "tx_Pkts65to127Octets"),
86 MIB_DESC(1, 0x6c, "rx_Pkts65to127Octets"),
87 MIB_DESC(1, 0x68, "tx_Pkts128to255Octets"),
88 MIB_DESC(1, 0x64, "rx_Pkts128to255Octets"),
89 MIB_DESC(1, 0x60, "tx_Pkts256to511Octets"),
90 MIB_DESC(1, 0x5c, "rx_Pkts256to511Octets"),
91 MIB_DESC(1, 0x58, "tx_Pkts512to1023Octets"),
92 MIB_DESC(1, 0x54, "rx_Pkts512to1023Octets"),
93 MIB_DESC(1, 0x50, "tx_Pkts1024to1518Octets"),
94 MIB_DESC(1, 0x4c, "rx_StatsPkts1024to1518Octets"),
95 MIB_DESC(1, 0x48, "tx_Pkts1519toMaxOctets"),
96 MIB_DESC(1, 0x44, "rx_Pkts1519toMaxOctets"),
97 MIB_DESC(1, 0x40, "rxMacDiscards")
98 };
99
100
101 /* DSA callbacks */
102
103
104 static enum dsa_tag_protocol rtl83xx_get_tag_protocol(struct dsa_switch *ds,
105 int port,
106 enum dsa_tag_protocol mprot)
107 {
108 /* The switch does not tag the frames, instead internally the header
109 * structure for each packet is tagged accordingly.
110 */
111 return DSA_TAG_PROTO_TRAILER;
112 }
113
114 /*
115 * Initialize all VLANS
116 */
117 static void rtl83xx_vlan_setup(struct rtl838x_switch_priv *priv)
118 {
119 struct rtl838x_vlan_info info;
120 int i;
121
122 pr_info("In %s\n", __func__);
123
124 priv->r->vlan_profile_setup(0);
125 priv->r->vlan_profile_setup(1);
126 pr_info("UNKNOWN_MC_PMASK: %016llx\n", priv->r->read_mcast_pmask(UNKNOWN_MC_PMASK));
127 priv->r->vlan_profile_dump(0);
128
129 info.fid = 0; // Default Forwarding ID / MSTI
130 info.hash_uc_fid = false; // Do not build the L2 lookup hash with FID, but VID
131 info.hash_mc_fid = false; // Do the same for Multicast packets
132 info.profile_id = 0; // Use default Vlan Profile 0
133 info.tagged_ports = 0; // Initially no port members
134 if (priv->family_id == RTL9310_FAMILY_ID) {
135 info.if_id = 0;
136 info.multicast_grp_mask = 0;
137 info.l2_tunnel_list_id = -1;
138 }
139
140 // Initialize all vlans 0-4095
141 for (i = 0; i < MAX_VLANS; i ++)
142 priv->r->vlan_set_tagged(i, &info);
143
144 // reset PVIDs; defaults to 1 on reset
145 for (i = 0; i <= priv->ds->num_ports; i++)
146 sw_w32(0, priv->r->vlan_port_pb + (i << 2));
147
148 // Set forwarding action based on inner VLAN tag
149 for (i = 0; i < priv->cpu_port; i++)
150 priv->r->vlan_fwd_on_inner(i, true);
151 }
152
153 static int rtl83xx_setup(struct dsa_switch *ds)
154 {
155 int i;
156 struct rtl838x_switch_priv *priv = ds->priv;
157 u64 port_bitmap = BIT_ULL(priv->cpu_port);
158
159 pr_debug("%s called\n", __func__);
160
161 /* Disable MAC polling the PHY so that we can start configuration */
162 priv->r->set_port_reg_le(0ULL, priv->r->smi_poll_ctrl);
163
164 for (i = 0; i < ds->num_ports; i++)
165 priv->ports[i].enable = false;
166 priv->ports[priv->cpu_port].enable = true;
167
168 /* Isolate ports from each other: traffic only CPU <-> port */
169 /* Setting bit j in register RTL838X_PORT_ISO_CTRL(i) allows
170 * traffic from source port i to destination port j
171 */
172 for (i = 0; i < priv->cpu_port; i++) {
173 if (priv->ports[i].phy) {
174 priv->r->set_port_reg_be(BIT_ULL(priv->cpu_port) | BIT_ULL(i),
175 priv->r->port_iso_ctrl(i));
176 port_bitmap |= BIT_ULL(i);
177 }
178 }
179 priv->r->set_port_reg_be(port_bitmap, priv->r->port_iso_ctrl(priv->cpu_port));
180
181 if (priv->family_id == RTL8380_FAMILY_ID)
182 rtl838x_print_matrix();
183 else
184 rtl839x_print_matrix();
185
186 rtl83xx_init_stats(priv);
187
188 rtl83xx_vlan_setup(priv);
189
190 ds->configure_vlan_while_not_filtering = true;
191
192 priv->r->l2_learning_setup();
193
194 /* Enable MAC Polling PHY again */
195 rtl83xx_enable_phy_polling(priv);
196 pr_debug("Please wait until PHY is settled\n");
197 msleep(1000);
198 priv->r->pie_init(priv);
199
200 return 0;
201 }
202
203 static int rtl93xx_setup(struct dsa_switch *ds)
204 {
205 int i;
206 struct rtl838x_switch_priv *priv = ds->priv;
207 u32 port_bitmap = BIT(priv->cpu_port);
208
209 pr_info("%s called\n", __func__);
210
211 /* Disable MAC polling the PHY so that we can start configuration */
212 if (priv->family_id == RTL9300_FAMILY_ID)
213 sw_w32(0, RTL930X_SMI_POLL_CTRL);
214
215 if (priv->family_id == RTL9310_FAMILY_ID) {
216 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL);
217 sw_w32(0, RTL931X_SMI_PORT_POLLING_CTRL + 4);
218 }
219
220 // Disable all ports except CPU port
221 for (i = 0; i < ds->num_ports; i++)
222 priv->ports[i].enable = false;
223 priv->ports[priv->cpu_port].enable = true;
224
225 for (i = 0; i < priv->cpu_port; i++) {
226 if (priv->ports[i].phy) {
227 priv->r->traffic_set(i, BIT_ULL(priv->cpu_port) | BIT_ULL(i));
228 port_bitmap |= BIT_ULL(i);
229 }
230 }
231 priv->r->traffic_set(priv->cpu_port, port_bitmap);
232
233 rtl930x_print_matrix();
234
235 // TODO: Initialize statistics
236
237 rtl83xx_vlan_setup(priv);
238
239 ds->configure_vlan_while_not_filtering = true;
240
241 priv->r->l2_learning_setup();
242
243 rtl83xx_enable_phy_polling(priv);
244
245 priv->r->pie_init(priv);
246
247 return 0;
248 }
249
250 static int rtl93xx_get_sds(struct phy_device *phydev)
251 {
252 struct device *dev = &phydev->mdio.dev;
253 struct device_node *dn;
254 u32 sds_num;
255
256 if (!dev)
257 return -1;
258 if (dev->of_node) {
259 dn = dev->of_node;
260 if (of_property_read_u32(dn, "sds", &sds_num))
261 sds_num = -1;
262 } else {
263 dev_err(dev, "No DT node.\n");
264 return -1;
265 }
266
267 return sds_num;
268 }
269
270 static void rtl83xx_phylink_validate(struct dsa_switch *ds, int port,
271 unsigned long *supported,
272 struct phylink_link_state *state)
273 {
274 struct rtl838x_switch_priv *priv = ds->priv;
275 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
276
277 pr_debug("In %s port %d, state is %d", __func__, port, state->interface);
278
279 if (!phy_interface_mode_is_rgmii(state->interface) &&
280 state->interface != PHY_INTERFACE_MODE_NA &&
281 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
282 state->interface != PHY_INTERFACE_MODE_MII &&
283 state->interface != PHY_INTERFACE_MODE_REVMII &&
284 state->interface != PHY_INTERFACE_MODE_GMII &&
285 state->interface != PHY_INTERFACE_MODE_QSGMII &&
286 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
287 state->interface != PHY_INTERFACE_MODE_SGMII) {
288 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
289 dev_err(ds->dev,
290 "Unsupported interface: %d for port %d\n",
291 state->interface, port);
292 return;
293 }
294
295 /* Allow all the expected bits */
296 phylink_set(mask, Autoneg);
297 phylink_set_port_modes(mask);
298 phylink_set(mask, Pause);
299 phylink_set(mask, Asym_Pause);
300
301 /* With the exclusion of MII and Reverse MII, we support Gigabit,
302 * including Half duplex
303 */
304 if (state->interface != PHY_INTERFACE_MODE_MII &&
305 state->interface != PHY_INTERFACE_MODE_REVMII) {
306 phylink_set(mask, 1000baseT_Full);
307 phylink_set(mask, 1000baseT_Half);
308 }
309
310 /* On both the 8380 and 8382, ports 24-27 are SFP ports */
311 if (port >= 24 && port <= 27 && priv->family_id == RTL8380_FAMILY_ID)
312 phylink_set(mask, 1000baseX_Full);
313
314 /* On the RTL839x family of SoCs, ports 48 to 51 are SFP ports */
315 if (port >= 48 && port <= 51 && priv->family_id == RTL8390_FAMILY_ID)
316 phylink_set(mask, 1000baseX_Full);
317
318 phylink_set(mask, 10baseT_Half);
319 phylink_set(mask, 10baseT_Full);
320 phylink_set(mask, 100baseT_Half);
321 phylink_set(mask, 100baseT_Full);
322
323 bitmap_and(supported, supported, mask,
324 __ETHTOOL_LINK_MODE_MASK_NBITS);
325 bitmap_and(state->advertising, state->advertising, mask,
326 __ETHTOOL_LINK_MODE_MASK_NBITS);
327 }
328
329 static void rtl93xx_phylink_validate(struct dsa_switch *ds, int port,
330 unsigned long *supported,
331 struct phylink_link_state *state)
332 {
333 struct rtl838x_switch_priv *priv = ds->priv;
334 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
335
336 pr_debug("In %s port %d, state is %d (%s)", __func__, port, state->interface,
337 phy_modes(state->interface));
338
339 if (!phy_interface_mode_is_rgmii(state->interface) &&
340 state->interface != PHY_INTERFACE_MODE_NA &&
341 state->interface != PHY_INTERFACE_MODE_1000BASEX &&
342 state->interface != PHY_INTERFACE_MODE_MII &&
343 state->interface != PHY_INTERFACE_MODE_REVMII &&
344 state->interface != PHY_INTERFACE_MODE_GMII &&
345 state->interface != PHY_INTERFACE_MODE_QSGMII &&
346 state->interface != PHY_INTERFACE_MODE_XGMII &&
347 state->interface != PHY_INTERFACE_MODE_HSGMII &&
348 state->interface != PHY_INTERFACE_MODE_10GKR &&
349 state->interface != PHY_INTERFACE_MODE_USXGMII &&
350 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
351 state->interface != PHY_INTERFACE_MODE_SGMII) {
352 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
353 dev_err(ds->dev,
354 "Unsupported interface: %d for port %d\n",
355 state->interface, port);
356 return;
357 }
358
359 /* Allow all the expected bits */
360 phylink_set(mask, Autoneg);
361 phylink_set_port_modes(mask);
362 phylink_set(mask, Pause);
363 phylink_set(mask, Asym_Pause);
364
365 /* With the exclusion of MII and Reverse MII, we support Gigabit,
366 * including Half duplex
367 */
368 if (state->interface != PHY_INTERFACE_MODE_MII &&
369 state->interface != PHY_INTERFACE_MODE_REVMII) {
370 phylink_set(mask, 1000baseT_Full);
371 phylink_set(mask, 1000baseT_Half);
372 }
373
374 // Internal phys of the RTL93xx family provide 10G
375 if (priv->ports[port].phy_is_integrated
376 && state->interface == PHY_INTERFACE_MODE_1000BASEX) {
377 phylink_set(mask, 1000baseX_Full);
378 } else if (priv->ports[port].phy_is_integrated) {
379 phylink_set(mask, 1000baseX_Full);
380 phylink_set(mask, 10000baseKR_Full);
381 phylink_set(mask, 10000baseSR_Full);
382 phylink_set(mask, 10000baseCR_Full);
383 }
384 if (state->interface == PHY_INTERFACE_MODE_INTERNAL) {
385 phylink_set(mask, 1000baseX_Full);
386 phylink_set(mask, 1000baseT_Full);
387 phylink_set(mask, 10000baseKR_Full);
388 phylink_set(mask, 10000baseT_Full);
389 phylink_set(mask, 10000baseSR_Full);
390 phylink_set(mask, 10000baseCR_Full);
391 }
392
393 phylink_set(mask, 10baseT_Half);
394 phylink_set(mask, 10baseT_Full);
395 phylink_set(mask, 100baseT_Half);
396 phylink_set(mask, 100baseT_Full);
397
398 bitmap_and(supported, supported, mask,
399 __ETHTOOL_LINK_MODE_MASK_NBITS);
400 bitmap_and(state->advertising, state->advertising, mask,
401 __ETHTOOL_LINK_MODE_MASK_NBITS);
402 pr_debug("%s leaving supported: %*pb", __func__, __ETHTOOL_LINK_MODE_MASK_NBITS, supported);
403 }
404
405 static int rtl83xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
406 struct phylink_link_state *state)
407 {
408 struct rtl838x_switch_priv *priv = ds->priv;
409 u64 speed;
410 u64 link;
411
412 if (port < 0 || port > priv->cpu_port)
413 return -EINVAL;
414
415 state->link = 0;
416 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
417 if (link & BIT_ULL(port))
418 state->link = 1;
419 pr_debug("%s: link state port %d: %llx\n", __func__, port, link & BIT_ULL(port));
420
421 state->duplex = 0;
422 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
423 state->duplex = 1;
424
425 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
426 speed >>= (port % 16) << 1;
427 switch (speed & 0x3) {
428 case 0:
429 state->speed = SPEED_10;
430 break;
431 case 1:
432 state->speed = SPEED_100;
433 break;
434 case 2:
435 state->speed = SPEED_1000;
436 break;
437 case 3:
438 if (priv->family_id == RTL9300_FAMILY_ID
439 && (port == 24 || port == 26)) /* Internal serdes */
440 state->speed = SPEED_2500;
441 else
442 state->speed = SPEED_100; /* Is in fact 500Mbit */
443 }
444
445 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
446 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
447 state->pause |= MLO_PAUSE_RX;
448 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
449 state->pause |= MLO_PAUSE_TX;
450 return 1;
451 }
452
453 static int rtl93xx_phylink_mac_link_state(struct dsa_switch *ds, int port,
454 struct phylink_link_state *state)
455 {
456 struct rtl838x_switch_priv *priv = ds->priv;
457 u64 speed;
458 u64 link;
459
460 if (port < 0 || port > priv->cpu_port)
461 return -EINVAL;
462
463 /*
464 * On the RTL9300 for at least the RTL8226B PHY, the MAC-side link
465 * state needs to be read twice in order to read a correct result.
466 * This would not be necessary for ports connected e.g. to RTL8218D
467 * PHYs.
468 */
469 state->link = 0;
470 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
471 link = priv->r->get_port_reg_le(priv->r->mac_link_sts);
472 if (link & BIT_ULL(port))
473 state->link = 1;
474 pr_debug("%s: link state port %d: %llx, media %08x\n", __func__, port,
475 link & BIT_ULL(port), sw_r32(RTL930X_MAC_LINK_MEDIA_STS));
476
477 state->duplex = 0;
478 if (priv->r->get_port_reg_le(priv->r->mac_link_dup_sts) & BIT_ULL(port))
479 state->duplex = 1;
480
481 speed = priv->r->get_port_reg_le(priv->r->mac_link_spd_sts(port));
482 speed >>= (port % 8) << 2;
483 switch (speed & 0xf) {
484 case 0:
485 state->speed = SPEED_10;
486 break;
487 case 1:
488 state->speed = SPEED_100;
489 break;
490 case 2:
491 case 7:
492 state->speed = SPEED_1000;
493 break;
494 case 4:
495 state->speed = SPEED_10000;
496 break;
497 case 5:
498 case 8:
499 state->speed = SPEED_2500;
500 break;
501 case 6:
502 state->speed = SPEED_5000;
503 break;
504 default:
505 pr_err("%s: unknown speed: %d\n", __func__, (u32)speed & 0xf);
506 }
507
508 if (priv->family_id == RTL9310_FAMILY_ID
509 && (port >= 52 || port <= 55)) { /* Internal serdes */
510 state->speed = SPEED_10000;
511 state->link = 1;
512 state->duplex = 1;
513 }
514
515 pr_debug("%s: speed is: %d %d\n", __func__, (u32)speed & 0xf, state->speed);
516 state->pause &= (MLO_PAUSE_RX | MLO_PAUSE_TX);
517 if (priv->r->get_port_reg_le(priv->r->mac_rx_pause_sts) & BIT_ULL(port))
518 state->pause |= MLO_PAUSE_RX;
519 if (priv->r->get_port_reg_le(priv->r->mac_tx_pause_sts) & BIT_ULL(port))
520 state->pause |= MLO_PAUSE_TX;
521 return 1;
522 }
523
524 static void rtl83xx_config_interface(int port, phy_interface_t interface)
525 {
526 u32 old, int_shift, sds_shift;
527
528 switch (port) {
529 case 24:
530 int_shift = 0;
531 sds_shift = 5;
532 break;
533 case 26:
534 int_shift = 3;
535 sds_shift = 0;
536 break;
537 default:
538 return;
539 }
540
541 old = sw_r32(RTL838X_SDS_MODE_SEL);
542 switch (interface) {
543 case PHY_INTERFACE_MODE_1000BASEX:
544 if ((old >> sds_shift & 0x1f) == 4)
545 return;
546 sw_w32_mask(0x7 << int_shift, 1 << int_shift, RTL838X_INT_MODE_CTRL);
547 sw_w32_mask(0x1f << sds_shift, 4 << sds_shift, RTL838X_SDS_MODE_SEL);
548 break;
549 case PHY_INTERFACE_MODE_SGMII:
550 if ((old >> sds_shift & 0x1f) == 2)
551 return;
552 sw_w32_mask(0x7 << int_shift, 2 << int_shift, RTL838X_INT_MODE_CTRL);
553 sw_w32_mask(0x1f << sds_shift, 2 << sds_shift, RTL838X_SDS_MODE_SEL);
554 break;
555 default:
556 return;
557 }
558 pr_debug("configured port %d for interface %s\n", port, phy_modes(interface));
559 }
560
561 static void rtl83xx_phylink_mac_config(struct dsa_switch *ds, int port,
562 unsigned int mode,
563 const struct phylink_link_state *state)
564 {
565 struct rtl838x_switch_priv *priv = ds->priv;
566 u32 reg;
567 int speed_bit = priv->family_id == RTL8380_FAMILY_ID ? 4 : 3;
568
569 pr_debug("%s port %d, mode %x\n", __func__, port, mode);
570
571 if (port == priv->cpu_port) {
572 /* Set Speed, duplex, flow control
573 * FORCE_EN | LINK_EN | NWAY_EN | DUP_SEL
574 * | SPD_SEL = 0b10 | FORCE_FC_EN | PHY_MASTER_SLV_MANUAL_EN
575 * | MEDIA_SEL
576 */
577 if (priv->family_id == RTL8380_FAMILY_ID) {
578 sw_w32(0x6192F, priv->r->mac_force_mode_ctrl(priv->cpu_port));
579 /* allow CRC errors on CPU-port */
580 sw_w32_mask(0, 0x8, RTL838X_MAC_PORT_CTRL(priv->cpu_port));
581 } else {
582 sw_w32_mask(0, 3, priv->r->mac_force_mode_ctrl(priv->cpu_port));
583 }
584 return;
585 }
586
587 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
588 /* Auto-Negotiation does not work for MAC in RTL8390 */
589 if (priv->family_id == RTL8380_FAMILY_ID) {
590 if (mode == MLO_AN_PHY || phylink_autoneg_inband(mode)) {
591 pr_debug("PHY autonegotiates\n");
592 reg |= RTL838X_NWAY_EN;
593 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
594 rtl83xx_config_interface(port, state->interface);
595 return;
596 }
597 }
598
599 if (mode != MLO_AN_FIXED)
600 pr_debug("Fixed state.\n");
601
602 /* Clear id_mode_dis bit, and the existing port mode, let
603 * RGMII_MODE_EN bet set by mac_link_{up,down} */
604 if (priv->family_id == RTL8380_FAMILY_ID) {
605 reg &= ~(RTL838X_RX_PAUSE_EN | RTL838X_TX_PAUSE_EN);
606 if (state->pause & MLO_PAUSE_TXRX_MASK) {
607 if (state->pause & MLO_PAUSE_TX)
608 reg |= RTL838X_TX_PAUSE_EN;
609 reg |= RTL838X_RX_PAUSE_EN;
610 }
611 } else if (priv->family_id == RTL8390_FAMILY_ID) {
612 reg &= ~(RTL839X_RX_PAUSE_EN | RTL839X_TX_PAUSE_EN);
613 if (state->pause & MLO_PAUSE_TXRX_MASK) {
614 if (state->pause & MLO_PAUSE_TX)
615 reg |= RTL839X_TX_PAUSE_EN;
616 reg |= RTL839X_RX_PAUSE_EN;
617 }
618 }
619
620
621 reg &= ~(3 << speed_bit);
622 switch (state->speed) {
623 case SPEED_1000:
624 reg |= 2 << speed_bit;
625 break;
626 case SPEED_100:
627 reg |= 1 << speed_bit;
628 break;
629 default:
630 break; // Ignore, including 10MBit which has a speed value of 0
631 }
632
633 if (priv->family_id == RTL8380_FAMILY_ID) {
634 reg &= ~(RTL838X_DUPLEX_MODE | RTL838X_FORCE_LINK_EN);
635 if (state->link)
636 reg |= RTL838X_FORCE_LINK_EN;
637 if (state->duplex == RTL838X_DUPLEX_MODE)
638 reg |= RTL838X_DUPLEX_MODE;
639 } else if (priv->family_id == RTL8390_FAMILY_ID) {
640 reg &= ~(RTL839X_DUPLEX_MODE | RTL839X_FORCE_LINK_EN);
641 if (state->link)
642 reg |= RTL839X_FORCE_LINK_EN;
643 if (state->duplex == RTL839X_DUPLEX_MODE)
644 reg |= RTL839X_DUPLEX_MODE;
645 }
646 // Disable AN
647 if (priv->family_id == RTL8380_FAMILY_ID)
648 reg &= ~RTL838X_NWAY_EN;
649 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
650 }
651
652 static void rtl931x_phylink_mac_config(struct dsa_switch *ds, int port,
653 unsigned int mode,
654 const struct phylink_link_state *state)
655 {
656 struct rtl838x_switch_priv *priv = ds->priv;
657 int sds_num;
658 u32 reg, band;
659
660 sds_num = priv->ports[port].sds_num;
661 pr_info("%s: speed %d sds_num %d\n", __func__, state->speed, sds_num);
662
663 switch (state->interface) {
664 case PHY_INTERFACE_MODE_HSGMII:
665 pr_info("%s setting mode PHY_INTERFACE_MODE_HSGMII\n", __func__);
666 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_HSGMII);
667 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_HSGMII);
668 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_HSGMII);
669 break;
670 case PHY_INTERFACE_MODE_1000BASEX:
671 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_1000BASEX);
672 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_1000BASEX);
673 break;
674 case PHY_INTERFACE_MODE_XGMII:
675 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_XGMII);
676 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_XGMII);
677 break;
678 case PHY_INTERFACE_MODE_10GBASER:
679 case PHY_INTERFACE_MODE_10GKR:
680 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_10GBASER);
681 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_10GBASER);
682 break;
683 case PHY_INTERFACE_MODE_USXGMII:
684 // Translates to MII_USXGMII_10GSXGMII
685 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_USXGMII);
686 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_USXGMII);
687 break;
688 case PHY_INTERFACE_MODE_SGMII:
689 pr_info("%s setting mode PHY_INTERFACE_MODE_SGMII\n", __func__);
690 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_SGMII);
691 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_SGMII);
692 band = rtl931x_sds_cmu_band_set(sds_num, true, 62, PHY_INTERFACE_MODE_SGMII);
693 break;
694 case PHY_INTERFACE_MODE_QSGMII:
695 band = rtl931x_sds_cmu_band_get(sds_num, PHY_INTERFACE_MODE_QSGMII);
696 rtl931x_sds_init(sds_num, PHY_INTERFACE_MODE_QSGMII);
697 break;
698 default:
699 pr_err("%s: unknown serdes mode: %s\n",
700 __func__, phy_modes(state->interface));
701 return;
702 }
703
704 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
705 pr_info("%s reading FORCE_MODE_CTRL: %08x\n", __func__, reg);
706
707 reg &= ~(RTL931X_DUPLEX_MODE | RTL931X_FORCE_EN | RTL931X_FORCE_LINK_EN);
708
709 reg &= ~(0xf << 12);
710 reg |= 0x2 << 12; // Set SMI speed to 0x2
711
712 reg |= BIT(17) | BIT(16); // Enable RX pause and TX pause
713
714 if (state->duplex == DUPLEX_FULL)
715 reg |= RTL931X_DUPLEX_MODE;
716
717 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
718
719 }
720
721 static void rtl93xx_phylink_mac_config(struct dsa_switch *ds, int port,
722 unsigned int mode,
723 const struct phylink_link_state *state)
724 {
725 struct rtl838x_switch_priv *priv = ds->priv;
726 int sds_num, sds_mode;
727 u32 reg;
728
729 pr_info("%s port %d, mode %x, phy-mode: %s, speed %d, link %d\n", __func__,
730 port, mode, phy_modes(state->interface), state->speed, state->link);
731
732 // Nothing to be done for the CPU-port
733 if (port == priv->cpu_port)
734 return;
735
736 if (priv->family_id == RTL9310_FAMILY_ID)
737 return rtl931x_phylink_mac_config(ds, port, mode, state);
738
739 reg = sw_r32(priv->r->mac_force_mode_ctrl(port));
740 reg &= ~(0xf << 3);
741
742 sds_num = priv->ports[port].sds_num;
743 pr_info("%s SDS is %d\n", __func__, sds_num);
744 if (sds_num >= 0) {
745 switch (state->interface) {
746 case PHY_INTERFACE_MODE_HSGMII:
747 sds_mode = 0x12;
748 break;
749 case PHY_INTERFACE_MODE_1000BASEX:
750 sds_mode = 0x1b; // 10G 1000X Auto
751 break;
752 case PHY_INTERFACE_MODE_XGMII:
753 sds_mode = 0x10;
754 break;
755 case PHY_INTERFACE_MODE_10GKR:
756 sds_mode = 0x1a;
757 // We need to use media sel for fibre media:
758 reg |= BIT(16);
759 break;
760 case PHY_INTERFACE_MODE_USXGMII:
761 sds_mode = 0x0d;
762 break;
763 default:
764 pr_err("%s: unknown serdes mode: %s\n",
765 __func__, phy_modes(state->interface));
766 return;
767 }
768 rtl9300_sds_rst(sds_num, sds_mode);
769 }
770
771 switch (state->speed) {
772 case SPEED_10000:
773 reg |= 4 << 3;
774 break;
775 case SPEED_5000:
776 reg |= 6 << 3;
777 break;
778 case SPEED_2500:
779 reg |= 5 << 3;
780 break;
781 case SPEED_1000:
782 reg |= 2 << 3;
783 break;
784 default:
785 reg |= 2 << 3;
786 break;
787 }
788
789 if (state->link)
790 reg |= RTL930X_FORCE_LINK_EN;
791
792 if (state->duplex == DUPLEX_FULL)
793 reg |= RTL930X_DUPLEX_MODE;
794
795 if (priv->ports[port].phy_is_integrated)
796 reg &= ~RTL930X_FORCE_EN; // Clear MAC_FORCE_EN to allow SDS-MAC link
797 else
798 reg |= RTL930X_FORCE_EN;
799
800 sw_w32(reg, priv->r->mac_force_mode_ctrl(port));
801 }
802
803 static void rtl83xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
804 unsigned int mode,
805 phy_interface_t interface)
806 {
807 struct rtl838x_switch_priv *priv = ds->priv;
808 /* Stop TX/RX to port */
809 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
810 }
811
812 static void rtl93xx_phylink_mac_link_down(struct dsa_switch *ds, int port,
813 unsigned int mode,
814 phy_interface_t interface)
815 {
816 struct rtl838x_switch_priv *priv = ds->priv;
817 /* Stop TX/RX to port */
818 sw_w32_mask(0x3, 0, priv->r->mac_port_ctrl(port));
819
820 // No longer force link
821 sw_w32_mask(3, 0, priv->r->mac_force_mode_ctrl(port));
822 }
823
824 static void rtl83xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
825 unsigned int mode,
826 phy_interface_t interface,
827 struct phy_device *phydev,
828 int speed, int duplex,
829 bool tx_pause, bool rx_pause)
830 {
831 struct rtl838x_switch_priv *priv = ds->priv;
832 /* Restart TX/RX to port */
833 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
834 // TODO: Set speed/duplex/pauses
835 }
836
837 static void rtl93xx_phylink_mac_link_up(struct dsa_switch *ds, int port,
838 unsigned int mode,
839 phy_interface_t interface,
840 struct phy_device *phydev,
841 int speed, int duplex,
842 bool tx_pause, bool rx_pause)
843 {
844 struct rtl838x_switch_priv *priv = ds->priv;
845
846 /* Restart TX/RX to port */
847 sw_w32_mask(0, 0x3, priv->r->mac_port_ctrl(port));
848 // TODO: Set speed/duplex/pauses
849 }
850
851 static void rtl83xx_get_strings(struct dsa_switch *ds,
852 int port, u32 stringset, u8 *data)
853 {
854 int i;
855
856 if (stringset != ETH_SS_STATS)
857 return;
858
859 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++)
860 strncpy(data + i * ETH_GSTRING_LEN, rtl83xx_mib[i].name,
861 ETH_GSTRING_LEN);
862 }
863
864 static void rtl83xx_get_ethtool_stats(struct dsa_switch *ds, int port,
865 uint64_t *data)
866 {
867 struct rtl838x_switch_priv *priv = ds->priv;
868 const struct rtl83xx_mib_desc *mib;
869 int i;
870 u64 h;
871
872 for (i = 0; i < ARRAY_SIZE(rtl83xx_mib); i++) {
873 mib = &rtl83xx_mib[i];
874
875 data[i] = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 252 - mib->offset);
876 if (mib->size == 2) {
877 h = sw_r32(priv->r->stat_port_std_mib + (port << 8) + 248 - mib->offset);
878 data[i] |= h << 32;
879 }
880 }
881 }
882
883 static int rtl83xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
884 {
885 if (sset != ETH_SS_STATS)
886 return 0;
887
888 return ARRAY_SIZE(rtl83xx_mib);
889 }
890
891 static int rtl83xx_port_enable(struct dsa_switch *ds, int port,
892 struct phy_device *phydev)
893 {
894 struct rtl838x_switch_priv *priv = ds->priv;
895 u64 v;
896
897 pr_debug("%s: %x %d", __func__, (u32) priv, port);
898 priv->ports[port].enable = true;
899
900 /* enable inner tagging on egress, do not keep any tags */
901 if (priv->family_id == RTL9310_FAMILY_ID)
902 sw_w32(BIT(4), priv->r->vlan_port_tag_sts_ctrl + (port << 2));
903 else
904 sw_w32(1, priv->r->vlan_port_tag_sts_ctrl + (port << 2));
905
906 if (dsa_is_cpu_port(ds, port))
907 return 0;
908
909 /* add port to switch mask of CPU_PORT */
910 priv->r->traffic_enable(priv->cpu_port, port);
911
912 /* add all other ports in the same bridge to switch mask of port */
913 v = priv->r->traffic_get(port);
914 v |= priv->ports[port].pm;
915 priv->r->traffic_set(port, v);
916
917 // TODO: Figure out if this is necessary
918 if (priv->family_id == RTL9300_FAMILY_ID) {
919 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_SABLK_CTRL);
920 sw_w32_mask(0, BIT(port), RTL930X_L2_PORT_DABLK_CTRL);
921 }
922
923 priv->ports[port].sds_num = rtl93xx_get_sds(phydev);
924
925 return 0;
926 }
927
928 static void rtl83xx_port_disable(struct dsa_switch *ds, int port)
929 {
930 struct rtl838x_switch_priv *priv = ds->priv;
931 u64 v;
932
933 pr_debug("%s %x: %d", __func__, (u32)priv, port);
934 /* you can only disable user ports */
935 if (!dsa_is_user_port(ds, port))
936 return;
937
938 // BUG: This does not work on RTL931X
939 /* remove port from switch mask of CPU_PORT */
940 priv->r->traffic_disable(priv->cpu_port, port);
941
942 /* remove all other ports in the same bridge from switch mask of port */
943 v = priv->r->traffic_get(port);
944 v &= ~priv->ports[port].pm;
945 priv->r->traffic_set(port, v);
946
947 priv->ports[port].enable = false;
948 }
949
950 static int rtl83xx_set_mac_eee(struct dsa_switch *ds, int port,
951 struct ethtool_eee *e)
952 {
953 struct rtl838x_switch_priv *priv = ds->priv;
954
955 if (e->eee_enabled && !priv->eee_enabled) {
956 pr_info("Globally enabling EEE\n");
957 priv->r->init_eee(priv, true);
958 }
959
960 priv->r->port_eee_set(priv, port, e->eee_enabled);
961
962 if (e->eee_enabled)
963 pr_info("Enabled EEE for port %d\n", port);
964 else
965 pr_info("Disabled EEE for port %d\n", port);
966 return 0;
967 }
968
969 static int rtl83xx_get_mac_eee(struct dsa_switch *ds, int port,
970 struct ethtool_eee *e)
971 {
972 struct rtl838x_switch_priv *priv = ds->priv;
973
974 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full;
975
976 priv->r->eee_port_ability(priv, e, port);
977
978 e->eee_enabled = priv->ports[port].eee_enabled;
979
980 e->eee_active = !!(e->advertised & e->lp_advertised);
981
982 return 0;
983 }
984
985 static int rtl93xx_get_mac_eee(struct dsa_switch *ds, int port,
986 struct ethtool_eee *e)
987 {
988 struct rtl838x_switch_priv *priv = ds->priv;
989
990 e->supported = SUPPORTED_100baseT_Full | SUPPORTED_1000baseT_Full
991 | SUPPORTED_2500baseX_Full;
992
993 priv->r->eee_port_ability(priv, e, port);
994
995 e->eee_enabled = priv->ports[port].eee_enabled;
996
997 e->eee_active = !!(e->advertised & e->lp_advertised);
998
999 return 0;
1000 }
1001
1002 /*
1003 * Set Switch L2 Aging time, t is time in milliseconds
1004 * t = 0: aging is disabled
1005 */
1006 static int rtl83xx_set_l2aging(struct dsa_switch *ds, u32 t)
1007 {
1008 struct rtl838x_switch_priv *priv = ds->priv;
1009 int t_max = priv->family_id == RTL8380_FAMILY_ID ? 0x7fffff : 0x1FFFFF;
1010
1011 /* Convert time in mseconds to internal value */
1012 if (t > 0x10000000) { /* Set to maximum */
1013 t = t_max;
1014 } else {
1015 if (priv->family_id == RTL8380_FAMILY_ID)
1016 t = ((t * 625) / 1000 + 127) / 128;
1017 else
1018 t = (t * 5 + 2) / 3;
1019 }
1020 sw_w32(t, priv->r->l2_ctrl_1);
1021 return 0;
1022 }
1023
1024 static int rtl83xx_port_bridge_join(struct dsa_switch *ds, int port,
1025 struct net_device *bridge)
1026 {
1027 struct rtl838x_switch_priv *priv = ds->priv;
1028 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1029 int i;
1030
1031 pr_debug("%s %x: %d %llx", __func__, (u32)priv, port, port_bitmap);
1032 mutex_lock(&priv->reg_mutex);
1033 for (i = 0; i < ds->num_ports; i++) {
1034 /* Add this port to the port matrix of the other ports in the
1035 * same bridge. If the port is disabled, port matrix is kept
1036 * and not being setup until the port becomes enabled.
1037 */
1038 if (dsa_is_user_port(ds, i) && i != port) {
1039 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1040 continue;
1041 if (priv->ports[i].enable)
1042 priv->r->traffic_enable(i, port);
1043
1044 priv->ports[i].pm |= BIT_ULL(port);
1045 port_bitmap |= BIT_ULL(i);
1046 }
1047 }
1048
1049 /* Add all other ports to this port matrix. */
1050 if (priv->ports[port].enable) {
1051 priv->r->traffic_enable(priv->cpu_port, port);
1052 v = priv->r->traffic_get(port);
1053 v |= port_bitmap;
1054 priv->r->traffic_set(port, v);
1055 }
1056 priv->ports[port].pm |= port_bitmap;
1057 mutex_unlock(&priv->reg_mutex);
1058
1059 return 0;
1060 }
1061
1062 static void rtl83xx_port_bridge_leave(struct dsa_switch *ds, int port,
1063 struct net_device *bridge)
1064 {
1065 struct rtl838x_switch_priv *priv = ds->priv;
1066 u64 port_bitmap = BIT_ULL(priv->cpu_port), v;
1067 int i;
1068
1069 pr_debug("%s %x: %d", __func__, (u32)priv, port);
1070 mutex_lock(&priv->reg_mutex);
1071 for (i = 0; i < ds->num_ports; i++) {
1072 /* Remove this port from the port matrix of the other ports
1073 * in the same bridge. If the port is disabled, port matrix
1074 * is kept and not being setup until the port becomes enabled.
1075 * And the other port's port matrix cannot be broken when the
1076 * other port is still a VLAN-aware port.
1077 */
1078 if (dsa_is_user_port(ds, i) && i != port) {
1079 if (dsa_to_port(ds, i)->bridge_dev != bridge)
1080 continue;
1081 if (priv->ports[i].enable)
1082 priv->r->traffic_disable(i, port);
1083
1084 priv->ports[i].pm |= BIT_ULL(port);
1085 port_bitmap &= ~BIT_ULL(i);
1086 }
1087 }
1088
1089 /* Add all other ports to this port matrix. */
1090 if (priv->ports[port].enable) {
1091 v = priv->r->traffic_get(port);
1092 v |= port_bitmap;
1093 priv->r->traffic_set(port, v);
1094 }
1095 priv->ports[port].pm &= ~port_bitmap;
1096
1097 mutex_unlock(&priv->reg_mutex);
1098 }
1099
1100 void rtl83xx_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
1101 {
1102 u32 msti = 0;
1103 u32 port_state[4];
1104 int index, bit;
1105 int pos = port;
1106 struct rtl838x_switch_priv *priv = ds->priv;
1107 int n = priv->port_width << 1;
1108
1109 /* Ports above or equal CPU port can never be configured */
1110 if (port >= priv->cpu_port)
1111 return;
1112
1113 mutex_lock(&priv->reg_mutex);
1114
1115 /* For the RTL839x and following, the bits are left-aligned, 838x and 930x
1116 * have 64 bit fields, 839x and 931x have 128 bit fields
1117 */
1118 if (priv->family_id == RTL8390_FAMILY_ID)
1119 pos += 12;
1120 if (priv->family_id == RTL9300_FAMILY_ID)
1121 pos += 3;
1122 if (priv->family_id == RTL9310_FAMILY_ID)
1123 pos += 8;
1124
1125 index = n - (pos >> 4) - 1;
1126 bit = (pos << 1) % 32;
1127
1128 priv->r->stp_get(priv, msti, port_state);
1129
1130 pr_debug("Current state, port %d: %d\n", port, (port_state[index] >> bit) & 3);
1131 port_state[index] &= ~(3 << bit);
1132
1133 switch (state) {
1134 case BR_STATE_DISABLED: /* 0 */
1135 port_state[index] |= (0 << bit);
1136 break;
1137 case BR_STATE_BLOCKING: /* 4 */
1138 case BR_STATE_LISTENING: /* 1 */
1139 port_state[index] |= (1 << bit);
1140 break;
1141 case BR_STATE_LEARNING: /* 2 */
1142 port_state[index] |= (2 << bit);
1143 break;
1144 case BR_STATE_FORWARDING: /* 3*/
1145 port_state[index] |= (3 << bit);
1146 default:
1147 break;
1148 }
1149
1150 priv->r->stp_set(priv, msti, port_state);
1151
1152 mutex_unlock(&priv->reg_mutex);
1153 }
1154
1155 void rtl83xx_fast_age(struct dsa_switch *ds, int port)
1156 {
1157 struct rtl838x_switch_priv *priv = ds->priv;
1158 int s = priv->family_id == RTL8390_FAMILY_ID ? 2 : 0;
1159
1160 pr_debug("FAST AGE port %d\n", port);
1161 mutex_lock(&priv->reg_mutex);
1162 /* RTL838X_L2_TBL_FLUSH_CTRL register bits, 839x has 1 bit larger
1163 * port fields:
1164 * 0-4: Replacing port
1165 * 5-9: Flushed/replaced port
1166 * 10-21: FVID
1167 * 22: Entry types: 1: dynamic, 0: also static
1168 * 23: Match flush port
1169 * 24: Match FVID
1170 * 25: Flush (0) or replace (1) L2 entries
1171 * 26: Status of action (1: Start, 0: Done)
1172 */
1173 sw_w32(1 << (26 + s) | 1 << (23 + s) | port << (5 + (s / 2)), priv->r->l2_tbl_flush_ctrl);
1174
1175 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(26 + s));
1176
1177 mutex_unlock(&priv->reg_mutex);
1178 }
1179
1180 void rtl930x_fast_age(struct dsa_switch *ds, int port)
1181 {
1182 struct rtl838x_switch_priv *priv = ds->priv;
1183
1184 pr_debug("FAST AGE port %d\n", port);
1185 mutex_lock(&priv->reg_mutex);
1186 sw_w32(port << 11, RTL930X_L2_TBL_FLUSH_CTRL + 4);
1187
1188 sw_w32(BIT(26) | BIT(30), RTL930X_L2_TBL_FLUSH_CTRL);
1189
1190 do { } while (sw_r32(priv->r->l2_tbl_flush_ctrl) & BIT(30));
1191
1192 mutex_unlock(&priv->reg_mutex);
1193 }
1194
1195 static int rtl83xx_vlan_filtering(struct dsa_switch *ds, int port,
1196 bool vlan_filtering,
1197 struct switchdev_trans *trans)
1198 {
1199 struct rtl838x_switch_priv *priv = ds->priv;
1200
1201 pr_debug("%s: port %d\n", __func__, port);
1202 mutex_lock(&priv->reg_mutex);
1203
1204 if (vlan_filtering) {
1205 /* Enable ingress and egress filtering
1206 * The VLAN_PORT_IGR_FILTER register uses 2 bits for each port to define
1207 * the filter action:
1208 * 0: Always Forward
1209 * 1: Drop packet
1210 * 2: Trap packet to CPU port
1211 * The Egress filter used 1 bit per state (0: DISABLED, 1: ENABLED)
1212 */
1213 if (port != priv->cpu_port)
1214 sw_w32_mask(0b10 << ((port % 16) << 1), 0b01 << ((port % 16) << 1),
1215 priv->r->vlan_port_igr_filter + ((port >> 4) << 2));
1216 sw_w32_mask(0, BIT(port % 32), priv->r->vlan_port_egr_filter + ((port >> 5) << 2));
1217 } else {
1218 /* Disable ingress and egress filtering */
1219 if (port != priv->cpu_port)
1220 sw_w32_mask(0b11 << ((port % 16) << 1), 0,
1221 priv->r->vlan_port_igr_filter + ((port >> 4) << 2));
1222 sw_w32_mask(BIT(port % 32), 0, priv->r->vlan_port_egr_filter + ((port >> 5) << 2));
1223 }
1224
1225 /* Do we need to do something to the CPU-Port, too? */
1226 mutex_unlock(&priv->reg_mutex);
1227
1228 return 0;
1229 }
1230
1231 static int rtl83xx_vlan_prepare(struct dsa_switch *ds, int port,
1232 const struct switchdev_obj_port_vlan *vlan)
1233 {
1234 struct rtl838x_vlan_info info;
1235 struct rtl838x_switch_priv *priv = ds->priv;
1236
1237 priv->r->vlan_tables_read(0, &info);
1238
1239 pr_debug("VLAN 0: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1240 info.tagged_ports, info.untagged_ports, info.profile_id,
1241 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1242
1243 priv->r->vlan_tables_read(1, &info);
1244 pr_debug("VLAN 1: Tagged ports %llx, untag %llx, profile %d, MC# %d, UC# %d, FID %x\n",
1245 info.tagged_ports, info.untagged_ports, info.profile_id,
1246 info.hash_mc_fid, info.hash_uc_fid, info.fid);
1247 priv->r->vlan_set_untagged(1, info.untagged_ports);
1248 pr_debug("SET: Untagged ports, VLAN %d: %llx\n", 1, info.untagged_ports);
1249
1250 priv->r->vlan_set_tagged(1, &info);
1251 pr_debug("SET: Tagged ports, VLAN %d: %llx\n", 1, info.tagged_ports);
1252
1253 mutex_unlock(&priv->reg_mutex);
1254 return 0;
1255 }
1256
1257 static void rtl83xx_vlan_add(struct dsa_switch *ds, int port,
1258 const struct switchdev_obj_port_vlan *vlan)
1259 {
1260 struct rtl838x_vlan_info info;
1261 struct rtl838x_switch_priv *priv = ds->priv;
1262 int v;
1263
1264 pr_debug("%s port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1265 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1266
1267 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1268 dev_err(priv->dev, "VLAN out of range: %d - %d",
1269 vlan->vid_begin, vlan->vid_end);
1270 return;
1271 }
1272
1273 mutex_lock(&priv->reg_mutex);
1274
1275 if (vlan->flags & BRIDGE_VLAN_INFO_PVID) {
1276 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1277 if (!v)
1278 continue;
1279 /* Set both inner and outer PVID of the port */
1280 sw_w32((v << 16) | v << 2, priv->r->vlan_port_pb + (port << 2));
1281 priv->ports[port].pvid = vlan->vid_end;
1282 }
1283 }
1284
1285 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1286 /* Get port memberships of this vlan */
1287 priv->r->vlan_tables_read(v, &info);
1288
1289 /* new VLAN? */
1290 if (!info.tagged_ports) {
1291 info.fid = 0;
1292 info.hash_mc_fid = false;
1293 info.hash_uc_fid = false;
1294 info.profile_id = 0;
1295 }
1296
1297 /* sanitize untagged_ports - must be a subset */
1298 if (info.untagged_ports & ~info.tagged_ports)
1299 info.untagged_ports = 0;
1300
1301 info.tagged_ports |= BIT_ULL(port);
1302 if (vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED)
1303 info.untagged_ports |= BIT_ULL(port);
1304
1305 priv->r->vlan_set_untagged(v, info.untagged_ports);
1306 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1307
1308 priv->r->vlan_set_tagged(v, &info);
1309 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1310 }
1311
1312 mutex_unlock(&priv->reg_mutex);
1313 }
1314
1315 static int rtl83xx_vlan_del(struct dsa_switch *ds, int port,
1316 const struct switchdev_obj_port_vlan *vlan)
1317 {
1318 struct rtl838x_vlan_info info;
1319 struct rtl838x_switch_priv *priv = ds->priv;
1320 int v;
1321 u16 pvid;
1322
1323 pr_debug("%s: port %d, vid_end %d, vid_end %d, flags %x\n", __func__,
1324 port, vlan->vid_begin, vlan->vid_end, vlan->flags);
1325
1326 if (vlan->vid_begin > 4095 || vlan->vid_end > 4095) {
1327 dev_err(priv->dev, "VLAN out of range: %d - %d",
1328 vlan->vid_begin, vlan->vid_end);
1329 return -ENOTSUPP;
1330 }
1331
1332 mutex_lock(&priv->reg_mutex);
1333 pvid = priv->ports[port].pvid;
1334
1335 for (v = vlan->vid_begin; v <= vlan->vid_end; v++) {
1336 /* Reset to default if removing the current PVID */
1337 if (v == pvid)
1338 sw_w32(0, priv->r->vlan_port_pb + (port << 2));
1339
1340 /* Get port memberships of this vlan */
1341 priv->r->vlan_tables_read(v, &info);
1342
1343 /* remove port from both tables */
1344 info.untagged_ports &= (~BIT_ULL(port));
1345 info.tagged_ports &= (~BIT_ULL(port));
1346
1347 priv->r->vlan_set_untagged(v, info.untagged_ports);
1348 pr_debug("Untagged ports, VLAN %d: %llx\n", v, info.untagged_ports);
1349
1350 priv->r->vlan_set_tagged(v, &info);
1351 pr_debug("Tagged ports, VLAN %d: %llx\n", v, info.tagged_ports);
1352 }
1353 mutex_unlock(&priv->reg_mutex);
1354
1355 return 0;
1356 }
1357
1358 static void dump_l2_entry(struct rtl838x_l2_entry *e)
1359 {
1360 pr_info("MAC: %02x:%02x:%02x:%02x:%02x:%02x vid: %d, rvid: %d, port: %d, valid: %d\n",
1361 e->mac[0], e->mac[1], e->mac[2], e->mac[3], e->mac[4], e->mac[5],
1362 e->vid, e->rvid, e->port, e->valid);
1363
1364 if (e->type != L2_MULTICAST) {
1365 pr_info("Type: %d, is_static: %d, is_ip_mc: %d, is_ipv6_mc: %d, block_da: %d\n",
1366 e->type, e->is_static, e->is_ip_mc, e->is_ipv6_mc, e->block_da);
1367 pr_info(" block_sa: %d, susp: %d, nh: %d, age: %d, is_trunk: %d, trunk: %d\n",
1368 e->block_sa, e->suspended, e->next_hop, e->age, e->is_trunk, e->trunk);
1369 }
1370 if (e->type == L2_MULTICAST)
1371 pr_info(" L2_MULTICAST mc_portmask_index: %d\n", e->mc_portmask_index);
1372 if (e->is_ip_mc || e->is_ipv6_mc)
1373 pr_info(" mc_portmask_index: %d, mc_gip: %d, mc_sip: %d\n",
1374 e->mc_portmask_index, e->mc_gip, e->mc_sip);
1375 pr_info(" stack_dev: %d\n", e->stack_dev);
1376 if (e->next_hop)
1377 pr_info(" nh_route_id: %d\n", e->nh_route_id);
1378 }
1379
1380 static void rtl83xx_setup_l2_uc_entry(struct rtl838x_l2_entry *e, int port, int vid, u64 mac)
1381 {
1382 e->is_ip_mc = e->is_ipv6_mc = false;
1383 e->valid = true;
1384 e->age = 3;
1385 e->port = port,
1386 e->vid = vid;
1387 u64_to_ether_addr(mac, e->mac);
1388 }
1389
1390 static void rtl83xx_setup_l2_mc_entry(struct rtl838x_switch_priv *priv,
1391 struct rtl838x_l2_entry *e, int vid, u64 mac, int mc_group)
1392 {
1393 e->is_ip_mc = e->is_ipv6_mc = false;
1394 e->valid = true;
1395 e->mc_portmask_index = mc_group;
1396 e->type = L2_MULTICAST;
1397 e->rvid = e->vid = vid;
1398 pr_debug("%s: vid: %d, rvid: %d\n", __func__, e->vid, e->rvid);
1399 u64_to_ether_addr(mac, e->mac);
1400 }
1401
1402 /*
1403 * Uses the seed to identify a hash bucket in the L2 using the derived hash key and then loops
1404 * over the entries in the bucket until either a matching entry is found or an empty slot
1405 * Returns the filled in rtl838x_l2_entry and the index in the bucket when an entry was found
1406 * when an empty slot was found and must exist is false, the index of the slot is returned
1407 * when no slots are available returns -1
1408 */
1409 static int rtl83xx_find_l2_hash_entry(struct rtl838x_switch_priv *priv, u64 seed,
1410 bool must_exist, struct rtl838x_l2_entry *e)
1411 {
1412 int i, idx = -1;
1413 u32 key = priv->r->l2_hash_key(priv, seed);
1414 u64 entry;
1415
1416 pr_debug("%s: using key %x, for seed %016llx\n", __func__, key, seed);
1417 // Loop over all entries in the hash-bucket and over the second block on 93xx SoCs
1418 for (i = 0; i < priv->l2_bucket_size; i++) {
1419 entry = priv->r->read_l2_entry_using_hash(key, i, e);
1420 pr_debug("valid %d, mac %016llx\n", e->valid, ether_addr_to_u64(&e->mac[0]));
1421 if (must_exist && !e->valid)
1422 continue;
1423 if (!e->valid || ((entry & 0x0fffffffffffffffULL) == seed)) {
1424 idx = i > 3 ? ((key >> 14) & 0xffff) | i >> 1 : ((key << 2) | i) & 0xffff;
1425 break;
1426 }
1427 }
1428
1429 return idx;
1430 }
1431
1432 /*
1433 * Uses the seed to identify an entry in the CAM by looping over all its entries
1434 * Returns the filled in rtl838x_l2_entry and the index in the CAM when an entry was found
1435 * when an empty slot was found the index of the slot is returned
1436 * when no slots are available returns -1
1437 */
1438 static int rtl83xx_find_l2_cam_entry(struct rtl838x_switch_priv *priv, u64 seed,
1439 bool must_exist, struct rtl838x_l2_entry *e)
1440 {
1441 int i, idx = -1;
1442 u64 entry;
1443
1444 for (i = 0; i < 64; i++) {
1445 entry = priv->r->read_cam(i, e);
1446 if (!must_exist && !e->valid) {
1447 if (idx < 0) /* First empty entry? */
1448 idx = i;
1449 break;
1450 } else if ((entry & 0x0fffffffffffffffULL) == seed) {
1451 pr_debug("Found entry in CAM\n");
1452 idx = i;
1453 break;
1454 }
1455 }
1456 return idx;
1457 }
1458
1459 static int rtl83xx_port_fdb_add(struct dsa_switch *ds, int port,
1460 const unsigned char *addr, u16 vid)
1461 {
1462 struct rtl838x_switch_priv *priv = ds->priv;
1463 u64 mac = ether_addr_to_u64(addr);
1464 struct rtl838x_l2_entry e;
1465 int err = 0, idx;
1466 u64 seed = priv->r->l2_hash_seed(mac, vid);
1467
1468 mutex_lock(&priv->reg_mutex);
1469
1470 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1471
1472 // Found an existing or empty entry
1473 if (idx >= 0) {
1474 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1475 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1476 goto out;
1477 }
1478
1479 // Hash buckets full, try CAM
1480 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1481
1482 if (idx >= 0) {
1483 rtl83xx_setup_l2_uc_entry(&e, port, vid, mac);
1484 priv->r->write_cam(idx, &e);
1485 goto out;
1486 }
1487
1488 err = -ENOTSUPP;
1489 out:
1490 mutex_unlock(&priv->reg_mutex);
1491 return err;
1492 }
1493
1494 static int rtl83xx_port_fdb_del(struct dsa_switch *ds, int port,
1495 const unsigned char *addr, u16 vid)
1496 {
1497 struct rtl838x_switch_priv *priv = ds->priv;
1498 u64 mac = ether_addr_to_u64(addr);
1499 struct rtl838x_l2_entry e;
1500 int err = 0, idx;
1501 u64 seed = priv->r->l2_hash_seed(mac, vid);
1502
1503 pr_info("In %s, mac %llx, vid: %d\n", __func__, mac, vid);
1504 mutex_lock(&priv->reg_mutex);
1505
1506 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1507
1508 pr_info("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1509 if (idx >= 0) {
1510 e.valid = false;
1511 dump_l2_entry(&e);
1512 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1513 goto out;
1514 }
1515
1516 /* Check CAM for spillover from hash buckets */
1517 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1518
1519 if (idx >= 0) {
1520 e.valid = false;
1521 priv->r->write_cam(idx, &e);
1522 goto out;
1523 }
1524 err = -ENOENT;
1525 out:
1526 mutex_unlock(&priv->reg_mutex);
1527 return err;
1528 }
1529
1530 static int rtl83xx_port_fdb_dump(struct dsa_switch *ds, int port,
1531 dsa_fdb_dump_cb_t *cb, void *data)
1532 {
1533 struct rtl838x_l2_entry e;
1534 struct rtl838x_switch_priv *priv = ds->priv;
1535 int i;
1536 u32 fid, pkey;
1537 u64 mac;
1538
1539 mutex_lock(&priv->reg_mutex);
1540
1541 for (i = 0; i < priv->fib_entries; i++) {
1542 priv->r->read_l2_entry_using_hash(i >> 2, i & 0x3, &e);
1543
1544 if (!e.valid)
1545 continue;
1546
1547 if (e.port == port || e.port == RTL930X_PORT_IGNORE) {
1548 u64 seed;
1549 u32 key;
1550
1551 fid = ((i >> 2) & 0x3ff) | (e.rvid & ~0x3ff);
1552 mac = ether_addr_to_u64(&e.mac[0]);
1553 pkey = priv->r->l2_hash_key(priv, priv->r->l2_hash_seed(mac, fid));
1554 fid = (pkey & 0x3ff) | (fid & ~0x3ff);
1555 pr_info("-> index %d, key %x, bucket %d, dmac %016llx, fid: %x rvid: %x\n",
1556 i, i >> 2, i & 0x3, mac, fid, e.rvid);
1557 dump_l2_entry(&e);
1558 seed = priv->r->l2_hash_seed(mac, e.rvid);
1559 key = priv->r->l2_hash_key(priv, seed);
1560 pr_info("seed: %016llx, key based on rvid: %08x\n", seed, key);
1561 cb(e.mac, e.vid, e.is_static, data);
1562 }
1563 if (e.type == L2_MULTICAST) {
1564 u64 portmask = priv->r->read_mcast_pmask(e.mc_portmask_index);
1565
1566 if (portmask & BIT_ULL(port)) {
1567 dump_l2_entry(&e);
1568 pr_info(" PM: %016llx\n", portmask);
1569 }
1570 }
1571 }
1572
1573 for (i = 0; i < 64; i++) {
1574 priv->r->read_cam(i, &e);
1575
1576 if (!e.valid)
1577 continue;
1578
1579 if (e.port == port)
1580 cb(e.mac, e.vid, e.is_static, data);
1581 }
1582
1583 mutex_unlock(&priv->reg_mutex);
1584 return 0;
1585 }
1586
1587 static int rtl83xx_port_mdb_prepare(struct dsa_switch *ds, int port,
1588 const struct switchdev_obj_port_mdb *mdb)
1589 {
1590 struct rtl838x_switch_priv *priv = ds->priv;
1591
1592 if (priv->id >= 0x9300)
1593 return -EOPNOTSUPP;
1594
1595 return 0;
1596 }
1597
1598 static int rtl83xx_mc_group_alloc(struct rtl838x_switch_priv *priv, int port)
1599 {
1600 int mc_group = find_first_zero_bit(priv->mc_group_bm, MAX_MC_GROUPS - 1);
1601 u64 portmask;
1602
1603 if (mc_group >= MAX_MC_GROUPS - 1)
1604 return -1;
1605
1606 pr_debug("Using MC group %d\n", mc_group);
1607 set_bit(mc_group, priv->mc_group_bm);
1608 mc_group++; // We cannot use group 0, as this is used for lookup miss flooding
1609 portmask = BIT_ULL(port);
1610 priv->r->write_mcast_pmask(mc_group, portmask);
1611
1612 return mc_group;
1613 }
1614
1615 static u64 rtl83xx_mc_group_add_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1616 {
1617 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1618
1619 portmask |= BIT_ULL(port);
1620 priv->r->write_mcast_pmask(mc_group, portmask);
1621
1622 return portmask;
1623 }
1624
1625 static u64 rtl83xx_mc_group_del_port(struct rtl838x_switch_priv *priv, int mc_group, int port)
1626 {
1627 u64 portmask = priv->r->read_mcast_pmask(mc_group);
1628
1629 portmask &= ~BIT_ULL(port);
1630 priv->r->write_mcast_pmask(mc_group, portmask);
1631 if (!portmask)
1632 clear_bit(mc_group, priv->mc_group_bm);
1633
1634 return portmask;
1635 }
1636
1637 static void rtl83xx_port_mdb_add(struct dsa_switch *ds, int port,
1638 const struct switchdev_obj_port_mdb *mdb)
1639 {
1640 struct rtl838x_switch_priv *priv = ds->priv;
1641 u64 mac = ether_addr_to_u64(mdb->addr);
1642 struct rtl838x_l2_entry e;
1643 int err = 0, idx;
1644 int vid = mdb->vid;
1645 u64 seed = priv->r->l2_hash_seed(mac, vid);
1646 int mc_group;
1647
1648 pr_debug("In %s port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1649 mutex_lock(&priv->reg_mutex);
1650
1651 idx = rtl83xx_find_l2_hash_entry(priv, seed, false, &e);
1652
1653 // Found an existing or empty entry
1654 if (idx >= 0) {
1655 if (e.valid) {
1656 pr_debug("Found an existing entry %016llx, mc_group %d\n",
1657 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1658 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1659 } else {
1660 pr_debug("New entry for seed %016llx\n", seed);
1661 mc_group = rtl83xx_mc_group_alloc(priv, port);
1662 if (mc_group < 0) {
1663 err = -ENOTSUPP;
1664 goto out;
1665 }
1666 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1667 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1668 }
1669 goto out;
1670 }
1671
1672 // Hash buckets full, try CAM
1673 rtl83xx_find_l2_cam_entry(priv, seed, false, &e);
1674
1675 if (idx >= 0) {
1676 if (e.valid) {
1677 pr_debug("Found existing CAM entry %016llx, mc_group %d\n",
1678 ether_addr_to_u64(e.mac), e.mc_portmask_index);
1679 rtl83xx_mc_group_add_port(priv, e.mc_portmask_index, port);
1680 } else {
1681 pr_debug("New entry\n");
1682 mc_group = rtl83xx_mc_group_alloc(priv, port);
1683 if (mc_group < 0) {
1684 err = -ENOTSUPP;
1685 goto out;
1686 }
1687 rtl83xx_setup_l2_mc_entry(priv, &e, vid, mac, mc_group);
1688 priv->r->write_cam(idx, &e);
1689 }
1690 goto out;
1691 }
1692
1693 err = -ENOTSUPP;
1694 out:
1695 mutex_unlock(&priv->reg_mutex);
1696 if (err)
1697 dev_err(ds->dev, "failed to add MDB entry\n");
1698 }
1699
1700 int rtl83xx_port_mdb_del(struct dsa_switch *ds, int port,
1701 const struct switchdev_obj_port_mdb *mdb)
1702 {
1703 struct rtl838x_switch_priv *priv = ds->priv;
1704 u64 mac = ether_addr_to_u64(mdb->addr);
1705 struct rtl838x_l2_entry e;
1706 int err = 0, idx;
1707 int vid = mdb->vid;
1708 u64 seed = priv->r->l2_hash_seed(mac, vid);
1709 u64 portmask;
1710
1711 pr_debug("In %s, port %d, mac %llx, vid: %d\n", __func__, port, mac, vid);
1712 mutex_lock(&priv->reg_mutex);
1713
1714 idx = rtl83xx_find_l2_hash_entry(priv, seed, true, &e);
1715
1716 pr_debug("Found entry index %d, key %d and bucket %d\n", idx, idx >> 2, idx & 3);
1717 if (idx >= 0) {
1718 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1719 if (!portmask) {
1720 e.valid = false;
1721 // dump_l2_entry(&e);
1722 priv->r->write_l2_entry_using_hash(idx >> 2, idx & 0x3, &e);
1723 }
1724 goto out;
1725 }
1726
1727 /* Check CAM for spillover from hash buckets */
1728 rtl83xx_find_l2_cam_entry(priv, seed, true, &e);
1729
1730 if (idx >= 0) {
1731 portmask = rtl83xx_mc_group_del_port(priv, e.mc_portmask_index, port);
1732 if (!portmask) {
1733 e.valid = false;
1734 // dump_l2_entry(&e);
1735 priv->r->write_cam(idx, &e);
1736 }
1737 goto out;
1738 }
1739 // TODO: Re-enable with a newer kernel: err = -ENOENT;
1740 out:
1741 mutex_unlock(&priv->reg_mutex);
1742 return err;
1743 }
1744
1745 static int rtl83xx_port_mirror_add(struct dsa_switch *ds, int port,
1746 struct dsa_mall_mirror_tc_entry *mirror,
1747 bool ingress)
1748 {
1749 /* We support 4 mirror groups, one destination port per group */
1750 int group;
1751 struct rtl838x_switch_priv *priv = ds->priv;
1752 int ctrl_reg, dpm_reg, spm_reg;
1753
1754 pr_debug("In %s\n", __func__);
1755
1756 for (group = 0; group < 4; group++) {
1757 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1758 break;
1759 }
1760 if (group >= 4) {
1761 for (group = 0; group < 4; group++) {
1762 if (priv->mirror_group_ports[group] < 0)
1763 break;
1764 }
1765 }
1766
1767 if (group >= 4)
1768 return -ENOSPC;
1769
1770 ctrl_reg = priv->r->mir_ctrl + group * 4;
1771 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1772 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1773
1774 pr_debug("Using group %d\n", group);
1775 mutex_lock(&priv->reg_mutex);
1776
1777 if (priv->family_id == RTL8380_FAMILY_ID) {
1778 /* Enable mirroring to port across VLANs (bit 11) */
1779 sw_w32(1 << 11 | (mirror->to_local_port << 4) | 1, ctrl_reg);
1780 } else {
1781 /* Enable mirroring to destination port */
1782 sw_w32((mirror->to_local_port << 4) | 1, ctrl_reg);
1783 }
1784
1785 if (ingress && (priv->r->get_port_reg_be(spm_reg) & (1ULL << port))) {
1786 mutex_unlock(&priv->reg_mutex);
1787 return -EEXIST;
1788 }
1789 if ((!ingress) && (priv->r->get_port_reg_be(dpm_reg) & (1ULL << port))) {
1790 mutex_unlock(&priv->reg_mutex);
1791 return -EEXIST;
1792 }
1793
1794 if (ingress)
1795 priv->r->mask_port_reg_be(0, 1ULL << port, spm_reg);
1796 else
1797 priv->r->mask_port_reg_be(0, 1ULL << port, dpm_reg);
1798
1799 priv->mirror_group_ports[group] = mirror->to_local_port;
1800 mutex_unlock(&priv->reg_mutex);
1801 return 0;
1802 }
1803
1804 static void rtl83xx_port_mirror_del(struct dsa_switch *ds, int port,
1805 struct dsa_mall_mirror_tc_entry *mirror)
1806 {
1807 int group = 0;
1808 struct rtl838x_switch_priv *priv = ds->priv;
1809 int ctrl_reg, dpm_reg, spm_reg;
1810
1811 pr_debug("In %s\n", __func__);
1812 for (group = 0; group < 4; group++) {
1813 if (priv->mirror_group_ports[group] == mirror->to_local_port)
1814 break;
1815 }
1816 if (group >= 4)
1817 return;
1818
1819 ctrl_reg = priv->r->mir_ctrl + group * 4;
1820 dpm_reg = priv->r->mir_dpm + group * 4 * priv->port_width;
1821 spm_reg = priv->r->mir_spm + group * 4 * priv->port_width;
1822
1823 mutex_lock(&priv->reg_mutex);
1824 if (mirror->ingress) {
1825 /* Ingress, clear source port matrix */
1826 priv->r->mask_port_reg_be(1ULL << port, 0, spm_reg);
1827 } else {
1828 /* Egress, clear destination port matrix */
1829 priv->r->mask_port_reg_be(1ULL << port, 0, dpm_reg);
1830 }
1831
1832 if (!(sw_r32(spm_reg) || sw_r32(dpm_reg))) {
1833 priv->mirror_group_ports[group] = -1;
1834 sw_w32(0, ctrl_reg);
1835 }
1836
1837 mutex_unlock(&priv->reg_mutex);
1838 }
1839
1840 int dsa_phy_read(struct dsa_switch *ds, int phy_addr, int phy_reg)
1841 {
1842 u32 val;
1843 u32 offset = 0;
1844 struct rtl838x_switch_priv *priv = ds->priv;
1845
1846 if (phy_addr >= 24 && phy_addr <= 27
1847 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1848 if (phy_addr == 26)
1849 offset = 0x100;
1850 val = sw_r32(RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2)) & 0xffff;
1851 return val;
1852 }
1853
1854 read_phy(phy_addr, 0, phy_reg, &val);
1855 return val;
1856 }
1857
1858 int dsa_phy_write(struct dsa_switch *ds, int phy_addr, int phy_reg, u16 val)
1859 {
1860 u32 offset = 0;
1861 struct rtl838x_switch_priv *priv = ds->priv;
1862
1863 if (phy_addr >= 24 && phy_addr <= 27
1864 && priv->ports[24].phy == PHY_RTL838X_SDS) {
1865 if (phy_addr == 26)
1866 offset = 0x100;
1867 sw_w32(val, RTL838X_SDS4_FIB_REG0 + offset + (phy_reg << 2));
1868 return 0;
1869 }
1870 return write_phy(phy_addr, 0, phy_reg, val);
1871 }
1872
1873 const struct dsa_switch_ops rtl83xx_switch_ops = {
1874 .get_tag_protocol = rtl83xx_get_tag_protocol,
1875 .setup = rtl83xx_setup,
1876
1877 .phy_read = dsa_phy_read,
1878 .phy_write = dsa_phy_write,
1879
1880 .phylink_validate = rtl83xx_phylink_validate,
1881 .phylink_mac_link_state = rtl83xx_phylink_mac_link_state,
1882 .phylink_mac_config = rtl83xx_phylink_mac_config,
1883 .phylink_mac_link_down = rtl83xx_phylink_mac_link_down,
1884 .phylink_mac_link_up = rtl83xx_phylink_mac_link_up,
1885
1886 .get_strings = rtl83xx_get_strings,
1887 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1888 .get_sset_count = rtl83xx_get_sset_count,
1889
1890 .port_enable = rtl83xx_port_enable,
1891 .port_disable = rtl83xx_port_disable,
1892
1893 .get_mac_eee = rtl83xx_get_mac_eee,
1894 .set_mac_eee = rtl83xx_set_mac_eee,
1895
1896 .set_ageing_time = rtl83xx_set_l2aging,
1897 .port_bridge_join = rtl83xx_port_bridge_join,
1898 .port_bridge_leave = rtl83xx_port_bridge_leave,
1899 .port_stp_state_set = rtl83xx_port_stp_state_set,
1900 .port_fast_age = rtl83xx_fast_age,
1901
1902 .port_vlan_filtering = rtl83xx_vlan_filtering,
1903 .port_vlan_prepare = rtl83xx_vlan_prepare,
1904 .port_vlan_add = rtl83xx_vlan_add,
1905 .port_vlan_del = rtl83xx_vlan_del,
1906
1907 .port_fdb_add = rtl83xx_port_fdb_add,
1908 .port_fdb_del = rtl83xx_port_fdb_del,
1909 .port_fdb_dump = rtl83xx_port_fdb_dump,
1910
1911 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1912 .port_mdb_add = rtl83xx_port_mdb_add,
1913 .port_mdb_del = rtl83xx_port_mdb_del,
1914
1915 .port_mirror_add = rtl83xx_port_mirror_add,
1916 .port_mirror_del = rtl83xx_port_mirror_del,
1917 };
1918
1919 const struct dsa_switch_ops rtl930x_switch_ops = {
1920 .get_tag_protocol = rtl83xx_get_tag_protocol,
1921 .setup = rtl93xx_setup,
1922
1923 .phy_read = dsa_phy_read,
1924 .phy_write = dsa_phy_write,
1925
1926 .phylink_validate = rtl93xx_phylink_validate,
1927 .phylink_mac_link_state = rtl93xx_phylink_mac_link_state,
1928 .phylink_mac_config = rtl93xx_phylink_mac_config,
1929 .phylink_mac_link_down = rtl93xx_phylink_mac_link_down,
1930 .phylink_mac_link_up = rtl93xx_phylink_mac_link_up,
1931
1932 .get_strings = rtl83xx_get_strings,
1933 .get_ethtool_stats = rtl83xx_get_ethtool_stats,
1934 .get_sset_count = rtl83xx_get_sset_count,
1935
1936 .port_enable = rtl83xx_port_enable,
1937 .port_disable = rtl83xx_port_disable,
1938
1939 .get_mac_eee = rtl93xx_get_mac_eee,
1940 .set_mac_eee = rtl83xx_set_mac_eee,
1941
1942 .set_ageing_time = rtl83xx_set_l2aging,
1943 .port_bridge_join = rtl83xx_port_bridge_join,
1944 .port_bridge_leave = rtl83xx_port_bridge_leave,
1945 .port_stp_state_set = rtl83xx_port_stp_state_set,
1946 .port_fast_age = rtl930x_fast_age,
1947
1948 .port_vlan_filtering = rtl83xx_vlan_filtering,
1949 .port_vlan_prepare = rtl83xx_vlan_prepare,
1950 .port_vlan_add = rtl83xx_vlan_add,
1951 .port_vlan_del = rtl83xx_vlan_del,
1952
1953 .port_fdb_add = rtl83xx_port_fdb_add,
1954 .port_fdb_del = rtl83xx_port_fdb_del,
1955 .port_fdb_dump = rtl83xx_port_fdb_dump,
1956
1957 .port_mdb_prepare = rtl83xx_port_mdb_prepare,
1958 .port_mdb_add = rtl83xx_port_mdb_add,
1959 .port_mdb_del = rtl83xx_port_mdb_del,
1960
1961 };
Staging tree of Zoltan Herpai