layerscape: add patches-5.4

[openwrt/staging/wigyori.git] / target / linux / layerscape / patches-5.4 / 806-dma-0006-MLK-15014-dma-fsl-edma-v3-clear-DONE-before-E_SG-ena.patch

diff --git a/target/linux/layerscape/patches-5.4/806-dma-0006-MLK-15014-dma-fsl-edma-v3-clear-DONE-before-E_SG-ena.patch b/target/linux/layerscape/patches-5.4/806-dma-0006-MLK-15014-dma-fsl-edma-v3-clear-DONE-before-E_SG-ena.patch
new file mode 100644 (file)
index 0000000..bb4a83c
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/806-dma-0006-MLK-15014-dma-fsl-edma-v3-clear-DONE-before-E_SG-ena.patch
@@ -0,0 +1,30 @@
+From 03691bf3038250def574c78576a8be39133923fd Mon Sep 17 00:00:00 2001
+From: Robin Gong <yibin.gong@nxp.com>
+Date: Tue, 6 Jun 2017 16:56:49 +0800
+Subject: [PATCH] MLK-15014 dma: fsl-edma-v3: clear DONE before E_SG enabled
+
+Below described in RM, otherwise, channel error status(CHa_ES)
+may be triggered:
+The user must clear the CHa_CSR[DONE] bit before writing the
+TCDa_CSR[MAJORELINK] or TCDa_CSR[ESG] bits.
+
+Signed-off-by: Robin Gong <yibin.gong@nxp.com>
+(cherry picked from commit c4164d0a15306174056c6ff423ba2408dd901fcf)
+---
+ drivers/dma/fsl-edma-v3.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/dma/fsl-edma-v3.c
++++ b/drivers/dma/fsl-edma-v3.c
+@@ -421,6 +421,11 @@ static void fsl_edma3_set_tcd_regs(struc
+ 
+       writel(le32_to_cpu(tcd->dlast_sga), addr + EDMA_TCD_DLAST_SGA);
+ 
++      /* Must clear CHa_CSR[DONE] bit before enable TCDa_CSR[ESG] */
++      if ((EDMA_TCD_CSR_E_SG | le16_to_cpu(tcd->csr)) &&
++              EDMA_CH_CSR_DONE | readl(addr + EDMA_CH_CSR))
++              writel(EDMA_CH_CSR_DONE, addr + EDMA_CH_CSR);
++
+       writew(le16_to_cpu(tcd->csr), addr + EDMA_TCD_CSR);
+ }
+