target/linux/adm5120-2.6/files/include/asm-mips/mach-adm5120/adm5120_switch.h

   1 /*
   2  *  ADM5120 ethernet switch definitions
   3  *
   4  *  This header file defines the hardware registers of the ADM5120 SoC
   5  *  built-in Ethernet switch.
   6  *
   7  *  Copyright (C) 2007 OpenWrt.org
   8  *  Copyright (C) 2007 Gabor Juhos <juhosg at openwrt.org>
   9  *
  10  *  This program is free software; you can redistribute it and/or
  11  *  modify it under the terms of the GNU General Public License
  12  *  as published by the Free Software Foundation; either version 2
  13  *  of the License, or (at your option) any later version.
  14  *
  15  *  This program is distributed in the hope that it will be useful,
  16  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  *  GNU General Public License for more details.
  19  *
  20  *  You should have received a copy of the GNU General Public License
  21  *  along with this program; if not, write to the
  22  *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
  23  *  Boston, MA  02110-1301, USA.
  24  */
  25
  26 #ifndef _ADM5120_SWITCH_H
  27 #define _ADM5120_SWITCH_H
  28
  29 #define BITMASK(len)    ((1 << (len))-1)
  30 #define ONEBIT(at)      (1 << (at))
  31
  32 /* Switch register offsets */
  33 #define SWITCH_REG_CODE         0x0000
  34 #define SWITCH_REG_SOFT_RESET   0x0004
  35 #define SWITCH_REG_MEMCTRL      0x001C
  36 #define SWITCH_REG_CPUP_CONF    0x0024
  37 #define SWITCH_REG_PORT_CONF0   0x0028
  38 #define SWITCH_REG_PORT_CONF1   0x002C
  39 #define SWITCH_REG_PORT_CONF2   0x0030
  40 #define SWITCH_REG_VLAN_G1      0x0040
  41 #define SWITCH_REG_VLAN_G2      0x0044
  42 #define SWITCH_REG_SEND_TRIG    0x0048
  43 #define SWITCH_REG_MAC_WT0      0x0058
  44 #define SWITCH_REG_MAC_WT1      0x005C
  45 #define SWITCH_REG_PHY_CNTL0    0x0068
  46 #define SWITCH_REG_PHY_CNTL1    0x006C
  47 #define SWITCH_REG_PHY_CNTL2    0x007C
  48 #define SWITCH_REG_PHY_CNTL3    0x0080
  49 #define SWITCH_REG_PRI_CNTL     0x0084
  50 #define SWITCH_REG_INT_STATUS   0x00B0
  51 #define SWITCH_REG_INT_MASK     0x00B4
  52 #define SWITCH_REG_GPIO_CONF0   0x00B8
  53 #define SWITCH_REG_GPIO_CONF2   0x00BC
  54 #define SWITCH_REG_WDOG0        0x00C0
  55 #define SWITCH_REG_WDOG1        0x00C4
  56 #define SWITCH_REG_PHY_CNTL4    0x00A0
  57
  58 #define SWITCH_REG_SEND_HBADDR  0x00D0
  59 #define SWITCH_REG_SEND_LBADDR  0x00D4
  60 #define SWITCH_REG_RECV_HBADDR  0x00D8
  61 #define SWITCH_REG_RECV_LBADDR  0x00DC
  62
  63 #define SWITCH_REG_TIMER_INT    0x00F0
  64 #define SWITCH_REG_TIMER        0x00F4
  65
  66 #define SWITCH_REG_PORT0_LED    0x0100
  67 #define SWITCH_REG_PORT1_LED    0x0104
  68 #define SWITCH_REG_PORT2_LED    0x0108
  69 #define SWITCH_REG_PORT3_LED    0x010C
  70 #define SWITCH_REG_PORT4_LED    0x0110
  71
  72 /* CODE register bits */
  73 #define CODE_PC_MASK            BITMASK(16)     /* Product Code */
  74 #define CODE_REV_SHIFT          16
  75 #define CODE_REV_MASK           BITMASK(4)      /* Product Revision */
  76 #define CODE_CLKS_SHIFT         20
  77 #define CODE_CLKS_MASK          BITMASK(2)      /* Clock Speed */
  78 #define CODE_CLKS_175           0               /* 175 MHz */
  79 #define CODE_CLKS_200           1               /* 200 MHz */
  80 #define CODE_CLKS_225           2               /* 225 MHz */
  81 #define CODE_CLKS_250           3               /* 250 MHz */
  82 #define CODE_NAB                ONEBIT(24)      /* NAND boot */
  83 #define CODE_PK_MASK            BITMASK(1)      /* Package type */
  84 #define CODE_PK_SHIFT           29
  85 #define CODE_PK_BGA             0               /* BGA package */
  86 #define CODE_PK_PQFP            1               /* PQFP package */
  87
  88 /* MEMCTRL register bits */
  89 #define MEMCTRL_SDRS_MASK       BITMASK(3)      /* SDRAM bank size */
  90 #define MEMCTRL_SDRS_4M         0x01
  91 #define MEMCTRL_SDRS_8M         0x02
  92 #define MEMCTRL_SDRS_16M        0x03
  93 #define MEMCTRL_SDRS_64M        0x04
  94 #define MEMCTRL_SDRS_128M       0x05
  95 #define MEMCTRL_SDR1_ENABLE     ONEBIT(5)       /* enable SDRAM bank 1 */
  96
  97 #define MEMCTRL_SRS0_SHIFT      8               /* shift for SRAM0 size */
  98 #define MEMCTRL_SRS1_SHIFT      16              /* shift for SRAM1 size */
  99 #define MEMCTRL_SRS_MASK        BITMASK(3)      /* SRAM size mask */
 100 #define MEMCTRL_SRS_DISABLED    0x00            /* Disabled */
 101 #define MEMCTRL_SRS_512K        0x01            /* 512KB*/
 102 #define MEMCTRL_SRS_1M          0x02            /* 1MB */
 103 #define MEMCTRL_SRS_2M          0x03            /* 2MB */
 104 #define MEMCTRL_SRS_4M          0x04            /* 4MB */
 105
 106 /* GPIO_CONF0 register bits */
 107 #define GPIO_CONF0_MASK         BITMASK(8)
 108 #define GPIO_CONF0_IM_SHIFT     0
 109 #define GPIO_CONF0_IV_SHIFT     8
 110 #define GPIO_CONF0_OE_SHIFT     16
 111 #define GPIO_CONF0_OV_SHIFT     24
 112 #define GPIO_CONF0_IM_MASK      (0xFF << GPIO_CONF0_IM_SHIFT)
 113 #define GPIO_CONF0_IV_MASK      (0xFF << GPIO_CONF0_IV_SHIFT)
 114 #define GPIO_CONF0_OE_MASK      (0xFF << GPIO_CONF0_OE_SHIFT)
 115 #define GPIO_CONF0_OV_MASK      (0xFF << GPIO_CONF0_OV_SHIFT)
 116
 117 /* TIMER_INT register bits */
 118 #define TIMER_INT_TOS           ONEBIT(1)       /* time-out status */
 119 #define TIMER_INT_TOM           ONEBIT(16)      /* mask time-out interrupt */
 120
 121 /* TIMER register bits */
 122 #define TIMER_PERIOD_MASK       BITMASK(16)     /* mask for timer period */
 123 #define TIMER_PERIOD_DEFAULT    0xFFFF          /* default timer period */
 124 #define TIMER_TE                ONEBIT(16)      /* timer enable bit */
 125
 126 /* PORTx_LED register bits */
 127 #define LED_MODE_MASK           BITMASK(4)
 128 #define LED_MODE_INPUT          0
 129 #define LED_MODE_FLASH          1
 130 #define LED_MODE_OUT_HIGH       2
 131 #define LED_MODE_OUT_LOW        3
 132 #define LED_MODE_LINK           4
 133 #define LED_MODE_SPEED          5
 134 #define LED_MODE_DUPLEX         6
 135 #define LED_MODE_ACT            7
 136 #define LED_MODE_COLL           8
 137 #define LED_MODE_LINK_ACT       9
 138 #define LED_MODE_DUPLEX_COLL    10
 139 #define LED_MODE_10M_ACT        11
 140 #define LED_MODE_100M_ACT       12
 141 #define LED0_MODE_SHIFT         0       /* LED0 mode shift */
 142 #define LED1_MODE_SHIFT         4       /* LED1 mode shift */
 143 #define LED2_MODE_SHIFT         8       /* LED2 mode shift */
 144 #define LED0_IV_SHIFT           12      /* LED0 input value shift */
 145 #define LED1_IV_SHIFT           13      /* LED1 input value shift */
 146 #define LED2_IV_SHIFT           14      /* LED2 input value shift */
 147
 148 #endif /* _ADM5120_SWITCH_H */