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[adm5120] USB driver cleanups, no it is still not finished
[openwrt/svn-archive/archive.git] / target / linux / adm5120 / files / drivers / usb / host / adm5120-hcd.c
1 /*
2 * OHCI HCD (Host Controller Driver) for USB.
3 *
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
6 *
7 * [ Initialisation is based on Linus' ]
8 * [ uhci code and gregs ahcd fragments ]
9 * [ (C) Copyright 1999 Linus Torvalds ]
10 * [ (C) Copyright 1999 Gregory P. Smith]
11 *
12 *
13 * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
14 * interfaces (though some non-x86 Intel chips use it). It supports
15 * smarter hardware than UHCI. A download link for the spec available
16 * through the http://www.usb.org website.
17 *
18 * This file is licenced under the GPL.
19 */
20
21 #include <linux/module.h>
22 #include <linux/moduleparam.h>
23 #include <linux/pci.h>
24 #include <linux/kernel.h>
25 #include <linux/delay.h>
26 #include <linux/ioport.h>
27 #include <linux/sched.h>
28 #include <linux/slab.h>
29 #include <linux/errno.h>
30 #include <linux/init.h>
31 #include <linux/timer.h>
32 #include <linux/list.h>
33 #include <linux/usb.h>
34 #include <linux/usb/otg.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/dmapool.h>
37 #include <linux/reboot.h>
38
39 #include <asm/io.h>
40 #include <asm/irq.h>
41 #include <asm/system.h>
42 #include <asm/unaligned.h>
43 #include <asm/byteorder.h>
44
45 #include "../core/hcd.h"
46 #include "../core/hub.h"
47
48 #define DRIVER_VERSION "v0.05"
49 #define DRIVER_AUTHOR "Gabor Juhos <juhosg at openwrt.org>"
50 #define DRIVER_DESC "ADMtek USB 1.1 Host Controller Driver"
51
52 /*-------------------------------------------------------------------------*/
53
54 #define ADMHC_VERBOSE_DEBUG /* not always helpful */
55
56 /* For initializing controller (mask in an HCFS mode too) */
57 #define OHCI_CONTROL_INIT OHCI_CTRL_CBSR
58
59 #define ADMHC_INTR_INIT \
60 ( ADMHC_INTR_MIE | ADMHC_INTR_INSM | ADMHC_INTR_FATI \
61 | ADMHC_INTR_RESI | ADMHC_INTR_TDC | ADMHC_INTR_BABI )
62
63 /*-------------------------------------------------------------------------*/
64
65 static const char hcd_name [] = "admhc-hcd";
66
67 #define STATECHANGE_DELAY msecs_to_jiffies(300)
68
69 #include "adm5120.h"
70
71 static void admhc_dump(struct admhcd *ahcd, int verbose);
72 static int admhc_init(struct admhcd *ahcd);
73 static void admhc_stop(struct usb_hcd *hcd);
74
75 #include "adm5120-dbg.c"
76 #include "adm5120-mem.c"
77 #include "adm5120-pm.c"
78 #include "adm5120-hub.c"
79 #include "adm5120-q.c"
80
81 /*-------------------------------------------------------------------------*/
82
83 /*
84 * queue up an urb for anything except the root hub
85 */
86 static int admhc_urb_enqueue(struct usb_hcd *hcd, struct usb_host_endpoint *ep,
87 struct urb *urb, gfp_t mem_flags)
88 {
89 struct admhcd *ahcd = hcd_to_admhcd(hcd);
90 struct ed *ed;
91 struct urb_priv *urb_priv;
92 unsigned int pipe = urb->pipe;
93 int td_cnt = 0;
94 unsigned long flags;
95 int ret = 0;
96
97 #ifdef ADMHC_VERBOSE_DEBUG
98 spin_lock_irqsave(&ahcd->lock, flags);
99 urb_print(ahcd, urb, "ENQEUE", usb_pipein(pipe));
100 spin_unlock_irqrestore(&ahcd->lock, flags);
101 #endif
102
103 /* every endpoint has an ed, locate and maybe (re)initialize it */
104 ed = ed_get(ahcd, ep, urb->dev, pipe, urb->interval);
105 if (!ed)
106 return -ENOMEM;
107
108 /* for the private part of the URB we need the number of TDs */
109 switch (ed->type) {
110 case PIPE_CONTROL:
111 if (urb->transfer_buffer_length > TD_DATALEN_MAX)
112 /* td_submit_urb() doesn't yet handle these */
113 return -EMSGSIZE;
114
115 /* 1 TD for setup, 1 for ACK, plus ... */
116 td_cnt = 2;
117 if (urb->transfer_buffer_length)
118 td_cnt++;
119 break;
120 case PIPE_BULK:
121 /* one TD for every 4096 Bytes (can be upto 8K) */
122 td_cnt = urb->transfer_buffer_length / TD_DATALEN_MAX;
123 /* ... and for any remaining bytes ... */
124 if ((urb->transfer_buffer_length % TD_DATALEN_MAX) != 0)
125 td_cnt++;
126 /* ... and maybe a zero length packet to wrap it up */
127 if (td_cnt == 0)
128 td_cnt++;
129 else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
130 && (urb->transfer_buffer_length
131 % usb_maxpacket(urb->dev, pipe,
132 usb_pipeout (pipe))) == 0)
133 td_cnt++;
134 break;
135 case PIPE_INTERRUPT:
136 /*
137 * for Interrupt IN/OUT transactions, each ED contains
138 * only 1 TD.
139 * TODO: check transfer_buffer_length?
140 */
141 td_cnt = 1;
142 break;
143 case PIPE_ISOCHRONOUS:
144 /* number of packets from URB */
145 td_cnt = urb->number_of_packets;
146 break;
147 default:
148 /* paranoia */
149 admhc_err(ahcd, "bad EP type %d", ed->type);
150 return -EINVAL;
151 }
152
153 urb_priv = urb_priv_alloc(ahcd, td_cnt, mem_flags);
154 if (!urb_priv)
155 return -ENOMEM;
156
157 urb_priv->ed = ed;
158 urb_priv->urb = urb;
159
160 spin_lock_irqsave(&ahcd->lock, flags);
161 /* don't submit to a dead HC */
162 if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
163 ret = -ENODEV;
164 goto fail;
165 }
166 if (!HC_IS_RUNNING(hcd->state)) {
167 ret = -ENODEV;
168 goto fail;
169 }
170
171 /* in case of unlink-during-submit */
172 spin_lock(&urb->lock);
173 if (urb->status != -EINPROGRESS) {
174 spin_unlock(&urb->lock);
175 urb->hcpriv = urb_priv;
176 finish_urb(ahcd, urb);
177 ret = 0;
178 goto fail;
179 }
180
181 if (ed->type == PIPE_ISOCHRONOUS) {
182 if (ed->state == ED_NEW) {
183 u16 frame = admhc_frame_no(ahcd);
184
185 /* delay a few frames before the first TD */
186 frame += max_t (u16, 8, ed->interval);
187 frame &= ~(ed->interval - 1);
188 frame |= ed->branch;
189 urb->start_frame = frame;
190
191 /* yes, only URB_ISO_ASAP is supported, and
192 * urb->start_frame is never used as input.
193 */
194 } else
195 urb->start_frame = ed->last_iso + ed->interval;
196 }
197
198 urb->hcpriv = urb_priv;
199 td_submit_urb(ahcd, urb_priv->urb);
200
201 /* append it to the ED's queue */
202 list_add_tail(&urb_priv->pending, &ed->urb_pending);
203
204 /* schedule the ED */
205 ret = ed_schedule(ahcd, ed);
206
207 spin_unlock(&urb->lock);
208 fail:
209 if (ret) {
210 urb_priv = urb->hcpriv;
211 urb_priv_free(ahcd, urb_priv);
212 }
213
214 spin_unlock_irqrestore(&ahcd->lock, flags);
215 return ret;
216 }
217
218 /*
219 * decouple the URB from the HC queues (TDs, urb_priv); it's
220 * already marked using urb->status. reporting is always done
221 * asynchronously, and we might be dealing with an urb that's
222 * partially transferred, or an ED with other urbs being unlinked.
223 */
224 static int admhc_urb_dequeue(struct usb_hcd *hcd, struct urb *urb)
225 {
226 struct admhcd *ahcd = hcd_to_admhcd(hcd);
227 struct urb_priv *up;
228 unsigned long flags;
229
230 up = urb->hcpriv;
231 if (!up)
232 return 0;
233
234 spin_lock_irqsave(&ahcd->lock, flags);
235
236 #ifdef ADMHC_VERBOSE_DEBUG
237 urb_print(ahcd, urb, "DEQEUE", 1);
238 #endif
239
240 if (HC_IS_RUNNING(hcd->state)) {
241 /* Unless an IRQ completed the unlink while it was being
242 * handed to us, flag it for unlink and giveback, and force
243 * some upcoming INTR_SF to call finish_unlinks()
244 */
245 if (up->ed->urb_active != up) {
246 list_del(&up->pending);
247 finish_urb(ahcd, urb);
248 } else {
249 ed_start_deschedule(ahcd, up->ed);
250 }
251 } else {
252 /*
253 * with HC dead, we won't respect hc queue pointers
254 * any more ... just clean up every urb's memory.
255 */
256 if (up->ed->urb_active != up) {
257 list_del(&up->pending);
258 finish_urb(ahcd, urb);
259 } else {
260 finish_urb(ahcd, urb);
261 up->ed->urb_active = NULL;
262 up->ed->state = ED_IDLE;
263 }
264 }
265 spin_unlock_irqrestore(&ahcd->lock, flags);
266
267 return 0;
268 }
269
270 /*-------------------------------------------------------------------------*/
271
272 /* frees config/altsetting state for endpoints,
273 * including ED memory, dummy TD, and bulk/intr data toggle
274 */
275 static void admhc_endpoint_disable(struct usb_hcd *hcd,
276 struct usb_host_endpoint *ep)
277 {
278 struct admhcd *ahcd = hcd_to_admhcd(hcd);
279 unsigned long flags;
280 struct ed *ed = ep->hcpriv;
281 unsigned limit = 1000;
282
283 /* ASSERT: any requests/urbs are being unlinked */
284 /* ASSERT: nobody can be submitting urbs for this any more */
285
286 if (!ed)
287 return;
288
289 #ifdef ADMHC_VERBOSE_DEBUG
290 spin_lock_irqsave(&ahcd->lock, flags);
291 admhc_dump_ed(ahcd, "EP-DISABLE", ed, 1);
292 spin_unlock_irqrestore(&ahcd->lock, flags);
293 #endif
294
295 rescan:
296 spin_lock_irqsave(&ahcd->lock, flags);
297
298 if (!HC_IS_RUNNING(hcd->state)) {
299 sanitize:
300 ed->state = ED_UNLINK;
301 admhc_finish_unlinks(ahcd, 0);
302 }
303
304 switch (ed->state) {
305 case ED_UNLINK: /* wait for hw to finish? */
306 /* major IRQ delivery trouble loses INTR_SOFI too... */
307 if (limit-- == 0) {
308 admhc_warn(ahcd, "IRQ INTR_SOFI lossage\n");
309 goto sanitize;
310 }
311 spin_unlock_irqrestore(&ahcd->lock, flags);
312 schedule_timeout_uninterruptible(1);
313 goto rescan;
314 case ED_IDLE:
315 case ED_NEW: /* fully unlinked */
316 if (list_empty(&ed->urb_pending)) {
317 td_free(ahcd, ed->dummy);
318 ed_free(ahcd, ed);
319 break;
320 }
321 /* else FALL THROUGH */
322 default:
323 /* caller was supposed to have unlinked any requests;
324 * that's not our job. can't recover; must leak ed.
325 */
326 admhc_err(ahcd, "leak ed %p (#%02x) %s act %p%s\n",
327 ed, ep->desc.bEndpointAddress,
328 ed_statestring(ed->state),
329 ed->urb_active,
330 list_empty(&ed->urb_pending) ? "" : " (has urbs)");
331 break;
332 }
333
334 ep->hcpriv = NULL;
335
336 spin_unlock_irqrestore(&ahcd->lock, flags);
337 return;
338 }
339
340 static int admhc_get_frame_number(struct usb_hcd *hcd)
341 {
342 struct admhcd *ahcd = hcd_to_admhcd(hcd);
343
344 return admhc_frame_no(ahcd);
345 }
346
347 static void admhc_usb_reset(struct admhcd *ahcd)
348 {
349 ahcd->host_control = ADMHC_BUSS_RESET;
350 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
351 }
352
353 /* admhc_shutdown forcibly disables IRQs and DMA, helping kexec and
354 * other cases where the next software may expect clean state from the
355 * "firmware". this is bus-neutral, unlike shutdown() methods.
356 */
357 static void
358 admhc_shutdown(struct usb_hcd *hcd)
359 {
360 struct admhcd *ahcd;
361
362 ahcd = hcd_to_admhcd(hcd);
363 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
364 admhc_dma_disable(ahcd);
365 admhc_usb_reset(ahcd);
366 }
367
368 /*-------------------------------------------------------------------------*
369 * HC functions
370 *-------------------------------------------------------------------------*/
371
372 static void admhc_eds_cleanup(struct admhcd *ahcd)
373 {
374 if (ahcd->ed_tails[PIPE_INTERRUPT]) {
375 ed_free(ahcd, ahcd->ed_tails[PIPE_INTERRUPT]);
376 ahcd->ed_tails[PIPE_INTERRUPT] = NULL;
377 }
378
379 if (ahcd->ed_tails[PIPE_ISOCHRONOUS]) {
380 ed_free(ahcd, ahcd->ed_tails[PIPE_ISOCHRONOUS]);
381 ahcd->ed_tails[PIPE_ISOCHRONOUS] = NULL;
382 }
383
384 if (ahcd->ed_tails[PIPE_CONTROL]) {
385 ed_free(ahcd, ahcd->ed_tails[PIPE_CONTROL]);
386 ahcd->ed_tails[PIPE_CONTROL] = NULL;
387 }
388
389 if (ahcd->ed_tails[PIPE_BULK]) {
390 ed_free(ahcd, ahcd->ed_tails[PIPE_BULK]);
391 ahcd->ed_tails[PIPE_BULK] = NULL;
392 }
393
394 ahcd->ed_head = NULL;
395 }
396
397 #define ED_DUMMY_INFO (ED_SPEED_FULL | ED_SKIP)
398
399 static int admhc_eds_init(struct admhcd *ahcd)
400 {
401 struct ed *ed;
402
403 ed = ed_create(ahcd, PIPE_INTERRUPT, ED_DUMMY_INFO);
404 if (!ed)
405 goto err;
406
407 ahcd->ed_tails[PIPE_INTERRUPT] = ed;
408
409 ed = ed_create(ahcd, PIPE_ISOCHRONOUS, ED_DUMMY_INFO);
410 if (!ed)
411 goto err;
412
413 ahcd->ed_tails[PIPE_ISOCHRONOUS] = ed;
414 ed->ed_prev = ahcd->ed_tails[PIPE_INTERRUPT];
415 ahcd->ed_tails[PIPE_INTERRUPT]->ed_next = ed;
416 ahcd->ed_tails[PIPE_INTERRUPT]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
417
418 ed = ed_create(ahcd, PIPE_CONTROL, ED_DUMMY_INFO);
419 if (!ed)
420 goto err;
421
422 ahcd->ed_tails[PIPE_CONTROL] = ed;
423 ed->ed_prev = ahcd->ed_tails[PIPE_ISOCHRONOUS];
424 ahcd->ed_tails[PIPE_ISOCHRONOUS]->ed_next = ed;
425 ahcd->ed_tails[PIPE_ISOCHRONOUS]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
426
427 ed = ed_create(ahcd, PIPE_BULK, ED_DUMMY_INFO);
428 if (!ed)
429 goto err;
430
431 ahcd->ed_tails[PIPE_BULK] = ed;
432 ed->ed_prev = ahcd->ed_tails[PIPE_CONTROL];
433 ahcd->ed_tails[PIPE_CONTROL]->ed_next = ed;
434 ahcd->ed_tails[PIPE_CONTROL]->hwNextED = cpu_to_hc32(ahcd, ed->dma);
435
436 ahcd->ed_head = ahcd->ed_tails[PIPE_INTERRUPT];
437
438 #ifdef ADMHC_VERBOSE_DEBUG
439 admhc_dump_ed(ahcd, "ed intr", ahcd->ed_tails[PIPE_INTERRUPT], 1);
440 admhc_dump_ed(ahcd, "ed isoc", ahcd->ed_tails[PIPE_ISOCHRONOUS], 1);
441 admhc_dump_ed(ahcd, "ed ctrl", ahcd->ed_tails[PIPE_CONTROL], 1);
442 admhc_dump_ed(ahcd, "ed bulk", ahcd->ed_tails[PIPE_BULK], 1);
443 #endif
444
445 return 0;
446
447 err:
448 admhc_eds_cleanup(ahcd);
449 return -ENOMEM;
450 }
451
452 /* init memory, and kick BIOS/SMM off */
453
454 static int admhc_init(struct admhcd *ahcd)
455 {
456 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
457 int ret;
458
459 admhc_disable(ahcd);
460 ahcd->regs = hcd->regs;
461
462 /* Disable HC interrupts */
463 admhc_intr_disable(ahcd, ADMHC_INTR_MIE);
464
465 /* Read the number of ports unless overridden */
466 if (ahcd->num_ports == 0)
467 ahcd->num_ports = admhc_read_rhdesc(ahcd) & ADMHC_RH_NUMP;
468
469 ret = admhc_mem_init(ahcd);
470 if (ret)
471 goto err;
472
473 /* init dummy endpoints */
474 ret = admhc_eds_init(ahcd);
475 if (ret)
476 goto err;
477
478 create_debug_files(ahcd);
479
480 return 0;
481
482 err:
483 admhc_stop(hcd);
484 return ret;
485 }
486
487 /*-------------------------------------------------------------------------*/
488
489 /* Start an OHCI controller, set the BUS operational
490 * resets USB and controller
491 * enable interrupts
492 */
493 static int admhc_run(struct admhcd *ahcd)
494 {
495 u32 temp;
496 int first = ahcd->fminterval == 0;
497 struct usb_hcd *hcd = admhcd_to_hcd(ahcd);
498
499 admhc_disable(ahcd);
500
501 /* boot firmware should have set this up (5.1.1.3.1) */
502 if (first) {
503 temp = admhc_readl(ahcd, &ahcd->regs->fminterval);
504 ahcd->fminterval = temp & ADMHC_SFI_FI_MASK;
505 if (ahcd->fminterval != FI)
506 admhc_dbg(ahcd, "fminterval delta %d\n",
507 ahcd->fminterval - FI);
508 ahcd->fminterval |=
509 (FSLDP(ahcd->fminterval) << ADMHC_SFI_FSLDP_SHIFT);
510 /* also: power/overcurrent flags in rhdesc */
511 }
512
513 switch (ahcd->host_control & ADMHC_HC_BUSS) {
514 case ADMHC_BUSS_OPER:
515 temp = 0;
516 break;
517 case ADMHC_BUSS_SUSPEND:
518 /* FALLTHROUGH ? */
519 case ADMHC_BUSS_RESUME:
520 ahcd->host_control = ADMHC_BUSS_RESUME;
521 temp = 10 /* msec wait */;
522 break;
523 /* case ADMHC_BUSS_RESET: */
524 default:
525 ahcd->host_control = ADMHC_BUSS_RESET;
526 temp = 50 /* msec wait */;
527 break;
528 }
529 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
530
531 msleep(temp);
532 temp = admhc_read_rhdesc(ahcd);
533 if (!(temp & ADMHC_RH_NPS)) {
534 /* power down each port */
535 for (temp = 0; temp < ahcd->num_ports; temp++)
536 admhc_write_portstatus(ahcd, temp, ADMHC_PS_CPP);
537 }
538
539 /* 2msec timelimit here means no irqs/preempt */
540 spin_lock_irq(&ahcd->lock);
541
542 admhc_writel(ahcd, ADMHC_CTRL_SR, &ahcd->regs->gencontrol);
543 temp = 30; /* ... allow extra time */
544 while ((admhc_readl(ahcd, &ahcd->regs->gencontrol) & ADMHC_CTRL_SR) != 0) {
545 if (--temp == 0) {
546 spin_unlock_irq(&ahcd->lock);
547 admhc_err(ahcd, "USB HC reset timed out!\n");
548 return -1;
549 }
550 udelay (1);
551 }
552
553 /* enable HOST mode, before access any host specific register */
554 admhc_writel(ahcd, ADMHC_CTRL_UHFE, &ahcd->regs->gencontrol);
555
556 /* Tell the controller where the descriptor list is */
557 admhc_writel(ahcd, (u32)ahcd->ed_head->dma, &ahcd->regs->hosthead);
558
559 periodic_reinit(ahcd);
560
561 /* use rhsc irqs after khubd is fully initialized */
562 hcd->poll_rh = 1;
563 hcd->uses_new_polling = 1;
564
565 #if 0
566 /* wake on ConnectStatusChange, matching external hubs */
567 admhc_writel(ahcd, RH_HS_DRWE, &ahcd->regs->roothub.status);
568 #else
569 /* FIXME roothub_write_status (ahcd, ADMHC_RH_DRWE); */
570 #endif
571
572 /* Choose the interrupts we care about now, others later on demand */
573 admhc_intr_ack(ahcd, ~0);
574 admhc_intr_enable(ahcd, ADMHC_INTR_INIT);
575
576 admhc_writel(ahcd, ADMHC_RH_NPS | ADMHC_RH_LPSC, &ahcd->regs->rhdesc);
577
578 /* start controller operations */
579 ahcd->host_control = ADMHC_BUSS_OPER;
580 admhc_writel(ahcd, ahcd->host_control, &ahcd->regs->host_control);
581
582 temp = 20;
583 while ((admhc_readl(ahcd, &ahcd->regs->host_control)
584 & ADMHC_HC_BUSS) != ADMHC_BUSS_OPER) {
585 if (--temp == 0) {
586 spin_unlock_irq(&ahcd->lock);
587 admhc_err(ahcd, "unable to setup operational mode!\n");
588 return -1;
589 }
590 mdelay(1);
591 }
592
593 hcd->state = HC_STATE_RUNNING;
594 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
595
596 spin_unlock_irq(&ahcd->lock);
597
598 mdelay(ADMHC_POTPGT);
599
600 return 0;
601 }
602
603 /*-------------------------------------------------------------------------*/
604
605 /* an interrupt happens */
606
607 static irqreturn_t admhc_irq(struct usb_hcd *hcd)
608 {
609 struct admhcd *ahcd = hcd_to_admhcd(hcd);
610 struct admhcd_regs __iomem *regs = ahcd->regs;
611 u32 ints;
612
613 ints = admhc_readl(ahcd, &regs->int_status);
614 if (!(ints & ADMHC_INTR_INTA))
615 /* no unmasked interrupt status is set */
616 return IRQ_NONE;
617
618 ints &= admhc_readl(ahcd, &regs->int_enable);
619 if (!ints)
620 return IRQ_NONE;
621
622 if (ints & ADMHC_INTR_FATI) {
623 admhc_disable(ahcd);
624 admhc_err(ahcd, "Fatal Error, controller disabled\n");
625 admhc_usb_reset(ahcd);
626 }
627
628 if (ints & ADMHC_INTR_BABI) {
629 admhc_disable(ahcd);
630 admhc_err(ahcd, "Babble Detected\n");
631 admhc_usb_reset(ahcd);
632 }
633
634 if (ints & ADMHC_INTR_INSM) {
635 admhc_vdbg(ahcd, "Root Hub Status Change\n");
636 ahcd->next_statechange = jiffies + STATECHANGE_DELAY;
637 admhc_intr_ack(ahcd, ADMHC_INTR_RESI | ADMHC_INTR_INSM);
638
639 /* NOTE: Vendors didn't always make the same implementation
640 * choices for RHSC. Many followed the spec; RHSC triggers
641 * on an edge, like setting and maybe clearing a port status
642 * change bit. With others it's level-triggered, active
643 * until khubd clears all the port status change bits. We'll
644 * always disable it here and rely on polling until khubd
645 * re-enables it.
646 */
647 admhc_intr_disable(ahcd, ADMHC_INTR_INSM);
648 usb_hcd_poll_rh_status(hcd);
649 } else if (ints & ADMHC_INTR_RESI) {
650 /* For connect and disconnect events, we expect the controller
651 * to turn on RHSC along with RD. But for remote wakeup events
652 * this might not happen.
653 */
654 admhc_vdbg(ahcd, "Resume Detect\n");
655 admhc_intr_ack(ahcd, ADMHC_INTR_RESI);
656 hcd->poll_rh = 1;
657 if (ahcd->autostop) {
658 admhc_rh_resume(ahcd);
659 } else
660 usb_hcd_resume_root_hub(hcd);
661 }
662
663 if (ints & ADMHC_INTR_TDC) {
664 admhc_intr_ack(ahcd, ADMHC_INTR_TDC);
665 if (HC_IS_RUNNING(hcd->state))
666 admhc_intr_disable(ahcd, ADMHC_INTR_TDC);
667 admhc_vdbg(ahcd, "Transfer Descriptor Complete\n");
668 spin_lock(&ahcd->lock);
669 admhc_td_complete(ahcd);
670 spin_unlock(&ahcd->lock);
671 if (HC_IS_RUNNING(hcd->state))
672 admhc_intr_enable(ahcd, ADMHC_INTR_TDC);
673 }
674
675 if (ints & ADMHC_INTR_SO) {
676 /* could track INTR_SO to reduce available PCI/... bandwidth */
677 admhc_vdbg(ahcd, "Schedule Overrun\n");
678 }
679
680 if (ints & ADMHC_INTR_SOFI) {
681 admhc_intr_ack(ahcd, ADMHC_INTR_SOFI);
682 spin_lock(&ahcd->lock);
683 /* handle any pending ED removes */
684 admhc_finish_unlinks(ahcd, admhc_frame_no(ahcd));
685 admhc_sof_refill(ahcd);
686 spin_unlock(&ahcd->lock);
687 }
688
689 if (HC_IS_RUNNING(hcd->state)) {
690 admhc_intr_ack(ahcd, ints);
691 admhc_intr_enable(ahcd, ADMHC_INTR_MIE);
692 }
693
694 return IRQ_HANDLED;
695 }
696
697 /*-------------------------------------------------------------------------*/
698
699 static void admhc_stop(struct usb_hcd *hcd)
700 {
701 struct admhcd *ahcd = hcd_to_admhcd(hcd);
702
703 admhc_dump(ahcd, 1);
704
705 flush_scheduled_work();
706
707 admhc_usb_reset(ahcd);
708 admhc_intr_disable(ahcd, ~0);
709
710 free_irq(hcd->irq, hcd);
711 hcd->irq = -1;
712
713 remove_debug_files(ahcd);
714 admhc_eds_cleanup(ahcd);
715 admhc_mem_cleanup(ahcd);
716 }
717
718 /*-------------------------------------------------------------------------*/
719
720 #ifdef CONFIG_MIPS_ADM5120
721 #include "adm5120-drv.c"
722 #define PLATFORM_DRIVER usb_hcd_adm5120_driver
723 #endif
724
725 #if !defined(PLATFORM_DRIVER)
726 #error "missing bus glue for admhc-hcd"
727 #endif
728
729 #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
730
731 static int __init admhc_hcd_mod_init(void)
732 {
733 int ret = 0;
734
735 if (usb_disabled())
736 return -ENODEV;
737
738 pr_info("%s: " DRIVER_INFO "\n", hcd_name);
739 pr_info("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
740 sizeof (struct ed), sizeof (struct td));
741
742 #ifdef PLATFORM_DRIVER
743 ret = platform_driver_register(&PLATFORM_DRIVER);
744 if (ret < 0)
745 goto error_platform;
746 #endif
747
748 return ret;
749
750 #ifdef PLATFORM_DRIVER
751 platform_driver_unregister(&PLATFORM_DRIVER);
752 error_platform:
753 #endif
754 return ret;
755 }
756 module_init(admhc_hcd_mod_init);
757
758 static void __exit admhc_hcd_mod_exit(void)
759 {
760 platform_driver_unregister(&PLATFORM_DRIVER);
761 }
762 module_exit(admhc_hcd_mod_exit);
763
764 MODULE_AUTHOR(DRIVER_AUTHOR);
765 MODULE_DESCRIPTION(DRIVER_INFO);
766 MODULE_LICENSE("GPL");
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