target/linux/amazon/files/arch/mips/amazon/interrupt.c

   1 /*
   2  *  Gary Jennejohn (C) 2003 <gj@denx.de>
   3  *  Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
   4  *  Copyright (C) 2007 John Crispin <blogic@openwrt.org>
   5  *
   6  *  This program is free software; you can distribute it and/or modify it
   7  *  under the terms of the GNU General Public License (Version 2) as
   8  *  published by the Free Software Foundation.
   9  *
  10  *  This program is distributed in the hope it will be useful, but WITHOUT
  11  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  *  for more details.
  14  *
  15  *  You should have received a copy of the GNU General Public License along
  16  *  with this program; if not, write to the Free Software Foundation, Inc.,
  17  *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
  18  *
  19  * Routines for generic manipulation of the interrupts found on the
  20  * AMAZON boards.
  21  */
  22
  23 #include <linux/init.h>
  24 #include <linux/sched.h>
  25 #include <linux/slab.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/kernel_stat.h>
  28 #include <linux/module.h>
  29
  30 #include <asm/amazon/amazon.h>
  31 #include <asm/amazon/irq.h>
  32 #include <asm/bootinfo.h>
  33 #include <asm/irq_cpu.h>
  34 #include <asm/irq.h>
  35 #include <asm/time.h>
  36
  37 static void amazon_disable_irq(struct irq_data *d)
  38 {
  39         int i;
  40         u32 amazon_ier = AMAZON_ICU_IM0_IER;
  41         unsigned int irq_nr = d->irq;
  42
  43         if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
  44                 amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
  45         else {
  46                 irq_nr -= INT_NUM_IRQ0;
  47                 for (i = 0; i <= 4; i++)
  48                 {
  49                         if (irq_nr <= 31)
  50                         amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier);
  51                         amazon_ier += 0x10;
  52                         irq_nr -= 32;
  53                 }
  54         }
  55 }
  56
  57 static void amazon_mask_and_ack_irq(struct irq_data *d)
  58 {
  59         int i;
  60         u32 amazon_ier = AMAZON_ICU_IM0_IER;
  61         u32 amazon_isr = AMAZON_ICU_IM0_ISR;
  62         unsigned int irq_nr = d->irq;
  63
  64         if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0){
  65                 amazon_writel(amazon_readl(amazon_ier) & (~(AMAZON_DMA_H_MASK)), amazon_ier);
  66                 amazon_writel(AMAZON_DMA_H_MASK, amazon_isr);
  67         } else {
  68                 irq_nr -= INT_NUM_IRQ0;
  69                 for (i = 0; i <= 4; i++)
  70                 {
  71                         if (irq_nr <= 31){
  72                         amazon_writel(amazon_readl(amazon_ier) & ~(1 << irq_nr ), amazon_ier);
  73                                 amazon_writel((1 << irq_nr ), amazon_isr);
  74                         }
  75                         amazon_ier += 0x10;
  76                         amazon_isr += 0x10;
  77                         irq_nr -= 32;
  78                 }
  79         }
  80 }
  81
  82 static void amazon_enable_irq(struct irq_data *d)
  83 {
  84         int i;
  85         u32 amazon_ier = AMAZON_ICU_IM0_IER;
  86         unsigned int irq_nr = d->irq;
  87
  88         if (irq_nr <= INT_NUM_IM0_IRL11 && irq_nr >= INT_NUM_IM0_IRL0)
  89                 amazon_writel(amazon_readl(amazon_ier) | AMAZON_DMA_H_MASK, amazon_ier);
  90         else {
  91                 irq_nr -= INT_NUM_IRQ0;
  92                 for (i = 0; i <= 4; i++)
  93                 {
  94                         if (irq_nr <= 31)
  95                                 amazon_writel(amazon_readl(amazon_ier) | (1 << irq_nr ), amazon_ier);
  96                         amazon_ier += 0x10;
  97                         irq_nr -= 32;
  98                 }
  99         }
 100 }
 101
 102 static unsigned int amazon_startup_irq(struct irq_data *d)
 103 {
 104         amazon_enable_irq(d);
 105         return 0;
 106 }
 107
 108 static struct irq_chip amazon_irq_type = {
 109         .name = "AMAZON",
 110         .irq_startup = amazon_startup_irq,
 111         .irq_enable = amazon_enable_irq,
 112         .irq_disable = amazon_disable_irq,
 113         .irq_unmask = amazon_enable_irq,
 114         .irq_ack = amazon_mask_and_ack_irq,
 115         .irq_mask = amazon_disable_irq,
 116         .irq_mask_ack = amazon_mask_and_ack_irq,
 117 };
 118
 119 /* Cascaded interrupts from IM0-4 */
 120 static inline void amazon_hw_irqdispatch(u8 line)
 121 {
 122         u32 irq;
 123
 124         irq = (amazon_readl(AMAZON_ICU_IM_VEC) >> (line * 5)) & AMAZON_ICU_IM0_VEC_MASK;
 125         if (line == 0 && irq <= 11 && irq >= 0) {
 126                 //DMA fixed to IM0_IRL0
 127                 irq = 0;
 128         }
 129         do_IRQ(irq + INT_NUM_IRQ0 + (line * 32));
 130 }
 131
 132 asmlinkage void plat_irq_dispatch(void)
 133 {
 134         unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
 135         if (pending & CAUSEF_IP7){
 136                 do_IRQ(MIPS_CPU_TIMER_IRQ);
 137                 goto out;
 138         } else {
 139                 unsigned int i;
 140                 for (i = 0; i <= 4; i++)
 141                 {
 142                         if(pending & (CAUSEF_IP2 << i)){
 143                                 amazon_hw_irqdispatch(i);
 144                                 goto out;
 145                         }
 146                 }
 147         }
 148         printk("Spurious IRQ: CAUSE=0x%08x\n", read_c0_status());
 149 out:
 150         return;
 151 }
 152
 153 static struct irqaction cascade = {
 154         .handler        = no_action,
 155         .flags          = IRQF_DISABLED,
 156         .name           = "cascade",
 157 };
 158
 159 void __init arch_init_irq(void)
 160 {
 161         int i;
 162
 163         /* mask all interrupt sources */
 164         for(i = 0; i <= 4; i++){
 165                 amazon_writel(0, AMAZON_ICU_IM0_IER + (i * 0x10));
 166         }
 167
 168         mips_cpu_irq_init();
 169
 170         /* set up irq cascade */
 171         for (i = 2; i <= 6; i++) {
 172                 setup_irq(i, &cascade);
 173         }
 174
 175         for (i = INT_NUM_IRQ0; i <= INT_NUM_IM4_IRL31; i++)
 176                 irq_set_chip_and_handler(i, &amazon_irq_type,
 177                         handle_level_irq);
 178
 179         set_c0_status(IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5);
 180 }
 181
 182 void __cpuinit arch_fixup_c0_irqs(void)
 183 {
 184         /* FIXME: check for CPUID and only do fix for specific chips/versions */
 185         cp0_compare_irq = CP0_LEGACY_COMPARE_IRQ;
 186         cp0_perfcount_irq = CP0_LEGACY_PERFCNT_IRQ;
 187 }