target/linux/ar71xx/files/arch/mips/ar71xx/irq.c

   1 /*
   2  *  Atheros AR71xx SoC specific interrupt handling
   3  *
   4  *  Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
   5  *  Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
   6  *  Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
   7  *
   8  *  Parts of this file are based on Atheros 2.6.15 BSP
   9  *  Parts of this file are based on Atheros 2.6.31 BSP
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License version 2 as published
  13  *  by the Free Software Foundation.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/irq.h>
  20
  21 #include <asm/irq_cpu.h>
  22 #include <asm/mipsregs.h>
  23
  24 #include <asm/mach-ar71xx/ar71xx.h>
  25
  26 static int ip2_flush_reg;
  27
  28 static void ar71xx_gpio_irq_dispatch(void)
  29 {
  30         void __iomem *base = ar71xx_gpio_base;
  31         u32 pending;
  32
  33         pending = __raw_readl(base + GPIO_REG_INT_PENDING) &
  34                   __raw_readl(base + GPIO_REG_INT_ENABLE);
  35
  36         if (pending)
  37                 do_IRQ(AR71XX_GPIO_IRQ_BASE + fls(pending) - 1);
  38         else
  39                 spurious_interrupt();
  40 }
  41
  42 static void ar71xx_gpio_irq_unmask(unsigned int irq)
  43 {
  44         void __iomem *base = ar71xx_gpio_base;
  45         u32 t;
  46
  47         irq -= AR71XX_GPIO_IRQ_BASE;
  48
  49         t = __raw_readl(base + GPIO_REG_INT_ENABLE);
  50         __raw_writel(t | (1 << irq), base + GPIO_REG_INT_ENABLE);
  51
  52         /* flush write */
  53         (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
  54 }
  55
  56 static void ar71xx_gpio_irq_mask(unsigned int irq)
  57 {
  58         void __iomem *base = ar71xx_gpio_base;
  59         u32 t;
  60
  61         irq -= AR71XX_GPIO_IRQ_BASE;
  62
  63         t = __raw_readl(base + GPIO_REG_INT_ENABLE);
  64         __raw_writel(t & ~(1 << irq), base + GPIO_REG_INT_ENABLE);
  65
  66         /* flush write */
  67         (void) __raw_readl(base + GPIO_REG_INT_ENABLE);
  68 }
  69
  70 #if 0
  71 static int ar71xx_gpio_irq_set_type(unsigned int irq, unsigned int flow_type)
  72 {
  73         /* TODO: implement */
  74         return 0;
  75 }
  76 #else
  77 #define ar71xx_gpio_irq_set_type        NULL
  78 #endif
  79
  80 static struct irq_chip ar71xx_gpio_irq_chip = {
  81         .name           = "AR71XX GPIO",
  82         .unmask         = ar71xx_gpio_irq_unmask,
  83         .mask           = ar71xx_gpio_irq_mask,
  84         .mask_ack       = ar71xx_gpio_irq_mask,
  85         .set_type       = ar71xx_gpio_irq_set_type,
  86 };
  87
  88 static struct irqaction ar71xx_gpio_irqaction = {
  89         .handler        = no_action,
  90         .name           = "cascade [AR71XX GPIO]",
  91 };
  92
  93 #define GPIO_INT_ALL    0xffff
  94
  95 static void __init ar71xx_gpio_irq_init(void)
  96 {
  97         void __iomem *base = ar71xx_gpio_base;
  98         int i;
  99
 100         __raw_writel(0, base + GPIO_REG_INT_ENABLE);
 101         __raw_writel(0, base + GPIO_REG_INT_PENDING);
 102
 103         /* setup type of all GPIO interrupts to level sensitive */
 104         __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_TYPE);
 105
 106         /* setup polarity of all GPIO interrupts to active high */
 107         __raw_writel(GPIO_INT_ALL, base + GPIO_REG_INT_POLARITY);
 108
 109         for (i = AR71XX_GPIO_IRQ_BASE;
 110              i < AR71XX_GPIO_IRQ_BASE + AR71XX_GPIO_IRQ_COUNT; i++)
 111                 set_irq_chip_and_handler(i, &ar71xx_gpio_irq_chip,
 112                                          handle_level_irq);
 113
 114         setup_irq(AR71XX_MISC_IRQ_GPIO, &ar71xx_gpio_irqaction);
 115 }
 116
 117 static void ar71xx_misc_irq_dispatch(void)
 118 {
 119         u32 pending;
 120
 121         pending = ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS)
 122             & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
 123
 124         if (pending & MISC_INT_UART)
 125                 do_IRQ(AR71XX_MISC_IRQ_UART);
 126
 127         else if (pending & MISC_INT_DMA)
 128                 do_IRQ(AR71XX_MISC_IRQ_DMA);
 129
 130         else if (pending & MISC_INT_PERFC)
 131                 do_IRQ(AR71XX_MISC_IRQ_PERFC);
 132
 133         else if (pending & MISC_INT_TIMER)
 134                 do_IRQ(AR71XX_MISC_IRQ_TIMER);
 135
 136         else if (pending & MISC_INT_OHCI)
 137                 do_IRQ(AR71XX_MISC_IRQ_OHCI);
 138
 139         else if (pending & MISC_INT_ERROR)
 140                 do_IRQ(AR71XX_MISC_IRQ_ERROR);
 141
 142         else if (pending & MISC_INT_GPIO)
 143                 ar71xx_gpio_irq_dispatch();
 144
 145         else if (pending & MISC_INT_WDOG)
 146                 do_IRQ(AR71XX_MISC_IRQ_WDOG);
 147
 148         else if (pending & MISC_INT_TIMER2)
 149                 do_IRQ(AR71XX_MISC_IRQ_TIMER2);
 150
 151         else if (pending & MISC_INT_TIMER3)
 152                 do_IRQ(AR71XX_MISC_IRQ_TIMER3);
 153
 154         else if (pending & MISC_INT_TIMER4)
 155                 do_IRQ(AR71XX_MISC_IRQ_TIMER4);
 156
 157         else if (pending & MISC_INT_DDR_PERF)
 158                 do_IRQ(AR71XX_MISC_IRQ_DDR_PERF);
 159
 160         else if (pending & MISC_INT_ENET_LINK)
 161                 do_IRQ(AR71XX_MISC_IRQ_ENET_LINK);
 162
 163         else
 164                 spurious_interrupt();
 165 }
 166
 167 static void ar71xx_misc_irq_unmask(unsigned int irq)
 168 {
 169         void __iomem *base = ar71xx_reset_base;
 170         u32 t;
 171
 172         irq -= AR71XX_MISC_IRQ_BASE;
 173
 174         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 175         __raw_writel(t | (1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 176
 177         /* flush write */
 178         (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 179 }
 180
 181 static void ar71xx_misc_irq_mask(unsigned int irq)
 182 {
 183         void __iomem *base = ar71xx_reset_base;
 184         u32 t;
 185
 186         irq -= AR71XX_MISC_IRQ_BASE;
 187
 188         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 189         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 190
 191         /* flush write */
 192         (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 193 }
 194
 195 static void ar724x_misc_irq_ack(unsigned int irq)
 196 {
 197         void __iomem *base = ar71xx_reset_base;
 198         u32 t;
 199
 200         irq -= AR71XX_MISC_IRQ_BASE;
 201
 202         t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 203         __raw_writel(t & ~(1 << irq), base + AR71XX_RESET_REG_MISC_INT_STATUS);
 204
 205         /* flush write */
 206         (void) __raw_readl(base + AR71XX_RESET_REG_MISC_INT_STATUS);
 207 }
 208
 209 static struct irq_chip ar71xx_misc_irq_chip = {
 210         .name           = "AR71XX MISC",
 211         .unmask         = ar71xx_misc_irq_unmask,
 212         .mask           = ar71xx_misc_irq_mask,
 213 };
 214
 215 static struct irqaction ar71xx_misc_irqaction = {
 216         .handler        = no_action,
 217         .name           = "cascade [AR71XX MISC]",
 218 };
 219
 220 static void __init ar71xx_misc_irq_init(void)
 221 {
 222         void __iomem *base = ar71xx_reset_base;
 223         int i;
 224
 225         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
 226         __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS);
 227
 228         switch (ar71xx_soc) {
 229         case AR71XX_SOC_AR7240:
 230         case AR71XX_SOC_AR7241:
 231         case AR71XX_SOC_AR7242:
 232         case AR71XX_SOC_AR9330:
 233         case AR71XX_SOC_AR9331:
 234         case AR71XX_SOC_AR9341:
 235         case AR71XX_SOC_AR9342:
 236         case AR71XX_SOC_AR9344:
 237                 ar71xx_misc_irq_chip.ack = ar724x_misc_irq_ack;
 238                 break;
 239         default:
 240                 ar71xx_misc_irq_chip.mask_ack = ar71xx_misc_irq_mask;
 241                 break;
 242         }
 243
 244         for (i = AR71XX_MISC_IRQ_BASE;
 245              i < AR71XX_MISC_IRQ_BASE + AR71XX_MISC_IRQ_COUNT; i++)
 246                 set_irq_chip_and_handler(i, &ar71xx_misc_irq_chip,
 247                                          handle_level_irq);
 248
 249         setup_irq(AR71XX_CPU_IRQ_MISC, &ar71xx_misc_irqaction);
 250 }
 251
 252 asmlinkage void plat_irq_dispatch(void)
 253 {
 254         unsigned long pending;
 255
 256         pending = read_c0_status() & read_c0_cause() & ST0_IM;
 257
 258         if (pending & STATUSF_IP7)
 259                 do_IRQ(AR71XX_CPU_IRQ_TIMER);
 260
 261         else if (pending & STATUSF_IP2) {
 262                 /*
 263                  * This IRQ is meant for a PCI device. Drivers for PCI devices
 264                  * typically allocate coherent DMA memory for the descriptor
 265                  * ring, however the DMA controller may still have some
 266                  * unsynchronized data in the FIFO.
 267                  * Issue a flush here to ensure that the driver sees the update.
 268                  */
 269                 ar71xx_ddr_flush(ip2_flush_reg);
 270                 do_IRQ(AR71XX_CPU_IRQ_IP2);
 271         }
 272
 273         else if (pending & STATUSF_IP4)
 274                 do_IRQ(AR71XX_CPU_IRQ_GE0);
 275
 276         else if (pending & STATUSF_IP5)
 277                 do_IRQ(AR71XX_CPU_IRQ_GE1);
 278
 279         else if (pending & STATUSF_IP3)
 280                 do_IRQ(AR71XX_CPU_IRQ_USB);
 281
 282         else if (pending & STATUSF_IP6)
 283                 ar71xx_misc_irq_dispatch();
 284
 285         else
 286                 spurious_interrupt();
 287 }
 288
 289 void __init arch_init_irq(void)
 290 {
 291         switch (ar71xx_soc) {
 292         case AR71XX_SOC_AR7130:
 293         case AR71XX_SOC_AR7141:
 294         case AR71XX_SOC_AR7161:
 295                 ip2_flush_reg = AR71XX_DDR_REG_FLUSH_PCI;
 296                 break;
 297
 298         case AR71XX_SOC_AR7240:
 299         case AR71XX_SOC_AR7241:
 300         case AR71XX_SOC_AR7242:
 301                 ip2_flush_reg = AR724X_DDR_REG_FLUSH_PCIE;
 302                 break;
 303
 304         case AR71XX_SOC_AR9130:
 305         case AR71XX_SOC_AR9132:
 306                 ip2_flush_reg = AR91XX_DDR_REG_FLUSH_WMAC;
 307                 break;
 308
 309         case AR71XX_SOC_AR9330:
 310         case AR71XX_SOC_AR9331:
 311                 ip2_flush_reg = AR933X_DDR_REG_FLUSH_WMAC;
 312                 break;
 313
 314         case AR71XX_SOC_AR9341:
 315         case AR71XX_SOC_AR9342:
 316         case AR71XX_SOC_AR9344:
 317                 ip2_flush_reg = AR934X_DDR_REG_FLUSH_PCIE;
 318                 break;
 319
 320         default:
 321                 BUG();
 322         }
 323
 324         mips_cpu_irq_init();
 325
 326         ar71xx_misc_irq_init();
 327
 328         cp0_perfcount_irq = AR71XX_MISC_IRQ_PERFC;
 329
 330         ar71xx_gpio_irq_init();
 331 }