target/linux/ar71xx/files/arch/mips/pci/pci-ar724x.c

   1 /*
   2  *  Atheros AR724x PCI host controller driver
   3  *
   4  *  Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  Parts of this file are based on Atheros' 2.6.15 BSP
   7  *
   8  *  This program is free software; you can redistribute it and/or modify it
   9  *  under the terms of the GNU General Public License version 2 as published
  10  *  by the Free Software Foundation.
  11  */
  12
  13 #include <linux/resource.h>
  14 #include <linux/types.h>
  15 #include <linux/delay.h>
  16 #include <linux/bitops.h>
  17 #include <linux/pci.h>
  18 #include <linux/pci_regs.h>
  19 #include <linux/interrupt.h>
  20
  21 #include <asm/mach-ar71xx/ar71xx.h>
  22 #include <asm/mach-ar71xx/pci.h>
  23
  24 #undef DEBUG
  25 #ifdef DEBUG
  26 #define DBG(fmt, args...)       printk(KERN_INFO fmt, ## args)
  27 #else
  28 #define DBG(fmt, args...)
  29 #endif
  30
  31 static void __iomem *ar724x_pci_localcfg_base;
  32 static void __iomem *ar724x_pci_devcfg_base;
  33 static int ar724x_pci_fixup_enable;
  34
  35 static DEFINE_SPINLOCK(ar724x_pci_lock);
  36
  37 static void ar724x_pci_read(void __iomem *base, int where, int size, u32 *value)
  38 {
  39         unsigned long flags;
  40         u32 data;
  41
  42         spin_lock_irqsave(&ar724x_pci_lock, flags);
  43         data = __raw_readl(base + (where & ~3));
  44
  45         switch (size) {
  46         case 1:
  47                 if (where & 1)
  48                         data >>= 8;
  49                 if (where & 2)
  50                         data >>= 16;
  51                 data &= 0xFF;
  52                 break;
  53         case 2:
  54                 if (where & 2)
  55                         data >>= 16;
  56                 data &= 0xFFFF;
  57                 break;
  58         }
  59
  60         *value = data;
  61         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  62 }
  63
  64 static void ar724x_pci_write(void __iomem *base, int where, int size, u32 value)
  65 {
  66         unsigned long flags;
  67         u32 data;
  68         int s;
  69
  70         spin_lock_irqsave(&ar724x_pci_lock, flags);
  71         data = __raw_readl(base + (where & ~3));
  72
  73         switch (size) {
  74         case 1:
  75                 s = ((where & 3) << 3);
  76                 data &= ~(0xFF << s);
  77                 data |= ((value & 0xFF) << s);
  78                 break;
  79         case 2:
  80                 s = ((where & 2) << 3);
  81                 data &= ~(0xFFFF << s);
  82                 data |= ((value & 0xFFFF) << s);
  83                 break;
  84         case 4:
  85                 data = value;
  86                 break;
  87         }
  88
  89         __raw_writel(data, base + (where & ~3));
  90         /* flush write */
  91         (void)__raw_readl(base + (where & ~3));
  92         spin_unlock_irqrestore(&ar724x_pci_lock, flags);
  93 }
  94
  95 static int ar724x_pci_read_config(struct pci_bus *bus, unsigned int devfn,
  96                                   int where, int size, u32 *value)
  97 {
  98
  99         if (bus->number != 0 || devfn != 0)
 100                 return PCIBIOS_DEVICE_NOT_FOUND;
 101
 102         ar724x_pci_read(ar724x_pci_devcfg_base, where, size, value);
 103
 104         DBG("PCI: read config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 105                         bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 106                         where, size, *value);
 107
 108         /*
 109          * WAR for BAR issue - We are unable to access the PCI device space
 110          * if we set the BAR with proper base address
 111          */
 112         if ((where == 0x10) && (size == 4))
 113                 ar724x_pci_write(ar724x_pci_devcfg_base, where, size, 0xffff);
 114
 115         return PCIBIOS_SUCCESSFUL;
 116 }
 117
 118 static int ar724x_pci_write_config(struct pci_bus *bus, unsigned int devfn,
 119                                    int where, int size, u32 value)
 120 {
 121         if (bus->number != 0 || devfn != 0)
 122                 return PCIBIOS_DEVICE_NOT_FOUND;
 123
 124         DBG("PCI: write config: %02x:%02x.%01x/%02x:%01d, value=%08x\n",
 125                 bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn),
 126                 where, size, value);
 127
 128         ar724x_pci_write(ar724x_pci_devcfg_base, where, size, value);
 129
 130         return PCIBIOS_SUCCESSFUL;
 131 }
 132
 133 static void ar724x_pci_fixup(struct pci_dev *dev)
 134 {
 135         u16 cmd;
 136
 137         if (!ar724x_pci_fixup_enable)
 138                 return;
 139
 140         if (dev->bus->number != 0 || dev->devfn != 0)
 141                 return;
 142
 143         /* setup COMMAND register */
 144         pci_read_config_word(dev, PCI_COMMAND, &cmd);
 145         cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 146                PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
 147                PCI_COMMAND_FAST_BACK;
 148
 149         pci_write_config_word(dev, PCI_COMMAND, cmd);
 150 }
 151 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ar724x_pci_fixup);
 152
 153 int __init ar724x_pcibios_map_irq(const struct pci_dev *dev, uint8_t slot,
 154                                   uint8_t pin)
 155 {
 156         int irq = -1;
 157         int i;
 158
 159         for (i = 0; i < ar71xx_pci_nr_irqs; i++) {
 160                 struct ar71xx_pci_irq *entry;
 161                 entry = &ar71xx_pci_irq_map[i];
 162
 163                 if (entry->slot == slot && entry->pin == pin) {
 164                         irq = entry->irq;
 165                         break;
 166                 }
 167         }
 168
 169         if (irq < 0)
 170                 printk(KERN_ALERT "PCI: no irq found for pin%u@%s\n",
 171                                 pin, pci_name((struct pci_dev *)dev));
 172         else
 173                 printk(KERN_INFO "PCI: mapping irq %d to pin%u@%s\n",
 174                                 irq, pin, pci_name((struct pci_dev *)dev));
 175
 176         return irq;
 177 }
 178
 179 static struct pci_ops ar724x_pci_ops = {
 180         .read   = ar724x_pci_read_config,
 181         .write  = ar724x_pci_write_config,
 182 };
 183
 184 static struct resource ar724x_pci_io_resource = {
 185         .name           = "PCI IO space",
 186         .start          = 0,
 187         .end            = 0,
 188         .flags          = IORESOURCE_IO,
 189 };
 190
 191 static struct resource ar724x_pci_mem_resource = {
 192         .name           = "PCI memory space",
 193         .start          = AR71XX_PCI_MEM_BASE,
 194         .end            = AR71XX_PCI_MEM_BASE + AR71XX_PCI_MEM_SIZE - 1,
 195         .flags          = IORESOURCE_MEM
 196 };
 197
 198 static struct pci_controller ar724x_pci_controller = {
 199         .pci_ops        = &ar724x_pci_ops,
 200         .mem_resource   = &ar724x_pci_mem_resource,
 201         .io_resource    = &ar724x_pci_io_resource,
 202 };
 203
 204 static void __init ar724x_pci_reset(void)
 205 {
 206         ar71xx_device_stop(AR724X_RESET_PCIE);
 207         ar71xx_device_stop(AR724X_RESET_PCIE_PHY);
 208         ar71xx_device_stop(AR724X_RESET_PCIE_PHY_SERIAL);
 209         udelay(100);
 210
 211         ar71xx_device_start(AR724X_RESET_PCIE_PHY_SERIAL);
 212         udelay(100);
 213         ar71xx_device_start(AR724X_RESET_PCIE_PHY);
 214         ar71xx_device_start(AR724X_RESET_PCIE);
 215 }
 216
 217 static int __init ar724x_pci_setup(void)
 218 {
 219         u32 t;
 220
 221         /* setup COMMAND register */
 222         t = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE |
 223             PCI_COMMAND_PARITY|PCI_COMMAND_SERR|PCI_COMMAND_FAST_BACK;
 224
 225         ar724x_pci_write(ar724x_pci_localcfg_base, PCI_COMMAND, 4, t);
 226         ar724x_pci_write(ar724x_pci_localcfg_base, 0x20, 4, 0x1ff01000);
 227         ar724x_pci_write(ar724x_pci_localcfg_base, 0x24, 4, 0x1ff01000);
 228
 229         t = ar724x_pci_rr(AR724X_PCI_REG_RESET);
 230         if (t != 0x7) {
 231                 udelay(100000);
 232                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 0);
 233                 udelay(100);
 234                 ar724x_pci_wr_nf(AR724X_PCI_REG_RESET, 4);
 235                 udelay(100000);
 236         }
 237
 238         ar724x_pci_wr(AR724X_PCI_REG_APP, AR724X_PCI_APP_LTSSM_ENABLE);
 239         udelay(1000);
 240
 241         t = ar724x_pci_rr(AR724X_PCI_REG_APP);
 242         if ((t & AR724X_PCI_APP_LTSSM_ENABLE) == 0x0) {
 243                 printk(KERN_WARNING "PCI: no PCIe module found\n");
 244                 return -ENODEV;
 245         }
 246
 247         return 0;
 248 }
 249
 250 static void ar724x_pci_irq_handler(unsigned int irq, struct irq_desc *desc)
 251 {
 252         u32 pending;
 253
 254         pending = ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) &
 255                   ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 256
 257         if (pending & AR724X_PCI_INT_DEV0)
 258                 generic_handle_irq(AR71XX_PCI_IRQ_DEV0);
 259
 260         else
 261                 spurious_interrupt();
 262 }
 263
 264 static void ar724x_pci_irq_unmask(unsigned int irq)
 265 {
 266         switch (irq) {
 267         case AR71XX_PCI_IRQ_DEV0:
 268                 irq -= AR71XX_PCI_IRQ_BASE;
 269                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 270                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) |
 271                                             AR724X_PCI_INT_DEV0);
 272                 /* flush write */
 273                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 274         }
 275 }
 276
 277 static void ar724x_pci_irq_mask(unsigned int irq)
 278 {
 279         switch (irq) {
 280         case AR71XX_PCI_IRQ_DEV0:
 281                 irq -= AR71XX_PCI_IRQ_BASE;
 282                 ar724x_pci_wr(AR724X_PCI_REG_INT_MASK,
 283                               ar724x_pci_rr(AR724X_PCI_REG_INT_MASK) &
 284                                             ~AR724X_PCI_INT_DEV0);
 285                 /* flush write */
 286                 ar724x_pci_rr(AR724X_PCI_REG_INT_MASK);
 287
 288                 ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS,
 289                               ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS) |
 290                                             AR724X_PCI_INT_DEV0);
 291                 /* flush write */
 292                 ar724x_pci_rr(AR724X_PCI_REG_INT_STATUS);
 293         }
 294 }
 295
 296 static struct irq_chip ar724x_pci_irq_chip = {
 297         .name           = "AR724X PCI ",
 298         .mask           = ar724x_pci_irq_mask,
 299         .unmask         = ar724x_pci_irq_unmask,
 300         .mask_ack       = ar724x_pci_irq_mask,
 301 };
 302
 303 static void __init ar724x_pci_irq_init(void)
 304 {
 305         u32 t;
 306         int i;
 307
 308         t = ar71xx_reset_rr(AR724X_RESET_REG_RESET_MODULE);
 309         if (t & (AR724X_RESET_PCIE | AR724X_RESET_PCIE_PHY |
 310                  AR724X_RESET_PCIE_PHY_SERIAL)) {
 311                 return;
 312         }
 313
 314         ar724x_pci_wr(AR724X_PCI_REG_INT_MASK, 0);
 315         ar724x_pci_wr(AR724X_PCI_REG_INT_STATUS, 0);
 316
 317         for (i = AR71XX_PCI_IRQ_BASE;
 318              i < AR71XX_PCI_IRQ_BASE + AR71XX_PCI_IRQ_COUNT; i++) {
 319                 irq_desc[i].status = IRQ_DISABLED;
 320                 set_irq_chip_and_handler(i, &ar724x_pci_irq_chip,
 321                                          handle_level_irq);
 322         }
 323
 324         set_irq_chained_handler(AR71XX_CPU_IRQ_IP2, ar724x_pci_irq_handler);
 325 }
 326
 327 int __init ar724x_pcibios_init(void)
 328 {
 329         int ret;
 330
 331         ar724x_pci_localcfg_base = ioremap_nocache(AR724X_PCI_CRP_BASE,
 332                                                    AR724X_PCI_CRP_SIZE);
 333
 334         ar724x_pci_devcfg_base = ioremap_nocache(AR724X_PCI_CFG_BASE,
 335                                                  AR724X_PCI_CFG_SIZE);
 336
 337         ar724x_pci_reset();
 338         ret = ar724x_pci_setup();
 339         if (ret)
 340                 return ret;
 341
 342         ar724x_pci_fixup_enable = 1;
 343         ar724x_pci_irq_init();
 344         register_pci_controller(&ar724x_pci_controller);
 345
 346         return 0;
 347 }