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[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.10 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/Kconfig
2 +++ b/drivers/net/ethernet/Kconfig
3 @@ -22,6 +22,7 @@ source "drivers/net/ethernet/adaptec/Kco
4 source "drivers/net/ethernet/aeroflex/Kconfig"
5 source "drivers/net/ethernet/alteon/Kconfig"
6 source "drivers/net/ethernet/amd/Kconfig"
7 +source "drivers/net/ethernet/ar231x/Kconfig"
8 source "drivers/net/ethernet/apple/Kconfig"
9 source "drivers/net/ethernet/atheros/Kconfig"
10 source "drivers/net/ethernet/cadence/Kconfig"
11 --- a/drivers/net/ethernet/Makefile
12 +++ b/drivers/net/ethernet/Makefile
13 @@ -9,6 +9,7 @@ obj-$(CONFIG_GRETH) += aeroflex/
14 obj-$(CONFIG_NET_VENDOR_ALTEON) += alteon/
15 obj-$(CONFIG_NET_VENDOR_AMD) += amd/
16 obj-$(CONFIG_NET_VENDOR_APPLE) += apple/
17 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x/
18 obj-$(CONFIG_NET_VENDOR_ATHEROS) += atheros/
19 obj-$(CONFIG_NET_CADENCE) += cadence/
20 obj-$(CONFIG_NET_BFIN) += adi/
21 --- /dev/null
22 +++ b/drivers/net/ethernet/ar231x/Kconfig
23 @@ -0,0 +1,5 @@
24 +config NET_VENDOR_AR231X
25 + tristate "AR231X Ethernet support"
26 + depends on ATHEROS_AR231X
27 + help
28 + Support for the AR231x/531x ethernet controller
29 --- /dev/null
30 +++ b/drivers/net/ethernet/ar231x/Makefile
31 @@ -0,0 +1 @@
32 +obj-$(CONFIG_NET_VENDOR_AR231X) += ar231x.o
33 --- /dev/null
34 +++ b/drivers/net/ethernet/ar231x/ar231x.c
35 @@ -0,0 +1,1249 @@
36 +/*
37 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
38 + *
39 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
40 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
41 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
42 + *
43 + * Thanks to Atheros for providing hardware and documentation
44 + * enabling me to write this driver.
45 + *
46 + * This program is free software; you can redistribute it and/or modify
47 + * it under the terms of the GNU General Public License as published by
48 + * the Free Software Foundation; either version 2 of the License, or
49 + * (at your option) any later version.
50 + *
51 + * Additional credits:
52 + * This code is taken from John Taylor's Sibyte driver and then
53 + * modified for the AR2313.
54 + */
55 +
56 +#include <linux/module.h>
57 +#include <linux/version.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/pci.h>
62 +#include <linux/netdevice.h>
63 +#include <linux/etherdevice.h>
64 +#include <linux/interrupt.h>
65 +#include <linux/hardirq.h>
66 +#include <linux/skbuff.h>
67 +#include <linux/init.h>
68 +#include <linux/delay.h>
69 +#include <linux/mm.h>
70 +#include <linux/highmem.h>
71 +#include <linux/sockios.h>
72 +#include <linux/pkt_sched.h>
73 +#include <linux/mii.h>
74 +#include <linux/phy.h>
75 +#include <linux/ethtool.h>
76 +#include <linux/ctype.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/io.h>
79 +#include <linux/uaccess.h>
80 +
81 +#include <net/sock.h>
82 +#include <net/ip.h>
83 +
84 +#define AR2313_MTU 1692
85 +#define AR2313_PRIOS 1
86 +#define AR2313_QUEUES (2*AR2313_PRIOS)
87 +#define AR2313_DESCR_ENTRIES 64
88 +
89 +
90 +#ifndef min
91 +#define min(a, b) (((a) < (b)) ? (a) : (b))
92 +#endif
93 +
94 +#ifndef SMP_CACHE_BYTES
95 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
96 +#endif
97 +
98 +#define AR2313_MBOX_SET_BIT 0x8
99 +
100 +#include "ar231x.h"
101 +
102 +/**
103 + * New interrupt handler strategy:
104 + *
105 + * An old interrupt handler worked using the traditional method of
106 + * replacing an skbuff with a new one when a packet arrives. However
107 + * the rx rings do not need to contain a static number of buffer
108 + * descriptors, thus it makes sense to move the memory allocation out
109 + * of the main interrupt handler and do it in a bottom half handler
110 + * and only allocate new buffers when the number of buffers in the
111 + * ring is below a certain threshold. In order to avoid starving the
112 + * NIC under heavy load it is however necessary to force allocation
113 + * when hitting a minimum threshold. The strategy for alloction is as
114 + * follows:
115 + *
116 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
117 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
118 + * the buffers in the interrupt handler
119 + * RX_RING_THRES - maximum number of buffers in the rx ring
120 + *
121 + * One advantagous side effect of this allocation approach is that the
122 + * entire rx processing can be done without holding any spin lock
123 + * since the rx rings and registers are totally independent of the tx
124 + * ring and its registers. This of course includes the kmalloc's of
125 + * new skb's. Thus start_xmit can run in parallel with rx processing
126 + * and the memory allocation on SMP systems.
127 + *
128 + * Note that running the skb reallocation in a bottom half opens up
129 + * another can of races which needs to be handled properly. In
130 + * particular it can happen that the interrupt handler tries to run
131 + * the reallocation while the bottom half is either running on another
132 + * CPU or was interrupted on the same CPU. To get around this the
133 + * driver uses bitops to prevent the reallocation routines from being
134 + * reentered.
135 + *
136 + * TX handling can also be done without holding any spin lock, wheee
137 + * this is fun! since tx_csm is only written to by the interrupt
138 + * handler.
139 + */
140 +
141 +/**
142 + * Threshold values for RX buffer allocation - the low water marks for
143 + * when to start refilling the rings are set to 75% of the ring
144 + * sizes. It seems to make sense to refill the rings entirely from the
145 + * intrrupt handler once it gets below the panic threshold, that way
146 + * we don't risk that the refilling is moved to another CPU when the
147 + * one running the interrupt handler just got the slab code hot in its
148 + * cache.
149 + */
150 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
151 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
152 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
153 +#define CRC_LEN 4
154 +#define RX_OFFSET 2
155 +
156 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
157 +#define VLAN_HDR 4
158 +#else
159 +#define VLAN_HDR 0
160 +#endif
161 +
162 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
163 + RX_OFFSET)
164 +
165 +#ifdef MODULE
166 +MODULE_LICENSE("GPL");
167 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@openwrt.org>");
168 +MODULE_DESCRIPTION("AR231x Ethernet driver");
169 +#endif
170 +
171 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
172 +
173 +/* prototypes */
174 +static void ar231x_halt(struct net_device *dev);
175 +static void rx_tasklet_func(unsigned long data);
176 +static void rx_tasklet_cleanup(struct net_device *dev);
177 +static void ar231x_multicast_list(struct net_device *dev);
178 +static void ar231x_tx_timeout(struct net_device *dev);
179 +
180 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
181 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
182 + u16 value);
183 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
184 +static int ar231x_mdiobus_probe(struct net_device *dev);
185 +static void ar231x_adjust_link(struct net_device *dev);
186 +
187 +#ifndef ERR
188 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
189 +#endif
190 +
191 +#ifdef CONFIG_NET_POLL_CONTROLLER
192 +static void
193 +ar231x_netpoll(struct net_device *dev)
194 +{
195 + unsigned long flags;
196 +
197 + local_irq_save(flags);
198 + ar231x_interrupt(dev->irq, dev);
199 + local_irq_restore(flags);
200 +}
201 +#endif
202 +
203 +static const struct net_device_ops ar231x_ops = {
204 + .ndo_open = ar231x_open,
205 + .ndo_stop = ar231x_close,
206 + .ndo_start_xmit = ar231x_start_xmit,
207 + .ndo_set_rx_mode = ar231x_multicast_list,
208 + .ndo_do_ioctl = ar231x_ioctl,
209 + .ndo_change_mtu = eth_change_mtu,
210 + .ndo_validate_addr = eth_validate_addr,
211 + .ndo_set_mac_address = eth_mac_addr,
212 + .ndo_tx_timeout = ar231x_tx_timeout,
213 +#ifdef CONFIG_NET_POLL_CONTROLLER
214 + .ndo_poll_controller = ar231x_netpoll,
215 +#endif
216 +};
217 +
218 +int ar231x_probe(struct platform_device *pdev)
219 +{
220 + struct net_device *dev;
221 + struct ar231x_private *sp;
222 + struct resource *res;
223 + unsigned long ar_eth_base;
224 + char buf[64];
225 +
226 + dev = alloc_etherdev(sizeof(struct ar231x_private));
227 +
228 + if (dev == NULL) {
229 + printk(KERN_ERR
230 + "ar231x: Unable to allocate net_device structure!\n");
231 + return -ENOMEM;
232 + }
233 +
234 + platform_set_drvdata(pdev, dev);
235 +
236 + sp = netdev_priv(dev);
237 + sp->dev = dev;
238 + sp->cfg = pdev->dev.platform_data;
239 +
240 + sprintf(buf, "eth%d_membase", pdev->id);
241 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
242 + if (!res)
243 + return -ENODEV;
244 +
245 + sp->link = 0;
246 + ar_eth_base = res->start;
247 +
248 + sprintf(buf, "eth%d_irq", pdev->id);
249 + dev->irq = platform_get_irq_byname(pdev, buf);
250 +
251 + spin_lock_init(&sp->lock);
252 +
253 + dev->features |= NETIF_F_HIGHDMA;
254 + dev->netdev_ops = &ar231x_ops;
255 +
256 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long) dev);
257 + tasklet_disable(&sp->rx_tasklet);
258 +
259 + sp->eth_regs = ioremap_nocache(virt_to_phys(ar_eth_base),
260 + sizeof(*sp->eth_regs));
261 + if (!sp->eth_regs) {
262 + printk("Can't remap eth registers\n");
263 + return -ENXIO;
264 + }
265 +
266 + /**
267 + * When there's only one MAC, PHY regs are typically on ENET0,
268 + * even though the MAC might be on ENET1.
269 + * Needto remap PHY regs separately in this case
270 + */
271 + if (virt_to_phys(ar_eth_base) == virt_to_phys(sp->phy_regs))
272 + sp->phy_regs = sp->eth_regs;
273 + else {
274 + sp->phy_regs =
275 + ioremap_nocache(virt_to_phys(sp->cfg->phy_base),
276 + sizeof(*sp->phy_regs));
277 + if (!sp->phy_regs) {
278 + printk("Can't remap phy registers\n");
279 + return -ENXIO;
280 + }
281 + }
282 +
283 + sp->dma_regs =
284 + ioremap_nocache(virt_to_phys(ar_eth_base + 0x1000),
285 + sizeof(*sp->dma_regs));
286 + dev->base_addr = (unsigned int) sp->dma_regs;
287 + if (!sp->dma_regs) {
288 + printk("Can't remap DMA registers\n");
289 + return -ENXIO;
290 + }
291 +
292 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
293 + sp->name[sizeof(sp->name) - 1] = '\0';
294 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
295 +
296 + if (ar231x_init(dev)) {
297 + /* ar231x_init() calls ar231x_init_cleanup() on error */
298 + kfree(dev);
299 + return -ENODEV;
300 + }
301 +
302 + if (register_netdev(dev)) {
303 + printk("%s: register_netdev failed\n", __func__);
304 + return -1;
305 + }
306 +
307 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
308 + dev->irq);
309 +
310 + sp->mii_bus = mdiobus_alloc();
311 + if (sp->mii_bus == NULL)
312 + return -1;
313 +
314 + sp->mii_bus->priv = dev;
315 + sp->mii_bus->read = ar231x_mdiobus_read;
316 + sp->mii_bus->write = ar231x_mdiobus_write;
317 + sp->mii_bus->reset = ar231x_mdiobus_reset;
318 + sp->mii_bus->name = "ar231x_eth_mii";
319 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
320 + sp->mii_bus->irq = kmalloc(sizeof(int), GFP_KERNEL);
321 + *sp->mii_bus->irq = PHY_POLL;
322 +
323 + mdiobus_register(sp->mii_bus);
324 +
325 + if (ar231x_mdiobus_probe(dev) != 0) {
326 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
327 + rx_tasklet_cleanup(dev);
328 + ar231x_init_cleanup(dev);
329 + unregister_netdev(dev);
330 + kfree(dev);
331 + return -ENODEV;
332 + }
333 +
334 + /* start link poll timer */
335 + ar231x_setup_timer(dev);
336 +
337 + return 0;
338 +}
339 +
340 +
341 +static void ar231x_multicast_list(struct net_device *dev)
342 +{
343 + struct ar231x_private *sp = netdev_priv(dev);
344 + unsigned int filter;
345 +
346 + filter = sp->eth_regs->mac_control;
347 +
348 + if (dev->flags & IFF_PROMISC)
349 + filter |= MAC_CONTROL_PR;
350 + else
351 + filter &= ~MAC_CONTROL_PR;
352 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
353 + filter |= MAC_CONTROL_PM;
354 + else
355 + filter &= ~MAC_CONTROL_PM;
356 +
357 + sp->eth_regs->mac_control = filter;
358 +}
359 +
360 +static void rx_tasklet_cleanup(struct net_device *dev)
361 +{
362 + struct ar231x_private *sp = netdev_priv(dev);
363 +
364 + /**
365 + * Tasklet may be scheduled. Need to get it removed from the list
366 + * since we're about to free the struct.
367 + */
368 +
369 + sp->unloading = 1;
370 + tasklet_enable(&sp->rx_tasklet);
371 + tasklet_kill(&sp->rx_tasklet);
372 +}
373 +
374 +static int ar231x_remove(struct platform_device *pdev)
375 +{
376 + struct net_device *dev = platform_get_drvdata(pdev);
377 + struct ar231x_private *sp = netdev_priv(dev);
378 + rx_tasklet_cleanup(dev);
379 + ar231x_init_cleanup(dev);
380 + unregister_netdev(dev);
381 + mdiobus_unregister(sp->mii_bus);
382 + mdiobus_free(sp->mii_bus);
383 + kfree(dev);
384 + return 0;
385 +}
386 +
387 +
388 +/**
389 + * Restart the AR2313 ethernet controller.
390 + */
391 +static int ar231x_restart(struct net_device *dev)
392 +{
393 + /* disable interrupts */
394 + disable_irq(dev->irq);
395 +
396 + /* stop mac */
397 + ar231x_halt(dev);
398 +
399 + /* initialize */
400 + ar231x_init(dev);
401 +
402 + /* enable interrupts */
403 + enable_irq(dev->irq);
404 +
405 + return 0;
406 +}
407 +
408 +static struct platform_driver ar231x_driver = {
409 + .driver.name = "ar231x-eth",
410 + .probe = ar231x_probe,
411 + .remove = ar231x_remove,
412 +};
413 +
414 +module_platform_driver(ar231x_driver);
415 +
416 +static void ar231x_free_descriptors(struct net_device *dev)
417 +{
418 + struct ar231x_private *sp = netdev_priv(dev);
419 + if (sp->rx_ring != NULL) {
420 + kfree((void *)KSEG0ADDR(sp->rx_ring));
421 + sp->rx_ring = NULL;
422 + sp->tx_ring = NULL;
423 + }
424 +}
425 +
426 +
427 +static int ar231x_allocate_descriptors(struct net_device *dev)
428 +{
429 + struct ar231x_private *sp = netdev_priv(dev);
430 + int size;
431 + int j;
432 + ar231x_descr_t *space;
433 +
434 + if (sp->rx_ring != NULL) {
435 + printk("%s: already done.\n", __func__);
436 + return 0;
437 + }
438 +
439 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
440 + space = kmalloc(size, GFP_KERNEL);
441 + if (space == NULL)
442 + return 1;
443 +
444 + /* invalidate caches */
445 + dma_cache_inv((unsigned int) space, size);
446 +
447 + /* now convert pointer to KSEG1 */
448 + space = (ar231x_descr_t *)KSEG1ADDR(space);
449 +
450 + memset((void *)space, 0, size);
451 +
452 + sp->rx_ring = space;
453 + space += AR2313_DESCR_ENTRIES;
454 +
455 + sp->tx_ring = space;
456 + space += AR2313_DESCR_ENTRIES;
457 +
458 + /* Initialize the transmit Descriptors */
459 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
460 + ar231x_descr_t *td = &sp->tx_ring[j];
461 + td->status = 0;
462 + td->devcs = DMA_TX1_CHAINED;
463 + td->addr = 0;
464 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
465 + }
466 +
467 + return 0;
468 +}
469 +
470 +
471 +/**
472 + * Generic cleanup handling data allocated during init. Used when the
473 + * module is unloaded or if an error occurs during initialization
474 + */
475 +static void ar231x_init_cleanup(struct net_device *dev)
476 +{
477 + struct ar231x_private *sp = netdev_priv(dev);
478 + struct sk_buff *skb;
479 + int j;
480 +
481 + ar231x_free_descriptors(dev);
482 +
483 + if (sp->eth_regs)
484 + iounmap((void *)sp->eth_regs);
485 + if (sp->dma_regs)
486 + iounmap((void *)sp->dma_regs);
487 +
488 + if (sp->rx_skb) {
489 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
490 + skb = sp->rx_skb[j];
491 + if (skb) {
492 + sp->rx_skb[j] = NULL;
493 + dev_kfree_skb(skb);
494 + }
495 + }
496 + kfree(sp->rx_skb);
497 + sp->rx_skb = NULL;
498 + }
499 +
500 + if (sp->tx_skb) {
501 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
502 + skb = sp->tx_skb[j];
503 + if (skb) {
504 + sp->tx_skb[j] = NULL;
505 + dev_kfree_skb(skb);
506 + }
507 + }
508 + kfree(sp->tx_skb);
509 + sp->tx_skb = NULL;
510 + }
511 +}
512 +
513 +static int ar231x_setup_timer(struct net_device *dev)
514 +{
515 + struct ar231x_private *sp = netdev_priv(dev);
516 +
517 + init_timer(&sp->link_timer);
518 +
519 + sp->link_timer.function = ar231x_link_timer_fn;
520 + sp->link_timer.data = (int) dev;
521 + sp->link_timer.expires = jiffies + HZ;
522 +
523 + add_timer(&sp->link_timer);
524 + return 0;
525 +}
526 +
527 +static void ar231x_link_timer_fn(unsigned long data)
528 +{
529 + struct net_device *dev = (struct net_device *)data;
530 + struct ar231x_private *sp = netdev_priv(dev);
531 +
532 + /**
533 + * See if the link status changed.
534 + * This was needed to make sure we set the PHY to the
535 + * autonegotiated value of half or full duplex.
536 + */
537 + ar231x_check_link(dev);
538 +
539 + /**
540 + * Loop faster when we don't have link.
541 + * This was needed to speed up the AP bootstrap time.
542 + */
543 + if (sp->link == 0)
544 + mod_timer(&sp->link_timer, jiffies + HZ / 2);
545 + else
546 + mod_timer(&sp->link_timer, jiffies + LINK_TIMER);
547 +}
548 +
549 +static void ar231x_check_link(struct net_device *dev)
550 +{
551 + struct ar231x_private *sp = netdev_priv(dev);
552 + u16 phy_data;
553 +
554 + phy_data = ar231x_mdiobus_read(sp->mii_bus, sp->phy, MII_BMSR);
555 + if (sp->phy_data != phy_data) {
556 + if (phy_data & BMSR_LSTATUS) {
557 + /**
558 + * Link is present, ready link partner ability to
559 + * deterine duplexity.
560 + */
561 + int duplex = 0;
562 + u16 reg;
563 +
564 + sp->link = 1;
565 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
566 + MII_BMCR);
567 + if (reg & BMCR_ANENABLE) {
568 + /* auto neg enabled */
569 + reg = ar231x_mdiobus_read(sp->mii_bus, sp->phy,
570 + MII_LPA);
571 + duplex = reg & (LPA_100FULL | LPA_10FULL) ?
572 + 1 : 0;
573 + } else {
574 + /* no auto neg, just read duplex config */
575 + duplex = (reg & BMCR_FULLDPLX) ? 1 : 0;
576 + }
577 +
578 + printk(KERN_INFO "%s: Configuring MAC for %s duplex\n",
579 + dev->name, (duplex) ? "full" : "half");
580 +
581 + if (duplex) {
582 + /* full duplex */
583 + sp->eth_regs->mac_control =
584 + (sp->eth_regs->mac_control |
585 + MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
586 + } else {
587 + /* half duplex */
588 + sp->eth_regs->mac_control =
589 + (sp->eth_regs->mac_control |
590 + MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
591 + }
592 + } else {
593 + /* no link */
594 + sp->link = 0;
595 + }
596 + sp->phy_data = phy_data;
597 + }
598 +}
599 +
600 +static int ar231x_reset_reg(struct net_device *dev)
601 +{
602 + struct ar231x_private *sp = netdev_priv(dev);
603 + unsigned int ethsal, ethsah;
604 + unsigned int flags;
605 +
606 + sp->cfg->reset_set(sp->cfg->reset_mac);
607 + mdelay(10);
608 + sp->cfg->reset_clear(sp->cfg->reset_mac);
609 + mdelay(10);
610 + sp->cfg->reset_set(sp->cfg->reset_phy);
611 + mdelay(10);
612 + sp->cfg->reset_clear(sp->cfg->reset_phy);
613 + mdelay(10);
614 +
615 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
616 + mdelay(10);
617 + sp->dma_regs->bus_mode =
618 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
619 +
620 + /* enable interrupts */
621 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
622 + DMA_STATUS_RI | DMA_STATUS_TI |
623 + DMA_STATUS_FBE;
624 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
625 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
626 + sp->dma_regs->control =
627 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
628 +
629 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
630 + sp->eth_regs->vlan_tag = (0x8100);
631 +
632 + /* Enable Ethernet Interface */
633 + flags = (MAC_CONTROL_TE | /* transmit enable */
634 + MAC_CONTROL_PM | /* pass mcast */
635 + MAC_CONTROL_F | /* full duplex */
636 + MAC_CONTROL_HBD); /* heart beat disabled */
637 +
638 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
639 + flags |= MAC_CONTROL_PR;
640 + }
641 + sp->eth_regs->mac_control = flags;
642 +
643 + /* Set all Ethernet station address registers to their initial values */
644 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
645 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
646 +
647 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
648 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
649 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
650 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
651 +
652 + sp->eth_regs->mac_addr[0] = ethsah;
653 + sp->eth_regs->mac_addr[1] = ethsal;
654 +
655 + mdelay(10);
656 +
657 + return 0;
658 +}
659 +
660 +
661 +static int ar231x_init(struct net_device *dev)
662 +{
663 + struct ar231x_private *sp = netdev_priv(dev);
664 + int ecode = 0;
665 +
666 + /* Allocate descriptors */
667 + if (ar231x_allocate_descriptors(dev)) {
668 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
669 + dev->name, __func__);
670 + ecode = -EAGAIN;
671 + goto init_error;
672 + }
673 +
674 + /* Get the memory for the skb rings */
675 + if (sp->rx_skb == NULL) {
676 + sp->rx_skb =
677 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
678 + GFP_KERNEL);
679 + if (!(sp->rx_skb)) {
680 + printk("%s: %s: rx_skb kmalloc failed\n",
681 + dev->name, __func__);
682 + ecode = -EAGAIN;
683 + goto init_error;
684 + }
685 + }
686 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
687 +
688 + if (sp->tx_skb == NULL) {
689 + sp->tx_skb =
690 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
691 + GFP_KERNEL);
692 + if (!(sp->tx_skb)) {
693 + printk("%s: %s: tx_skb kmalloc failed\n",
694 + dev->name, __func__);
695 + ecode = -EAGAIN;
696 + goto init_error;
697 + }
698 + }
699 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
700 +
701 + /**
702 + * Set tx_csm before we start receiving interrupts, otherwise
703 + * the interrupt handler might think it is supposed to process
704 + * tx ints before we are up and running, which may cause a null
705 + * pointer access in the int handler.
706 + */
707 + sp->rx_skbprd = 0;
708 + sp->cur_rx = 0;
709 + sp->tx_prd = 0;
710 + sp->tx_csm = 0;
711 +
712 + /* Zero the stats before starting the interface */
713 + memset(&dev->stats, 0, sizeof(dev->stats));
714 +
715 + /**
716 + * We load the ring here as there seem to be no way to tell the
717 + * firmware to wipe the ring without re-initializing it.
718 + */
719 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
720 +
721 + /* Init hardware */
722 + ar231x_reset_reg(dev);
723 +
724 + /* Get the IRQ */
725 + ecode =
726 + request_irq(dev->irq, &ar231x_interrupt,
727 + IRQF_DISABLED,
728 + dev->name, dev);
729 + if (ecode) {
730 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
731 + dev->name, __func__, dev->irq);
732 + goto init_error;
733 + }
734 +
735 +
736 + tasklet_enable(&sp->rx_tasklet);
737 +
738 + return 0;
739 +
740 +init_error:
741 + ar231x_init_cleanup(dev);
742 + return ecode;
743 +}
744 +
745 +/**
746 + * Load the rx ring.
747 + *
748 + * Loading rings is safe without holding the spin lock since this is
749 + * done only before the device is enabled, thus no interrupts are
750 + * generated and by the interrupt handler/tasklet handler.
751 + */
752 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
753 +{
754 + struct ar231x_private *sp = netdev_priv(dev);
755 + short i, idx;
756 +
757 + idx = sp->rx_skbprd;
758 +
759 + for (i = 0; i < nr_bufs; i++) {
760 + struct sk_buff *skb;
761 + ar231x_descr_t *rd;
762 +
763 + if (sp->rx_skb[idx])
764 + break;
765 +
766 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
767 + if (!skb) {
768 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
769 + __func__);
770 + break;
771 + }
772 +
773 + /* Make sure IP header starts on a fresh cache line */
774 + skb->dev = dev;
775 + sp->rx_skb[idx] = skb;
776 +
777 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
778 +
779 + /* initialize dma descriptor */
780 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
781 + DMA_RX1_CHAINED);
782 + rd->addr = virt_to_phys(skb->data);
783 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
784 + rd->status = DMA_RX_OWN;
785 +
786 + idx = DSC_NEXT(idx);
787 + }
788 +
789 + if (i)
790 + sp->rx_skbprd = idx;
791 +
792 + return;
793 +}
794 +
795 +#define AR2313_MAX_PKTS_PER_CALL 64
796 +
797 +static int ar231x_rx_int(struct net_device *dev)
798 +{
799 + struct ar231x_private *sp = netdev_priv(dev);
800 + struct sk_buff *skb, *skb_new;
801 + ar231x_descr_t *rxdesc;
802 + unsigned int status;
803 + u32 idx;
804 + int pkts = 0;
805 + int rval;
806 +
807 + idx = sp->cur_rx;
808 +
809 + /* process at most the entire ring and then wait for another int */
810 + while (1) {
811 + rxdesc = &sp->rx_ring[idx];
812 + status = rxdesc->status;
813 +
814 + if (status & DMA_RX_OWN) {
815 + /* SiByte owns descriptor or descr not yet filled in */
816 + rval = 0;
817 + break;
818 + }
819 +
820 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
821 + rval = 1;
822 + break;
823 + }
824 +
825 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
826 + dev->stats.rx_errors++;
827 + dev->stats.rx_dropped++;
828 +
829 + /* add statistics counters */
830 + if (status & DMA_RX_ERR_CRC)
831 + dev->stats.rx_crc_errors++;
832 + if (status & DMA_RX_ERR_COL)
833 + dev->stats.rx_over_errors++;
834 + if (status & DMA_RX_ERR_LENGTH)
835 + dev->stats.rx_length_errors++;
836 + if (status & DMA_RX_ERR_RUNT)
837 + dev->stats.rx_over_errors++;
838 + if (status & DMA_RX_ERR_DESC)
839 + dev->stats.rx_over_errors++;
840 +
841 + } else {
842 + /* alloc new buffer. */
843 + skb_new = netdev_alloc_skb_ip_align(dev,
844 + AR2313_BUFSIZE);
845 + if (skb_new != NULL) {
846 + skb = sp->rx_skb[idx];
847 + /* set skb */
848 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
849 + 0x3fff) - CRC_LEN);
850 +
851 + dev->stats.rx_bytes += skb->len;
852 + skb->protocol = eth_type_trans(skb, dev);
853 + /* pass the packet to upper layers */
854 + netif_rx(skb);
855 +
856 + skb_new->dev = dev;
857 + /* reset descriptor's curr_addr */
858 + rxdesc->addr = virt_to_phys(skb_new->data);
859 +
860 + dev->stats.rx_packets++;
861 + sp->rx_skb[idx] = skb_new;
862 + } else {
863 + dev->stats.rx_dropped++;
864 + }
865 + }
866 +
867 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
868 + DMA_RX1_CHAINED);
869 + rxdesc->status = DMA_RX_OWN;
870 +
871 + idx = DSC_NEXT(idx);
872 + }
873 +
874 + sp->cur_rx = idx;
875 +
876 + return rval;
877 +}
878 +
879 +
880 +static void ar231x_tx_int(struct net_device *dev)
881 +{
882 + struct ar231x_private *sp = netdev_priv(dev);
883 + u32 idx;
884 + struct sk_buff *skb;
885 + ar231x_descr_t *txdesc;
886 + unsigned int status = 0;
887 +
888 + idx = sp->tx_csm;
889 +
890 + while (idx != sp->tx_prd) {
891 + txdesc = &sp->tx_ring[idx];
892 + status = txdesc->status;
893 +
894 + if (status & DMA_TX_OWN) {
895 + /* ar231x dma still owns descr */
896 + break;
897 + }
898 + /* done with this descriptor */
899 + dma_unmap_single(NULL, txdesc->addr,
900 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
901 + DMA_TO_DEVICE);
902 + txdesc->status = 0;
903 +
904 + if (status & DMA_TX_ERROR) {
905 + dev->stats.tx_errors++;
906 + dev->stats.tx_dropped++;
907 + if (status & DMA_TX_ERR_UNDER)
908 + dev->stats.tx_fifo_errors++;
909 + if (status & DMA_TX_ERR_HB)
910 + dev->stats.tx_heartbeat_errors++;
911 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
912 + dev->stats.tx_carrier_errors++;
913 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
914 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
915 + dev->stats.tx_aborted_errors++;
916 + } else {
917 + /* transmit OK */
918 + dev->stats.tx_packets++;
919 + }
920 +
921 + skb = sp->tx_skb[idx];
922 + sp->tx_skb[idx] = NULL;
923 + idx = DSC_NEXT(idx);
924 + dev->stats.tx_bytes += skb->len;
925 + dev_kfree_skb_irq(skb);
926 + }
927 +
928 + sp->tx_csm = idx;
929 +
930 + return;
931 +}
932 +
933 +
934 +static void rx_tasklet_func(unsigned long data)
935 +{
936 + struct net_device *dev = (struct net_device *)data;
937 + struct ar231x_private *sp = netdev_priv(dev);
938 +
939 + if (sp->unloading)
940 + return;
941 +
942 + if (ar231x_rx_int(dev)) {
943 + tasklet_hi_schedule(&sp->rx_tasklet);
944 + } else {
945 + unsigned long flags;
946 + spin_lock_irqsave(&sp->lock, flags);
947 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
948 + spin_unlock_irqrestore(&sp->lock, flags);
949 + }
950 +}
951 +
952 +static void rx_schedule(struct net_device *dev)
953 +{
954 + struct ar231x_private *sp = netdev_priv(dev);
955 +
956 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
957 +
958 + tasklet_hi_schedule(&sp->rx_tasklet);
959 +}
960 +
961 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
962 +{
963 + struct net_device *dev = (struct net_device *)dev_id;
964 + struct ar231x_private *sp = netdev_priv(dev);
965 + unsigned int status, enabled;
966 +
967 + /* clear interrupt */
968 + /* Don't clear RI bit if currently disabled */
969 + status = sp->dma_regs->status;
970 + enabled = sp->dma_regs->intr_ena;
971 + sp->dma_regs->status = status & enabled;
972 +
973 + if (status & DMA_STATUS_NIS) {
974 + /* normal status */
975 + /**
976 + * Don't schedule rx processing if interrupt
977 + * is already disabled.
978 + */
979 + if (status & enabled & DMA_STATUS_RI) {
980 + /* receive interrupt */
981 + rx_schedule(dev);
982 + }
983 + if (status & DMA_STATUS_TI) {
984 + /* transmit interrupt */
985 + ar231x_tx_int(dev);
986 + }
987 + }
988 +
989 + /* abnormal status */
990 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
991 + ar231x_restart(dev);
992 +
993 + return IRQ_HANDLED;
994 +}
995 +
996 +
997 +static int ar231x_open(struct net_device *dev)
998 +{
999 + struct ar231x_private *sp = netdev_priv(dev);
1000 + unsigned int ethsal, ethsah;
1001 +
1002 + /* reset the hardware, in case the MAC address changed */
1003 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
1004 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
1005 +
1006 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
1007 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
1008 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
1009 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
1010 +
1011 + sp->eth_regs->mac_addr[0] = ethsah;
1012 + sp->eth_regs->mac_addr[1] = ethsal;
1013 +
1014 + mdelay(10);
1015 +
1016 + dev->mtu = 1500;
1017 + netif_start_queue(dev);
1018 +
1019 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
1020 +
1021 + return 0;
1022 +}
1023 +
1024 +static void ar231x_tx_timeout(struct net_device *dev)
1025 +{
1026 + struct ar231x_private *sp = netdev_priv(dev);
1027 + unsigned long flags;
1028 +
1029 + spin_lock_irqsave(&sp->lock, flags);
1030 + ar231x_restart(dev);
1031 + spin_unlock_irqrestore(&sp->lock, flags);
1032 +}
1033 +
1034 +static void ar231x_halt(struct net_device *dev)
1035 +{
1036 + struct ar231x_private *sp = netdev_priv(dev);
1037 + int j;
1038 +
1039 + tasklet_disable(&sp->rx_tasklet);
1040 +
1041 + /* kill the MAC */
1042 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
1043 + MAC_CONTROL_TE); /* disable Transmits */
1044 + /* stop dma */
1045 + sp->dma_regs->control = 0;
1046 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
1047 +
1048 + /* place phy and MAC in reset */
1049 + sp->cfg->reset_set(sp->cfg->reset_mac);
1050 + sp->cfg->reset_set(sp->cfg->reset_phy);
1051 +
1052 + /* free buffers on tx ring */
1053 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
1054 + struct sk_buff *skb;
1055 + ar231x_descr_t *txdesc;
1056 +
1057 + txdesc = &sp->tx_ring[j];
1058 + txdesc->descr = 0;
1059 +
1060 + skb = sp->tx_skb[j];
1061 + if (skb) {
1062 + dev_kfree_skb(skb);
1063 + sp->tx_skb[j] = NULL;
1064 + }
1065 + }
1066 +}
1067 +
1068 +/**
1069 + * close should do nothing. Here's why. It's called when
1070 + * 'ifconfig bond0 down' is run. If it calls free_irq then
1071 + * the irq is gone forever ! When bond0 is made 'up' again,
1072 + * the ar231x_open () does not call request_irq (). Worse,
1073 + * the call to ar231x_halt() generates a WDOG reset due to
1074 + * the write to reset register and the box reboots.
1075 + * Commenting this out is good since it allows the
1076 + * system to resume when bond0 is made up again.
1077 + */
1078 +static int ar231x_close(struct net_device *dev)
1079 +{
1080 +#if 0
1081 + /* Disable interrupts */
1082 + disable_irq(dev->irq);
1083 +
1084 + /**
1085 + * Without (or before) releasing irq and stopping hardware, this
1086 + * is an absolute non-sense, by the way. It will be reset instantly
1087 + * by the first irq.
1088 + */
1089 + netif_stop_queue(dev);
1090 +
1091 + /* stop the MAC and DMA engines */
1092 + ar231x_halt(dev);
1093 +
1094 + /* release the interrupt */
1095 + free_irq(dev->irq, dev);
1096 +
1097 +#endif
1098 + return 0;
1099 +}
1100 +
1101 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
1102 +{
1103 + struct ar231x_private *sp = netdev_priv(dev);
1104 + ar231x_descr_t *td;
1105 + u32 idx;
1106 +
1107 + idx = sp->tx_prd;
1108 + td = &sp->tx_ring[idx];
1109 +
1110 + if (td->status & DMA_TX_OWN) {
1111 + /* free skbuf and lie to the caller that we sent it out */
1112 + dev->stats.tx_dropped++;
1113 + dev_kfree_skb(skb);
1114 +
1115 + /* restart transmitter in case locked */
1116 + sp->dma_regs->xmt_poll = 0;
1117 + return 0;
1118 + }
1119 +
1120 + /* Setup the transmit descriptor. */
1121 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1122 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1123 + td->addr = dma_map_single(NULL, skb->data, skb->len, DMA_TO_DEVICE);
1124 + td->status = DMA_TX_OWN;
1125 +
1126 + /* kick transmitter last */
1127 + sp->dma_regs->xmt_poll = 0;
1128 +
1129 + sp->tx_skb[idx] = skb;
1130 + idx = DSC_NEXT(idx);
1131 + sp->tx_prd = idx;
1132 +
1133 + return 0;
1134 +}
1135 +
1136 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1137 +{
1138 + struct ar231x_private *sp = netdev_priv(dev);
1139 + int ret;
1140 +
1141 + switch (cmd) {
1142 + case SIOCETHTOOL:
1143 + spin_lock_irq(&sp->lock);
1144 + ret = phy_ethtool_ioctl(sp->phy_dev, (void *)ifr->ifr_data);
1145 + spin_unlock_irq(&sp->lock);
1146 + return ret;
1147 +
1148 + case SIOCSIFHWADDR:
1149 + if (copy_from_user
1150 + (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
1151 + return -EFAULT;
1152 + return 0;
1153 +
1154 + case SIOCGIFHWADDR:
1155 + if (copy_to_user
1156 + (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
1157 + return -EFAULT;
1158 + return 0;
1159 +
1160 + case SIOCGMIIPHY:
1161 + case SIOCGMIIREG:
1162 + case SIOCSMIIREG:
1163 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1164 +
1165 + default:
1166 + break;
1167 + }
1168 +
1169 + return -EOPNOTSUPP;
1170 +}
1171 +
1172 +static void ar231x_adjust_link(struct net_device *dev)
1173 +{
1174 + struct ar231x_private *sp = netdev_priv(dev);
1175 + unsigned int mc;
1176 +
1177 + if (!sp->phy_dev->link)
1178 + return;
1179 +
1180 + if (sp->phy_dev->duplex != sp->oldduplex) {
1181 + mc = readl(&sp->eth_regs->mac_control);
1182 + mc &= ~(MAC_CONTROL_F | MAC_CONTROL_DRO);
1183 + if (sp->phy_dev->duplex)
1184 + mc |= MAC_CONTROL_F;
1185 + else
1186 + mc |= MAC_CONTROL_DRO;
1187 + writel(mc, &sp->eth_regs->mac_control);
1188 + sp->oldduplex = sp->phy_dev->duplex;
1189 + }
1190 +}
1191 +
1192 +#define MII_ADDR(phy, reg) \
1193 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1194 +
1195 +static int
1196 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1197 +{
1198 + struct net_device *const dev = bus->priv;
1199 + struct ar231x_private *sp = netdev_priv(dev);
1200 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1201 +
1202 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1203 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1204 + ;
1205 + return ethernet->mii_data >> MII_DATA_SHIFT;
1206 +}
1207 +
1208 +static int
1209 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1210 +{
1211 + struct net_device *const dev = bus->priv;
1212 + struct ar231x_private *sp = netdev_priv(dev);
1213 + volatile ETHERNET_STRUCT *ethernet = sp->phy_regs;
1214 +
1215 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1216 + ;
1217 + ethernet->mii_data = value << MII_DATA_SHIFT;
1218 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1219 +
1220 + return 0;
1221 +}
1222 +
1223 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1224 +{
1225 + struct net_device *const dev = bus->priv;
1226 +
1227 + ar231x_reset_reg(dev);
1228 +
1229 + return 0;
1230 +}
1231 +
1232 +static int ar231x_mdiobus_probe(struct net_device *dev)
1233 +{
1234 + struct ar231x_private *const sp = netdev_priv(dev);
1235 + struct phy_device *phydev = NULL;
1236 + int phy_addr;
1237 +
1238 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1239 + for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++)
1240 + if (sp->mii_bus->phy_map[phy_addr]) {
1241 + phydev = sp->mii_bus->phy_map[phy_addr];
1242 + sp->phy = phy_addr;
1243 + break; /* break out with first one found */
1244 + }
1245 +
1246 + if (!phydev) {
1247 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1248 + return -1;
1249 + }
1250 +
1251 + /* now we are supposed to have a proper phydev, to attach to... */
1252 + BUG_ON(!phydev);
1253 + BUG_ON(phydev->attached_dev);
1254 +
1255 + phydev = phy_connect(dev, dev_name(&phydev->dev), &ar231x_adjust_link,
1256 + PHY_INTERFACE_MODE_MII);
1257 +
1258 + if (IS_ERR(phydev)) {
1259 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1260 + return PTR_ERR(phydev);
1261 + }
1262 +
1263 + /* mask with MAC supported features */
1264 + phydev->supported &= (SUPPORTED_10baseT_Half
1265 + | SUPPORTED_10baseT_Full
1266 + | SUPPORTED_100baseT_Half
1267 + | SUPPORTED_100baseT_Full
1268 + | SUPPORTED_Autoneg
1269 + /* | SUPPORTED_Pause | SUPPORTED_Asym_Pause */
1270 + | SUPPORTED_MII
1271 + | SUPPORTED_TP);
1272 +
1273 + phydev->advertising = phydev->supported;
1274 +
1275 + sp->oldduplex = -1;
1276 + sp->phy_dev = phydev;
1277 +
1278 + printk(KERN_INFO "%s: attached PHY driver [%s] "
1279 + "(mii_bus:phy_addr=%s)\n",
1280 + dev->name, phydev->drv->name, dev_name(&phydev->dev));
1281 +
1282 + return 0;
1283 +}
1284 +
1285 --- /dev/null
1286 +++ b/drivers/net/ethernet/ar231x/ar231x.h
1287 @@ -0,0 +1,287 @@
1288 +/*
1289 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1290 + *
1291 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1292 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1293 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1294 + *
1295 + * Thanks to Atheros for providing hardware and documentation
1296 + * enabling me to write this driver.
1297 + *
1298 + * This program is free software; you can redistribute it and/or modify
1299 + * it under the terms of the GNU General Public License as published by
1300 + * the Free Software Foundation; either version 2 of the License, or
1301 + * (at your option) any later version.
1302 + */
1303 +
1304 +#ifndef _AR2313_H_
1305 +#define _AR2313_H_
1306 +
1307 +#include <linux/interrupt.h>
1308 +#include <generated/autoconf.h>
1309 +#include <linux/bitops.h>
1310 +#include <ar231x_platform.h>
1311 +
1312 +/* probe link timer - 5 secs */
1313 +#define LINK_TIMER (5*HZ)
1314 +
1315 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1316 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1317 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1318 +
1319 +#define AR2313_TX_TIMEOUT (HZ/4)
1320 +
1321 +/* Rings */
1322 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1323 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1324 +
1325 +#define AR2313_MBGET 2
1326 +#define AR2313_MBSET 3
1327 +#define AR2313_PCI_RECONFIG 4
1328 +#define AR2313_PCI_DUMP 5
1329 +#define AR2313_TEST_PANIC 6
1330 +#define AR2313_TEST_NULLPTR 7
1331 +#define AR2313_READ_DATA 8
1332 +#define AR2313_WRITE_DATA 9
1333 +#define AR2313_GET_VERSION 10
1334 +#define AR2313_TEST_HANG 11
1335 +#define AR2313_SYNC 12
1336 +
1337 +#define DMA_RX_ERR_CRC BIT(1)
1338 +#define DMA_RX_ERR_DRIB BIT(2)
1339 +#define DMA_RX_ERR_MII BIT(3)
1340 +#define DMA_RX_EV2 BIT(5)
1341 +#define DMA_RX_ERR_COL BIT(6)
1342 +#define DMA_RX_LONG BIT(7)
1343 +#define DMA_RX_LS BIT(8) /* last descriptor */
1344 +#define DMA_RX_FS BIT(9) /* first descriptor */
1345 +#define DMA_RX_MF BIT(10) /* multicast frame */
1346 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1347 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1348 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1349 +#define DMA_RX_ERROR BIT(15) /* error summary */
1350 +#define DMA_RX_LEN_MASK 0x3fff0000
1351 +#define DMA_RX_LEN_SHIFT 16
1352 +#define DMA_RX_FILT BIT(30)
1353 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1354 +
1355 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1356 +#define DMA_RX1_BSIZE_SHIFT 0
1357 +#define DMA_RX1_CHAINED BIT(24)
1358 +#define DMA_RX1_RER BIT(25)
1359 +
1360 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1361 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1362 +#define DMA_TX_COL_MASK 0x78
1363 +#define DMA_TX_COL_SHIFT 3
1364 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1365 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1366 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1367 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1368 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1369 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1370 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1371 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1372 +
1373 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1374 +#define DMA_TX1_BSIZE_SHIFT 0
1375 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1376 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1377 +#define DMA_TX1_FS BIT(29) /* first segment */
1378 +#define DMA_TX1_LS BIT(30) /* last segment */
1379 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1380 +
1381 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1382 +
1383 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1384 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1385 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1386 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1387 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1388 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1389 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1390 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1391 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1392 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1393 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1394 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1395 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1396 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1397 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1398 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1399 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1400 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1401 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1402 +
1403 +#define MII_ADDR_BUSY BIT(0)
1404 +#define MII_ADDR_WRITE BIT(1)
1405 +#define MII_ADDR_REG_SHIFT 6
1406 +#define MII_ADDR_PHY_SHIFT 11
1407 +#define MII_DATA_SHIFT 0
1408 +
1409 +#define FLOW_CONTROL_FCE BIT(1)
1410 +
1411 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1412 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1413 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1414 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1415 +
1416 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1417 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1418 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1419 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1420 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1421 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1422 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1423 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1424 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1425 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1426 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1427 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1428 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1429 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1430 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1431 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1432 +
1433 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1434 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1435 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1436 +
1437 +
1438 +typedef struct {
1439 + volatile unsigned int status; /* OWN, Device control and status. */
1440 + volatile unsigned int devcs; /* pkt Control bits + Length */
1441 + volatile unsigned int addr; /* Current Address. */
1442 + volatile unsigned int descr; /* Next descriptor in chain. */
1443 +} ar231x_descr_t;
1444 +
1445 +
1446 +
1447 +/**
1448 + * New Combo structure for Both Eth0 AND eth1
1449 + */
1450 +typedef struct {
1451 + volatile unsigned int mac_control; /* 0x00 */
1452 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1453 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1454 + volatile unsigned int mii_addr; /* 0x14 */
1455 + volatile unsigned int mii_data; /* 0x18 */
1456 + volatile unsigned int flow_control; /* 0x1c */
1457 + volatile unsigned int vlan_tag; /* 0x20 */
1458 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1459 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1460 +
1461 +} ETHERNET_STRUCT;
1462 +
1463 +/********************************************************************
1464 + * Interrupt controller
1465 + ********************************************************************/
1466 +
1467 +typedef struct {
1468 + volatile unsigned int wdog_control; /* 0x08 */
1469 + volatile unsigned int wdog_timer; /* 0x0c */
1470 + volatile unsigned int misc_status; /* 0x10 */
1471 + volatile unsigned int misc_mask; /* 0x14 */
1472 + volatile unsigned int global_status; /* 0x18 */
1473 + volatile unsigned int reserved; /* 0x1c */
1474 + volatile unsigned int reset_control; /* 0x20 */
1475 +} INTERRUPT;
1476 +
1477 +/********************************************************************
1478 + * DMA controller
1479 + ********************************************************************/
1480 +typedef struct {
1481 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1482 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1483 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1484 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1485 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1486 + volatile unsigned int status; /* 0x14 (CSR5) */
1487 + volatile unsigned int control; /* 0x18 (CSR6) */
1488 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1489 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1490 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1491 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1492 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1493 +} DMA;
1494 +
1495 +/**
1496 + * Struct private for the Sibyte.
1497 + *
1498 + * Elements are grouped so variables used by the tx handling goes
1499 + * together, and will go into the same cache lines etc. in order to
1500 + * avoid cache line contention between the rx and tx handling on SMP.
1501 + *
1502 + * Frequently accessed variables are put at the beginning of the
1503 + * struct to help the compiler generate better/shorter code.
1504 + */
1505 +struct ar231x_private {
1506 + struct net_device *dev;
1507 + int version;
1508 + u32 mb[2];
1509 +
1510 + volatile ETHERNET_STRUCT *phy_regs;
1511 + volatile ETHERNET_STRUCT *eth_regs;
1512 + volatile DMA *dma_regs;
1513 + struct ar231x_eth *cfg;
1514 +
1515 + spinlock_t lock; /* Serialise access to device */
1516 +
1517 + /* RX and TX descriptors, must be adjacent */
1518 + ar231x_descr_t *rx_ring;
1519 + ar231x_descr_t *tx_ring;
1520 +
1521 +
1522 + struct sk_buff **rx_skb;
1523 + struct sk_buff **tx_skb;
1524 +
1525 + /* RX elements */
1526 + u32 rx_skbprd;
1527 + u32 cur_rx;
1528 +
1529 + /* TX elements */
1530 + u32 tx_prd;
1531 + u32 tx_csm;
1532 +
1533 + /* Misc elements */
1534 + char name[48];
1535 + struct {
1536 + u32 address;
1537 + u32 length;
1538 + char *mapping;
1539 + } desc;
1540 +
1541 +
1542 + struct timer_list link_timer;
1543 + unsigned short phy; /* merlot phy = 1, samsung phy = 0x1f */
1544 + unsigned short mac;
1545 + unsigned short link; /* 0 - link down, 1 - link up */
1546 + u16 phy_data;
1547 +
1548 + struct tasklet_struct rx_tasklet;
1549 + int unloading;
1550 +
1551 + struct phy_device *phy_dev;
1552 + struct mii_bus *mii_bus;
1553 + int oldduplex;
1554 +};
1555 +
1556 +
1557 +/* Prototypes */
1558 +static int ar231x_init(struct net_device *dev);
1559 +#ifdef TX_TIMEOUT
1560 +static void ar231x_tx_timeout(struct net_device *dev);
1561 +#endif
1562 +static int ar231x_restart(struct net_device *dev);
1563 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1564 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1565 +static int ar231x_open(struct net_device *dev);
1566 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1567 +static int ar231x_close(struct net_device *dev);
1568 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr,
1569 + int cmd);
1570 +static void ar231x_init_cleanup(struct net_device *dev);
1571 +static int ar231x_setup_timer(struct net_device *dev);
1572 +static void ar231x_link_timer_fn(unsigned long data);
1573 +static void ar231x_check_link(struct net_device *dev);
1574 +#endif /* _AR2313_H_ */
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