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[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select IRQ_DOMAIN
14 + select SYS_HAS_CPU_MIPS32_R1
15 + select SYS_SUPPORTS_BIG_ENDIAN
16 + select SYS_SUPPORTS_32BIT_KERNEL
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,244 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ath25_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ath25_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(const void __iomem *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(const void __iomem *addr)
122 +{
123 + return __raw_readl(addr) != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(const void __iomem *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (__raw_readl(addr) == ATH25_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + /* broken board data detected, use radio data to find the
136 + * offset, user will fix this */
137 +
138 + if (check_radio_magic(addr + 0x1000))
139 + return true;
140 + if (check_radio_magic(addr + 0xf8))
141 + return true;
142 +
143 + return false;
144 +}
145 +
146 +static const void __iomem * __init find_board_config(const void __iomem *limit,
147 + const bool broken)
148 +{
149 + const void __iomem *addr;
150 + const void __iomem *begin = limit - 0x1000;
151 + const void __iomem *end = limit - 0x30000;
152 +
153 + for (addr = begin; addr >= end; addr -= 0x1000)
154 + if (check_board_data(addr, broken))
155 + return addr;
156 +
157 + return NULL;
158 +}
159 +
160 +static const void __iomem * __init find_radio_config(const void __iomem *limit,
161 + const void __iomem *bcfg)
162 +{
163 + const void __iomem *rcfg, *begin, *end;
164 +
165 + /*
166 + * Now find the start of Radio Configuration data, using heuristics:
167 + * Search forward from Board Configuration data by 0x1000 bytes
168 + * at a time until we find non-0xffffffff.
169 + */
170 + begin = bcfg + 0x1000;
171 + end = limit;
172 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
173 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
174 + return rcfg;
175 +
176 + /* AR2316 relocates radio config to new location */
177 + begin = bcfg + 0xf8;
178 + end = limit - 0x1000 + 0xf8;
179 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
180 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
181 + return rcfg;
182 +
183 + return NULL;
184 +}
185 +
186 +/*
187 + * NB: Search region size could be larger than the actual flash size,
188 + * but this shouldn't be a problem here, because the flash
189 + * will simply be mapped multiple times.
190 + */
191 +int __init ath25_find_config(phys_addr_t base, unsigned long size)
192 +{
193 + const void __iomem *flash_base, *flash_limit;
194 + struct ath25_boarddata *config;
195 + unsigned int rcfg_size;
196 + int broken_boarddata = 0;
197 + const void __iomem *bcfg, *rcfg;
198 + u8 *board_data;
199 + u8 *radio_data;
200 + u8 *mac_addr;
201 + u32 offset;
202 +
203 + flash_base = ioremap_nocache(base, size);
204 + flash_limit = flash_base + size;
205 +
206 + ath25_board.config = NULL;
207 + ath25_board.radio = NULL;
208 +
209 + /* Copy the board and radio data to RAM, because accessing the mapped
210 + * memory of the flash directly after booting is not safe */
211 +
212 + /* Try to find valid board and radio data */
213 + bcfg = find_board_config(flash_limit, false);
214 +
215 + /* If that fails, try to at least find valid radio data */
216 + if (!bcfg) {
217 + bcfg = find_board_config(flash_limit, true);
218 + broken_boarddata = 1;
219 + }
220 +
221 + if (!bcfg) {
222 + pr_warn("WARNING: No board configuration data found!\n");
223 + goto error;
224 + }
225 +
226 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
227 + ath25_board.config = (struct ath25_boarddata *)board_data;
228 + memcpy_fromio(board_data, bcfg, 0x100);
229 + if (broken_boarddata) {
230 + pr_warn("WARNING: broken board data detected\n");
231 + config = ath25_board.config;
232 + if (is_zero_ether_addr(config->enet0_mac)) {
233 + pr_info("Fixing up empty mac addresses\n");
234 + config->reset_config_gpio = 0xffff;
235 + config->sys_led_gpio = 0xffff;
236 + random_ether_addr(config->wlan0_mac);
237 + config->wlan0_mac[0] &= ~0x06;
238 + random_ether_addr(config->enet0_mac);
239 + random_ether_addr(config->enet1_mac);
240 + }
241 + }
242 +
243 + /* Radio config starts 0x100 bytes after board config, regardless
244 + * of what the physical layout on the flash chip looks like */
245 +
246 + rcfg = find_radio_config(flash_limit, bcfg);
247 + if (!rcfg) {
248 + pr_warn("WARNING: Could not find Radio Configuration data\n");
249 + goto error;
250 + }
251 +
252 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
253 + ath25_board.radio = radio_data;
254 + offset = radio_data - board_data;
255 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
256 + offset);
257 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
258 + memcpy_fromio(radio_data, rcfg, rcfg_size);
259 +
260 + mac_addr = &radio_data[0x1d * 2];
261 + if (is_broadcast_ether_addr(mac_addr)) {
262 + pr_info("Radio MAC is blank; using board-data\n");
263 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
264 + }
265 +
266 + iounmap(flash_base);
267 +
268 + return 0;
269 +
270 +error:
271 + iounmap(flash_base);
272 + return -ENODEV;
273 +}
274 +
275 +static void ath25_halt(void)
276 +{
277 + local_irq_disable();
278 + while (1)
279 + ;
280 +}
281 +
282 +void __init plat_mem_setup(void)
283 +{
284 + _machine_halt = ath25_halt;
285 + pm_power_off = ath25_halt;
286 +
287 + if (is_ar5312())
288 + ar5312_plat_mem_setup();
289 + else
290 + ar2315_plat_mem_setup();
291 +
292 + /* Disable data watchpoints */
293 + write_c0_watchlo0(0);
294 +}
295 +
296 +asmlinkage void plat_irq_dispatch(void)
297 +{
298 + ath25_irq_dispatch();
299 +}
300 +
301 +void __init plat_time_init(void)
302 +{
303 + if (is_ar5312())
304 + ar5312_plat_time_init();
305 + else
306 + ar2315_plat_time_init();
307 +}
308 +
309 +unsigned int __cpuinit get_c0_compare_int(void)
310 +{
311 + return CP0_LEGACY_COMPARE_IRQ;
312 +}
313 +
314 +void __init arch_init_irq(void)
315 +{
316 + clear_c0_status(ST0_IM);
317 + mips_cpu_irq_init();
318 +
319 + /* Initialize interrupt controllers */
320 + if (is_ar5312())
321 + ar5312_arch_init_irq();
322 + else
323 + ar2315_arch_init_irq();
324 +}
325 --- /dev/null
326 +++ b/arch/mips/ath25/prom.c
327 @@ -0,0 +1,26 @@
328 +/*
329 + * This file is subject to the terms and conditions of the GNU General Public
330 + * License. See the file "COPYING" in the main directory of this archive
331 + * for more details.
332 + *
333 + * Copyright MontaVista Software Inc
334 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
335 + * Copyright (C) 2006 FON Technology, SL.
336 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
337 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
338 + */
339 +
340 +/*
341 + * Prom setup file for ar231x
342 + */
343 +
344 +#include <linux/init.h>
345 +#include <asm/bootinfo.h>
346 +
347 +void __init prom_init(void)
348 +{
349 +}
350 +
351 +void __init prom_free_prom_memory(void)
352 +{
353 +}
354 --- /dev/null
355 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
356 @@ -0,0 +1,73 @@
357 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
358 +#define __ASM_MACH_ATH25_PLATFORM_H
359 +
360 +#include <linux/etherdevice.h>
361 +
362 +/*
363 + * This is board-specific data that is stored in a "fixed" location in flash.
364 + * It is shared across operating systems, so it should not be changed lightly.
365 + * The main reason we need it is in order to extract the ethernet MAC
366 + * address(es).
367 + */
368 +struct ath25_boarddata {
369 + u32 magic; /* board data is valid */
370 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
371 + u16 cksum; /* checksum (starting with BD_REV 2) */
372 + u16 rev; /* revision of this struct */
373 +#define BD_REV 4
374 + char board_name[64]; /* Name of board */
375 + u16 major; /* Board major number */
376 + u16 minor; /* Board minor number */
377 + u32 flags; /* Board configuration */
378 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
379 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
380 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
381 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
382 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
383 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
384 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
385 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
386 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
387 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
388 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
389 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
390 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
391 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
392 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
393 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
394 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
395 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
396 + u16 reset_config_gpio; /* Reset factory GPIO pin */
397 + u16 sys_led_gpio; /* System LED GPIO pin */
398 +
399 + u32 cpu_freq; /* CPU core frequency in Hz */
400 + u32 sys_freq; /* System frequency in Hz */
401 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
402 +
403 + u8 wlan0_mac[ETH_ALEN];
404 + u8 enet0_mac[ETH_ALEN];
405 + u8 enet1_mac[ETH_ALEN];
406 +
407 + u16 pci_id; /* Pseudo PCIID for common code */
408 + u16 mem_cap; /* cap bank1 in MB */
409 +
410 + /* version 3 */
411 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
412 +};
413 +
414 +#define BOARD_CONFIG_BUFSZ 0x1000
415 +
416 +/*
417 + * Platform device information for the Wireless MAC
418 + */
419 +struct ar231x_board_config {
420 + u16 devid;
421 +
422 + /* board config data */
423 + struct ath25_boarddata *config;
424 +
425 + /* radio calibration data */
426 + const char *radio;
427 +};
428 +
429 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
430 --- /dev/null
431 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
432 @@ -0,0 +1,64 @@
433 +/*
434 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
435 + *
436 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
437 + *
438 + * This file was derived from: include/asm-mips/cpu-features.h
439 + * Copyright (C) 2003, 2004 Ralf Baechle
440 + * Copyright (C) 2004 Maciej W. Rozycki
441 + *
442 + * This program is free software; you can redistribute it and/or modify it
443 + * under the terms of the GNU General Public License version 2 as published
444 + * by the Free Software Foundation.
445 + *
446 + */
447 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
448 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
449 +
450 +/*
451 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
452 + */
453 +#define cpu_has_tlb 1
454 +#define cpu_has_4kex 1
455 +#define cpu_has_3k_cache 0
456 +#define cpu_has_4k_cache 1
457 +#define cpu_has_tx39_cache 0
458 +#define cpu_has_sb1_cache 0
459 +#define cpu_has_fpu 0
460 +#define cpu_has_32fpr 0
461 +#define cpu_has_counter 1
462 +#define cpu_has_ejtag 1
463 +
464 +#if !defined(CONFIG_SOC_AR5312)
465 +# define cpu_has_llsc 1
466 +#else
467 +/*
468 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
469 + * ll/sc instructions.
470 + */
471 +# define cpu_has_llsc 0
472 +#endif
473 +
474 +#define cpu_has_mips16 0
475 +#define cpu_has_mdmx 0
476 +#define cpu_has_mips3d 0
477 +#define cpu_has_smartmips 0
478 +
479 +#define cpu_has_mips32r1 1
480 +
481 +#if !defined(CONFIG_SOC_AR5312)
482 +# define cpu_has_mips32r2 1
483 +#endif
484 +
485 +#define cpu_has_mips64r1 0
486 +#define cpu_has_mips64r2 0
487 +
488 +#define cpu_has_dsp 0
489 +#define cpu_has_mipsmt 0
490 +
491 +#define cpu_has_64bits 0
492 +#define cpu_has_64bit_zero_reg 0
493 +#define cpu_has_64bit_gp_regs 0
494 +#define cpu_has_64bit_addresses 0
495 +
496 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
497 --- /dev/null
498 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
499 @@ -0,0 +1,82 @@
500 +/*
501 + * This file is subject to the terms and conditions of the GNU General Public
502 + * License. See the file "COPYING" in the main directory of this archive
503 + * for more details.
504 + *
505 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
506 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
507 + *
508 + */
509 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
510 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
511 +
512 +#include <linux/device.h>
513 +
514 +/*
515 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
516 + * of PCI host controller to enable DMA. The same value should be used as the
517 + * offset to calculate the physical address of DMA buffer for PCI devices.
518 + */
519 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
520 +
521 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
522 +{
523 +#ifdef CONFIG_PCI
524 + extern struct bus_type pci_bus_type;
525 +
526 + if (dev && dev->bus == &pci_bus_type)
527 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
528 +#endif
529 + return 0;
530 +}
531 +
532 +static inline dma_addr_t
533 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
534 +{
535 + return virt_to_phys(addr) + ath25_dev_offset(dev);
536 +}
537 +
538 +static inline dma_addr_t
539 +plat_map_dma_mem_page(struct device *dev, struct page *page)
540 +{
541 + return page_to_phys(page) + ath25_dev_offset(dev);
542 +}
543 +
544 +static inline unsigned long
545 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
546 +{
547 + return dma_addr - ath25_dev_offset(dev);
548 +}
549 +
550 +static inline void
551 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
552 + enum dma_data_direction direction)
553 +{
554 +}
555 +
556 +static inline int plat_dma_supported(struct device *dev, u64 mask)
557 +{
558 + return 1;
559 +}
560 +
561 +static inline void plat_extra_sync_for_device(struct device *dev)
562 +{
563 +}
564 +
565 +static inline int plat_dma_mapping_error(struct device *dev,
566 + dma_addr_t dma_addr)
567 +{
568 + return 0;
569 +}
570 +
571 +static inline int plat_device_is_coherent(struct device *dev)
572 +{
573 +#ifdef CONFIG_DMA_COHERENT
574 + return 1;
575 +#endif
576 +#ifdef CONFIG_DMA_NONCOHERENT
577 + return 0;
578 +#endif
579 +}
580 +
581 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
582 --- /dev/null
583 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
584 @@ -0,0 +1,16 @@
585 +#ifndef __ASM_MACH_ATH25_GPIO_H
586 +#define __ASM_MACH_ATH25_GPIO_H
587 +
588 +#include <asm-generic/gpio.h>
589 +
590 +#define gpio_get_value __gpio_get_value
591 +#define gpio_set_value __gpio_set_value
592 +#define gpio_cansleep __gpio_cansleep
593 +#define gpio_to_irq __gpio_to_irq
594 +
595 +static inline int irq_to_gpio(unsigned irq)
596 +{
597 + return -EINVAL;
598 +}
599 +
600 +#endif /* __ASM_MACH_ATH25_GPIO_H */
601 --- /dev/null
602 +++ b/arch/mips/include/asm/mach-ath25/war.h
603 @@ -0,0 +1,25 @@
604 +/*
605 + * This file is subject to the terms and conditions of the GNU General Public
606 + * License. See the file "COPYING" in the main directory of this archive
607 + * for more details.
608 + *
609 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
610 + */
611 +#ifndef __ASM_MACH_ATH25_WAR_H
612 +#define __ASM_MACH_ATH25_WAR_H
613 +
614 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
615 +#define R4600_V1_HIT_CACHEOP_WAR 0
616 +#define R4600_V2_HIT_CACHEOP_WAR 0
617 +#define R5432_CP0_INTERRUPT_WAR 0
618 +#define BCM1250_M3_WAR 0
619 +#define SIBYTE_1956_WAR 0
620 +#define MIPS4K_ICACHE_REFILL_WAR 0
621 +#define MIPS_CACHE_SYNC_WAR 0
622 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
623 +#define RM9000_CDEX_SMP_WAR 0
624 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
625 +#define R10000_LLSC_WAR 0
626 +#define MIPS34K_MISSED_ITLB_WAR 0
627 +
628 +#endif /* __ASM_MACH_ATH25_WAR_H */
629 --- /dev/null
630 +++ b/arch/mips/ath25/ar2315_regs.h
631 @@ -0,0 +1,471 @@
632 +/*
633 + * Register definitions for AR2315+
634 + *
635 + * This file is subject to the terms and conditions of the GNU General Public
636 + * License. See the file "COPYING" in the main directory of this archive
637 + * for more details.
638 + *
639 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
640 + * Copyright (C) 2006 FON Technology, SL.
641 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
642 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
643 + */
644 +
645 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
646 +#define __ASM_MACH_ATH25_AR2315_REGS_H
647 +
648 +/*
649 + * IRQs
650 + */
651 +#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
652 +#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
653 +#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
654 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
655 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
656 +
657 +/*
658 + * Miscellaneous interrupts, which share IP2.
659 + */
660 +#define AR2315_MISC_IRQ_UART0 0
661 +#define AR2315_MISC_IRQ_I2C_RSVD 1
662 +#define AR2315_MISC_IRQ_SPI 2
663 +#define AR2315_MISC_IRQ_AHB 3
664 +#define AR2315_MISC_IRQ_APB 4
665 +#define AR2315_MISC_IRQ_TIMER 5
666 +#define AR2315_MISC_IRQ_GPIO 6
667 +#define AR2315_MISC_IRQ_WATCHDOG 7
668 +#define AR2315_MISC_IRQ_IR_RSVD 8
669 +#define AR2315_MISC_IRQ_COUNT 9
670 +
671 +/*
672 + * Address map
673 + */
674 +#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
675 +#define AR2315_SPI_READ_SIZE 0x01000000
676 +#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
677 +#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
678 +#define AR2315_PCI_SIZE 0x00001000
679 +#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
680 +#define AR2315_SDRAMCTL_SIZE 0x00000020
681 +#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
682 +#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
683 +#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
684 +#define AR2315_RST_SIZE 0x00000100
685 +#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
686 +#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
687 +#define AR2315_SPI_MMR_SIZE 0x00000010
688 +#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
689 +#define AR2315_PCI_EXT_SIZE 0x40000000
690 +
691 +/*
692 + * Cold reset register
693 + */
694 +#define AR2315_COLD_RESET 0x0000
695 +
696 +#define AR2315_RESET_COLD_AHB 0x00000001
697 +#define AR2315_RESET_COLD_APB 0x00000002
698 +#define AR2315_RESET_COLD_CPU 0x00000004
699 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
700 +#define AR2315_RESET_SYSTEM \
701 + (RESET_COLD_CPU |\
702 + RESET_COLD_APB |\
703 + RESET_COLD_AHB) /* full system */
704 +#define AR2317_RESET_SYSTEM 0x00000010
705 +
706 +/*
707 + * Reset register
708 + */
709 +#define AR2315_RESET 0x0004
710 +
711 +/* warm reset WLAN0 MAC */
712 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
713 +/* warm reset WLAN0 BaseBand */
714 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
715 +/* warm reset MPEG-TS */
716 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
717 +/* warm reset PCI ahb/dma */
718 +#define AR2315_RESET_PCIDMA 0x00000008
719 +/* warm reset memory controller */
720 +#define AR2315_RESET_MEMCTL 0x00000010
721 +/* warm reset local bus */
722 +#define AR2315_RESET_LOCAL 0x00000020
723 +/* warm reset I2C bus */
724 +#define AR2315_RESET_I2C_RSVD 0x00000040
725 +/* warm reset SPI interface */
726 +#define AR2315_RESET_SPI 0x00000080
727 +/* warm reset UART0 */
728 +#define AR2315_RESET_UART0 0x00000100
729 +/* warm reset IR interface */
730 +#define AR2315_RESET_IR_RSVD 0x00000200
731 +/* cold reset ENET0 phy */
732 +#define AR2315_RESET_EPHY0 0x00000400
733 +/* cold reset ENET0 mac */
734 +#define AR2315_RESET_ENET0 0x00000800
735 +
736 +/*
737 + * AHB master arbitration control
738 + */
739 +#define AR2315_AHB_ARB_CTL 0x0008
740 +
741 +/* CPU, default */
742 +#define AR2315_ARB_CPU 0x00000001
743 +/* WLAN */
744 +#define AR2315_ARB_WLAN 0x00000002
745 +/* MPEG-TS */
746 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
747 +/* LOCAL */
748 +#define AR2315_ARB_LOCAL 0x00000008
749 +/* PCI */
750 +#define AR2315_ARB_PCI 0x00000010
751 +/* Ethernet */
752 +#define AR2315_ARB_ETHERNET 0x00000020
753 +/* retry policy, debug only */
754 +#define AR2315_ARB_RETRY 0x00000100
755 +
756 +/*
757 + * Config Register
758 + */
759 +#define AR2315_ENDIAN_CTL 0x000c
760 +
761 +/* EC - AHB bridge endianess */
762 +#define AR2315_CONFIG_AHB 0x00000001
763 +/* WLAN byteswap */
764 +#define AR2315_CONFIG_WLAN 0x00000002
765 +/* MPEG-TS byteswap */
766 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
767 +/* PCI byteswap */
768 +#define AR2315_CONFIG_PCI 0x00000008
769 +/* Memory controller endianess */
770 +#define AR2315_CONFIG_MEMCTL 0x00000010
771 +/* Local bus byteswap */
772 +#define AR2315_CONFIG_LOCAL 0x00000020
773 +/* Ethernet byteswap */
774 +#define AR2315_CONFIG_ETHERNET 0x00000040
775 +
776 +/* CPU write buffer merge */
777 +#define AR2315_CONFIG_MERGE 0x00000200
778 +/* CPU big endian */
779 +#define AR2315_CONFIG_CPU 0x00000400
780 +#define AR2315_CONFIG_PCIAHB 0x00000800
781 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
782 +/* SPI byteswap */
783 +#define AR2315_CONFIG_SPI 0x00008000
784 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
785 +#define AR2315_CONFIG_CPU_PCI 0x00020000
786 +#define AR2315_CONFIG_CPU_MMR 0x00040000
787 +#define AR2315_CONFIG_BIG 0x00000400
788 +
789 +/*
790 + * NMI control
791 + */
792 +#define AR2315_NMI_CTL 0x0010
793 +
794 +#define AR2315_NMI_EN 1
795 +
796 +/*
797 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
798 + */
799 +#define AR2315_SREV 0x0014
800 +
801 +#define AR2315_REV_MAJ 0x00f0
802 +#define AR2315_REV_MAJ_S 4
803 +#define AR2315_REV_MIN 0x000f
804 +#define AR2315_REV_MIN_S 0
805 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
806 +
807 +/*
808 + * Interface Enable
809 + */
810 +#define AR2315_IF_CTL 0x0018
811 +
812 +#define AR2315_IF_MASK 0x00000007
813 +#define AR2315_IF_DISABLED 0
814 +#define AR2315_IF_PCI 1
815 +#define AR2315_IF_TS_LOCAL 2
816 +/* only for emulation with separate pins */
817 +#define AR2315_IF_ALL 3
818 +#define AR2315_IF_LOCAL_HOST 0x00000008
819 +#define AR2315_IF_PCI_HOST 0x00000010
820 +#define AR2315_IF_PCI_INTR 0x00000020
821 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
822 +#define AR2315_IF_PCI_CLK_INPUT 0
823 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
824 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
825 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
826 +#define AR2315_IF_PCI_CLK_SHIFT 16
827 +
828 +/*
829 + * APB Interrupt control
830 + */
831 +
832 +#define AR2315_ISR 0x0020
833 +#define AR2315_IMR 0x0024
834 +#define AR2315_GISR 0x0028
835 +
836 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
837 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
838 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
839 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
840 +#define AR2315_ISR_APB 0x0010 /* APB error */
841 +#define AR2315_ISR_TIMER 0x0020 /* timer */
842 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
843 +#define AR2315_ISR_WD 0x0080 /* watchdog */
844 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
845 +
846 +#define AR2315_GISR_MISC 0x0001
847 +#define AR2315_GISR_WLAN0 0x0002
848 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
849 +#define AR2315_GISR_LOCALPCI 0x0008
850 +#define AR2315_GISR_WMACPOLL 0x0010
851 +#define AR2315_GISR_TIMER 0x0020
852 +#define AR2315_GISR_ETHERNET 0x0040
853 +
854 +/*
855 + * Timers
856 + */
857 +#define AR2315_TIMER 0x0030
858 +#define AR2315_RELOAD 0x0034
859 +
860 +#define AR2315_WDT_TIMER 0x0038
861 +#define AR2315_WDT_CTRL 0x003c
862 +
863 +#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
864 +#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
865 +#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
866 +
867 +/*
868 + * CPU Performance Counters
869 + */
870 +#define AR2315_PERFCNT0 0x0048
871 +#define AR2315_PERFCNT1 0x004c
872 +
873 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
874 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
875 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
876 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
877 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
878 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
879 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
880 +
881 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
882 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
883 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
884 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
885 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
886 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
887 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
888 +
889 +/*
890 + * AHB Error Reporting.
891 + */
892 +#define AR2315_AHB_ERR0 0x0050 /* error */
893 +#define AR2315_AHB_ERR1 0x0054 /* haddr */
894 +#define AR2315_AHB_ERR2 0x0058 /* hwdata */
895 +#define AR2315_AHB_ERR3 0x005c /* hrdata */
896 +#define AR2315_AHB_ERR4 0x0060 /* status */
897 +
898 +#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
899 + /* write 1 to clear all bits in ERR0 */
900 +#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
901 +#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
902 +
903 +#define AR2315_PROCERR_HMAST 0x0000000f
904 +#define AR2315_PROCERR_HMAST_DFLT 0
905 +#define AR2315_PROCERR_HMAST_WMAC 1
906 +#define AR2315_PROCERR_HMAST_ENET 2
907 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
908 +#define AR2315_PROCERR_HMAST_LOCAL 4
909 +#define AR2315_PROCERR_HMAST_CPU 5
910 +#define AR2315_PROCERR_HMAST_PCITGT 6
911 +
912 +#define AR2315_PROCERR_HMAST_S 0
913 +#define AR2315_PROCERR_HWRITE 0x00000010
914 +#define AR2315_PROCERR_HSIZE 0x00000060
915 +#define AR2315_PROCERR_HSIZE_S 5
916 +#define AR2315_PROCERR_HTRANS 0x00000180
917 +#define AR2315_PROCERR_HTRANS_S 7
918 +#define AR2315_PROCERR_HBURST 0x00000e00
919 +#define AR2315_PROCERR_HBURST_S 9
920 +
921 +/*
922 + * Clock Control
923 + */
924 +#define AR2315_PLLC_CTL 0x0064
925 +#define AR2315_PLLV_CTL 0x0068
926 +#define AR2315_CPUCLK 0x006c
927 +#define AR2315_AMBACLK 0x0070
928 +#define AR2315_SYNCCLK 0x0074
929 +#define AR2315_DSL_SLEEP_CTL 0x0080
930 +#define AR2315_DSL_SLEEP_DUR 0x0084
931 +
932 +/* PLLc Control fields */
933 +#define AR2315_PLLC_REF_DIV_M 0x00000003
934 +#define AR2315_PLLC_REF_DIV_S 0
935 +#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
936 +#define AR2315_PLLC_FDBACK_DIV_S 2
937 +#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
938 +#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
939 +#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
940 +#define AR2315_PLLC_CLKC_DIV_S 14
941 +#define AR2315_PLLC_CLKM_DIV_M 0x00700000
942 +#define AR2315_PLLC_CLKM_DIV_S 20
943 +
944 +/* CPU CLK Control fields */
945 +#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
946 +#define AR2315_CPUCLK_CLK_SEL_S 0
947 +#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
948 +#define AR2315_CPUCLK_CLK_DIV_S 2
949 +
950 +/* AMBA CLK Control fields */
951 +#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
952 +#define AR2315_AMBACLK_CLK_SEL_S 0
953 +#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
954 +#define AR2315_AMBACLK_CLK_DIV_S 2
955 +
956 +/*
957 + * PCI Clock Control
958 + */
959 +#define AR2315_PCICLK 0x00a4
960 +
961 +#define AR2315_PCICLK_INPUT_M 0x3
962 +#define AR2315_PCICLK_INPUT_S 0
963 +
964 +#define AR2315_PCICLK_PLLC_CLKM 0
965 +#define AR2315_PCICLK_PLLC_CLKM1 1
966 +#define AR2315_PCICLK_PLLC_CLKC 2
967 +#define AR2315_PCICLK_REF_CLK 3
968 +
969 +#define AR2315_PCICLK_DIV_M 0xc
970 +#define AR2315_PCICLK_DIV_S 2
971 +
972 +#define AR2315_PCICLK_IN_FREQ 0
973 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
974 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
975 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
976 +
977 +/*
978 + * Observation Control Register
979 + */
980 +#define AR2315_OCR 0x00b0
981 +
982 +#define AR2315_OCR_GPIO0_IRIN 0x00000040
983 +#define AR2315_OCR_GPIO1_IROUT 0x00000080
984 +#define AR2315_OCR_GPIO3_RXCLR 0x00000200
985 +
986 +/*
987 + * General Clock Control
988 + */
989 +#define AR2315_MISCCLK 0x00b4
990 +
991 +#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
992 +#define AR2315_MISCCLK_PROCREFCLK 0x00000002
993 +
994 +/*
995 + * SDRAM Controller
996 + * - No read or write buffers are included.
997 + */
998 +#define AR2315_MEM_CFG 0x0000
999 +#define AR2315_MEM_CTRL 0x000c
1000 +#define AR2315_MEM_REF 0x0010
1001 +
1002 +#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
1003 +#define AR2315_MEM_CFG_DATA_WIDTH_S 13
1004 +#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
1005 +#define AR2315_MEM_CFG_COL_WIDTH_S 9
1006 +#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
1007 +#define AR2315_MEM_CFG_ROW_WIDTH_S 5
1008 +#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
1009 +#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
1010 +
1011 +/*
1012 + * Local Bus Interface Registers
1013 + */
1014 +#define AR2315_LB_CONFIG 0x0000
1015 +
1016 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1017 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1018 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1019 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1020 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1021 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1022 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1023 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1024 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1025 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1026 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1027 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1028 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1029 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1030 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1031 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1032 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1033 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1034 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1035 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1036 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1037 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1038 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1039 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1040 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1041 +
1042 +#define AR2315_LB_CLKSEL 0x0004
1043 +
1044 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1045 +
1046 +#define AR2315_LB_1MS 0x0008
1047 +
1048 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1049 +
1050 +#define AR2315_LB_MISCCFG 0x000c
1051 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1052 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1053 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1054 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1055 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1056 +#define AR2315_LBM_TIMEOUT_M 0x00ffff80
1057 +#define AR2315_LBM_TIMEOUT_S 7
1058 +#define AR2315_LBM_PORTMUX 0x07000000
1059 +
1060 +#define AR2315_LB_RXTSOFF 0x0010
1061 +
1062 +#define AR2315_LB_TX_CHAIN_EN 0x0100
1063 +
1064 +#define AR2315_LB_TXEN_0 0x01
1065 +#define AR2315_LB_TXEN_1 0x02
1066 +#define AR2315_LB_TXEN_2 0x04
1067 +#define AR2315_LB_TXEN_3 0x08
1068 +
1069 +#define AR2315_LB_TX_CHAIN_DIS 0x0104
1070 +#define AR2315_LB_TX_DESC_PTR 0x0200
1071 +
1072 +#define AR2315_LB_RX_CHAIN_EN 0x0400
1073 +
1074 +#define AR2315_LB_RXEN 0x01
1075 +
1076 +#define AR2315_LB_RX_CHAIN_DIS 0x0404
1077 +#define AR2315_LB_RX_DESC_PTR 0x0408
1078 +
1079 +#define AR2315_LB_INT_STATUS 0x0500
1080 +
1081 +#define AR2315_LB_INT_TX_DESC 0x00000001
1082 +#define AR2315_LB_INT_TX_OK 0x00000002
1083 +#define AR2315_LB_INT_TX_ERR 0x00000004
1084 +#define AR2315_LB_INT_TX_EOF 0x00000008
1085 +#define AR2315_LB_INT_RX_DESC 0x00000010
1086 +#define AR2315_LB_INT_RX_OK 0x00000020
1087 +#define AR2315_LB_INT_RX_ERR 0x00000040
1088 +#define AR2315_LB_INT_RX_EOF 0x00000080
1089 +#define AR2315_LB_INT_TX_TRUNC 0x00000100
1090 +#define AR2315_LB_INT_TX_STARVE 0x00000200
1091 +#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
1092 +#define AR2315_LB_INT_LB_ERR 0x00000800
1093 +#define AR2315_LB_INT_MBOX_WR 0x00001000
1094 +#define AR2315_LB_INT_MBOX_RD 0x00002000
1095 +
1096 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1097 +#define AR2315_LB_INT_MASK 0x0504
1098 +
1099 +#define AR2315_LB_INT_EN 0x0508
1100 +#define AR2315_LB_MBOX 0x0600
1101 +
1102 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1103 --- /dev/null
1104 +++ b/arch/mips/ath25/ar5312_regs.h
1105 @@ -0,0 +1,225 @@
1106 +/*
1107 + * This file is subject to the terms and conditions of the GNU General Public
1108 + * License. See the file "COPYING" in the main directory of this archive
1109 + * for more details.
1110 + *
1111 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1112 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1113 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1114 + */
1115 +
1116 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1117 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1118 +
1119 +#include <asm/addrspace.h>
1120 +
1121 +/*
1122 + * IRQs
1123 + */
1124 +#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
1125 +#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
1126 +#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
1127 +#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
1128 +#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
1129 +
1130 +/*
1131 + * Miscellaneous interrupts, which share IP6.
1132 + */
1133 +#define AR5312_MISC_IRQ_TIMER 0
1134 +#define AR5312_MISC_IRQ_AHB_PROC 1
1135 +#define AR5312_MISC_IRQ_AHB_DMA 2
1136 +#define AR5312_MISC_IRQ_GPIO 3
1137 +#define AR5312_MISC_IRQ_UART0 4
1138 +#define AR5312_MISC_IRQ_UART0_DMA 5
1139 +#define AR5312_MISC_IRQ_WATCHDOG 6
1140 +#define AR5312_MISC_IRQ_LOCAL 7
1141 +#define AR5312_MISC_IRQ_SPI 8
1142 +#define AR5312_MISC_IRQ_COUNT 9
1143 +
1144 +/*
1145 + * Address Map
1146 + *
1147 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1148 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1149 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1150 + */
1151 +#define AR5312_WLAN0_BASE 0x18000000
1152 +#define AR5312_ENET0_BASE 0x18100000
1153 +#define AR5312_ENET1_BASE 0x18200000
1154 +#define AR5312_SDRAMCTL_BASE 0x18300000
1155 +#define AR5312_SDRAMCTL_SIZE 0x00000010
1156 +#define AR5312_FLASHCTL_BASE 0x18400000
1157 +#define AR5312_FLASHCTL_SIZE 0x00000010
1158 +#define AR5312_WLAN1_BASE 0x18500000
1159 +#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
1160 +#define AR5312_GPIO_BASE 0x1c002000
1161 +#define AR5312_GPIO_SIZE 0x00000010
1162 +#define AR5312_RST_BASE 0x1c003000
1163 +#define AR5312_RST_SIZE 0x00000100
1164 +#define AR5312_FLASH_BASE 0x1e000000
1165 +#define AR5312_FLASH_SIZE 0x00800000
1166 +
1167 +/*
1168 + * Need these defines to determine true number of ethernet MACs
1169 + */
1170 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1171 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1172 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1173 +
1174 +/* Reset/Timer Block Address Map */
1175 +#define AR5312_TIMER 0x0000 /* countdown timer */
1176 +#define AR5312_RELOAD 0x0004 /* timer reload value */
1177 +#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
1178 +#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
1179 +#define AR5312_ISR 0x0010 /* Intr Status Reg */
1180 +#define AR5312_IMR 0x0014 /* Intr Mask Reg */
1181 +#define AR5312_RESET 0x0020
1182 +#define AR5312_CLOCKCTL1 0x0064
1183 +#define AR5312_SCRATCH 0x006c
1184 +#define AR5312_PROCADDR 0x0070
1185 +#define AR5312_PROC1 0x0074
1186 +#define AR5312_DMAADDR 0x0078
1187 +#define AR5312_DMA1 0x007c
1188 +#define AR5312_ENABLE 0x0080 /* interface enb */
1189 +#define AR5312_REV 0x0090 /* revision */
1190 +
1191 +/* AR5312_WDT_CTRL register bit field definitions */
1192 +#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
1193 +#define AR5312_WDT_CTRL_NMI 0x00000001
1194 +#define AR5312_WDT_CTRL_RESET 0x00000002
1195 +
1196 +/* AR5312_ISR register bit field definitions */
1197 +#define AR5312_ISR_TIMER 0x0001
1198 +#define AR5312_ISR_AHBPROC 0x0002
1199 +#define AR5312_ISR_AHBDMA 0x0004
1200 +#define AR5312_ISR_GPIO 0x0008
1201 +#define AR5312_ISR_UART0 0x0010
1202 +#define AR5312_ISR_UART0DMA 0x0020
1203 +#define AR5312_ISR_WD 0x0040
1204 +#define AR5312_ISR_LOCAL 0x0080
1205 +
1206 +/* AR5312_RESET register bit field definitions */
1207 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1208 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1209 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1210 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1211 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1212 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1213 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1214 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1215 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1216 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1217 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1218 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1219 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1220 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1221 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1222 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1223 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1224 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1225 +
1226 +#define AR5312_RESET_WMAC0_BITS \
1227 + (AR5312_RESET_WLAN0 |\
1228 + AR5312_RESET_WARM_WLAN0_MAC |\
1229 + AR5312_RESET_WARM_WLAN0_BB)
1230 +
1231 +#define AR5312_RESET_WMAC1_BITS \
1232 + (AR5312_RESET_WLAN1 |\
1233 + AR5312_RESET_WARM_WLAN1_MAC |\
1234 + AR5312_RESET_WARM_WLAN1_BB)
1235 +
1236 +/* AR5312_CLOCKCTL1 register bit field definitions */
1237 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1238 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1239 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1240 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1241 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1242 +
1243 +/* Valid for AR5312 and AR2312 */
1244 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1245 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1246 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1247 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1248 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1249 +
1250 +/* Valid for AR2313 */
1251 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1252 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1253 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1254 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1255 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1256 +
1257 +/* AR5312_ENABLE register bit field definitions */
1258 +#define AR5312_ENABLE_WLAN0 0x0001
1259 +#define AR5312_ENABLE_ENET0 0x0002
1260 +#define AR5312_ENABLE_ENET1 0x0004
1261 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1262 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1263 +#define AR5312_ENABLE_WLAN1 \
1264 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1265 + AR5312_ENABLE_WLAN1_DMA)
1266 +
1267 +/* AR5312_REV register bit field definitions */
1268 +#define AR5312_REV_WMAC_MAJ 0xf000
1269 +#define AR5312_REV_WMAC_MAJ_S 12
1270 +#define AR5312_REV_WMAC_MIN 0x0f00
1271 +#define AR5312_REV_WMAC_MIN_S 8
1272 +#define AR5312_REV_MAJ 0x00f0
1273 +#define AR5312_REV_MAJ_S 4
1274 +#define AR5312_REV_MIN 0x000f
1275 +#define AR5312_REV_MIN_S 0
1276 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1277 +
1278 +/* Major revision numbers, bits 7..4 of Revision ID register */
1279 +#define AR5312_REV_MAJ_AR5312 0x4
1280 +#define AR5312_REV_MAJ_AR2313 0x5
1281 +
1282 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1283 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1284 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1285 +
1286 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1287 +#define AR5312_FLASHCTL0 0x0000
1288 +#define AR5312_FLASHCTL1 0x0004
1289 +#define AR5312_FLASHCTL2 0x0008
1290 +
1291 +/* AR5312_FLASHCTL register bit field definitions */
1292 +#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
1293 +#define AR5312_FLASHCTL_IDCY_S 0
1294 +#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1295 +#define AR5312_FLASHCTL_WST1_S 5
1296 +#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1297 +#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1298 +#define AR5312_FLASHCTL_WST2_S 11
1299 +#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
1300 +#define AR5312_FLASHCTL_AC_S 16
1301 +#define AR5312_FLASHCTL_AC_128K 0x00000000
1302 +#define AR5312_FLASHCTL_AC_256K 0x00010000
1303 +#define AR5312_FLASHCTL_AC_512K 0x00020000
1304 +#define AR5312_FLASHCTL_AC_1M 0x00030000
1305 +#define AR5312_FLASHCTL_AC_2M 0x00040000
1306 +#define AR5312_FLASHCTL_AC_4M 0x00050000
1307 +#define AR5312_FLASHCTL_AC_8M 0x00060000
1308 +#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1309 +#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1310 +#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
1311 +#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
1312 +#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
1313 +#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
1314 +#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
1315 +#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
1316 +#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
1317 +#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
1318 +#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
1319 +#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
1320 +#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
1321 +
1322 +/* ARM SDRAM Controller -- just enough to determine memory size */
1323 +#define AR5312_MEM_CFG1 0x0004
1324 +
1325 +#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
1326 +#define AR5312_MEM_CFG1_AC0_S 8
1327 +#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
1328 +#define AR5312_MEM_CFG1_AC1_S 12
1329 +
1330 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1331 --- /dev/null
1332 +++ b/arch/mips/ath25/ar5312.c
1333 @@ -0,0 +1,401 @@
1334 +/*
1335 + * This file is subject to the terms and conditions of the GNU General Public
1336 + * License. See the file "COPYING" in the main directory of this archive
1337 + * for more details.
1338 + *
1339 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1340 + * Copyright (C) 2006 FON Technology, SL.
1341 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1342 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1343 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1344 + */
1345 +
1346 +/*
1347 + * Platform devices for Atheros SoCs
1348 + */
1349 +
1350 +#include <generated/autoconf.h>
1351 +#include <linux/init.h>
1352 +#include <linux/module.h>
1353 +#include <linux/types.h>
1354 +#include <linux/string.h>
1355 +#include <linux/mtd/physmap.h>
1356 +#include <linux/platform_device.h>
1357 +#include <linux/kernel.h>
1358 +#include <linux/bitops.h>
1359 +#include <linux/irqdomain.h>
1360 +#include <linux/reboot.h>
1361 +#include <asm/bootinfo.h>
1362 +#include <asm/reboot.h>
1363 +#include <asm/time.h>
1364 +#include <linux/irq.h>
1365 +#include <linux/io.h>
1366 +
1367 +#include <ath25_platform.h>
1368 +
1369 +#include "devices.h"
1370 +#include "ar5312.h"
1371 +#include "ar5312_regs.h"
1372 +
1373 +static void __iomem *ar5312_rst_base;
1374 +static struct irq_domain *ar5312_misc_irq_domain;
1375 +
1376 +static inline u32 ar5312_rst_reg_read(u32 reg)
1377 +{
1378 + return __raw_readl(ar5312_rst_base + reg);
1379 +}
1380 +
1381 +static inline void ar5312_rst_reg_write(u32 reg, u32 val)
1382 +{
1383 + __raw_writel(val, ar5312_rst_base + reg);
1384 +}
1385 +
1386 +static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
1387 +{
1388 + u32 ret = ar5312_rst_reg_read(reg);
1389 +
1390 + ret &= ~mask;
1391 + ret |= val;
1392 + ar5312_rst_reg_write(reg, ret);
1393 +}
1394 +
1395 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1396 +{
1397 + u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
1398 + u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
1399 + u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
1400 + u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
1401 +
1402 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1403 + proc_addr, proc1, dma_addr, dma1);
1404 +
1405 + machine_restart("AHB error"); /* Catastrophic failure */
1406 + return IRQ_HANDLED;
1407 +}
1408 +
1409 +static struct irqaction ar5312_ahb_err_interrupt = {
1410 + .handler = ar5312_ahb_err_handler,
1411 + .name = "ar5312-ahb-error",
1412 +};
1413 +
1414 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1415 +{
1416 + u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
1417 + ar5312_rst_reg_read(AR5312_IMR);
1418 + unsigned nr, misc_irq = 0;
1419 +
1420 + if (pending) {
1421 + struct irq_domain *domain = irq_get_handler_data(irq);
1422 +
1423 + nr = __ffs(pending);
1424 + misc_irq = irq_find_mapping(domain, nr);
1425 + }
1426 +
1427 + if (misc_irq) {
1428 + generic_handle_irq(misc_irq);
1429 + if (nr == AR5312_MISC_IRQ_TIMER)
1430 + ar5312_rst_reg_read(AR5312_TIMER);
1431 + } else {
1432 + spurious_interrupt();
1433 + }
1434 +}
1435 +
1436 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1437 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1438 +{
1439 + ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
1440 +}
1441 +
1442 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1443 +static void ar5312_misc_irq_mask(struct irq_data *d)
1444 +{
1445 + ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
1446 + ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
1447 +}
1448 +
1449 +static struct irq_chip ar5312_misc_irq_chip = {
1450 + .name = "ar5312-misc",
1451 + .irq_unmask = ar5312_misc_irq_unmask,
1452 + .irq_mask = ar5312_misc_irq_mask,
1453 +};
1454 +
1455 +static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
1456 + irq_hw_number_t hw)
1457 +{
1458 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
1459 + return 0;
1460 +}
1461 +
1462 +static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
1463 + .map = ar5312_misc_irq_map,
1464 +};
1465 +
1466 +static void ar5312_irq_dispatch(void)
1467 +{
1468 + u32 pending = read_c0_status() & read_c0_cause();
1469 +
1470 + if (pending & CAUSEF_IP2)
1471 + do_IRQ(AR5312_IRQ_WLAN0);
1472 + else if (pending & CAUSEF_IP5)
1473 + do_IRQ(AR5312_IRQ_WLAN1);
1474 + else if (pending & CAUSEF_IP6)
1475 + do_IRQ(AR5312_IRQ_MISC);
1476 + else if (pending & CAUSEF_IP7)
1477 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1478 + else
1479 + spurious_interrupt();
1480 +}
1481 +
1482 +void __init ar5312_arch_init_irq(void)
1483 +{
1484 + struct irq_domain *domain;
1485 + unsigned irq;
1486 +
1487 + ath25_irq_dispatch = ar5312_irq_dispatch;
1488 +
1489 + domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
1490 + &ar5312_misc_irq_domain_ops, NULL);
1491 + if (!domain)
1492 + panic("Failed to add IRQ domain");
1493 +
1494 + irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
1495 + setup_irq(irq, &ar5312_ahb_err_interrupt);
1496 +
1497 + irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
1498 + irq_set_handler_data(AR5312_IRQ_MISC, domain);
1499 +
1500 + ar5312_misc_irq_domain = domain;
1501 +}
1502 +
1503 +static struct physmap_flash_data ar5312_flash_data = {
1504 + .width = 2,
1505 +};
1506 +
1507 +static struct resource ar5312_flash_resource = {
1508 + .start = AR5312_FLASH_BASE,
1509 + .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
1510 + .flags = IORESOURCE_MEM,
1511 +};
1512 +
1513 +static struct platform_device ar5312_physmap_flash = {
1514 + .name = "physmap-flash",
1515 + .id = 0,
1516 + .dev.platform_data = &ar5312_flash_data,
1517 + .resource = &ar5312_flash_resource,
1518 + .num_resources = 1,
1519 +};
1520 +
1521 +static void __init ar5312_flash_init(void)
1522 +{
1523 + void __iomem *flashctl_base;
1524 + u32 ctl;
1525 +
1526 + flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
1527 + AR5312_FLASHCTL_SIZE);
1528 +
1529 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
1530 + ctl &= AR5312_FLASHCTL_MW;
1531 +
1532 + /* fixup flash width */
1533 + switch (ctl) {
1534 + case AR5312_FLASHCTL_MW16:
1535 + ar5312_flash_data.width = 2;
1536 + break;
1537 + case AR5312_FLASHCTL_MW8:
1538 + default:
1539 + ar5312_flash_data.width = 1;
1540 + break;
1541 + }
1542 +
1543 + /*
1544 + * Configure flash bank 0.
1545 + * Assume 8M window size. Flash will be aliased if it's smaller
1546 + */
1547 + ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
1548 + ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
1549 + ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
1550 + ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
1551 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
1552 +
1553 + /* Disable other flash banks */
1554 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
1555 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1556 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
1557 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
1558 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1559 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
1560 +
1561 + iounmap(flashctl_base);
1562 +}
1563 +
1564 +void __init ar5312_init_devices(void)
1565 +{
1566 + struct ath25_boarddata *config;
1567 +
1568 + ar5312_flash_init();
1569 +
1570 + /* Locate board/radio config data */
1571 + ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
1572 + config = ath25_board.config;
1573 +
1574 + /* AR2313 has CPU minor rev. 10 */
1575 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1576 + ath25_soc = ATH25_SOC_AR2313;
1577 +
1578 + /* AR2312 shares the same Silicon ID as AR5312 */
1579 + else if (config->flags & BD_ISCASPER)
1580 + ath25_soc = ATH25_SOC_AR2312;
1581 +
1582 + /* Everything else is probably AR5312 or compatible */
1583 + else
1584 + ath25_soc = ATH25_SOC_AR5312;
1585 +
1586 + platform_device_register(&ar5312_physmap_flash);
1587 +
1588 + switch (ath25_soc) {
1589 + case ATH25_SOC_AR5312:
1590 + if (!ath25_board.radio)
1591 + return;
1592 +
1593 + if (!(config->flags & BD_WLAN0))
1594 + break;
1595 +
1596 + ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1597 + break;
1598 + case ATH25_SOC_AR2312:
1599 + case ATH25_SOC_AR2313:
1600 + if (!ath25_board.radio)
1601 + return;
1602 + break;
1603 + default:
1604 + break;
1605 + }
1606 +
1607 + if (config->flags & BD_WLAN1)
1608 + ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
1609 +}
1610 +
1611 +static void ar5312_restart(char *command)
1612 +{
1613 + /* reset the system */
1614 + local_irq_disable();
1615 + while (1)
1616 + ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
1617 +}
1618 +
1619 +/*
1620 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1621 + * to determine the predevisor value.
1622 + */
1623 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1624 +
1625 +static unsigned __init ar5312_cpu_frequency(void)
1626 +{
1627 + unsigned int scratch;
1628 + unsigned int predivide_mask, predivide_shift;
1629 + unsigned int multiplier_mask, multiplier_shift;
1630 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1631 + unsigned int doubler_mask;
1632 + u16 devid;
1633 +
1634 + /* Trust the bootrom's idea of cpu frequency. */
1635 + scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
1636 + if (scratch)
1637 + return scratch;
1638 +
1639 + devid = ar5312_rst_reg_read(AR5312_REV);
1640 + devid &= AR5312_REV_MAJ;
1641 + devid >>= AR5312_REV_MAJ_S;
1642 + if (devid == AR5312_REV_MAJ_AR2313) {
1643 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1644 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1645 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1646 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1647 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1648 + } else { /* AR5312 and AR2312 */
1649 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1650 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1651 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1652 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1653 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1654 + }
1655 +
1656 + /*
1657 + * Clocking is derived from a fixed 40MHz input clock.
1658 + *
1659 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1660 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1661 + * flash, Timer, Watchdog Timer)
1662 + *
1663 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1664 + *
1665 + * So, for example, with a PLL multiplier of 5, we have
1666 + *
1667 + * cpu_freq = 200MHz
1668 + * sys_freq = 50MHz
1669 + * cnt_freq = 100MHz
1670 + *
1671 + * We compute the CPU frequency, based on PLL settings.
1672 + */
1673 +
1674 + clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
1675 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1676 + predivisor = clockctl1_predivide_table[predivide_select];
1677 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1678 +
1679 + if (clock_ctl1 & doubler_mask)
1680 + multiplier = multiplier << 1;
1681 +
1682 + return (40000000 / predivisor) * multiplier;
1683 +}
1684 +
1685 +static inline unsigned ar5312_sys_frequency(void)
1686 +{
1687 + return ar5312_cpu_frequency() / 4;
1688 +}
1689 +
1690 +void __init ar5312_plat_time_init(void)
1691 +{
1692 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1693 +}
1694 +
1695 +void __init ar5312_plat_mem_setup(void)
1696 +{
1697 + void __iomem *sdram_base;
1698 + u32 memsize, memcfg, bank0_ac, bank1_ac;
1699 + u32 devid;
1700 +
1701 + /* Detect memory size */
1702 + sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
1703 + AR5312_SDRAMCTL_SIZE);
1704 + memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
1705 + bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
1706 + bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
1707 + memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
1708 + (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
1709 + memsize <<= 20;
1710 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1711 + iounmap(sdram_base);
1712 +
1713 + ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
1714 +
1715 + devid = ar5312_rst_reg_read(AR5312_REV);
1716 + devid >>= AR5312_REV_WMAC_MIN_S;
1717 + devid &= AR5312_REV_CHIP;
1718 + ath25_board.devid = (u16)devid;
1719 +
1720 + /* Clear any lingering AHB errors */
1721 + ar5312_rst_reg_read(AR5312_PROCADDR);
1722 + ar5312_rst_reg_read(AR5312_DMAADDR);
1723 + ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
1724 +
1725 + _machine_restart = ar5312_restart;
1726 +}
1727 +
1728 +void __init ar5312_arch_init(void)
1729 +{
1730 + unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
1731 + AR5312_MISC_IRQ_UART0);
1732 +
1733 + ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
1734 +}
1735 --- /dev/null
1736 +++ b/arch/mips/ath25/ar2315.c
1737 @@ -0,0 +1,312 @@
1738 +/*
1739 + * This file is subject to the terms and conditions of the GNU General Public
1740 + * License. See the file "COPYING" in the main directory of this archive
1741 + * for more details.
1742 + *
1743 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1744 + * Copyright (C) 2006 FON Technology, SL.
1745 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1746 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1747 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1748 + */
1749 +
1750 +/*
1751 + * Platform devices for Atheros SoCs
1752 + */
1753 +
1754 +#include <generated/autoconf.h>
1755 +#include <linux/init.h>
1756 +#include <linux/module.h>
1757 +#include <linux/types.h>
1758 +#include <linux/string.h>
1759 +#include <linux/platform_device.h>
1760 +#include <linux/kernel.h>
1761 +#include <linux/bitops.h>
1762 +#include <linux/irqdomain.h>
1763 +#include <linux/reboot.h>
1764 +#include <asm/bootinfo.h>
1765 +#include <asm/reboot.h>
1766 +#include <asm/time.h>
1767 +#include <linux/irq.h>
1768 +#include <linux/io.h>
1769 +
1770 +#include <ath25_platform.h>
1771 +
1772 +#include "devices.h"
1773 +#include "ar2315.h"
1774 +#include "ar2315_regs.h"
1775 +
1776 +static void __iomem *ar2315_rst_base;
1777 +static struct irq_domain *ar2315_misc_irq_domain;
1778 +
1779 +static inline u32 ar2315_rst_reg_read(u32 reg)
1780 +{
1781 + return __raw_readl(ar2315_rst_base + reg);
1782 +}
1783 +
1784 +static inline void ar2315_rst_reg_write(u32 reg, u32 val)
1785 +{
1786 + __raw_writel(val, ar2315_rst_base + reg);
1787 +}
1788 +
1789 +static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
1790 +{
1791 + u32 ret = ar2315_rst_reg_read(reg);
1792 +
1793 + ret &= ~mask;
1794 + ret |= val;
1795 + ar2315_rst_reg_write(reg, ret);
1796 +}
1797 +
1798 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1799 +{
1800 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
1801 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1802 +
1803 + pr_emerg("AHB fatal error\n");
1804 + machine_restart("AHB error"); /* Catastrophic failure */
1805 +
1806 + return IRQ_HANDLED;
1807 +}
1808 +
1809 +static struct irqaction ar2315_ahb_err_interrupt = {
1810 + .handler = ar2315_ahb_err_handler,
1811 + .name = "ar2315-ahb-error",
1812 +};
1813 +
1814 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1815 +{
1816 + u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
1817 + ar2315_rst_reg_read(AR2315_IMR);
1818 + unsigned nr, misc_irq = 0;
1819 +
1820 + if (pending) {
1821 + struct irq_domain *domain = irq_get_handler_data(irq);
1822 +
1823 + nr = __ffs(pending);
1824 + misc_irq = irq_find_mapping(domain, nr);
1825 + }
1826 +
1827 + if (misc_irq) {
1828 + if (nr == AR2315_MISC_IRQ_GPIO)
1829 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
1830 + else if (nr == AR2315_MISC_IRQ_WATCHDOG)
1831 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
1832 + generic_handle_irq(misc_irq);
1833 + } else {
1834 + spurious_interrupt();
1835 + }
1836 +}
1837 +
1838 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1839 +{
1840 + ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
1841 +}
1842 +
1843 +static void ar2315_misc_irq_mask(struct irq_data *d)
1844 +{
1845 + ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
1846 +}
1847 +
1848 +static struct irq_chip ar2315_misc_irq_chip = {
1849 + .name = "ar2315-misc",
1850 + .irq_unmask = ar2315_misc_irq_unmask,
1851 + .irq_mask = ar2315_misc_irq_mask,
1852 +};
1853 +
1854 +static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
1855 + irq_hw_number_t hw)
1856 +{
1857 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
1858 + return 0;
1859 +}
1860 +
1861 +static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
1862 + .map = ar2315_misc_irq_map,
1863 +};
1864 +
1865 +/*
1866 + * Called when an interrupt is received, this function
1867 + * determines exactly which interrupt it was, and it
1868 + * invokes the appropriate handler.
1869 + *
1870 + * Implicitly, we also define interrupt priority by
1871 + * choosing which to dispatch first.
1872 + */
1873 +static void ar2315_irq_dispatch(void)
1874 +{
1875 + u32 pending = read_c0_status() & read_c0_cause();
1876 +
1877 + if (pending & CAUSEF_IP3)
1878 + do_IRQ(AR2315_IRQ_WLAN0);
1879 + else if (pending & CAUSEF_IP2)
1880 + do_IRQ(AR2315_IRQ_MISC);
1881 + else if (pending & CAUSEF_IP7)
1882 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1883 + else
1884 + spurious_interrupt();
1885 +}
1886 +
1887 +void __init ar2315_arch_init_irq(void)
1888 +{
1889 + struct irq_domain *domain;
1890 + unsigned irq;
1891 +
1892 + ath25_irq_dispatch = ar2315_irq_dispatch;
1893 +
1894 + domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
1895 + &ar2315_misc_irq_domain_ops, NULL);
1896 + if (!domain)
1897 + panic("Failed to add IRQ domain");
1898 +
1899 + irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
1900 + setup_irq(irq, &ar2315_ahb_err_interrupt);
1901 +
1902 + irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
1903 + irq_set_handler_data(AR2315_IRQ_MISC, domain);
1904 +
1905 + ar2315_misc_irq_domain = domain;
1906 +}
1907 +
1908 +void __init ar2315_init_devices(void)
1909 +{
1910 + /* Find board configuration */
1911 + ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
1912 +
1913 + ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
1914 +}
1915 +
1916 +static void ar2315_restart(char *command)
1917 +{
1918 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
1919 +
1920 + local_irq_disable();
1921 +
1922 + /* try reset the system via reset control */
1923 + ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
1924 +
1925 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
1926 + * a workaround. Give it some time to attempt a gpio based hardware
1927 + * reset (atheros reference design workaround) */
1928 +
1929 + /* TODO: implement the GPIO reset workaround */
1930 +
1931 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
1932 + * workaround. Attempt to jump to the mips reset location -
1933 + * the boot loader itself might be able to recover the system */
1934 + mips_reset_vec();
1935 +}
1936 +
1937 +/*
1938 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1939 + * to determine the predevisor value.
1940 + */
1941 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1942 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
1943 +
1944 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
1945 +{
1946 + unsigned int pllc_ctrl, cpu_div;
1947 + unsigned int pllc_out, refdiv, fdiv, divby2;
1948 + unsigned int clk_div;
1949 +
1950 + pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
1951 + refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
1952 + refdiv = clockctl1_predivide_table[refdiv];
1953 + fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
1954 + divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
1955 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
1956 +
1957 + /* clkm input selected */
1958 + switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
1959 + case 0:
1960 + case 1:
1961 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
1962 + clk_div = pllc_divide_table[clk_div];
1963 + break;
1964 + case 2:
1965 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
1966 + clk_div = pllc_divide_table[clk_div];
1967 + break;
1968 + default:
1969 + pllc_out = 40000000;
1970 + clk_div = 1;
1971 + break;
1972 + }
1973 +
1974 + cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
1975 + cpu_div = cpu_div * 2 ?: 1;
1976 +
1977 + return pllc_out / (clk_div * cpu_div);
1978 +}
1979 +
1980 +static inline unsigned ar2315_cpu_frequency(void)
1981 +{
1982 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
1983 +}
1984 +
1985 +static inline unsigned ar2315_apb_frequency(void)
1986 +{
1987 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
1988 +}
1989 +
1990 +void __init ar2315_plat_time_init(void)
1991 +{
1992 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
1993 +}
1994 +
1995 +void __init ar2315_plat_mem_setup(void)
1996 +{
1997 + void __iomem *sdram_base;
1998 + u32 memsize, memcfg;
1999 + u32 devid;
2000 + u32 config;
2001 +
2002 + sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
2003 + AR2315_SDRAMCTL_SIZE);
2004 + memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
2005 + memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
2006 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
2007 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
2008 + memsize <<= 3;
2009 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2010 + iounmap(sdram_base);
2011 +
2012 + ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
2013 +
2014 + /* Detect the hardware based on the device ID */
2015 + devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
2016 + switch (devid) {
2017 + case 0x91: /* Need to check */
2018 + ath25_soc = ATH25_SOC_AR2318;
2019 + break;
2020 + case 0x90:
2021 + ath25_soc = ATH25_SOC_AR2317;
2022 + break;
2023 + case 0x87:
2024 + ath25_soc = ATH25_SOC_AR2316;
2025 + break;
2026 + case 0x86:
2027 + default:
2028 + ath25_soc = ATH25_SOC_AR2315;
2029 + break;
2030 + }
2031 + ath25_board.devid = devid;
2032 +
2033 + /* Clear any lingering AHB errors */
2034 + config = read_c0_config();
2035 + write_c0_config(config & ~0x3);
2036 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
2037 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
2038 + ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
2039 +
2040 + _machine_restart = ar2315_restart;
2041 +}
2042 +
2043 +void __init ar2315_arch_init(void)
2044 +{
2045 + unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
2046 + AR2315_MISC_IRQ_UART0);
2047 +
2048 + ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
2049 +}
2050 --- /dev/null
2051 +++ b/arch/mips/ath25/ar2315.h
2052 @@ -0,0 +1,36 @@
2053 +#ifndef __AR2315_H
2054 +#define __AR2315_H
2055 +
2056 +#ifdef CONFIG_SOC_AR2315
2057 +
2058 +void ar2315_arch_init_irq(void);
2059 +void ar2315_init_devices(void);
2060 +void ar2315_plat_time_init(void);
2061 +void ar2315_plat_mem_setup(void);
2062 +void ar2315_arch_init(void);
2063 +
2064 +#else
2065 +
2066 +static inline void ar2315_arch_init_irq(void)
2067 +{
2068 +}
2069 +
2070 +static inline void ar2315_init_devices(void)
2071 +{
2072 +}
2073 +
2074 +static inline void ar2315_plat_time_init(void)
2075 +{
2076 +}
2077 +
2078 +static inline void ar2315_plat_mem_setup(void)
2079 +{
2080 +}
2081 +
2082 +static inline void ar2315_arch_init(void)
2083 +{
2084 +}
2085 +
2086 +#endif
2087 +
2088 +#endif
2089 --- /dev/null
2090 +++ b/arch/mips/ath25/ar5312.h
2091 @@ -0,0 +1,36 @@
2092 +#ifndef __AR5312_H
2093 +#define __AR5312_H
2094 +
2095 +#ifdef CONFIG_SOC_AR5312
2096 +
2097 +void ar5312_arch_init_irq(void);
2098 +void ar5312_init_devices(void);
2099 +void ar5312_plat_time_init(void);
2100 +void ar5312_plat_mem_setup(void);
2101 +void ar5312_arch_init(void);
2102 +
2103 +#else
2104 +
2105 +static inline void ar5312_arch_init_irq(void)
2106 +{
2107 +}
2108 +
2109 +static inline void ar5312_init_devices(void)
2110 +{
2111 +}
2112 +
2113 +static inline void ar5312_plat_time_init(void)
2114 +{
2115 +}
2116 +
2117 +static inline void ar5312_plat_mem_setup(void)
2118 +{
2119 +}
2120 +
2121 +static inline void ar5312_arch_init(void)
2122 +{
2123 +}
2124 +
2125 +#endif
2126 +
2127 +#endif
2128 --- /dev/null
2129 +++ b/arch/mips/ath25/devices.h
2130 @@ -0,0 +1,41 @@
2131 +#ifndef __ATH25_DEVICES_H
2132 +#define __ATH25_DEVICES_H
2133 +
2134 +#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
2135 +
2136 +#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
2137 +
2138 +enum ath25_soc_type {
2139 + /* handled by ar5312.c */
2140 + ATH25_SOC_AR2312,
2141 + ATH25_SOC_AR2313,
2142 + ATH25_SOC_AR5312,
2143 +
2144 + /* handled by ar2315.c */
2145 + ATH25_SOC_AR2315,
2146 + ATH25_SOC_AR2316,
2147 + ATH25_SOC_AR2317,
2148 + ATH25_SOC_AR2318,
2149 +
2150 + ATH25_SOC_UNKNOWN
2151 +};
2152 +
2153 +extern enum ath25_soc_type ath25_soc;
2154 +extern struct ar231x_board_config ath25_board;
2155 +extern void (*ath25_irq_dispatch)(void);
2156 +
2157 +int ath25_find_config(phys_addr_t offset, unsigned long size);
2158 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2159 +int ath25_add_wmac(int nr, u32 base, int irq);
2160 +
2161 +static inline bool is_ar2315(void)
2162 +{
2163 + return (current_cpu_data.cputype == CPU_4KEC);
2164 +}
2165 +
2166 +static inline bool is_ar5312(void)
2167 +{
2168 + return !is_ar2315();
2169 +}
2170 +
2171 +#endif
2172 --- /dev/null
2173 +++ b/arch/mips/ath25/devices.c
2174 @@ -0,0 +1,127 @@
2175 +#include <linux/kernel.h>
2176 +#include <linux/init.h>
2177 +#include <linux/serial.h>
2178 +#include <linux/serial_core.h>
2179 +#include <linux/serial_8250.h>
2180 +#include <linux/platform_device.h>
2181 +#include <asm/bootinfo.h>
2182 +
2183 +#include <ath25_platform.h>
2184 +#include "devices.h"
2185 +#include "ar5312.h"
2186 +#include "ar2315.h"
2187 +
2188 +struct ar231x_board_config ath25_board;
2189 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2190 +
2191 +static struct resource ath25_wmac0_res[] = {
2192 + {
2193 + .name = "wmac0_membase",
2194 + .flags = IORESOURCE_MEM,
2195 + },
2196 + {
2197 + .name = "wmac0_irq",
2198 + .flags = IORESOURCE_IRQ,
2199 + }
2200 +};
2201 +
2202 +static struct resource ath25_wmac1_res[] = {
2203 + {
2204 + .name = "wmac1_membase",
2205 + .flags = IORESOURCE_MEM,
2206 + },
2207 + {
2208 + .name = "wmac1_irq",
2209 + .flags = IORESOURCE_IRQ,
2210 + }
2211 +};
2212 +
2213 +static struct platform_device ath25_wmac[] = {
2214 + {
2215 + .id = 0,
2216 + .name = "ar231x-wmac",
2217 + .resource = ath25_wmac0_res,
2218 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2219 + .dev.platform_data = &ath25_board,
2220 + },
2221 + {
2222 + .id = 1,
2223 + .name = "ar231x-wmac",
2224 + .resource = ath25_wmac1_res,
2225 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2226 + .dev.platform_data = &ath25_board,
2227 + },
2228 +};
2229 +
2230 +static const char * const soc_type_strings[] = {
2231 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2232 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2233 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2234 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2235 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2236 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2237 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2238 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2239 +};
2240 +
2241 +const char *get_system_type(void)
2242 +{
2243 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2244 + !soc_type_strings[ath25_soc])
2245 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2246 + return soc_type_strings[ath25_soc];
2247 +}
2248 +
2249 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2250 +{
2251 + struct uart_port s;
2252 +
2253 + memset(&s, 0, sizeof(s));
2254 +
2255 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2256 + s.iotype = UPIO_MEM32;
2257 + s.irq = irq;
2258 + s.regshift = 2;
2259 + s.mapbase = mapbase;
2260 + s.uartclk = uartclk;
2261 +
2262 + early_serial_setup(&s);
2263 +}
2264 +
2265 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2266 +{
2267 + struct resource *res;
2268 +
2269 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2270 + res = &ath25_wmac[nr].resource[0];
2271 + res->start = base;
2272 + res->end = base + 0x10000 - 1;
2273 + res++;
2274 + res->start = irq;
2275 + res->end = irq;
2276 + return platform_device_register(&ath25_wmac[nr]);
2277 +}
2278 +
2279 +static int __init ath25_register_devices(void)
2280 +{
2281 + if (is_ar5312())
2282 + ar5312_init_devices();
2283 + else
2284 + ar2315_init_devices();
2285 +
2286 + return 0;
2287 +}
2288 +
2289 +device_initcall(ath25_register_devices);
2290 +
2291 +static int __init ath25_arch_init(void)
2292 +{
2293 + if (is_ar5312())
2294 + ar5312_arch_init();
2295 + else
2296 + ar2315_arch_init();
2297 +
2298 + return 0;
2299 +}
2300 +
2301 +arch_initcall(ath25_arch_init);
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