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7dd0b7aa368bb8624c06575ae577cba8993ebfbe
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,20 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select IRQ_DOMAIN
14 + select SYS_HAS_CPU_MIPS32_R1
15 + select SYS_SUPPORTS_BIG_ENDIAN
16 + select SYS_SUPPORTS_32BIT_KERNEL
17 + select ARCH_REQUIRE_GPIOLIB
18 + help
19 + Support for AR231x and AR531x based boards
20 +
21 config ATH79
22 bool "Atheros AR71XX/AR724X/AR913X based boards"
23 select ARCH_REQUIRE_GPIOLIB
24 @@ -834,6 +848,7 @@ config MIPS_PARAVIRT
25
26 endchoice
27
28 +source "arch/mips/ath25/Kconfig"
29 source "arch/mips/alchemy/Kconfig"
30 source "arch/mips/ath79/Kconfig"
31 source "arch/mips/bcm47xx/Kconfig"
32 --- a/arch/mips/Kbuild.platforms
33 +++ b/arch/mips/Kbuild.platforms
34 @@ -2,6 +2,7 @@
35
36 platforms += alchemy
37 platforms += ar7
38 +platforms += ath25
39 platforms += ath79
40 platforms += bcm47xx
41 platforms += bcm63xx
42 --- /dev/null
43 +++ b/arch/mips/ath25/Platform
44 @@ -0,0 +1,6 @@
45 +#
46 +# Atheros AR531X/AR231X WiSoC
47 +#
48 +platform-$(CONFIG_ATH25) += ath25/
49 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
50 +load-$(CONFIG_ATH25) += 0xffffffff80041000
51 --- /dev/null
52 +++ b/arch/mips/ath25/Kconfig
53 @@ -0,0 +1,9 @@
54 +config SOC_AR5312
55 + bool "Atheros 5312/2312+ support"
56 + depends on ATH25
57 + default y
58 +
59 +config SOC_AR2315
60 + bool "Atheros 2315+ support"
61 + depends on ATH25
62 + default y
63 --- /dev/null
64 +++ b/arch/mips/ath25/Makefile
65 @@ -0,0 +1,13 @@
66 +#
67 +# This file is subject to the terms and conditions of the GNU General Public
68 +# License. See the file "COPYING" in the main directory of this archive
69 +# for more details.
70 +#
71 +# Copyright (C) 2006 FON Technology, SL.
72 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
73 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
74 +#
75 +
76 +obj-y += board.o prom.o devices.o
77 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
78 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
79 --- /dev/null
80 +++ b/arch/mips/ath25/board.c
81 @@ -0,0 +1,244 @@
82 +/*
83 + * This file is subject to the terms and conditions of the GNU General Public
84 + * License. See the file "COPYING" in the main directory of this archive
85 + * for more details.
86 + *
87 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
88 + * Copyright (C) 2006 FON Technology, SL.
89 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
90 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
91 + */
92 +
93 +#include <generated/autoconf.h>
94 +#include <linux/init.h>
95 +#include <linux/module.h>
96 +#include <linux/types.h>
97 +#include <linux/string.h>
98 +#include <linux/platform_device.h>
99 +#include <linux/kernel.h>
100 +#include <linux/random.h>
101 +#include <linux/etherdevice.h>
102 +#include <linux/irq.h>
103 +#include <linux/io.h>
104 +#include <asm/irq_cpu.h>
105 +#include <asm/reboot.h>
106 +#include <asm/bootinfo.h>
107 +#include <asm/time.h>
108 +
109 +#include <ath25_platform.h>
110 +#include "devices.h"
111 +#include "ar5312.h"
112 +#include "ar2315.h"
113 +
114 +void (*ath25_irq_dispatch)(void);
115 +
116 +static inline bool check_radio_magic(const void __iomem *addr)
117 +{
118 + addr += 0x7a; /* offset for flash magic */
119 + return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
120 +}
121 +
122 +static inline bool check_notempty(const void __iomem *addr)
123 +{
124 + return __raw_readl(addr) != 0xffffffff;
125 +}
126 +
127 +static inline bool check_board_data(const void __iomem *addr, bool broken)
128 +{
129 + /* config magic found */
130 + if (__raw_readl(addr) == ATH25_BD_MAGIC)
131 + return true;
132 +
133 + if (!broken)
134 + return false;
135 +
136 + /* broken board data detected, use radio data to find the
137 + * offset, user will fix this */
138 +
139 + if (check_radio_magic(addr + 0x1000))
140 + return true;
141 + if (check_radio_magic(addr + 0xf8))
142 + return true;
143 +
144 + return false;
145 +}
146 +
147 +static const void __iomem * __init find_board_config(const void __iomem *limit,
148 + const bool broken)
149 +{
150 + const void __iomem *addr;
151 + const void __iomem *begin = limit - 0x1000;
152 + const void __iomem *end = limit - 0x30000;
153 +
154 + for (addr = begin; addr >= end; addr -= 0x1000)
155 + if (check_board_data(addr, broken))
156 + return addr;
157 +
158 + return NULL;
159 +}
160 +
161 +static const void __iomem * __init find_radio_config(const void __iomem *limit,
162 + const void __iomem *bcfg)
163 +{
164 + const void __iomem *rcfg, *begin, *end;
165 +
166 + /*
167 + * Now find the start of Radio Configuration data, using heuristics:
168 + * Search forward from Board Configuration data by 0x1000 bytes
169 + * at a time until we find non-0xffffffff.
170 + */
171 + begin = bcfg + 0x1000;
172 + end = limit;
173 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
174 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
175 + return rcfg;
176 +
177 + /* AR2316 relocates radio config to new location */
178 + begin = bcfg + 0xf8;
179 + end = limit - 0x1000 + 0xf8;
180 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
181 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
182 + return rcfg;
183 +
184 + return NULL;
185 +}
186 +
187 +/*
188 + * NB: Search region size could be larger than the actual flash size,
189 + * but this shouldn't be a problem here, because the flash
190 + * will simply be mapped multiple times.
191 + */
192 +int __init ath25_find_config(phys_addr_t base, unsigned long size)
193 +{
194 + const void __iomem *flash_base, *flash_limit;
195 + struct ath25_boarddata *config;
196 + unsigned int rcfg_size;
197 + int broken_boarddata = 0;
198 + const void __iomem *bcfg, *rcfg;
199 + u8 *board_data;
200 + u8 *radio_data;
201 + u8 *mac_addr;
202 + u32 offset;
203 +
204 + flash_base = ioremap_nocache(base, size);
205 + flash_limit = flash_base + size;
206 +
207 + ath25_board.config = NULL;
208 + ath25_board.radio = NULL;
209 +
210 + /* Copy the board and radio data to RAM, because accessing the mapped
211 + * memory of the flash directly after booting is not safe */
212 +
213 + /* Try to find valid board and radio data */
214 + bcfg = find_board_config(flash_limit, false);
215 +
216 + /* If that fails, try to at least find valid radio data */
217 + if (!bcfg) {
218 + bcfg = find_board_config(flash_limit, true);
219 + broken_boarddata = 1;
220 + }
221 +
222 + if (!bcfg) {
223 + pr_warn("WARNING: No board configuration data found!\n");
224 + goto error;
225 + }
226 +
227 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
228 + ath25_board.config = (struct ath25_boarddata *)board_data;
229 + memcpy_fromio(board_data, bcfg, 0x100);
230 + if (broken_boarddata) {
231 + pr_warn("WARNING: broken board data detected\n");
232 + config = ath25_board.config;
233 + if (is_zero_ether_addr(config->enet0_mac)) {
234 + pr_info("Fixing up empty mac addresses\n");
235 + config->reset_config_gpio = 0xffff;
236 + config->sys_led_gpio = 0xffff;
237 + random_ether_addr(config->wlan0_mac);
238 + config->wlan0_mac[0] &= ~0x06;
239 + random_ether_addr(config->enet0_mac);
240 + random_ether_addr(config->enet1_mac);
241 + }
242 + }
243 +
244 + /* Radio config starts 0x100 bytes after board config, regardless
245 + * of what the physical layout on the flash chip looks like */
246 +
247 + rcfg = find_radio_config(flash_limit, bcfg);
248 + if (!rcfg) {
249 + pr_warn("WARNING: Could not find Radio Configuration data\n");
250 + goto error;
251 + }
252 +
253 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
254 + ath25_board.radio = radio_data;
255 + offset = radio_data - board_data;
256 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
257 + offset);
258 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
259 + memcpy_fromio(radio_data, rcfg, rcfg_size);
260 +
261 + mac_addr = &radio_data[0x1d * 2];
262 + if (is_broadcast_ether_addr(mac_addr)) {
263 + pr_info("Radio MAC is blank; using board-data\n");
264 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
265 + }
266 +
267 + iounmap(flash_base);
268 +
269 + return 0;
270 +
271 +error:
272 + iounmap(flash_base);
273 + return -ENODEV;
274 +}
275 +
276 +static void ath25_halt(void)
277 +{
278 + local_irq_disable();
279 + while (1)
280 + ;
281 +}
282 +
283 +void __init plat_mem_setup(void)
284 +{
285 + _machine_halt = ath25_halt;
286 + pm_power_off = ath25_halt;
287 +
288 + if (is_ar5312())
289 + ar5312_plat_mem_setup();
290 + else
291 + ar2315_plat_mem_setup();
292 +
293 + /* Disable data watchpoints */
294 + write_c0_watchlo0(0);
295 +}
296 +
297 +asmlinkage void plat_irq_dispatch(void)
298 +{
299 + ath25_irq_dispatch();
300 +}
301 +
302 +void __init plat_time_init(void)
303 +{
304 + if (is_ar5312())
305 + ar5312_plat_time_init();
306 + else
307 + ar2315_plat_time_init();
308 +}
309 +
310 +unsigned int __cpuinit get_c0_compare_int(void)
311 +{
312 + return CP0_LEGACY_COMPARE_IRQ;
313 +}
314 +
315 +void __init arch_init_irq(void)
316 +{
317 + clear_c0_status(ST0_IM);
318 + mips_cpu_irq_init();
319 +
320 + /* Initialize interrupt controllers */
321 + if (is_ar5312())
322 + ar5312_arch_init_irq();
323 + else
324 + ar2315_arch_init_irq();
325 +}
326 --- /dev/null
327 +++ b/arch/mips/ath25/prom.c
328 @@ -0,0 +1,26 @@
329 +/*
330 + * This file is subject to the terms and conditions of the GNU General Public
331 + * License. See the file "COPYING" in the main directory of this archive
332 + * for more details.
333 + *
334 + * Copyright MontaVista Software Inc
335 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
336 + * Copyright (C) 2006 FON Technology, SL.
337 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
338 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
339 + */
340 +
341 +/*
342 + * Prom setup file for ar231x
343 + */
344 +
345 +#include <linux/init.h>
346 +#include <asm/bootinfo.h>
347 +
348 +void __init prom_init(void)
349 +{
350 +}
351 +
352 +void __init prom_free_prom_memory(void)
353 +{
354 +}
355 --- /dev/null
356 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
357 @@ -0,0 +1,84 @@
358 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
359 +#define __ASM_MACH_ATH25_PLATFORM_H
360 +
361 +#include <linux/etherdevice.h>
362 +
363 +/*
364 + * This is board-specific data that is stored in a "fixed" location in flash.
365 + * It is shared across operating systems, so it should not be changed lightly.
366 + * The main reason we need it is in order to extract the ethernet MAC
367 + * address(es).
368 + */
369 +struct ath25_boarddata {
370 + u32 magic; /* board data is valid */
371 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
372 + u16 cksum; /* checksum (starting with BD_REV 2) */
373 + u16 rev; /* revision of this struct */
374 +#define BD_REV 4
375 + char board_name[64]; /* Name of board */
376 + u16 major; /* Board major number */
377 + u16 minor; /* Board minor number */
378 + u32 flags; /* Board configuration */
379 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
380 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
381 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
382 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
383 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
384 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
385 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
386 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
387 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
388 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
389 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
390 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
391 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
392 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
393 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
394 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
395 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
396 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
397 + u16 reset_config_gpio; /* Reset factory GPIO pin */
398 + u16 sys_led_gpio; /* System LED GPIO pin */
399 +
400 + u32 cpu_freq; /* CPU core frequency in Hz */
401 + u32 sys_freq; /* System frequency in Hz */
402 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
403 +
404 + u8 wlan0_mac[ETH_ALEN];
405 + u8 enet0_mac[ETH_ALEN];
406 + u8 enet1_mac[ETH_ALEN];
407 +
408 + u16 pci_id; /* Pseudo PCIID for common code */
409 + u16 mem_cap; /* cap bank1 in MB */
410 +
411 + /* version 3 */
412 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
413 +};
414 +
415 +#define BOARD_CONFIG_BUFSZ 0x1000
416 +
417 +/*
418 + * Platform device information for the Wireless MAC
419 + */
420 +struct ar231x_board_config {
421 + u16 devid;
422 +
423 + /* board config data */
424 + struct ath25_boarddata *config;
425 +
426 + /* radio calibration data */
427 + const char *radio;
428 +};
429 +
430 +/*
431 + * Platform device information for the Ethernet MAC
432 + */
433 +struct ar231x_eth {
434 + void (*reset_set)(u32);
435 + void (*reset_clear)(u32);
436 + u32 reset_mac;
437 + u32 reset_phy;
438 + char *macaddr;
439 +};
440 +
441 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
442 --- /dev/null
443 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
444 @@ -0,0 +1,64 @@
445 +/*
446 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
447 + *
448 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
449 + *
450 + * This file was derived from: include/asm-mips/cpu-features.h
451 + * Copyright (C) 2003, 2004 Ralf Baechle
452 + * Copyright (C) 2004 Maciej W. Rozycki
453 + *
454 + * This program is free software; you can redistribute it and/or modify it
455 + * under the terms of the GNU General Public License version 2 as published
456 + * by the Free Software Foundation.
457 + *
458 + */
459 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
460 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
461 +
462 +/*
463 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
464 + */
465 +#define cpu_has_tlb 1
466 +#define cpu_has_4kex 1
467 +#define cpu_has_3k_cache 0
468 +#define cpu_has_4k_cache 1
469 +#define cpu_has_tx39_cache 0
470 +#define cpu_has_sb1_cache 0
471 +#define cpu_has_fpu 0
472 +#define cpu_has_32fpr 0
473 +#define cpu_has_counter 1
474 +#define cpu_has_ejtag 1
475 +
476 +#if !defined(CONFIG_SOC_AR5312)
477 +# define cpu_has_llsc 1
478 +#else
479 +/*
480 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
481 + * ll/sc instructions.
482 + */
483 +# define cpu_has_llsc 0
484 +#endif
485 +
486 +#define cpu_has_mips16 0
487 +#define cpu_has_mdmx 0
488 +#define cpu_has_mips3d 0
489 +#define cpu_has_smartmips 0
490 +
491 +#define cpu_has_mips32r1 1
492 +
493 +#if !defined(CONFIG_SOC_AR5312)
494 +# define cpu_has_mips32r2 1
495 +#endif
496 +
497 +#define cpu_has_mips64r1 0
498 +#define cpu_has_mips64r2 0
499 +
500 +#define cpu_has_dsp 0
501 +#define cpu_has_mipsmt 0
502 +
503 +#define cpu_has_64bits 0
504 +#define cpu_has_64bit_zero_reg 0
505 +#define cpu_has_64bit_gp_regs 0
506 +#define cpu_has_64bit_addresses 0
507 +
508 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
509 --- /dev/null
510 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
511 @@ -0,0 +1,82 @@
512 +/*
513 + * This file is subject to the terms and conditions of the GNU General Public
514 + * License. See the file "COPYING" in the main directory of this archive
515 + * for more details.
516 + *
517 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
518 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
519 + *
520 + */
521 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
522 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
523 +
524 +#include <linux/device.h>
525 +
526 +/*
527 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
528 + * of PCI host controller to enable DMA. The same value should be used as the
529 + * offset to calculate the physical address of DMA buffer for PCI devices.
530 + */
531 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
532 +
533 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
534 +{
535 +#ifdef CONFIG_PCI
536 + extern struct bus_type pci_bus_type;
537 +
538 + if (dev && dev->bus == &pci_bus_type)
539 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
540 +#endif
541 + return 0;
542 +}
543 +
544 +static inline dma_addr_t
545 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
546 +{
547 + return virt_to_phys(addr) + ath25_dev_offset(dev);
548 +}
549 +
550 +static inline dma_addr_t
551 +plat_map_dma_mem_page(struct device *dev, struct page *page)
552 +{
553 + return page_to_phys(page) + ath25_dev_offset(dev);
554 +}
555 +
556 +static inline unsigned long
557 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
558 +{
559 + return dma_addr - ath25_dev_offset(dev);
560 +}
561 +
562 +static inline void
563 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
564 + enum dma_data_direction direction)
565 +{
566 +}
567 +
568 +static inline int plat_dma_supported(struct device *dev, u64 mask)
569 +{
570 + return 1;
571 +}
572 +
573 +static inline void plat_extra_sync_for_device(struct device *dev)
574 +{
575 +}
576 +
577 +static inline int plat_dma_mapping_error(struct device *dev,
578 + dma_addr_t dma_addr)
579 +{
580 + return 0;
581 +}
582 +
583 +static inline int plat_device_is_coherent(struct device *dev)
584 +{
585 +#ifdef CONFIG_DMA_COHERENT
586 + return 1;
587 +#endif
588 +#ifdef CONFIG_DMA_NONCOHERENT
589 + return 0;
590 +#endif
591 +}
592 +
593 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
594 --- /dev/null
595 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
596 @@ -0,0 +1,16 @@
597 +#ifndef __ASM_MACH_ATH25_GPIO_H
598 +#define __ASM_MACH_ATH25_GPIO_H
599 +
600 +#include <asm-generic/gpio.h>
601 +
602 +#define gpio_get_value __gpio_get_value
603 +#define gpio_set_value __gpio_set_value
604 +#define gpio_cansleep __gpio_cansleep
605 +#define gpio_to_irq __gpio_to_irq
606 +
607 +static inline int irq_to_gpio(unsigned irq)
608 +{
609 + return -EINVAL;
610 +}
611 +
612 +#endif /* __ASM_MACH_ATH25_GPIO_H */
613 --- /dev/null
614 +++ b/arch/mips/include/asm/mach-ath25/war.h
615 @@ -0,0 +1,25 @@
616 +/*
617 + * This file is subject to the terms and conditions of the GNU General Public
618 + * License. See the file "COPYING" in the main directory of this archive
619 + * for more details.
620 + *
621 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
622 + */
623 +#ifndef __ASM_MACH_ATH25_WAR_H
624 +#define __ASM_MACH_ATH25_WAR_H
625 +
626 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
627 +#define R4600_V1_HIT_CACHEOP_WAR 0
628 +#define R4600_V2_HIT_CACHEOP_WAR 0
629 +#define R5432_CP0_INTERRUPT_WAR 0
630 +#define BCM1250_M3_WAR 0
631 +#define SIBYTE_1956_WAR 0
632 +#define MIPS4K_ICACHE_REFILL_WAR 0
633 +#define MIPS_CACHE_SYNC_WAR 0
634 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
635 +#define RM9000_CDEX_SMP_WAR 0
636 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
637 +#define R10000_LLSC_WAR 0
638 +#define MIPS34K_MISSED_ITLB_WAR 0
639 +
640 +#endif /* __ASM_MACH_ATH25_WAR_H */
641 --- /dev/null
642 +++ b/arch/mips/ath25/ar2315_regs.h
643 @@ -0,0 +1,479 @@
644 +/*
645 + * Register definitions for AR2315+
646 + *
647 + * This file is subject to the terms and conditions of the GNU General Public
648 + * License. See the file "COPYING" in the main directory of this archive
649 + * for more details.
650 + *
651 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
652 + * Copyright (C) 2006 FON Technology, SL.
653 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
654 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
655 + */
656 +
657 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
658 +#define __ASM_MACH_ATH25_AR2315_REGS_H
659 +
660 +/*
661 + * IRQs
662 + */
663 +#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
664 +#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
665 +#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
666 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
667 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
668 +
669 +/*
670 + * Miscellaneous interrupts, which share IP2.
671 + */
672 +#define AR2315_MISC_IRQ_UART0 0
673 +#define AR2315_MISC_IRQ_I2C_RSVD 1
674 +#define AR2315_MISC_IRQ_SPI 2
675 +#define AR2315_MISC_IRQ_AHB 3
676 +#define AR2315_MISC_IRQ_APB 4
677 +#define AR2315_MISC_IRQ_TIMER 5
678 +#define AR2315_MISC_IRQ_GPIO 6
679 +#define AR2315_MISC_IRQ_WATCHDOG 7
680 +#define AR2315_MISC_IRQ_IR_RSVD 8
681 +#define AR2315_MISC_IRQ_COUNT 9
682 +
683 +/*
684 + * Address map
685 + */
686 +#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
687 +#define AR2315_SPI_READ_SIZE 0x01000000
688 +#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
689 +#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
690 +#define AR2315_PCI_SIZE 0x00001000
691 +#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
692 +#define AR2315_SDRAMCTL_SIZE 0x00000020
693 +#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
694 +#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
695 +#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
696 +#define AR2315_RST_SIZE 0x00000100
697 +#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
698 +#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
699 +#define AR2315_SPI_MMR_SIZE 0x00000010
700 +#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
701 +#define AR2315_PCI_EXT_SIZE 0x40000000
702 +
703 +/* MII registers offset inside Ethernet MMR region */
704 +#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
705 +
706 +/*
707 + * Cold reset register
708 + */
709 +#define AR2315_COLD_RESET 0x0000
710 +
711 +#define AR2315_RESET_COLD_AHB 0x00000001
712 +#define AR2315_RESET_COLD_APB 0x00000002
713 +#define AR2315_RESET_COLD_CPU 0x00000004
714 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
715 +#define AR2315_RESET_SYSTEM \
716 + (RESET_COLD_CPU |\
717 + RESET_COLD_APB |\
718 + RESET_COLD_AHB) /* full system */
719 +#define AR2317_RESET_SYSTEM 0x00000010
720 +
721 +/*
722 + * Reset register
723 + */
724 +#define AR2315_RESET 0x0004
725 +
726 +/* warm reset WLAN0 MAC */
727 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
728 +/* warm reset WLAN0 BaseBand */
729 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
730 +/* warm reset MPEG-TS */
731 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
732 +/* warm reset PCI ahb/dma */
733 +#define AR2315_RESET_PCIDMA 0x00000008
734 +/* warm reset memory controller */
735 +#define AR2315_RESET_MEMCTL 0x00000010
736 +/* warm reset local bus */
737 +#define AR2315_RESET_LOCAL 0x00000020
738 +/* warm reset I2C bus */
739 +#define AR2315_RESET_I2C_RSVD 0x00000040
740 +/* warm reset SPI interface */
741 +#define AR2315_RESET_SPI 0x00000080
742 +/* warm reset UART0 */
743 +#define AR2315_RESET_UART0 0x00000100
744 +/* warm reset IR interface */
745 +#define AR2315_RESET_IR_RSVD 0x00000200
746 +/* cold reset ENET0 phy */
747 +#define AR2315_RESET_EPHY0 0x00000400
748 +/* cold reset ENET0 mac */
749 +#define AR2315_RESET_ENET0 0x00000800
750 +
751 +/*
752 + * AHB master arbitration control
753 + */
754 +#define AR2315_AHB_ARB_CTL 0x0008
755 +
756 +/* CPU, default */
757 +#define AR2315_ARB_CPU 0x00000001
758 +/* WLAN */
759 +#define AR2315_ARB_WLAN 0x00000002
760 +/* MPEG-TS */
761 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
762 +/* LOCAL */
763 +#define AR2315_ARB_LOCAL 0x00000008
764 +/* PCI */
765 +#define AR2315_ARB_PCI 0x00000010
766 +/* Ethernet */
767 +#define AR2315_ARB_ETHERNET 0x00000020
768 +/* retry policy, debug only */
769 +#define AR2315_ARB_RETRY 0x00000100
770 +
771 +/*
772 + * Config Register
773 + */
774 +#define AR2315_ENDIAN_CTL 0x000c
775 +
776 +/* EC - AHB bridge endianess */
777 +#define AR2315_CONFIG_AHB 0x00000001
778 +/* WLAN byteswap */
779 +#define AR2315_CONFIG_WLAN 0x00000002
780 +/* MPEG-TS byteswap */
781 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
782 +/* PCI byteswap */
783 +#define AR2315_CONFIG_PCI 0x00000008
784 +/* Memory controller endianess */
785 +#define AR2315_CONFIG_MEMCTL 0x00000010
786 +/* Local bus byteswap */
787 +#define AR2315_CONFIG_LOCAL 0x00000020
788 +/* Ethernet byteswap */
789 +#define AR2315_CONFIG_ETHERNET 0x00000040
790 +
791 +/* CPU write buffer merge */
792 +#define AR2315_CONFIG_MERGE 0x00000200
793 +/* CPU big endian */
794 +#define AR2315_CONFIG_CPU 0x00000400
795 +#define AR2315_CONFIG_PCIAHB 0x00000800
796 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
797 +/* SPI byteswap */
798 +#define AR2315_CONFIG_SPI 0x00008000
799 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
800 +#define AR2315_CONFIG_CPU_PCI 0x00020000
801 +#define AR2315_CONFIG_CPU_MMR 0x00040000
802 +#define AR2315_CONFIG_BIG 0x00000400
803 +
804 +/*
805 + * NMI control
806 + */
807 +#define AR2315_NMI_CTL 0x0010
808 +
809 +#define AR2315_NMI_EN 1
810 +
811 +/*
812 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
813 + */
814 +#define AR2315_SREV 0x0014
815 +
816 +#define AR2315_REV_MAJ 0x00f0
817 +#define AR2315_REV_MAJ_S 4
818 +#define AR2315_REV_MIN 0x000f
819 +#define AR2315_REV_MIN_S 0
820 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
821 +
822 +/*
823 + * Interface Enable
824 + */
825 +#define AR2315_IF_CTL 0x0018
826 +
827 +#define AR2315_IF_MASK 0x00000007
828 +#define AR2315_IF_DISABLED 0
829 +#define AR2315_IF_PCI 1
830 +#define AR2315_IF_TS_LOCAL 2
831 +/* only for emulation with separate pins */
832 +#define AR2315_IF_ALL 3
833 +#define AR2315_IF_LOCAL_HOST 0x00000008
834 +#define AR2315_IF_PCI_HOST 0x00000010
835 +#define AR2315_IF_PCI_INTR 0x00000020
836 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
837 +#define AR2315_IF_PCI_CLK_INPUT 0
838 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
839 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
840 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
841 +#define AR2315_IF_PCI_CLK_SHIFT 16
842 +
843 +/*
844 + * APB Interrupt control
845 + */
846 +
847 +#define AR2315_ISR 0x0020
848 +#define AR2315_IMR 0x0024
849 +#define AR2315_GISR 0x0028
850 +
851 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
852 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
853 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
854 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
855 +#define AR2315_ISR_APB 0x0010 /* APB error */
856 +#define AR2315_ISR_TIMER 0x0020 /* timer */
857 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
858 +#define AR2315_ISR_WD 0x0080 /* watchdog */
859 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
860 +
861 +#define AR2315_GISR_MISC 0x0001
862 +#define AR2315_GISR_WLAN0 0x0002
863 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
864 +#define AR2315_GISR_LOCALPCI 0x0008
865 +#define AR2315_GISR_WMACPOLL 0x0010
866 +#define AR2315_GISR_TIMER 0x0020
867 +#define AR2315_GISR_ETHERNET 0x0040
868 +
869 +/*
870 + * Timers
871 + */
872 +#define AR2315_TIMER 0x0030
873 +#define AR2315_RELOAD 0x0034
874 +
875 +#define AR2315_WDT_TIMER 0x0038
876 +#define AR2315_WDT_CTRL 0x003c
877 +
878 +#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
879 +#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
880 +#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
881 +
882 +/*
883 + * CPU Performance Counters
884 + */
885 +#define AR2315_PERFCNT0 0x0048
886 +#define AR2315_PERFCNT1 0x004c
887 +
888 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
889 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
890 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
891 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
892 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
893 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
894 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
895 +
896 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
897 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
898 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
899 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
900 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
901 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
902 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
903 +
904 +/*
905 + * AHB Error Reporting.
906 + */
907 +#define AR2315_AHB_ERR0 0x0050 /* error */
908 +#define AR2315_AHB_ERR1 0x0054 /* haddr */
909 +#define AR2315_AHB_ERR2 0x0058 /* hwdata */
910 +#define AR2315_AHB_ERR3 0x005c /* hrdata */
911 +#define AR2315_AHB_ERR4 0x0060 /* status */
912 +
913 +#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
914 + /* write 1 to clear all bits in ERR0 */
915 +#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
916 +#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
917 +
918 +#define AR2315_PROCERR_HMAST 0x0000000f
919 +#define AR2315_PROCERR_HMAST_DFLT 0
920 +#define AR2315_PROCERR_HMAST_WMAC 1
921 +#define AR2315_PROCERR_HMAST_ENET 2
922 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
923 +#define AR2315_PROCERR_HMAST_LOCAL 4
924 +#define AR2315_PROCERR_HMAST_CPU 5
925 +#define AR2315_PROCERR_HMAST_PCITGT 6
926 +
927 +#define AR2315_PROCERR_HMAST_S 0
928 +#define AR2315_PROCERR_HWRITE 0x00000010
929 +#define AR2315_PROCERR_HSIZE 0x00000060
930 +#define AR2315_PROCERR_HSIZE_S 5
931 +#define AR2315_PROCERR_HTRANS 0x00000180
932 +#define AR2315_PROCERR_HTRANS_S 7
933 +#define AR2315_PROCERR_HBURST 0x00000e00
934 +#define AR2315_PROCERR_HBURST_S 9
935 +
936 +/*
937 + * Clock Control
938 + */
939 +#define AR2315_PLLC_CTL 0x0064
940 +#define AR2315_PLLV_CTL 0x0068
941 +#define AR2315_CPUCLK 0x006c
942 +#define AR2315_AMBACLK 0x0070
943 +#define AR2315_SYNCCLK 0x0074
944 +#define AR2315_DSL_SLEEP_CTL 0x0080
945 +#define AR2315_DSL_SLEEP_DUR 0x0084
946 +
947 +/* PLLc Control fields */
948 +#define AR2315_PLLC_REF_DIV_M 0x00000003
949 +#define AR2315_PLLC_REF_DIV_S 0
950 +#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
951 +#define AR2315_PLLC_FDBACK_DIV_S 2
952 +#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
953 +#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
954 +#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
955 +#define AR2315_PLLC_CLKC_DIV_S 14
956 +#define AR2315_PLLC_CLKM_DIV_M 0x00700000
957 +#define AR2315_PLLC_CLKM_DIV_S 20
958 +
959 +/* CPU CLK Control fields */
960 +#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
961 +#define AR2315_CPUCLK_CLK_SEL_S 0
962 +#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
963 +#define AR2315_CPUCLK_CLK_DIV_S 2
964 +
965 +/* AMBA CLK Control fields */
966 +#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
967 +#define AR2315_AMBACLK_CLK_SEL_S 0
968 +#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
969 +#define AR2315_AMBACLK_CLK_DIV_S 2
970 +
971 +/* GPIO MMR base address */
972 +#define AR2315_GPIO 0x0088
973 +
974 +#define AR2315_RESET_GPIO 5
975 +
976 +/*
977 + * PCI Clock Control
978 + */
979 +#define AR2315_PCICLK 0x00a4
980 +
981 +#define AR2315_PCICLK_INPUT_M 0x3
982 +#define AR2315_PCICLK_INPUT_S 0
983 +
984 +#define AR2315_PCICLK_PLLC_CLKM 0
985 +#define AR2315_PCICLK_PLLC_CLKM1 1
986 +#define AR2315_PCICLK_PLLC_CLKC 2
987 +#define AR2315_PCICLK_REF_CLK 3
988 +
989 +#define AR2315_PCICLK_DIV_M 0xc
990 +#define AR2315_PCICLK_DIV_S 2
991 +
992 +#define AR2315_PCICLK_IN_FREQ 0
993 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
994 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
995 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
996 +
997 +/*
998 + * Observation Control Register
999 + */
1000 +#define AR2315_OCR 0x00b0
1001 +
1002 +#define AR2315_OCR_GPIO0_IRIN 0x00000040
1003 +#define AR2315_OCR_GPIO1_IROUT 0x00000080
1004 +#define AR2315_OCR_GPIO3_RXCLR 0x00000200
1005 +
1006 +/*
1007 + * General Clock Control
1008 + */
1009 +#define AR2315_MISCCLK 0x00b4
1010 +
1011 +#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
1012 +#define AR2315_MISCCLK_PROCREFCLK 0x00000002
1013 +
1014 +/*
1015 + * SDRAM Controller
1016 + * - No read or write buffers are included.
1017 + */
1018 +#define AR2315_MEM_CFG 0x0000
1019 +#define AR2315_MEM_CTRL 0x000c
1020 +#define AR2315_MEM_REF 0x0010
1021 +
1022 +#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
1023 +#define AR2315_MEM_CFG_DATA_WIDTH_S 13
1024 +#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
1025 +#define AR2315_MEM_CFG_COL_WIDTH_S 9
1026 +#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
1027 +#define AR2315_MEM_CFG_ROW_WIDTH_S 5
1028 +#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
1029 +#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
1030 +
1031 +/*
1032 + * Local Bus Interface Registers
1033 + */
1034 +#define AR2315_LB_CONFIG 0x0000
1035 +
1036 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1037 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1038 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1039 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1040 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1041 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1042 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1043 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1044 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1045 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1046 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1047 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1048 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1049 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1050 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1051 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1052 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1053 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1054 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1055 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1056 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1057 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1058 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1059 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1060 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1061 +
1062 +#define AR2315_LB_CLKSEL 0x0004
1063 +
1064 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1065 +
1066 +#define AR2315_LB_1MS 0x0008
1067 +
1068 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1069 +
1070 +#define AR2315_LB_MISCCFG 0x000c
1071 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1072 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1073 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1074 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1075 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1076 +#define AR2315_LBM_TIMEOUT_M 0x00ffff80
1077 +#define AR2315_LBM_TIMEOUT_S 7
1078 +#define AR2315_LBM_PORTMUX 0x07000000
1079 +
1080 +#define AR2315_LB_RXTSOFF 0x0010
1081 +
1082 +#define AR2315_LB_TX_CHAIN_EN 0x0100
1083 +
1084 +#define AR2315_LB_TXEN_0 0x01
1085 +#define AR2315_LB_TXEN_1 0x02
1086 +#define AR2315_LB_TXEN_2 0x04
1087 +#define AR2315_LB_TXEN_3 0x08
1088 +
1089 +#define AR2315_LB_TX_CHAIN_DIS 0x0104
1090 +#define AR2315_LB_TX_DESC_PTR 0x0200
1091 +
1092 +#define AR2315_LB_RX_CHAIN_EN 0x0400
1093 +
1094 +#define AR2315_LB_RXEN 0x01
1095 +
1096 +#define AR2315_LB_RX_CHAIN_DIS 0x0404
1097 +#define AR2315_LB_RX_DESC_PTR 0x0408
1098 +
1099 +#define AR2315_LB_INT_STATUS 0x0500
1100 +
1101 +#define AR2315_LB_INT_TX_DESC 0x00000001
1102 +#define AR2315_LB_INT_TX_OK 0x00000002
1103 +#define AR2315_LB_INT_TX_ERR 0x00000004
1104 +#define AR2315_LB_INT_TX_EOF 0x00000008
1105 +#define AR2315_LB_INT_RX_DESC 0x00000010
1106 +#define AR2315_LB_INT_RX_OK 0x00000020
1107 +#define AR2315_LB_INT_RX_ERR 0x00000040
1108 +#define AR2315_LB_INT_RX_EOF 0x00000080
1109 +#define AR2315_LB_INT_TX_TRUNC 0x00000100
1110 +#define AR2315_LB_INT_TX_STARVE 0x00000200
1111 +#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
1112 +#define AR2315_LB_INT_LB_ERR 0x00000800
1113 +#define AR2315_LB_INT_MBOX_WR 0x00001000
1114 +#define AR2315_LB_INT_MBOX_RD 0x00002000
1115 +
1116 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1117 +#define AR2315_LB_INT_MASK 0x0504
1118 +
1119 +#define AR2315_LB_INT_EN 0x0508
1120 +#define AR2315_LB_MBOX 0x0600
1121 +
1122 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1123 --- /dev/null
1124 +++ b/arch/mips/ath25/ar5312_regs.h
1125 @@ -0,0 +1,229 @@
1126 +/*
1127 + * This file is subject to the terms and conditions of the GNU General Public
1128 + * License. See the file "COPYING" in the main directory of this archive
1129 + * for more details.
1130 + *
1131 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1132 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1133 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1134 + */
1135 +
1136 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1137 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1138 +
1139 +#include <asm/addrspace.h>
1140 +
1141 +/*
1142 + * IRQs
1143 + */
1144 +#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
1145 +#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
1146 +#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
1147 +#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
1148 +#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
1149 +
1150 +/*
1151 + * Miscellaneous interrupts, which share IP6.
1152 + */
1153 +#define AR5312_MISC_IRQ_TIMER 0
1154 +#define AR5312_MISC_IRQ_AHB_PROC 1
1155 +#define AR5312_MISC_IRQ_AHB_DMA 2
1156 +#define AR5312_MISC_IRQ_GPIO 3
1157 +#define AR5312_MISC_IRQ_UART0 4
1158 +#define AR5312_MISC_IRQ_UART0_DMA 5
1159 +#define AR5312_MISC_IRQ_WATCHDOG 6
1160 +#define AR5312_MISC_IRQ_LOCAL 7
1161 +#define AR5312_MISC_IRQ_SPI 8
1162 +#define AR5312_MISC_IRQ_COUNT 9
1163 +
1164 +/*
1165 + * Address Map
1166 + *
1167 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1168 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1169 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1170 + */
1171 +#define AR5312_WLAN0_BASE 0x18000000
1172 +#define AR5312_ENET0_BASE 0x18100000
1173 +#define AR5312_ENET1_BASE 0x18200000
1174 +#define AR5312_SDRAMCTL_BASE 0x18300000
1175 +#define AR5312_SDRAMCTL_SIZE 0x00000010
1176 +#define AR5312_FLASHCTL_BASE 0x18400000
1177 +#define AR5312_FLASHCTL_SIZE 0x00000010
1178 +#define AR5312_WLAN1_BASE 0x18500000
1179 +#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
1180 +#define AR5312_GPIO_BASE 0x1c002000
1181 +#define AR5312_GPIO_SIZE 0x00000010
1182 +#define AR5312_RST_BASE 0x1c003000
1183 +#define AR5312_RST_SIZE 0x00000100
1184 +#define AR5312_FLASH_BASE 0x1e000000
1185 +#define AR5312_FLASH_SIZE 0x00800000
1186 +
1187 +/*
1188 + * Need these defines to determine true number of ethernet MACs
1189 + */
1190 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1191 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1192 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1193 +
1194 +/* MII registers offset inside Ethernet MMR region */
1195 +#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
1196 +#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
1197 +
1198 +/* Reset/Timer Block Address Map */
1199 +#define AR5312_TIMER 0x0000 /* countdown timer */
1200 +#define AR5312_RELOAD 0x0004 /* timer reload value */
1201 +#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
1202 +#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
1203 +#define AR5312_ISR 0x0010 /* Intr Status Reg */
1204 +#define AR5312_IMR 0x0014 /* Intr Mask Reg */
1205 +#define AR5312_RESET 0x0020
1206 +#define AR5312_CLOCKCTL1 0x0064
1207 +#define AR5312_SCRATCH 0x006c
1208 +#define AR5312_PROCADDR 0x0070
1209 +#define AR5312_PROC1 0x0074
1210 +#define AR5312_DMAADDR 0x0078
1211 +#define AR5312_DMA1 0x007c
1212 +#define AR5312_ENABLE 0x0080 /* interface enb */
1213 +#define AR5312_REV 0x0090 /* revision */
1214 +
1215 +/* AR5312_WDT_CTRL register bit field definitions */
1216 +#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
1217 +#define AR5312_WDT_CTRL_NMI 0x00000001
1218 +#define AR5312_WDT_CTRL_RESET 0x00000002
1219 +
1220 +/* AR5312_ISR register bit field definitions */
1221 +#define AR5312_ISR_TIMER 0x0001
1222 +#define AR5312_ISR_AHBPROC 0x0002
1223 +#define AR5312_ISR_AHBDMA 0x0004
1224 +#define AR5312_ISR_GPIO 0x0008
1225 +#define AR5312_ISR_UART0 0x0010
1226 +#define AR5312_ISR_UART0DMA 0x0020
1227 +#define AR5312_ISR_WD 0x0040
1228 +#define AR5312_ISR_LOCAL 0x0080
1229 +
1230 +/* AR5312_RESET register bit field definitions */
1231 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1232 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1233 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1234 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1235 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1236 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1237 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1238 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1239 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1240 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1241 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1242 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1243 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1244 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1245 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1246 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1247 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1248 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1249 +
1250 +#define AR5312_RESET_WMAC0_BITS \
1251 + (AR5312_RESET_WLAN0 |\
1252 + AR5312_RESET_WARM_WLAN0_MAC |\
1253 + AR5312_RESET_WARM_WLAN0_BB)
1254 +
1255 +#define AR5312_RESET_WMAC1_BITS \
1256 + (AR5312_RESET_WLAN1 |\
1257 + AR5312_RESET_WARM_WLAN1_MAC |\
1258 + AR5312_RESET_WARM_WLAN1_BB)
1259 +
1260 +/* AR5312_CLOCKCTL1 register bit field definitions */
1261 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1262 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1263 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1264 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1265 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1266 +
1267 +/* Valid for AR5312 and AR2312 */
1268 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1269 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1270 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1271 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1272 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1273 +
1274 +/* Valid for AR2313 */
1275 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1276 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1277 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1278 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1279 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1280 +
1281 +/* AR5312_ENABLE register bit field definitions */
1282 +#define AR5312_ENABLE_WLAN0 0x0001
1283 +#define AR5312_ENABLE_ENET0 0x0002
1284 +#define AR5312_ENABLE_ENET1 0x0004
1285 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1286 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1287 +#define AR5312_ENABLE_WLAN1 \
1288 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1289 + AR5312_ENABLE_WLAN1_DMA)
1290 +
1291 +/* AR5312_REV register bit field definitions */
1292 +#define AR5312_REV_WMAC_MAJ 0xf000
1293 +#define AR5312_REV_WMAC_MAJ_S 12
1294 +#define AR5312_REV_WMAC_MIN 0x0f00
1295 +#define AR5312_REV_WMAC_MIN_S 8
1296 +#define AR5312_REV_MAJ 0x00f0
1297 +#define AR5312_REV_MAJ_S 4
1298 +#define AR5312_REV_MIN 0x000f
1299 +#define AR5312_REV_MIN_S 0
1300 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1301 +
1302 +/* Major revision numbers, bits 7..4 of Revision ID register */
1303 +#define AR5312_REV_MAJ_AR5312 0x4
1304 +#define AR5312_REV_MAJ_AR2313 0x5
1305 +
1306 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1307 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1308 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1309 +
1310 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1311 +#define AR5312_FLASHCTL0 0x0000
1312 +#define AR5312_FLASHCTL1 0x0004
1313 +#define AR5312_FLASHCTL2 0x0008
1314 +
1315 +/* AR5312_FLASHCTL register bit field definitions */
1316 +#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
1317 +#define AR5312_FLASHCTL_IDCY_S 0
1318 +#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1319 +#define AR5312_FLASHCTL_WST1_S 5
1320 +#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1321 +#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1322 +#define AR5312_FLASHCTL_WST2_S 11
1323 +#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
1324 +#define AR5312_FLASHCTL_AC_S 16
1325 +#define AR5312_FLASHCTL_AC_128K 0x00000000
1326 +#define AR5312_FLASHCTL_AC_256K 0x00010000
1327 +#define AR5312_FLASHCTL_AC_512K 0x00020000
1328 +#define AR5312_FLASHCTL_AC_1M 0x00030000
1329 +#define AR5312_FLASHCTL_AC_2M 0x00040000
1330 +#define AR5312_FLASHCTL_AC_4M 0x00050000
1331 +#define AR5312_FLASHCTL_AC_8M 0x00060000
1332 +#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1333 +#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1334 +#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
1335 +#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
1336 +#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
1337 +#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
1338 +#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
1339 +#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
1340 +#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
1341 +#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
1342 +#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
1343 +#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
1344 +#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
1345 +
1346 +/* ARM SDRAM Controller -- just enough to determine memory size */
1347 +#define AR5312_MEM_CFG1 0x0004
1348 +
1349 +#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
1350 +#define AR5312_MEM_CFG1_AC0_S 8
1351 +#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
1352 +#define AR5312_MEM_CFG1_AC1_S 12
1353 +
1354 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1355 --- /dev/null
1356 +++ b/arch/mips/ath25/ar5312.c
1357 @@ -0,0 +1,492 @@
1358 +/*
1359 + * This file is subject to the terms and conditions of the GNU General Public
1360 + * License. See the file "COPYING" in the main directory of this archive
1361 + * for more details.
1362 + *
1363 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1364 + * Copyright (C) 2006 FON Technology, SL.
1365 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1366 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1367 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1368 + */
1369 +
1370 +/*
1371 + * Platform devices for Atheros SoCs
1372 + */
1373 +
1374 +#include <generated/autoconf.h>
1375 +#include <linux/init.h>
1376 +#include <linux/module.h>
1377 +#include <linux/types.h>
1378 +#include <linux/string.h>
1379 +#include <linux/mtd/physmap.h>
1380 +#include <linux/platform_device.h>
1381 +#include <linux/kernel.h>
1382 +#include <linux/bitops.h>
1383 +#include <linux/irqdomain.h>
1384 +#include <linux/reboot.h>
1385 +#include <linux/leds.h>
1386 +#include <linux/gpio.h>
1387 +#include <asm/bootinfo.h>
1388 +#include <asm/reboot.h>
1389 +#include <asm/time.h>
1390 +#include <linux/irq.h>
1391 +#include <linux/io.h>
1392 +
1393 +#include <ath25_platform.h>
1394 +
1395 +#include "devices.h"
1396 +#include "ar5312.h"
1397 +#include "ar5312_regs.h"
1398 +
1399 +static void __iomem *ar5312_rst_base;
1400 +static struct irq_domain *ar5312_misc_irq_domain;
1401 +
1402 +static inline u32 ar5312_rst_reg_read(u32 reg)
1403 +{
1404 + return __raw_readl(ar5312_rst_base + reg);
1405 +}
1406 +
1407 +static inline void ar5312_rst_reg_write(u32 reg, u32 val)
1408 +{
1409 + __raw_writel(val, ar5312_rst_base + reg);
1410 +}
1411 +
1412 +static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
1413 +{
1414 + u32 ret = ar5312_rst_reg_read(reg);
1415 +
1416 + ret &= ~mask;
1417 + ret |= val;
1418 + ar5312_rst_reg_write(reg, ret);
1419 +}
1420 +
1421 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1422 +{
1423 + u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
1424 + u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
1425 + u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
1426 + u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
1427 +
1428 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1429 + proc_addr, proc1, dma_addr, dma1);
1430 +
1431 + machine_restart("AHB error"); /* Catastrophic failure */
1432 + return IRQ_HANDLED;
1433 +}
1434 +
1435 +static struct irqaction ar5312_ahb_err_interrupt = {
1436 + .handler = ar5312_ahb_err_handler,
1437 + .name = "ar5312-ahb-error",
1438 +};
1439 +
1440 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1441 +{
1442 + u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
1443 + ar5312_rst_reg_read(AR5312_IMR);
1444 + unsigned nr, misc_irq = 0;
1445 +
1446 + if (pending) {
1447 + struct irq_domain *domain = irq_get_handler_data(irq);
1448 +
1449 + nr = __ffs(pending);
1450 + misc_irq = irq_find_mapping(domain, nr);
1451 + }
1452 +
1453 + if (misc_irq) {
1454 + generic_handle_irq(misc_irq);
1455 + if (nr == AR5312_MISC_IRQ_TIMER)
1456 + ar5312_rst_reg_read(AR5312_TIMER);
1457 + } else {
1458 + spurious_interrupt();
1459 + }
1460 +}
1461 +
1462 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1463 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1464 +{
1465 + ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
1466 +}
1467 +
1468 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1469 +static void ar5312_misc_irq_mask(struct irq_data *d)
1470 +{
1471 + ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
1472 + ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
1473 +}
1474 +
1475 +static struct irq_chip ar5312_misc_irq_chip = {
1476 + .name = "ar5312-misc",
1477 + .irq_unmask = ar5312_misc_irq_unmask,
1478 + .irq_mask = ar5312_misc_irq_mask,
1479 +};
1480 +
1481 +static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
1482 + irq_hw_number_t hw)
1483 +{
1484 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
1485 + return 0;
1486 +}
1487 +
1488 +static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
1489 + .map = ar5312_misc_irq_map,
1490 +};
1491 +
1492 +static void ar5312_irq_dispatch(void)
1493 +{
1494 + u32 pending = read_c0_status() & read_c0_cause();
1495 +
1496 + if (pending & CAUSEF_IP2)
1497 + do_IRQ(AR5312_IRQ_WLAN0);
1498 + else if (pending & CAUSEF_IP3)
1499 + do_IRQ(AR5312_IRQ_ENET0);
1500 + else if (pending & CAUSEF_IP4)
1501 + do_IRQ(AR5312_IRQ_ENET1);
1502 + else if (pending & CAUSEF_IP5)
1503 + do_IRQ(AR5312_IRQ_WLAN1);
1504 + else if (pending & CAUSEF_IP6)
1505 + do_IRQ(AR5312_IRQ_MISC);
1506 + else if (pending & CAUSEF_IP7)
1507 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1508 + else
1509 + spurious_interrupt();
1510 +}
1511 +
1512 +void __init ar5312_arch_init_irq(void)
1513 +{
1514 + struct irq_domain *domain;
1515 + unsigned irq;
1516 +
1517 + ath25_irq_dispatch = ar5312_irq_dispatch;
1518 +
1519 + domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
1520 + &ar5312_misc_irq_domain_ops, NULL);
1521 + if (!domain)
1522 + panic("Failed to add IRQ domain");
1523 +
1524 + irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
1525 + setup_irq(irq, &ar5312_ahb_err_interrupt);
1526 +
1527 + irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
1528 + irq_set_handler_data(AR5312_IRQ_MISC, domain);
1529 +
1530 + ar5312_misc_irq_domain = domain;
1531 +}
1532 +
1533 +static void ar5312_device_reset_set(u32 mask)
1534 +{
1535 + u32 val;
1536 +
1537 + val = ar5312_rst_reg_read(AR5312_RESET);
1538 + ar5312_rst_reg_write(AR5312_RESET, val | mask);
1539 +}
1540 +
1541 +static void ar5312_device_reset_clear(u32 mask)
1542 +{
1543 + u32 val;
1544 +
1545 + val = ar5312_rst_reg_read(AR5312_RESET);
1546 + ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
1547 +}
1548 +
1549 +static struct physmap_flash_data ar5312_flash_data = {
1550 + .width = 2,
1551 +};
1552 +
1553 +static struct resource ar5312_flash_resource = {
1554 + .start = AR5312_FLASH_BASE,
1555 + .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
1556 + .flags = IORESOURCE_MEM,
1557 +};
1558 +
1559 +static struct ar231x_eth ar5312_eth0_data = {
1560 + .reset_set = ar5312_device_reset_set,
1561 + .reset_clear = ar5312_device_reset_clear,
1562 + .reset_mac = AR5312_RESET_ENET0,
1563 + .reset_phy = AR5312_RESET_EPHY0,
1564 +};
1565 +
1566 +static struct ar231x_eth ar5312_eth1_data = {
1567 + .reset_set = ar5312_device_reset_set,
1568 + .reset_clear = ar5312_device_reset_clear,
1569 + .reset_mac = AR5312_RESET_ENET1,
1570 + .reset_phy = AR5312_RESET_EPHY1,
1571 +};
1572 +
1573 +static struct platform_device ar5312_physmap_flash = {
1574 + .name = "physmap-flash",
1575 + .id = 0,
1576 + .dev.platform_data = &ar5312_flash_data,
1577 + .resource = &ar5312_flash_resource,
1578 + .num_resources = 1,
1579 +};
1580 +
1581 +#ifdef CONFIG_LEDS_GPIO
1582 +static struct gpio_led ar5312_leds[] = {
1583 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1584 +};
1585 +
1586 +static const struct gpio_led_platform_data ar5312_led_data = {
1587 + .num_leds = ARRAY_SIZE(ar5312_leds),
1588 + .leds = (void *)ar5312_leds,
1589 +};
1590 +
1591 +static struct platform_device ar5312_gpio_leds = {
1592 + .name = "leds-gpio",
1593 + .id = -1,
1594 + .dev.platform_data = (void *)&ar5312_led_data,
1595 +};
1596 +#endif
1597 +
1598 +static void __init ar5312_flash_init(void)
1599 +{
1600 + void __iomem *flashctl_base;
1601 + u32 ctl;
1602 +
1603 + flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
1604 + AR5312_FLASHCTL_SIZE);
1605 +
1606 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
1607 + ctl &= AR5312_FLASHCTL_MW;
1608 +
1609 + /* fixup flash width */
1610 + switch (ctl) {
1611 + case AR5312_FLASHCTL_MW16:
1612 + ar5312_flash_data.width = 2;
1613 + break;
1614 + case AR5312_FLASHCTL_MW8:
1615 + default:
1616 + ar5312_flash_data.width = 1;
1617 + break;
1618 + }
1619 +
1620 + /*
1621 + * Configure flash bank 0.
1622 + * Assume 8M window size. Flash will be aliased if it's smaller
1623 + */
1624 + ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
1625 + ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
1626 + ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
1627 + ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
1628 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
1629 +
1630 + /* Disable other flash banks */
1631 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
1632 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1633 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
1634 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
1635 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1636 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
1637 +
1638 + iounmap(flashctl_base);
1639 +}
1640 +
1641 +void __init ar5312_init_devices(void)
1642 +{
1643 + struct ath25_boarddata *config;
1644 + u8 *c;
1645 +
1646 + ar5312_flash_init();
1647 +
1648 + /* Locate board/radio config data */
1649 + ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
1650 + config = ath25_board.config;
1651 +
1652 + /* AR2313 has CPU minor rev. 10 */
1653 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1654 + ath25_soc = ATH25_SOC_AR2313;
1655 +
1656 + /* AR2312 shares the same Silicon ID as AR5312 */
1657 + else if (config->flags & BD_ISCASPER)
1658 + ath25_soc = ATH25_SOC_AR2312;
1659 +
1660 + /* Everything else is probably AR5312 or compatible */
1661 + else
1662 + ath25_soc = ATH25_SOC_AR5312;
1663 +
1664 + platform_device_register(&ar5312_physmap_flash);
1665 +
1666 +#ifdef CONFIG_LEDS_GPIO
1667 + ar5312_leds[0].gpio = config->sys_led_gpio;
1668 + platform_device_register(&ar5312_gpio_leds);
1669 +#endif
1670 +
1671 + /* Fix up MAC addresses if necessary */
1672 + if (is_broadcast_ether_addr(config->enet0_mac))
1673 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1674 +
1675 + /* If ENET0 and ENET1 have the same mac address,
1676 + * increment the one from ENET1 */
1677 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1678 + c = config->enet1_mac + 5;
1679 + while ((c >= config->enet1_mac) && !(++(*c)))
1680 + c--;
1681 + }
1682 +
1683 + switch (ath25_soc) {
1684 + case ATH25_SOC_AR5312:
1685 + ar5312_eth0_data.macaddr = config->enet0_mac;
1686 + ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
1687 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
1688 + &ar5312_eth0_data);
1689 +
1690 + ar5312_eth1_data.macaddr = config->enet1_mac;
1691 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
1692 + AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
1693 + &ar5312_eth1_data);
1694 +
1695 + if (!ath25_board.radio)
1696 + return;
1697 +
1698 + if (!(config->flags & BD_WLAN0))
1699 + break;
1700 +
1701 + ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1702 + break;
1703 + /*
1704 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1705 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1706 + */
1707 + case ATH25_SOC_AR2312:
1708 + case ATH25_SOC_AR2313:
1709 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1710 + ar5312_eth1_data.macaddr = config->enet0_mac;
1711 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
1712 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
1713 + &ar5312_eth1_data);
1714 +
1715 + if (!ath25_board.radio)
1716 + return;
1717 + break;
1718 + default:
1719 + break;
1720 + }
1721 +
1722 + if (config->flags & BD_WLAN1)
1723 + ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
1724 +}
1725 +
1726 +static void ar5312_restart(char *command)
1727 +{
1728 + /* reset the system */
1729 + local_irq_disable();
1730 + while (1)
1731 + ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
1732 +}
1733 +
1734 +/*
1735 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1736 + * to determine the predevisor value.
1737 + */
1738 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1739 +
1740 +static unsigned __init ar5312_cpu_frequency(void)
1741 +{
1742 + unsigned int scratch;
1743 + unsigned int predivide_mask, predivide_shift;
1744 + unsigned int multiplier_mask, multiplier_shift;
1745 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1746 + unsigned int doubler_mask;
1747 + u16 devid;
1748 +
1749 + /* Trust the bootrom's idea of cpu frequency. */
1750 + scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
1751 + if (scratch)
1752 + return scratch;
1753 +
1754 + devid = ar5312_rst_reg_read(AR5312_REV);
1755 + devid &= AR5312_REV_MAJ;
1756 + devid >>= AR5312_REV_MAJ_S;
1757 + if (devid == AR5312_REV_MAJ_AR2313) {
1758 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1759 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1760 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1761 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1762 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1763 + } else { /* AR5312 and AR2312 */
1764 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1765 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1766 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1767 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1768 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1769 + }
1770 +
1771 + /*
1772 + * Clocking is derived from a fixed 40MHz input clock.
1773 + *
1774 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1775 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1776 + * flash, Timer, Watchdog Timer)
1777 + *
1778 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1779 + *
1780 + * So, for example, with a PLL multiplier of 5, we have
1781 + *
1782 + * cpu_freq = 200MHz
1783 + * sys_freq = 50MHz
1784 + * cnt_freq = 100MHz
1785 + *
1786 + * We compute the CPU frequency, based on PLL settings.
1787 + */
1788 +
1789 + clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
1790 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1791 + predivisor = clockctl1_predivide_table[predivide_select];
1792 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1793 +
1794 + if (clock_ctl1 & doubler_mask)
1795 + multiplier = multiplier << 1;
1796 +
1797 + return (40000000 / predivisor) * multiplier;
1798 +}
1799 +
1800 +static inline unsigned ar5312_sys_frequency(void)
1801 +{
1802 + return ar5312_cpu_frequency() / 4;
1803 +}
1804 +
1805 +void __init ar5312_plat_time_init(void)
1806 +{
1807 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1808 +}
1809 +
1810 +void __init ar5312_plat_mem_setup(void)
1811 +{
1812 + void __iomem *sdram_base;
1813 + u32 memsize, memcfg, bank0_ac, bank1_ac;
1814 + u32 devid;
1815 +
1816 + /* Detect memory size */
1817 + sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
1818 + AR5312_SDRAMCTL_SIZE);
1819 + memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
1820 + bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
1821 + bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
1822 + memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
1823 + (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
1824 + memsize <<= 20;
1825 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1826 + iounmap(sdram_base);
1827 +
1828 + ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
1829 +
1830 + devid = ar5312_rst_reg_read(AR5312_REV);
1831 + devid >>= AR5312_REV_WMAC_MIN_S;
1832 + devid &= AR5312_REV_CHIP;
1833 + ath25_board.devid = (u16)devid;
1834 +
1835 + /* Clear any lingering AHB errors */
1836 + ar5312_rst_reg_read(AR5312_PROCADDR);
1837 + ar5312_rst_reg_read(AR5312_DMAADDR);
1838 + ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
1839 +
1840 + _machine_restart = ar5312_restart;
1841 +}
1842 +
1843 +void __init ar5312_arch_init(void)
1844 +{
1845 + unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
1846 + AR5312_MISC_IRQ_UART0);
1847 +
1848 + ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
1849 +}
1850 --- /dev/null
1851 +++ b/arch/mips/ath25/ar2315.c
1852 @@ -0,0 +1,438 @@
1853 +/*
1854 + * This file is subject to the terms and conditions of the GNU General Public
1855 + * License. See the file "COPYING" in the main directory of this archive
1856 + * for more details.
1857 + *
1858 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1859 + * Copyright (C) 2006 FON Technology, SL.
1860 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1861 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1862 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1863 + */
1864 +
1865 +/*
1866 + * Platform devices for Atheros SoCs
1867 + */
1868 +
1869 +#include <generated/autoconf.h>
1870 +#include <linux/init.h>
1871 +#include <linux/module.h>
1872 +#include <linux/types.h>
1873 +#include <linux/string.h>
1874 +#include <linux/platform_device.h>
1875 +#include <linux/kernel.h>
1876 +#include <linux/bitops.h>
1877 +#include <linux/irqdomain.h>
1878 +#include <linux/reboot.h>
1879 +#include <linux/delay.h>
1880 +#include <linux/leds.h>
1881 +#include <linux/gpio.h>
1882 +#include <asm/bootinfo.h>
1883 +#include <asm/reboot.h>
1884 +#include <asm/time.h>
1885 +#include <linux/irq.h>
1886 +#include <linux/io.h>
1887 +
1888 +#include <ath25_platform.h>
1889 +
1890 +#include "devices.h"
1891 +#include "ar2315.h"
1892 +#include "ar2315_regs.h"
1893 +
1894 +static void __iomem *ar2315_rst_base;
1895 +static struct irq_domain *ar2315_misc_irq_domain;
1896 +
1897 +static inline u32 ar2315_rst_reg_read(u32 reg)
1898 +{
1899 + return __raw_readl(ar2315_rst_base + reg);
1900 +}
1901 +
1902 +static inline void ar2315_rst_reg_write(u32 reg, u32 val)
1903 +{
1904 + __raw_writel(val, ar2315_rst_base + reg);
1905 +}
1906 +
1907 +static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
1908 +{
1909 + u32 ret = ar2315_rst_reg_read(reg);
1910 +
1911 + ret &= ~mask;
1912 + ret |= val;
1913 + ar2315_rst_reg_write(reg, ret);
1914 +}
1915 +
1916 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1917 +{
1918 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
1919 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1920 +
1921 + pr_emerg("AHB fatal error\n");
1922 + machine_restart("AHB error"); /* Catastrophic failure */
1923 +
1924 + return IRQ_HANDLED;
1925 +}
1926 +
1927 +static struct irqaction ar2315_ahb_err_interrupt = {
1928 + .handler = ar2315_ahb_err_handler,
1929 + .name = "ar2315-ahb-error",
1930 +};
1931 +
1932 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1933 +{
1934 + u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
1935 + ar2315_rst_reg_read(AR2315_IMR);
1936 + unsigned nr, misc_irq = 0;
1937 +
1938 + if (pending) {
1939 + struct irq_domain *domain = irq_get_handler_data(irq);
1940 +
1941 + nr = __ffs(pending);
1942 + misc_irq = irq_find_mapping(domain, nr);
1943 + }
1944 +
1945 + if (misc_irq) {
1946 + if (nr == AR2315_MISC_IRQ_GPIO)
1947 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
1948 + else if (nr == AR2315_MISC_IRQ_WATCHDOG)
1949 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
1950 + generic_handle_irq(misc_irq);
1951 + } else {
1952 + spurious_interrupt();
1953 + }
1954 +}
1955 +
1956 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1957 +{
1958 + ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
1959 +}
1960 +
1961 +static void ar2315_misc_irq_mask(struct irq_data *d)
1962 +{
1963 + ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
1964 +}
1965 +
1966 +static struct irq_chip ar2315_misc_irq_chip = {
1967 + .name = "ar2315-misc",
1968 + .irq_unmask = ar2315_misc_irq_unmask,
1969 + .irq_mask = ar2315_misc_irq_mask,
1970 +};
1971 +
1972 +static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
1973 + irq_hw_number_t hw)
1974 +{
1975 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
1976 + return 0;
1977 +}
1978 +
1979 +static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
1980 + .map = ar2315_misc_irq_map,
1981 +};
1982 +
1983 +/*
1984 + * Called when an interrupt is received, this function
1985 + * determines exactly which interrupt it was, and it
1986 + * invokes the appropriate handler.
1987 + *
1988 + * Implicitly, we also define interrupt priority by
1989 + * choosing which to dispatch first.
1990 + */
1991 +static void ar2315_irq_dispatch(void)
1992 +{
1993 + u32 pending = read_c0_status() & read_c0_cause();
1994 +
1995 + if (pending & CAUSEF_IP3)
1996 + do_IRQ(AR2315_IRQ_WLAN0);
1997 + else if (pending & CAUSEF_IP4)
1998 + do_IRQ(AR2315_IRQ_ENET0);
1999 + else if (pending & CAUSEF_IP2)
2000 + do_IRQ(AR2315_IRQ_MISC);
2001 + else if (pending & CAUSEF_IP7)
2002 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
2003 + else
2004 + spurious_interrupt();
2005 +}
2006 +
2007 +void __init ar2315_arch_init_irq(void)
2008 +{
2009 + struct irq_domain *domain;
2010 + unsigned irq;
2011 +
2012 + ath25_irq_dispatch = ar2315_irq_dispatch;
2013 +
2014 + domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
2015 + &ar2315_misc_irq_domain_ops, NULL);
2016 + if (!domain)
2017 + panic("Failed to add IRQ domain");
2018 +
2019 + irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
2020 + setup_irq(irq, &ar2315_ahb_err_interrupt);
2021 +
2022 + irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
2023 + irq_set_handler_data(AR2315_IRQ_MISC, domain);
2024 +
2025 + ar2315_misc_irq_domain = domain;
2026 +}
2027 +
2028 +static void ar2315_device_reset_set(u32 mask)
2029 +{
2030 + u32 val;
2031 +
2032 + val = ar2315_rst_reg_read(AR2315_RESET);
2033 + ar2315_rst_reg_write(AR2315_RESET, val | mask);
2034 +}
2035 +
2036 +static void ar2315_device_reset_clear(u32 mask)
2037 +{
2038 + u32 val;
2039 +
2040 + val = ar2315_rst_reg_read(AR2315_RESET);
2041 + ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
2042 +}
2043 +
2044 +static struct ar231x_eth ar2315_eth_data = {
2045 + .reset_set = ar2315_device_reset_set,
2046 + .reset_clear = ar2315_device_reset_clear,
2047 + .reset_mac = AR2315_RESET_ENET0,
2048 + .reset_phy = AR2315_RESET_EPHY0,
2049 +};
2050 +
2051 +static struct resource ar2315_spiflash_res[] = {
2052 + {
2053 + .name = "spiflash_read",
2054 + .flags = IORESOURCE_MEM,
2055 + .start = AR2315_SPI_READ_BASE,
2056 + .end = AR2315_SPI_READ_BASE + AR2315_SPI_READ_SIZE - 1,
2057 + },
2058 + {
2059 + .name = "spiflash_mmr",
2060 + .flags = IORESOURCE_MEM,
2061 + .start = AR2315_SPI_MMR_BASE,
2062 + .end = AR2315_SPI_MMR_BASE + AR2315_SPI_MMR_SIZE - 1,
2063 + },
2064 +};
2065 +
2066 +static struct platform_device ar2315_spiflash = {
2067 + .id = 0,
2068 + .name = "ar2315-spiflash",
2069 + .resource = ar2315_spiflash_res,
2070 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2071 +};
2072 +
2073 +static struct resource ar2315_wdt_res[] = {
2074 + {
2075 + .flags = IORESOURCE_MEM,
2076 + .start = AR2315_RST_BASE + AR2315_WDT_TIMER,
2077 + .end = AR2315_RST_BASE + AR2315_WDT_TIMER + 8 - 1,
2078 + },
2079 + {
2080 + .flags = IORESOURCE_IRQ,
2081 + }
2082 +};
2083 +
2084 +static struct platform_device ar2315_wdt = {
2085 + .id = 0,
2086 + .name = "ar2315-wdt",
2087 + .resource = ar2315_wdt_res,
2088 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2089 +};
2090 +
2091 +#ifdef CONFIG_LEDS_GPIO
2092 +static struct gpio_led ar2315_leds[6];
2093 +static struct gpio_led_platform_data ar2315_led_data = {
2094 + .leds = (void *)ar2315_leds,
2095 +};
2096 +
2097 +static struct platform_device ar2315_gpio_leds = {
2098 + .name = "leds-gpio",
2099 + .id = -1,
2100 + .dev = {
2101 + .platform_data = (void *)&ar2315_led_data,
2102 + }
2103 +};
2104 +
2105 +static void __init ar2315_init_gpio_leds(void)
2106 +{
2107 + static char led_names[6][6];
2108 + int i, led = 0;
2109 +
2110 + ar2315_led_data.num_leds = 0;
2111 + for (i = 1; i < 8; i++) {
2112 + if ((i == AR2315_RESET_GPIO) ||
2113 + (i == ath25_board.config->reset_config_gpio))
2114 + continue;
2115 +
2116 + if (i == ath25_board.config->sys_led_gpio)
2117 + strcpy(led_names[led], "wlan");
2118 + else
2119 + sprintf(led_names[led], "gpio%d", i);
2120 +
2121 + ar2315_leds[led].name = led_names[led];
2122 + ar2315_leds[led].gpio = i;
2123 + ar2315_leds[led].active_low = 0;
2124 + led++;
2125 + }
2126 + ar2315_led_data.num_leds = led;
2127 + platform_device_register(&ar2315_gpio_leds);
2128 +}
2129 +#else
2130 +static inline void ar2315_init_gpio_leds(void)
2131 +{
2132 +}
2133 +#endif
2134 +
2135 +void __init ar2315_init_devices(void)
2136 +{
2137 + /* Find board configuration */
2138 + ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
2139 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
2140 +
2141 + ar2315_init_gpio_leds();
2142 +
2143 + ar2315_wdt_res[1].start = irq_create_mapping(ar2315_misc_irq_domain,
2144 + AR2315_MISC_IRQ_WATCHDOG);
2145 + ar2315_wdt_res[1].end = ar2315_wdt_res[1].start;
2146 + platform_device_register(&ar2315_wdt);
2147 +
2148 + platform_device_register(&ar2315_spiflash);
2149 +
2150 + ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
2151 + AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
2152 + &ar2315_eth_data);
2153 +
2154 + ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
2155 +}
2156 +
2157 +static void ar2315_restart(char *command)
2158 +{
2159 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2160 +
2161 + local_irq_disable();
2162 +
2163 + /* try reset the system via reset control */
2164 + ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2165 +
2166 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2167 + * a workaround. Give it some time to attempt a gpio based hardware
2168 + * reset (atheros reference design workaround) */
2169 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2170 + mdelay(100);
2171 +
2172 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2173 + * workaround. Attempt to jump to the mips reset location -
2174 + * the boot loader itself might be able to recover the system */
2175 + mips_reset_vec();
2176 +}
2177 +
2178 +/*
2179 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2180 + * to determine the predevisor value.
2181 + */
2182 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2183 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2184 +
2185 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
2186 +{
2187 + unsigned int pllc_ctrl, cpu_div;
2188 + unsigned int pllc_out, refdiv, fdiv, divby2;
2189 + unsigned int clk_div;
2190 +
2191 + pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
2192 + refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
2193 + refdiv = clockctl1_predivide_table[refdiv];
2194 + fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
2195 + divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
2196 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2197 +
2198 + /* clkm input selected */
2199 + switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
2200 + case 0:
2201 + case 1:
2202 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
2203 + clk_div = pllc_divide_table[clk_div];
2204 + break;
2205 + case 2:
2206 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
2207 + clk_div = pllc_divide_table[clk_div];
2208 + break;
2209 + default:
2210 + pllc_out = 40000000;
2211 + clk_div = 1;
2212 + break;
2213 + }
2214 +
2215 + cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
2216 + cpu_div = cpu_div * 2 ?: 1;
2217 +
2218 + return pllc_out / (clk_div * cpu_div);
2219 +}
2220 +
2221 +static inline unsigned ar2315_cpu_frequency(void)
2222 +{
2223 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
2224 +}
2225 +
2226 +static inline unsigned ar2315_apb_frequency(void)
2227 +{
2228 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
2229 +}
2230 +
2231 +void __init ar2315_plat_time_init(void)
2232 +{
2233 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2234 +}
2235 +
2236 +void __init ar2315_plat_mem_setup(void)
2237 +{
2238 + void __iomem *sdram_base;
2239 + u32 memsize, memcfg;
2240 + u32 devid;
2241 + u32 config;
2242 +
2243 + sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
2244 + AR2315_SDRAMCTL_SIZE);
2245 + memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
2246 + memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
2247 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
2248 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
2249 + memsize <<= 3;
2250 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2251 + iounmap(sdram_base);
2252 +
2253 + ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
2254 +
2255 + /* Detect the hardware based on the device ID */
2256 + devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
2257 + switch (devid) {
2258 + case 0x91: /* Need to check */
2259 + ath25_soc = ATH25_SOC_AR2318;
2260 + break;
2261 + case 0x90:
2262 + ath25_soc = ATH25_SOC_AR2317;
2263 + break;
2264 + case 0x87:
2265 + ath25_soc = ATH25_SOC_AR2316;
2266 + break;
2267 + case 0x86:
2268 + default:
2269 + ath25_soc = ATH25_SOC_AR2315;
2270 + break;
2271 + }
2272 + ath25_board.devid = devid;
2273 +
2274 + /* Clear any lingering AHB errors */
2275 + config = read_c0_config();
2276 + write_c0_config(config & ~0x3);
2277 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
2278 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
2279 + ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
2280 +
2281 + _machine_restart = ar2315_restart;
2282 +}
2283 +
2284 +void __init ar2315_arch_init(void)
2285 +{
2286 + unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
2287 + AR2315_MISC_IRQ_UART0);
2288 +
2289 + ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
2290 +}
2291 --- /dev/null
2292 +++ b/arch/mips/ath25/ar2315.h
2293 @@ -0,0 +1,36 @@
2294 +#ifndef __AR2315_H
2295 +#define __AR2315_H
2296 +
2297 +#ifdef CONFIG_SOC_AR2315
2298 +
2299 +void ar2315_arch_init_irq(void);
2300 +void ar2315_init_devices(void);
2301 +void ar2315_plat_time_init(void);
2302 +void ar2315_plat_mem_setup(void);
2303 +void ar2315_arch_init(void);
2304 +
2305 +#else
2306 +
2307 +static inline void ar2315_arch_init_irq(void)
2308 +{
2309 +}
2310 +
2311 +static inline void ar2315_init_devices(void)
2312 +{
2313 +}
2314 +
2315 +static inline void ar2315_plat_time_init(void)
2316 +{
2317 +}
2318 +
2319 +static inline void ar2315_plat_mem_setup(void)
2320 +{
2321 +}
2322 +
2323 +static inline void ar2315_arch_init(void)
2324 +{
2325 +}
2326 +
2327 +#endif
2328 +
2329 +#endif
2330 --- /dev/null
2331 +++ b/arch/mips/ath25/ar5312.h
2332 @@ -0,0 +1,36 @@
2333 +#ifndef __AR5312_H
2334 +#define __AR5312_H
2335 +
2336 +#ifdef CONFIG_SOC_AR5312
2337 +
2338 +void ar5312_arch_init_irq(void);
2339 +void ar5312_init_devices(void);
2340 +void ar5312_plat_time_init(void);
2341 +void ar5312_plat_mem_setup(void);
2342 +void ar5312_arch_init(void);
2343 +
2344 +#else
2345 +
2346 +static inline void ar5312_arch_init_irq(void)
2347 +{
2348 +}
2349 +
2350 +static inline void ar5312_init_devices(void)
2351 +{
2352 +}
2353 +
2354 +static inline void ar5312_plat_time_init(void)
2355 +{
2356 +}
2357 +
2358 +static inline void ar5312_plat_mem_setup(void)
2359 +{
2360 +}
2361 +
2362 +static inline void ar5312_arch_init(void)
2363 +{
2364 +}
2365 +
2366 +#endif
2367 +
2368 +#endif
2369 --- /dev/null
2370 +++ b/arch/mips/ath25/devices.h
2371 @@ -0,0 +1,45 @@
2372 +#ifndef __ATH25_DEVICES_H
2373 +#define __ATH25_DEVICES_H
2374 +
2375 +#define AR231X_GPIO_IRQ_BASE 0x30
2376 +
2377 +#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
2378 +
2379 +#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
2380 +
2381 +enum ath25_soc_type {
2382 + /* handled by ar5312.c */
2383 + ATH25_SOC_AR2312,
2384 + ATH25_SOC_AR2313,
2385 + ATH25_SOC_AR5312,
2386 +
2387 + /* handled by ar2315.c */
2388 + ATH25_SOC_AR2315,
2389 + ATH25_SOC_AR2316,
2390 + ATH25_SOC_AR2317,
2391 + ATH25_SOC_AR2318,
2392 +
2393 + ATH25_SOC_UNKNOWN
2394 +};
2395 +
2396 +extern enum ath25_soc_type ath25_soc;
2397 +extern struct ar231x_board_config ath25_board;
2398 +extern void (*ath25_irq_dispatch)(void);
2399 +
2400 +int ath25_find_config(phys_addr_t offset, unsigned long size);
2401 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2402 + int irq, void *pdata);
2403 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2404 +int ath25_add_wmac(int nr, u32 base, int irq);
2405 +
2406 +static inline bool is_ar2315(void)
2407 +{
2408 + return (current_cpu_data.cputype == CPU_4KEC);
2409 +}
2410 +
2411 +static inline bool is_ar5312(void)
2412 +{
2413 + return !is_ar2315();
2414 +}
2415 +
2416 +#endif
2417 --- /dev/null
2418 +++ b/arch/mips/ath25/devices.c
2419 @@ -0,0 +1,191 @@
2420 +#include <linux/kernel.h>
2421 +#include <linux/init.h>
2422 +#include <linux/serial.h>
2423 +#include <linux/serial_core.h>
2424 +#include <linux/serial_8250.h>
2425 +#include <linux/platform_device.h>
2426 +#include <asm/bootinfo.h>
2427 +
2428 +#include <ath25_platform.h>
2429 +#include "devices.h"
2430 +#include "ar5312.h"
2431 +#include "ar2315.h"
2432 +
2433 +struct ar231x_board_config ath25_board;
2434 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2435 +
2436 +static struct resource ath25_eth0_res[] = {
2437 + {
2438 + .name = "eth0_membase",
2439 + .flags = IORESOURCE_MEM,
2440 + },
2441 + {
2442 + .name = "eth0_mii",
2443 + .flags = IORESOURCE_MEM,
2444 + },
2445 + {
2446 + .name = "eth0_irq",
2447 + .flags = IORESOURCE_IRQ,
2448 + }
2449 +};
2450 +
2451 +static struct resource ath25_eth1_res[] = {
2452 + {
2453 + .name = "eth1_membase",
2454 + .flags = IORESOURCE_MEM,
2455 + },
2456 + {
2457 + .name = "eth1_mii",
2458 + .flags = IORESOURCE_MEM,
2459 + },
2460 + {
2461 + .name = "eth1_irq",
2462 + .flags = IORESOURCE_IRQ,
2463 + }
2464 +};
2465 +
2466 +static struct platform_device ath25_eth[] = {
2467 + {
2468 + .id = 0,
2469 + .name = "ar231x-eth",
2470 + .resource = ath25_eth0_res,
2471 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
2472 + },
2473 + {
2474 + .id = 1,
2475 + .name = "ar231x-eth",
2476 + .resource = ath25_eth1_res,
2477 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
2478 + }
2479 +};
2480 +
2481 +static struct resource ath25_wmac0_res[] = {
2482 + {
2483 + .name = "wmac0_membase",
2484 + .flags = IORESOURCE_MEM,
2485 + },
2486 + {
2487 + .name = "wmac0_irq",
2488 + .flags = IORESOURCE_IRQ,
2489 + }
2490 +};
2491 +
2492 +static struct resource ath25_wmac1_res[] = {
2493 + {
2494 + .name = "wmac1_membase",
2495 + .flags = IORESOURCE_MEM,
2496 + },
2497 + {
2498 + .name = "wmac1_irq",
2499 + .flags = IORESOURCE_IRQ,
2500 + }
2501 +};
2502 +
2503 +static struct platform_device ath25_wmac[] = {
2504 + {
2505 + .id = 0,
2506 + .name = "ar231x-wmac",
2507 + .resource = ath25_wmac0_res,
2508 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2509 + .dev.platform_data = &ath25_board,
2510 + },
2511 + {
2512 + .id = 1,
2513 + .name = "ar231x-wmac",
2514 + .resource = ath25_wmac1_res,
2515 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2516 + .dev.platform_data = &ath25_board,
2517 + },
2518 +};
2519 +
2520 +static const char * const soc_type_strings[] = {
2521 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2522 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2523 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2524 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2525 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2526 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2527 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2528 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2529 +};
2530 +
2531 +const char *get_system_type(void)
2532 +{
2533 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2534 + !soc_type_strings[ath25_soc])
2535 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2536 + return soc_type_strings[ath25_soc];
2537 +}
2538 +
2539 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
2540 + u32 mii_base, int irq, void *pdata)
2541 +{
2542 + struct resource *res;
2543 +
2544 + ath25_eth[nr].dev.platform_data = pdata;
2545 + res = &ath25_eth[nr].resource[0];
2546 + res->start = base;
2547 + res->end = base + 0x2000 - 1;
2548 + res++;
2549 + res->name = mii_name;
2550 + res->start = mii_base;
2551 + res->end = mii_base + 8 - 1;
2552 + res++;
2553 + res->start = irq;
2554 + res->end = irq;
2555 + return platform_device_register(&ath25_eth[nr]);
2556 +}
2557 +
2558 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2559 +{
2560 + struct uart_port s;
2561 +
2562 + memset(&s, 0, sizeof(s));
2563 +
2564 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2565 + s.iotype = UPIO_MEM32;
2566 + s.irq = irq;
2567 + s.regshift = 2;
2568 + s.mapbase = mapbase;
2569 + s.uartclk = uartclk;
2570 +
2571 + early_serial_setup(&s);
2572 +}
2573 +
2574 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2575 +{
2576 + struct resource *res;
2577 +
2578 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2579 + res = &ath25_wmac[nr].resource[0];
2580 + res->start = base;
2581 + res->end = base + 0x10000 - 1;
2582 + res++;
2583 + res->start = irq;
2584 + res->end = irq;
2585 + return platform_device_register(&ath25_wmac[nr]);
2586 +}
2587 +
2588 +static int __init ath25_register_devices(void)
2589 +{
2590 + if (is_ar5312())
2591 + ar5312_init_devices();
2592 + else
2593 + ar2315_init_devices();
2594 +
2595 + return 0;
2596 +}
2597 +
2598 +device_initcall(ath25_register_devices);
2599 +
2600 +static int __init ath25_arch_init(void)
2601 +{
2602 + if (is_ar5312())
2603 + ar5312_arch_init();
2604 + else
2605 + ar2315_arch_init();
2606 +
2607 + return 0;
2608 +}
2609 +
2610 +arch_initcall(ath25_arch_init);
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