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f14de337da5e569abbcde6418f8c5ffaf53ec323
[openwrt/svn-archive/archive.git] / target / linux / bcm53xx / patches-3.14 / 001-mtd-spi-nor.patch
1 This patches adds the SPI-NOR device support code form kernel 3.17-rc1.
2 This patch does not contain any further code not in this mainline kernel.
3
4 --- a/drivers/mtd/Kconfig
5 +++ b/drivers/mtd/Kconfig
6 @@ -371,6 +371,8 @@ source "drivers/mtd/onenand/Kconfig"
7
8 source "drivers/mtd/lpddr/Kconfig"
9
10 +source "drivers/mtd/spi-nor/Kconfig"
11 +
12 source "drivers/mtd/ubi/Kconfig"
13
14 endif # MTD
15 --- a/drivers/mtd/Makefile
16 +++ b/drivers/mtd/Makefile
17 @@ -39,4 +39,5 @@ inftl-objs := inftlcore.o inftlmount.o
18
19 obj-y += chips/ lpddr/ maps/ devices/ nand/ onenand/ tests/
20
21 +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor/
22 obj-$(CONFIG_MTD_UBI) += ubi/
23 --- /dev/null
24 +++ b/drivers/mtd/spi-nor/fsl-quadspi.c
25 @@ -0,0 +1,1009 @@
26 +/*
27 + * Freescale QuadSPI driver.
28 + *
29 + * Copyright (C) 2013 Freescale Semiconductor, Inc.
30 + *
31 + * This program is free software; you can redistribute it and/or modify
32 + * it under the terms of the GNU General Public License as published by
33 + * the Free Software Foundation; either version 2 of the License, or
34 + * (at your option) any later version.
35 + */
36 +#include <linux/kernel.h>
37 +#include <linux/module.h>
38 +#include <linux/interrupt.h>
39 +#include <linux/errno.h>
40 +#include <linux/platform_device.h>
41 +#include <linux/sched.h>
42 +#include <linux/delay.h>
43 +#include <linux/io.h>
44 +#include <linux/clk.h>
45 +#include <linux/err.h>
46 +#include <linux/of.h>
47 +#include <linux/of_device.h>
48 +#include <linux/timer.h>
49 +#include <linux/jiffies.h>
50 +#include <linux/completion.h>
51 +#include <linux/mtd/mtd.h>
52 +#include <linux/mtd/partitions.h>
53 +#include <linux/mtd/spi-nor.h>
54 +
55 +/* The registers */
56 +#define QUADSPI_MCR 0x00
57 +#define QUADSPI_MCR_RESERVED_SHIFT 16
58 +#define QUADSPI_MCR_RESERVED_MASK (0xF << QUADSPI_MCR_RESERVED_SHIFT)
59 +#define QUADSPI_MCR_MDIS_SHIFT 14
60 +#define QUADSPI_MCR_MDIS_MASK (1 << QUADSPI_MCR_MDIS_SHIFT)
61 +#define QUADSPI_MCR_CLR_TXF_SHIFT 11
62 +#define QUADSPI_MCR_CLR_TXF_MASK (1 << QUADSPI_MCR_CLR_TXF_SHIFT)
63 +#define QUADSPI_MCR_CLR_RXF_SHIFT 10
64 +#define QUADSPI_MCR_CLR_RXF_MASK (1 << QUADSPI_MCR_CLR_RXF_SHIFT)
65 +#define QUADSPI_MCR_DDR_EN_SHIFT 7
66 +#define QUADSPI_MCR_DDR_EN_MASK (1 << QUADSPI_MCR_DDR_EN_SHIFT)
67 +#define QUADSPI_MCR_END_CFG_SHIFT 2
68 +#define QUADSPI_MCR_END_CFG_MASK (3 << QUADSPI_MCR_END_CFG_SHIFT)
69 +#define QUADSPI_MCR_SWRSTHD_SHIFT 1
70 +#define QUADSPI_MCR_SWRSTHD_MASK (1 << QUADSPI_MCR_SWRSTHD_SHIFT)
71 +#define QUADSPI_MCR_SWRSTSD_SHIFT 0
72 +#define QUADSPI_MCR_SWRSTSD_MASK (1 << QUADSPI_MCR_SWRSTSD_SHIFT)
73 +
74 +#define QUADSPI_IPCR 0x08
75 +#define QUADSPI_IPCR_SEQID_SHIFT 24
76 +#define QUADSPI_IPCR_SEQID_MASK (0xF << QUADSPI_IPCR_SEQID_SHIFT)
77 +
78 +#define QUADSPI_BUF0CR 0x10
79 +#define QUADSPI_BUF1CR 0x14
80 +#define QUADSPI_BUF2CR 0x18
81 +#define QUADSPI_BUFXCR_INVALID_MSTRID 0xe
82 +
83 +#define QUADSPI_BUF3CR 0x1c
84 +#define QUADSPI_BUF3CR_ALLMST_SHIFT 31
85 +#define QUADSPI_BUF3CR_ALLMST (1 << QUADSPI_BUF3CR_ALLMST_SHIFT)
86 +
87 +#define QUADSPI_BFGENCR 0x20
88 +#define QUADSPI_BFGENCR_PAR_EN_SHIFT 16
89 +#define QUADSPI_BFGENCR_PAR_EN_MASK (1 << (QUADSPI_BFGENCR_PAR_EN_SHIFT))
90 +#define QUADSPI_BFGENCR_SEQID_SHIFT 12
91 +#define QUADSPI_BFGENCR_SEQID_MASK (0xF << QUADSPI_BFGENCR_SEQID_SHIFT)
92 +
93 +#define QUADSPI_BUF0IND 0x30
94 +#define QUADSPI_BUF1IND 0x34
95 +#define QUADSPI_BUF2IND 0x38
96 +#define QUADSPI_SFAR 0x100
97 +
98 +#define QUADSPI_SMPR 0x108
99 +#define QUADSPI_SMPR_DDRSMP_SHIFT 16
100 +#define QUADSPI_SMPR_DDRSMP_MASK (7 << QUADSPI_SMPR_DDRSMP_SHIFT)
101 +#define QUADSPI_SMPR_FSDLY_SHIFT 6
102 +#define QUADSPI_SMPR_FSDLY_MASK (1 << QUADSPI_SMPR_FSDLY_SHIFT)
103 +#define QUADSPI_SMPR_FSPHS_SHIFT 5
104 +#define QUADSPI_SMPR_FSPHS_MASK (1 << QUADSPI_SMPR_FSPHS_SHIFT)
105 +#define QUADSPI_SMPR_HSENA_SHIFT 0
106 +#define QUADSPI_SMPR_HSENA_MASK (1 << QUADSPI_SMPR_HSENA_SHIFT)
107 +
108 +#define QUADSPI_RBSR 0x10c
109 +#define QUADSPI_RBSR_RDBFL_SHIFT 8
110 +#define QUADSPI_RBSR_RDBFL_MASK (0x3F << QUADSPI_RBSR_RDBFL_SHIFT)
111 +
112 +#define QUADSPI_RBCT 0x110
113 +#define QUADSPI_RBCT_WMRK_MASK 0x1F
114 +#define QUADSPI_RBCT_RXBRD_SHIFT 8
115 +#define QUADSPI_RBCT_RXBRD_USEIPS (0x1 << QUADSPI_RBCT_RXBRD_SHIFT)
116 +
117 +#define QUADSPI_TBSR 0x150
118 +#define QUADSPI_TBDR 0x154
119 +#define QUADSPI_SR 0x15c
120 +#define QUADSPI_SR_IP_ACC_SHIFT 1
121 +#define QUADSPI_SR_IP_ACC_MASK (0x1 << QUADSPI_SR_IP_ACC_SHIFT)
122 +#define QUADSPI_SR_AHB_ACC_SHIFT 2
123 +#define QUADSPI_SR_AHB_ACC_MASK (0x1 << QUADSPI_SR_AHB_ACC_SHIFT)
124 +
125 +#define QUADSPI_FR 0x160
126 +#define QUADSPI_FR_TFF_MASK 0x1
127 +
128 +#define QUADSPI_SFA1AD 0x180
129 +#define QUADSPI_SFA2AD 0x184
130 +#define QUADSPI_SFB1AD 0x188
131 +#define QUADSPI_SFB2AD 0x18c
132 +#define QUADSPI_RBDR 0x200
133 +
134 +#define QUADSPI_LUTKEY 0x300
135 +#define QUADSPI_LUTKEY_VALUE 0x5AF05AF0
136 +
137 +#define QUADSPI_LCKCR 0x304
138 +#define QUADSPI_LCKER_LOCK 0x1
139 +#define QUADSPI_LCKER_UNLOCK 0x2
140 +
141 +#define QUADSPI_RSER 0x164
142 +#define QUADSPI_RSER_TFIE (0x1 << 0)
143 +
144 +#define QUADSPI_LUT_BASE 0x310
145 +
146 +/*
147 + * The definition of the LUT register shows below:
148 + *
149 + * ---------------------------------------------------
150 + * | INSTR1 | PAD1 | OPRND1 | INSTR0 | PAD0 | OPRND0 |
151 + * ---------------------------------------------------
152 + */
153 +#define OPRND0_SHIFT 0
154 +#define PAD0_SHIFT 8
155 +#define INSTR0_SHIFT 10
156 +#define OPRND1_SHIFT 16
157 +
158 +/* Instruction set for the LUT register. */
159 +#define LUT_STOP 0
160 +#define LUT_CMD 1
161 +#define LUT_ADDR 2
162 +#define LUT_DUMMY 3
163 +#define LUT_MODE 4
164 +#define LUT_MODE2 5
165 +#define LUT_MODE4 6
166 +#define LUT_READ 7
167 +#define LUT_WRITE 8
168 +#define LUT_JMP_ON_CS 9
169 +#define LUT_ADDR_DDR 10
170 +#define LUT_MODE_DDR 11
171 +#define LUT_MODE2_DDR 12
172 +#define LUT_MODE4_DDR 13
173 +#define LUT_READ_DDR 14
174 +#define LUT_WRITE_DDR 15
175 +#define LUT_DATA_LEARN 16
176 +
177 +/*
178 + * The PAD definitions for LUT register.
179 + *
180 + * The pad stands for the lines number of IO[0:3].
181 + * For example, the Quad read need four IO lines, so you should
182 + * set LUT_PAD4 which means we use four IO lines.
183 + */
184 +#define LUT_PAD1 0
185 +#define LUT_PAD2 1
186 +#define LUT_PAD4 2
187 +
188 +/* Oprands for the LUT register. */
189 +#define ADDR24BIT 0x18
190 +#define ADDR32BIT 0x20
191 +
192 +/* Macros for constructing the LUT register. */
193 +#define LUT0(ins, pad, opr) \
194 + (((opr) << OPRND0_SHIFT) | ((LUT_##pad) << PAD0_SHIFT) | \
195 + ((LUT_##ins) << INSTR0_SHIFT))
196 +
197 +#define LUT1(ins, pad, opr) (LUT0(ins, pad, opr) << OPRND1_SHIFT)
198 +
199 +/* other macros for LUT register. */
200 +#define QUADSPI_LUT(x) (QUADSPI_LUT_BASE + (x) * 4)
201 +#define QUADSPI_LUT_NUM 64
202 +
203 +/* SEQID -- we can have 16 seqids at most. */
204 +#define SEQID_QUAD_READ 0
205 +#define SEQID_WREN 1
206 +#define SEQID_WRDI 2
207 +#define SEQID_RDSR 3
208 +#define SEQID_SE 4
209 +#define SEQID_CHIP_ERASE 5
210 +#define SEQID_PP 6
211 +#define SEQID_RDID 7
212 +#define SEQID_WRSR 8
213 +#define SEQID_RDCR 9
214 +#define SEQID_EN4B 10
215 +#define SEQID_BRWR 11
216 +
217 +enum fsl_qspi_devtype {
218 + FSL_QUADSPI_VYBRID,
219 + FSL_QUADSPI_IMX6SX,
220 +};
221 +
222 +struct fsl_qspi_devtype_data {
223 + enum fsl_qspi_devtype devtype;
224 + int rxfifo;
225 + int txfifo;
226 +};
227 +
228 +static struct fsl_qspi_devtype_data vybrid_data = {
229 + .devtype = FSL_QUADSPI_VYBRID,
230 + .rxfifo = 128,
231 + .txfifo = 64
232 +};
233 +
234 +static struct fsl_qspi_devtype_data imx6sx_data = {
235 + .devtype = FSL_QUADSPI_IMX6SX,
236 + .rxfifo = 128,
237 + .txfifo = 512
238 +};
239 +
240 +#define FSL_QSPI_MAX_CHIP 4
241 +struct fsl_qspi {
242 + struct mtd_info mtd[FSL_QSPI_MAX_CHIP];
243 + struct spi_nor nor[FSL_QSPI_MAX_CHIP];
244 + void __iomem *iobase;
245 + void __iomem *ahb_base; /* Used when read from AHB bus */
246 + u32 memmap_phy;
247 + struct clk *clk, *clk_en;
248 + struct device *dev;
249 + struct completion c;
250 + struct fsl_qspi_devtype_data *devtype_data;
251 + u32 nor_size;
252 + u32 nor_num;
253 + u32 clk_rate;
254 + unsigned int chip_base_addr; /* We may support two chips. */
255 +};
256 +
257 +static inline int is_vybrid_qspi(struct fsl_qspi *q)
258 +{
259 + return q->devtype_data->devtype == FSL_QUADSPI_VYBRID;
260 +}
261 +
262 +static inline int is_imx6sx_qspi(struct fsl_qspi *q)
263 +{
264 + return q->devtype_data->devtype == FSL_QUADSPI_IMX6SX;
265 +}
266 +
267 +/*
268 + * An IC bug makes us to re-arrange the 32-bit data.
269 + * The following chips, such as IMX6SLX, have fixed this bug.
270 + */
271 +static inline u32 fsl_qspi_endian_xchg(struct fsl_qspi *q, u32 a)
272 +{
273 + return is_vybrid_qspi(q) ? __swab32(a) : a;
274 +}
275 +
276 +static inline void fsl_qspi_unlock_lut(struct fsl_qspi *q)
277 +{
278 + writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
279 + writel(QUADSPI_LCKER_UNLOCK, q->iobase + QUADSPI_LCKCR);
280 +}
281 +
282 +static inline void fsl_qspi_lock_lut(struct fsl_qspi *q)
283 +{
284 + writel(QUADSPI_LUTKEY_VALUE, q->iobase + QUADSPI_LUTKEY);
285 + writel(QUADSPI_LCKER_LOCK, q->iobase + QUADSPI_LCKCR);
286 +}
287 +
288 +static irqreturn_t fsl_qspi_irq_handler(int irq, void *dev_id)
289 +{
290 + struct fsl_qspi *q = dev_id;
291 + u32 reg;
292 +
293 + /* clear interrupt */
294 + reg = readl(q->iobase + QUADSPI_FR);
295 + writel(reg, q->iobase + QUADSPI_FR);
296 +
297 + if (reg & QUADSPI_FR_TFF_MASK)
298 + complete(&q->c);
299 +
300 + dev_dbg(q->dev, "QUADSPI_FR : 0x%.8x:0x%.8x\n", q->chip_base_addr, reg);
301 + return IRQ_HANDLED;
302 +}
303 +
304 +static void fsl_qspi_init_lut(struct fsl_qspi *q)
305 +{
306 + void __iomem *base = q->iobase;
307 + int rxfifo = q->devtype_data->rxfifo;
308 + u32 lut_base;
309 + u8 cmd, addrlen, dummy;
310 + int i;
311 +
312 + fsl_qspi_unlock_lut(q);
313 +
314 + /* Clear all the LUT table */
315 + for (i = 0; i < QUADSPI_LUT_NUM; i++)
316 + writel(0, base + QUADSPI_LUT_BASE + i * 4);
317 +
318 + /* Quad Read */
319 + lut_base = SEQID_QUAD_READ * 4;
320 +
321 + if (q->nor_size <= SZ_16M) {
322 + cmd = SPINOR_OP_READ_1_1_4;
323 + addrlen = ADDR24BIT;
324 + dummy = 8;
325 + } else {
326 + /* use the 4-byte address */
327 + cmd = SPINOR_OP_READ_1_1_4;
328 + addrlen = ADDR32BIT;
329 + dummy = 8;
330 + }
331 +
332 + writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
333 + base + QUADSPI_LUT(lut_base));
334 + writel(LUT0(DUMMY, PAD1, dummy) | LUT1(READ, PAD4, rxfifo),
335 + base + QUADSPI_LUT(lut_base + 1));
336 +
337 + /* Write enable */
338 + lut_base = SEQID_WREN * 4;
339 + writel(LUT0(CMD, PAD1, SPINOR_OP_WREN), base + QUADSPI_LUT(lut_base));
340 +
341 + /* Page Program */
342 + lut_base = SEQID_PP * 4;
343 +
344 + if (q->nor_size <= SZ_16M) {
345 + cmd = SPINOR_OP_PP;
346 + addrlen = ADDR24BIT;
347 + } else {
348 + /* use the 4-byte address */
349 + cmd = SPINOR_OP_PP;
350 + addrlen = ADDR32BIT;
351 + }
352 +
353 + writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
354 + base + QUADSPI_LUT(lut_base));
355 + writel(LUT0(WRITE, PAD1, 0), base + QUADSPI_LUT(lut_base + 1));
356 +
357 + /* Read Status */
358 + lut_base = SEQID_RDSR * 4;
359 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDSR) | LUT1(READ, PAD1, 0x1),
360 + base + QUADSPI_LUT(lut_base));
361 +
362 + /* Erase a sector */
363 + lut_base = SEQID_SE * 4;
364 +
365 + if (q->nor_size <= SZ_16M) {
366 + cmd = SPINOR_OP_SE;
367 + addrlen = ADDR24BIT;
368 + } else {
369 + /* use the 4-byte address */
370 + cmd = SPINOR_OP_SE;
371 + addrlen = ADDR32BIT;
372 + }
373 +
374 + writel(LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen),
375 + base + QUADSPI_LUT(lut_base));
376 +
377 + /* Erase the whole chip */
378 + lut_base = SEQID_CHIP_ERASE * 4;
379 + writel(LUT0(CMD, PAD1, SPINOR_OP_CHIP_ERASE),
380 + base + QUADSPI_LUT(lut_base));
381 +
382 + /* READ ID */
383 + lut_base = SEQID_RDID * 4;
384 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDID) | LUT1(READ, PAD1, 0x8),
385 + base + QUADSPI_LUT(lut_base));
386 +
387 + /* Write Register */
388 + lut_base = SEQID_WRSR * 4;
389 + writel(LUT0(CMD, PAD1, SPINOR_OP_WRSR) | LUT1(WRITE, PAD1, 0x2),
390 + base + QUADSPI_LUT(lut_base));
391 +
392 + /* Read Configuration Register */
393 + lut_base = SEQID_RDCR * 4;
394 + writel(LUT0(CMD, PAD1, SPINOR_OP_RDCR) | LUT1(READ, PAD1, 0x1),
395 + base + QUADSPI_LUT(lut_base));
396 +
397 + /* Write disable */
398 + lut_base = SEQID_WRDI * 4;
399 + writel(LUT0(CMD, PAD1, SPINOR_OP_WRDI), base + QUADSPI_LUT(lut_base));
400 +
401 + /* Enter 4 Byte Mode (Micron) */
402 + lut_base = SEQID_EN4B * 4;
403 + writel(LUT0(CMD, PAD1, SPINOR_OP_EN4B), base + QUADSPI_LUT(lut_base));
404 +
405 + /* Enter 4 Byte Mode (Spansion) */
406 + lut_base = SEQID_BRWR * 4;
407 + writel(LUT0(CMD, PAD1, SPINOR_OP_BRWR), base + QUADSPI_LUT(lut_base));
408 +
409 + fsl_qspi_lock_lut(q);
410 +}
411 +
412 +/* Get the SEQID for the command */
413 +static int fsl_qspi_get_seqid(struct fsl_qspi *q, u8 cmd)
414 +{
415 + switch (cmd) {
416 + case SPINOR_OP_READ_1_1_4:
417 + return SEQID_QUAD_READ;
418 + case SPINOR_OP_WREN:
419 + return SEQID_WREN;
420 + case SPINOR_OP_WRDI:
421 + return SEQID_WRDI;
422 + case SPINOR_OP_RDSR:
423 + return SEQID_RDSR;
424 + case SPINOR_OP_SE:
425 + return SEQID_SE;
426 + case SPINOR_OP_CHIP_ERASE:
427 + return SEQID_CHIP_ERASE;
428 + case SPINOR_OP_PP:
429 + return SEQID_PP;
430 + case SPINOR_OP_RDID:
431 + return SEQID_RDID;
432 + case SPINOR_OP_WRSR:
433 + return SEQID_WRSR;
434 + case SPINOR_OP_RDCR:
435 + return SEQID_RDCR;
436 + case SPINOR_OP_EN4B:
437 + return SEQID_EN4B;
438 + case SPINOR_OP_BRWR:
439 + return SEQID_BRWR;
440 + default:
441 + dev_err(q->dev, "Unsupported cmd 0x%.2x\n", cmd);
442 + break;
443 + }
444 + return -EINVAL;
445 +}
446 +
447 +static int
448 +fsl_qspi_runcmd(struct fsl_qspi *q, u8 cmd, unsigned int addr, int len)
449 +{
450 + void __iomem *base = q->iobase;
451 + int seqid;
452 + u32 reg, reg2;
453 + int err;
454 +
455 + init_completion(&q->c);
456 + dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len:%d, cmd:%.2x\n",
457 + q->chip_base_addr, addr, len, cmd);
458 +
459 + /* save the reg */
460 + reg = readl(base + QUADSPI_MCR);
461 +
462 + writel(q->memmap_phy + q->chip_base_addr + addr, base + QUADSPI_SFAR);
463 + writel(QUADSPI_RBCT_WMRK_MASK | QUADSPI_RBCT_RXBRD_USEIPS,
464 + base + QUADSPI_RBCT);
465 + writel(reg | QUADSPI_MCR_CLR_RXF_MASK, base + QUADSPI_MCR);
466 +
467 + do {
468 + reg2 = readl(base + QUADSPI_SR);
469 + if (reg2 & (QUADSPI_SR_IP_ACC_MASK | QUADSPI_SR_AHB_ACC_MASK)) {
470 + udelay(1);
471 + dev_dbg(q->dev, "The controller is busy, 0x%x\n", reg2);
472 + continue;
473 + }
474 + break;
475 + } while (1);
476 +
477 + /* trigger the LUT now */
478 + seqid = fsl_qspi_get_seqid(q, cmd);
479 + writel((seqid << QUADSPI_IPCR_SEQID_SHIFT) | len, base + QUADSPI_IPCR);
480 +
481 + /* Wait for the interrupt. */
482 + err = wait_for_completion_timeout(&q->c, msecs_to_jiffies(1000));
483 + if (!err) {
484 + dev_err(q->dev,
485 + "cmd 0x%.2x timeout, addr@%.8x, FR:0x%.8x, SR:0x%.8x\n",
486 + cmd, addr, readl(base + QUADSPI_FR),
487 + readl(base + QUADSPI_SR));
488 + err = -ETIMEDOUT;
489 + } else {
490 + err = 0;
491 + }
492 +
493 + /* restore the MCR */
494 + writel(reg, base + QUADSPI_MCR);
495 +
496 + return err;
497 +}
498 +
499 +/* Read out the data from the QUADSPI_RBDR buffer registers. */
500 +static void fsl_qspi_read_data(struct fsl_qspi *q, int len, u8 *rxbuf)
501 +{
502 + u32 tmp;
503 + int i = 0;
504 +
505 + while (len > 0) {
506 + tmp = readl(q->iobase + QUADSPI_RBDR + i * 4);
507 + tmp = fsl_qspi_endian_xchg(q, tmp);
508 + dev_dbg(q->dev, "chip addr:0x%.8x, rcv:0x%.8x\n",
509 + q->chip_base_addr, tmp);
510 +
511 + if (len >= 4) {
512 + *((u32 *)rxbuf) = tmp;
513 + rxbuf += 4;
514 + } else {
515 + memcpy(rxbuf, &tmp, len);
516 + break;
517 + }
518 +
519 + len -= 4;
520 + i++;
521 + }
522 +}
523 +
524 +/*
525 + * If we have changed the content of the flash by writing or erasing,
526 + * we need to invalidate the AHB buffer. If we do not do so, we may read out
527 + * the wrong data. The spec tells us reset the AHB domain and Serial Flash
528 + * domain at the same time.
529 + */
530 +static inline void fsl_qspi_invalid(struct fsl_qspi *q)
531 +{
532 + u32 reg;
533 +
534 + reg = readl(q->iobase + QUADSPI_MCR);
535 + reg |= QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK;
536 + writel(reg, q->iobase + QUADSPI_MCR);
537 +
538 + /*
539 + * The minimum delay : 1 AHB + 2 SFCK clocks.
540 + * Delay 1 us is enough.
541 + */
542 + udelay(1);
543 +
544 + reg &= ~(QUADSPI_MCR_SWRSTHD_MASK | QUADSPI_MCR_SWRSTSD_MASK);
545 + writel(reg, q->iobase + QUADSPI_MCR);
546 +}
547 +
548 +static int fsl_qspi_nor_write(struct fsl_qspi *q, struct spi_nor *nor,
549 + u8 opcode, unsigned int to, u32 *txbuf,
550 + unsigned count, size_t *retlen)
551 +{
552 + int ret, i, j;
553 + u32 tmp;
554 +
555 + dev_dbg(q->dev, "to 0x%.8x:0x%.8x, len : %d\n",
556 + q->chip_base_addr, to, count);
557 +
558 + /* clear the TX FIFO. */
559 + tmp = readl(q->iobase + QUADSPI_MCR);
560 + writel(tmp | QUADSPI_MCR_CLR_RXF_MASK, q->iobase + QUADSPI_MCR);
561 +
562 + /* fill the TX data to the FIFO */
563 + for (j = 0, i = ((count + 3) / 4); j < i; j++) {
564 + tmp = fsl_qspi_endian_xchg(q, *txbuf);
565 + writel(tmp, q->iobase + QUADSPI_TBDR);
566 + txbuf++;
567 + }
568 +
569 + /* Trigger it */
570 + ret = fsl_qspi_runcmd(q, opcode, to, count);
571 +
572 + if (ret == 0 && retlen)
573 + *retlen += count;
574 +
575 + return ret;
576 +}
577 +
578 +static void fsl_qspi_set_map_addr(struct fsl_qspi *q)
579 +{
580 + int nor_size = q->nor_size;
581 + void __iomem *base = q->iobase;
582 +
583 + writel(nor_size + q->memmap_phy, base + QUADSPI_SFA1AD);
584 + writel(nor_size * 2 + q->memmap_phy, base + QUADSPI_SFA2AD);
585 + writel(nor_size * 3 + q->memmap_phy, base + QUADSPI_SFB1AD);
586 + writel(nor_size * 4 + q->memmap_phy, base + QUADSPI_SFB2AD);
587 +}
588 +
589 +/*
590 + * There are two different ways to read out the data from the flash:
591 + * the "IP Command Read" and the "AHB Command Read".
592 + *
593 + * The IC guy suggests we use the "AHB Command Read" which is faster
594 + * then the "IP Command Read". (What's more is that there is a bug in
595 + * the "IP Command Read" in the Vybrid.)
596 + *
597 + * After we set up the registers for the "AHB Command Read", we can use
598 + * the memcpy to read the data directly. A "missed" access to the buffer
599 + * causes the controller to clear the buffer, and use the sequence pointed
600 + * by the QUADSPI_BFGENCR[SEQID] to initiate a read from the flash.
601 + */
602 +static void fsl_qspi_init_abh_read(struct fsl_qspi *q)
603 +{
604 + void __iomem *base = q->iobase;
605 + int seqid;
606 +
607 + /* AHB configuration for access buffer 0/1/2 .*/
608 + writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF0CR);
609 + writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF1CR);
610 + writel(QUADSPI_BUFXCR_INVALID_MSTRID, base + QUADSPI_BUF2CR);
611 + writel(QUADSPI_BUF3CR_ALLMST, base + QUADSPI_BUF3CR);
612 +
613 + /* We only use the buffer3 */
614 + writel(0, base + QUADSPI_BUF0IND);
615 + writel(0, base + QUADSPI_BUF1IND);
616 + writel(0, base + QUADSPI_BUF2IND);
617 +
618 + /* Set the default lut sequence for AHB Read. */
619 + seqid = fsl_qspi_get_seqid(q, q->nor[0].read_opcode);
620 + writel(seqid << QUADSPI_BFGENCR_SEQID_SHIFT,
621 + q->iobase + QUADSPI_BFGENCR);
622 +}
623 +
624 +/* We use this function to do some basic init for spi_nor_scan(). */
625 +static int fsl_qspi_nor_setup(struct fsl_qspi *q)
626 +{
627 + void __iomem *base = q->iobase;
628 + u32 reg;
629 + int ret;
630 +
631 + /* the default frequency, we will change it in the future.*/
632 + ret = clk_set_rate(q->clk, 66000000);
633 + if (ret)
634 + return ret;
635 +
636 + /* Init the LUT table. */
637 + fsl_qspi_init_lut(q);
638 +
639 + /* Disable the module */
640 + writel(QUADSPI_MCR_MDIS_MASK | QUADSPI_MCR_RESERVED_MASK,
641 + base + QUADSPI_MCR);
642 +
643 + reg = readl(base + QUADSPI_SMPR);
644 + writel(reg & ~(QUADSPI_SMPR_FSDLY_MASK
645 + | QUADSPI_SMPR_FSPHS_MASK
646 + | QUADSPI_SMPR_HSENA_MASK
647 + | QUADSPI_SMPR_DDRSMP_MASK), base + QUADSPI_SMPR);
648 +
649 + /* Enable the module */
650 + writel(QUADSPI_MCR_RESERVED_MASK | QUADSPI_MCR_END_CFG_MASK,
651 + base + QUADSPI_MCR);
652 +
653 + /* enable the interrupt */
654 + writel(QUADSPI_RSER_TFIE, q->iobase + QUADSPI_RSER);
655 +
656 + return 0;
657 +}
658 +
659 +static int fsl_qspi_nor_setup_last(struct fsl_qspi *q)
660 +{
661 + unsigned long rate = q->clk_rate;
662 + int ret;
663 +
664 + if (is_imx6sx_qspi(q))
665 + rate *= 4;
666 +
667 + ret = clk_set_rate(q->clk, rate);
668 + if (ret)
669 + return ret;
670 +
671 + /* Init the LUT table again. */
672 + fsl_qspi_init_lut(q);
673 +
674 + /* Init for AHB read */
675 + fsl_qspi_init_abh_read(q);
676 +
677 + return 0;
678 +}
679 +
680 +static struct of_device_id fsl_qspi_dt_ids[] = {
681 + { .compatible = "fsl,vf610-qspi", .data = (void *)&vybrid_data, },
682 + { .compatible = "fsl,imx6sx-qspi", .data = (void *)&imx6sx_data, },
683 + { /* sentinel */ }
684 +};
685 +MODULE_DEVICE_TABLE(of, fsl_qspi_dt_ids);
686 +
687 +static void fsl_qspi_set_base_addr(struct fsl_qspi *q, struct spi_nor *nor)
688 +{
689 + q->chip_base_addr = q->nor_size * (nor - q->nor);
690 +}
691 +
692 +static int fsl_qspi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
693 +{
694 + int ret;
695 + struct fsl_qspi *q = nor->priv;
696 +
697 + ret = fsl_qspi_runcmd(q, opcode, 0, len);
698 + if (ret)
699 + return ret;
700 +
701 + fsl_qspi_read_data(q, len, buf);
702 + return 0;
703 +}
704 +
705 +static int fsl_qspi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
706 + int write_enable)
707 +{
708 + struct fsl_qspi *q = nor->priv;
709 + int ret;
710 +
711 + if (!buf) {
712 + ret = fsl_qspi_runcmd(q, opcode, 0, 1);
713 + if (ret)
714 + return ret;
715 +
716 + if (opcode == SPINOR_OP_CHIP_ERASE)
717 + fsl_qspi_invalid(q);
718 +
719 + } else if (len > 0) {
720 + ret = fsl_qspi_nor_write(q, nor, opcode, 0,
721 + (u32 *)buf, len, NULL);
722 + } else {
723 + dev_err(q->dev, "invalid cmd %d\n", opcode);
724 + ret = -EINVAL;
725 + }
726 +
727 + return ret;
728 +}
729 +
730 +static void fsl_qspi_write(struct spi_nor *nor, loff_t to,
731 + size_t len, size_t *retlen, const u_char *buf)
732 +{
733 + struct fsl_qspi *q = nor->priv;
734 +
735 + fsl_qspi_nor_write(q, nor, nor->program_opcode, to,
736 + (u32 *)buf, len, retlen);
737 +
738 + /* invalid the data in the AHB buffer. */
739 + fsl_qspi_invalid(q);
740 +}
741 +
742 +static int fsl_qspi_read(struct spi_nor *nor, loff_t from,
743 + size_t len, size_t *retlen, u_char *buf)
744 +{
745 + struct fsl_qspi *q = nor->priv;
746 + u8 cmd = nor->read_opcode;
747 + int ret;
748 +
749 + dev_dbg(q->dev, "cmd [%x],read from (0x%p, 0x%.8x, 0x%.8x),len:%d\n",
750 + cmd, q->ahb_base, q->chip_base_addr, (unsigned int)from, len);
751 +
752 + /* Wait until the previous command is finished. */
753 + ret = nor->wait_till_ready(nor);
754 + if (ret)
755 + return ret;
756 +
757 + /* Read out the data directly from the AHB buffer.*/
758 + memcpy(buf, q->ahb_base + q->chip_base_addr + from, len);
759 +
760 + *retlen += len;
761 + return 0;
762 +}
763 +
764 +static int fsl_qspi_erase(struct spi_nor *nor, loff_t offs)
765 +{
766 + struct fsl_qspi *q = nor->priv;
767 + int ret;
768 +
769 + dev_dbg(nor->dev, "%dKiB at 0x%08x:0x%08x\n",
770 + nor->mtd->erasesize / 1024, q->chip_base_addr, (u32)offs);
771 +
772 + /* Wait until finished previous write command. */
773 + ret = nor->wait_till_ready(nor);
774 + if (ret)
775 + return ret;
776 +
777 + /* Send write enable, then erase commands. */
778 + ret = nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
779 + if (ret)
780 + return ret;
781 +
782 + ret = fsl_qspi_runcmd(q, nor->erase_opcode, offs, 0);
783 + if (ret)
784 + return ret;
785 +
786 + fsl_qspi_invalid(q);
787 + return 0;
788 +}
789 +
790 +static int fsl_qspi_prep(struct spi_nor *nor, enum spi_nor_ops ops)
791 +{
792 + struct fsl_qspi *q = nor->priv;
793 + int ret;
794 +
795 + ret = clk_enable(q->clk_en);
796 + if (ret)
797 + return ret;
798 +
799 + ret = clk_enable(q->clk);
800 + if (ret) {
801 + clk_disable(q->clk_en);
802 + return ret;
803 + }
804 +
805 + fsl_qspi_set_base_addr(q, nor);
806 + return 0;
807 +}
808 +
809 +static void fsl_qspi_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
810 +{
811 + struct fsl_qspi *q = nor->priv;
812 +
813 + clk_disable(q->clk);
814 + clk_disable(q->clk_en);
815 +}
816 +
817 +static int fsl_qspi_probe(struct platform_device *pdev)
818 +{
819 + struct device_node *np = pdev->dev.of_node;
820 + struct mtd_part_parser_data ppdata;
821 + struct device *dev = &pdev->dev;
822 + struct fsl_qspi *q;
823 + struct resource *res;
824 + struct spi_nor *nor;
825 + struct mtd_info *mtd;
826 + int ret, i = 0;
827 + bool has_second_chip = false;
828 + const struct of_device_id *of_id =
829 + of_match_device(fsl_qspi_dt_ids, &pdev->dev);
830 +
831 + q = devm_kzalloc(dev, sizeof(*q), GFP_KERNEL);
832 + if (!q)
833 + return -ENOMEM;
834 +
835 + q->nor_num = of_get_child_count(dev->of_node);
836 + if (!q->nor_num || q->nor_num > FSL_QSPI_MAX_CHIP)
837 + return -ENODEV;
838 +
839 + /* find the resources */
840 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "QuadSPI");
841 + q->iobase = devm_ioremap_resource(dev, res);
842 + if (IS_ERR(q->iobase)) {
843 + ret = PTR_ERR(q->iobase);
844 + goto map_failed;
845 + }
846 +
847 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
848 + "QuadSPI-memory");
849 + q->ahb_base = devm_ioremap_resource(dev, res);
850 + if (IS_ERR(q->ahb_base)) {
851 + ret = PTR_ERR(q->ahb_base);
852 + goto map_failed;
853 + }
854 + q->memmap_phy = res->start;
855 +
856 + /* find the clocks */
857 + q->clk_en = devm_clk_get(dev, "qspi_en");
858 + if (IS_ERR(q->clk_en)) {
859 + ret = PTR_ERR(q->clk_en);
860 + goto map_failed;
861 + }
862 +
863 + q->clk = devm_clk_get(dev, "qspi");
864 + if (IS_ERR(q->clk)) {
865 + ret = PTR_ERR(q->clk);
866 + goto map_failed;
867 + }
868 +
869 + ret = clk_prepare_enable(q->clk_en);
870 + if (ret) {
871 + dev_err(dev, "can not enable the qspi_en clock\n");
872 + goto map_failed;
873 + }
874 +
875 + ret = clk_prepare_enable(q->clk);
876 + if (ret) {
877 + clk_disable_unprepare(q->clk_en);
878 + dev_err(dev, "can not enable the qspi clock\n");
879 + goto map_failed;
880 + }
881 +
882 + /* find the irq */
883 + ret = platform_get_irq(pdev, 0);
884 + if (ret < 0) {
885 + dev_err(dev, "failed to get the irq\n");
886 + goto irq_failed;
887 + }
888 +
889 + ret = devm_request_irq(dev, ret,
890 + fsl_qspi_irq_handler, 0, pdev->name, q);
891 + if (ret) {
892 + dev_err(dev, "failed to request irq.\n");
893 + goto irq_failed;
894 + }
895 +
896 + q->dev = dev;
897 + q->devtype_data = (struct fsl_qspi_devtype_data *)of_id->data;
898 + platform_set_drvdata(pdev, q);
899 +
900 + ret = fsl_qspi_nor_setup(q);
901 + if (ret)
902 + goto irq_failed;
903 +
904 + if (of_get_property(np, "fsl,qspi-has-second-chip", NULL))
905 + has_second_chip = true;
906 +
907 + /* iterate the subnodes. */
908 + for_each_available_child_of_node(dev->of_node, np) {
909 + const struct spi_device_id *id;
910 + char modalias[40];
911 +
912 + /* skip the holes */
913 + if (!has_second_chip)
914 + i *= 2;
915 +
916 + nor = &q->nor[i];
917 + mtd = &q->mtd[i];
918 +
919 + nor->mtd = mtd;
920 + nor->dev = dev;
921 + nor->priv = q;
922 + mtd->priv = nor;
923 +
924 + /* fill the hooks */
925 + nor->read_reg = fsl_qspi_read_reg;
926 + nor->write_reg = fsl_qspi_write_reg;
927 + nor->read = fsl_qspi_read;
928 + nor->write = fsl_qspi_write;
929 + nor->erase = fsl_qspi_erase;
930 +
931 + nor->prepare = fsl_qspi_prep;
932 + nor->unprepare = fsl_qspi_unprep;
933 +
934 + if (of_modalias_node(np, modalias, sizeof(modalias)) < 0)
935 + goto map_failed;
936 +
937 + id = spi_nor_match_id(modalias);
938 + if (!id)
939 + goto map_failed;
940 +
941 + ret = of_property_read_u32(np, "spi-max-frequency",
942 + &q->clk_rate);
943 + if (ret < 0)
944 + goto map_failed;
945 +
946 + /* set the chip address for READID */
947 + fsl_qspi_set_base_addr(q, nor);
948 +
949 + ret = spi_nor_scan(nor, id, SPI_NOR_QUAD);
950 + if (ret)
951 + goto map_failed;
952 +
953 + ppdata.of_node = np;
954 + ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
955 + if (ret)
956 + goto map_failed;
957 +
958 + /* Set the correct NOR size now. */
959 + if (q->nor_size == 0) {
960 + q->nor_size = mtd->size;
961 +
962 + /* Map the SPI NOR to accessiable address */
963 + fsl_qspi_set_map_addr(q);
964 + }
965 +
966 + /*
967 + * The TX FIFO is 64 bytes in the Vybrid, but the Page Program
968 + * may writes 265 bytes per time. The write is working in the
969 + * unit of the TX FIFO, not in the unit of the SPI NOR's page
970 + * size.
971 + *
972 + * So shrink the spi_nor->page_size if it is larger then the
973 + * TX FIFO.
974 + */
975 + if (nor->page_size > q->devtype_data->txfifo)
976 + nor->page_size = q->devtype_data->txfifo;
977 +
978 + i++;
979 + }
980 +
981 + /* finish the rest init. */
982 + ret = fsl_qspi_nor_setup_last(q);
983 + if (ret)
984 + goto last_init_failed;
985 +
986 + clk_disable(q->clk);
987 + clk_disable(q->clk_en);
988 + dev_info(dev, "QuadSPI SPI NOR flash driver\n");
989 + return 0;
990 +
991 +last_init_failed:
992 + for (i = 0; i < q->nor_num; i++)
993 + mtd_device_unregister(&q->mtd[i]);
994 +
995 +irq_failed:
996 + clk_disable_unprepare(q->clk);
997 + clk_disable_unprepare(q->clk_en);
998 +map_failed:
999 + dev_err(dev, "Freescale QuadSPI probe failed\n");
1000 + return ret;
1001 +}
1002 +
1003 +static int fsl_qspi_remove(struct platform_device *pdev)
1004 +{
1005 + struct fsl_qspi *q = platform_get_drvdata(pdev);
1006 + int i;
1007 +
1008 + for (i = 0; i < q->nor_num; i++)
1009 + mtd_device_unregister(&q->mtd[i]);
1010 +
1011 + /* disable the hardware */
1012 + writel(QUADSPI_MCR_MDIS_MASK, q->iobase + QUADSPI_MCR);
1013 + writel(0x0, q->iobase + QUADSPI_RSER);
1014 +
1015 + clk_unprepare(q->clk);
1016 + clk_unprepare(q->clk_en);
1017 + return 0;
1018 +}
1019 +
1020 +static struct platform_driver fsl_qspi_driver = {
1021 + .driver = {
1022 + .name = "fsl-quadspi",
1023 + .bus = &platform_bus_type,
1024 + .owner = THIS_MODULE,
1025 + .of_match_table = fsl_qspi_dt_ids,
1026 + },
1027 + .probe = fsl_qspi_probe,
1028 + .remove = fsl_qspi_remove,
1029 +};
1030 +module_platform_driver(fsl_qspi_driver);
1031 +
1032 +MODULE_DESCRIPTION("Freescale QuadSPI Controller Driver");
1033 +MODULE_AUTHOR("Freescale Semiconductor Inc.");
1034 +MODULE_LICENSE("GPL v2");
1035 --- /dev/null
1036 +++ b/drivers/mtd/spi-nor/Kconfig
1037 @@ -0,0 +1,17 @@
1038 +menuconfig MTD_SPI_NOR
1039 + tristate "SPI-NOR device support"
1040 + depends on MTD
1041 + help
1042 + This is the framework for the SPI NOR which can be used by the SPI
1043 + device drivers and the SPI-NOR device driver.
1044 +
1045 +if MTD_SPI_NOR
1046 +
1047 +config SPI_FSL_QUADSPI
1048 + tristate "Freescale Quad SPI controller"
1049 + depends on ARCH_MXC
1050 + help
1051 + This enables support for the Quad SPI controller in master mode.
1052 + We only connect the NOR to this controller now.
1053 +
1054 +endif # MTD_SPI_NOR
1055 --- /dev/null
1056 +++ b/drivers/mtd/spi-nor/Makefile
1057 @@ -0,0 +1,2 @@
1058 +obj-$(CONFIG_MTD_SPI_NOR) += spi-nor.o
1059 +obj-$(CONFIG_SPI_FSL_QUADSPI) += fsl-quadspi.o
1060 --- /dev/null
1061 +++ b/drivers/mtd/spi-nor/spi-nor.c
1062 @@ -0,0 +1,1160 @@
1063 +/*
1064 + * Based on m25p80.c, by Mike Lavender (mike@steroidmicros.com), with
1065 + * influence from lart.c (Abraham Van Der Merwe) and mtd_dataflash.c
1066 + *
1067 + * Copyright (C) 2005, Intec Automation Inc.
1068 + * Copyright (C) 2014, Freescale Semiconductor, Inc.
1069 + *
1070 + * This code is free software; you can redistribute it and/or modify
1071 + * it under the terms of the GNU General Public License version 2 as
1072 + * published by the Free Software Foundation.
1073 + */
1074 +
1075 +#include <linux/err.h>
1076 +#include <linux/errno.h>
1077 +#include <linux/module.h>
1078 +#include <linux/device.h>
1079 +#include <linux/mutex.h>
1080 +#include <linux/math64.h>
1081 +
1082 +#include <linux/mtd/cfi.h>
1083 +#include <linux/mtd/mtd.h>
1084 +#include <linux/of_platform.h>
1085 +#include <linux/spi/flash.h>
1086 +#include <linux/mtd/spi-nor.h>
1087 +
1088 +/* Define max times to check status register before we give up. */
1089 +#define MAX_READY_WAIT_JIFFIES (40 * HZ) /* M25P16 specs 40s max chip erase */
1090 +
1091 +#define JEDEC_MFR(_jedec_id) ((_jedec_id) >> 16)
1092 +
1093 +/*
1094 + * Read the status register, returning its value in the location
1095 + * Return the status register value.
1096 + * Returns negative if error occurred.
1097 + */
1098 +static int read_sr(struct spi_nor *nor)
1099 +{
1100 + int ret;
1101 + u8 val;
1102 +
1103 + ret = nor->read_reg(nor, SPINOR_OP_RDSR, &val, 1);
1104 + if (ret < 0) {
1105 + pr_err("error %d reading SR\n", (int) ret);
1106 + return ret;
1107 + }
1108 +
1109 + return val;
1110 +}
1111 +
1112 +/*
1113 + * Read the flag status register, returning its value in the location
1114 + * Return the status register value.
1115 + * Returns negative if error occurred.
1116 + */
1117 +static int read_fsr(struct spi_nor *nor)
1118 +{
1119 + int ret;
1120 + u8 val;
1121 +
1122 + ret = nor->read_reg(nor, SPINOR_OP_RDFSR, &val, 1);
1123 + if (ret < 0) {
1124 + pr_err("error %d reading FSR\n", ret);
1125 + return ret;
1126 + }
1127 +
1128 + return val;
1129 +}
1130 +
1131 +/*
1132 + * Read configuration register, returning its value in the
1133 + * location. Return the configuration register value.
1134 + * Returns negative if error occured.
1135 + */
1136 +static int read_cr(struct spi_nor *nor)
1137 +{
1138 + int ret;
1139 + u8 val;
1140 +
1141 + ret = nor->read_reg(nor, SPINOR_OP_RDCR, &val, 1);
1142 + if (ret < 0) {
1143 + dev_err(nor->dev, "error %d reading CR\n", ret);
1144 + return ret;
1145 + }
1146 +
1147 + return val;
1148 +}
1149 +
1150 +/*
1151 + * Dummy Cycle calculation for different type of read.
1152 + * It can be used to support more commands with
1153 + * different dummy cycle requirements.
1154 + */
1155 +static inline int spi_nor_read_dummy_cycles(struct spi_nor *nor)
1156 +{
1157 + switch (nor->flash_read) {
1158 + case SPI_NOR_FAST:
1159 + case SPI_NOR_DUAL:
1160 + case SPI_NOR_QUAD:
1161 + return 1;
1162 + case SPI_NOR_NORMAL:
1163 + return 0;
1164 + }
1165 + return 0;
1166 +}
1167 +
1168 +/*
1169 + * Write status register 1 byte
1170 + * Returns negative if error occurred.
1171 + */
1172 +static inline int write_sr(struct spi_nor *nor, u8 val)
1173 +{
1174 + nor->cmd_buf[0] = val;
1175 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
1176 +}
1177 +
1178 +/*
1179 + * Set write enable latch with Write Enable command.
1180 + * Returns negative if error occurred.
1181 + */
1182 +static inline int write_enable(struct spi_nor *nor)
1183 +{
1184 + return nor->write_reg(nor, SPINOR_OP_WREN, NULL, 0, 0);
1185 +}
1186 +
1187 +/*
1188 + * Send write disble instruction to the chip.
1189 + */
1190 +static inline int write_disable(struct spi_nor *nor)
1191 +{
1192 + return nor->write_reg(nor, SPINOR_OP_WRDI, NULL, 0, 0);
1193 +}
1194 +
1195 +static inline struct spi_nor *mtd_to_spi_nor(struct mtd_info *mtd)
1196 +{
1197 + return mtd->priv;
1198 +}
1199 +
1200 +/* Enable/disable 4-byte addressing mode. */
1201 +static inline int set_4byte(struct spi_nor *nor, u32 jedec_id, int enable)
1202 +{
1203 + int status;
1204 + bool need_wren = false;
1205 + u8 cmd;
1206 +
1207 + switch (JEDEC_MFR(jedec_id)) {
1208 + case CFI_MFR_ST: /* Micron, actually */
1209 + /* Some Micron need WREN command; all will accept it */
1210 + need_wren = true;
1211 + case CFI_MFR_MACRONIX:
1212 + case 0xEF /* winbond */:
1213 + if (need_wren)
1214 + write_enable(nor);
1215 +
1216 + cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B;
1217 + status = nor->write_reg(nor, cmd, NULL, 0, 0);
1218 + if (need_wren)
1219 + write_disable(nor);
1220 +
1221 + return status;
1222 + default:
1223 + /* Spansion style */
1224 + nor->cmd_buf[0] = enable << 7;
1225 + return nor->write_reg(nor, SPINOR_OP_BRWR, nor->cmd_buf, 1, 0);
1226 + }
1227 +}
1228 +
1229 +static int spi_nor_wait_till_ready(struct spi_nor *nor)
1230 +{
1231 + unsigned long deadline;
1232 + int sr;
1233 +
1234 + deadline = jiffies + MAX_READY_WAIT_JIFFIES;
1235 +
1236 + do {
1237 + cond_resched();
1238 +
1239 + sr = read_sr(nor);
1240 + if (sr < 0)
1241 + break;
1242 + else if (!(sr & SR_WIP))
1243 + return 0;
1244 + } while (!time_after_eq(jiffies, deadline));
1245 +
1246 + return -ETIMEDOUT;
1247 +}
1248 +
1249 +static int spi_nor_wait_till_fsr_ready(struct spi_nor *nor)
1250 +{
1251 + unsigned long deadline;
1252 + int sr;
1253 + int fsr;
1254 +
1255 + deadline = jiffies + MAX_READY_WAIT_JIFFIES;
1256 +
1257 + do {
1258 + cond_resched();
1259 +
1260 + sr = read_sr(nor);
1261 + if (sr < 0) {
1262 + break;
1263 + } else if (!(sr & SR_WIP)) {
1264 + fsr = read_fsr(nor);
1265 + if (fsr < 0)
1266 + break;
1267 + if (fsr & FSR_READY)
1268 + return 0;
1269 + }
1270 + } while (!time_after_eq(jiffies, deadline));
1271 +
1272 + return -ETIMEDOUT;
1273 +}
1274 +
1275 +/*
1276 + * Service routine to read status register until ready, or timeout occurs.
1277 + * Returns non-zero if error.
1278 + */
1279 +static int wait_till_ready(struct spi_nor *nor)
1280 +{
1281 + return nor->wait_till_ready(nor);
1282 +}
1283 +
1284 +/*
1285 + * Erase the whole flash memory
1286 + *
1287 + * Returns 0 if successful, non-zero otherwise.
1288 + */
1289 +static int erase_chip(struct spi_nor *nor)
1290 +{
1291 + int ret;
1292 +
1293 + dev_dbg(nor->dev, " %lldKiB\n", (long long)(nor->mtd->size >> 10));
1294 +
1295 + /* Wait until finished previous write command. */
1296 + ret = wait_till_ready(nor);
1297 + if (ret)
1298 + return ret;
1299 +
1300 + /* Send write enable, then erase commands. */
1301 + write_enable(nor);
1302 +
1303 + return nor->write_reg(nor, SPINOR_OP_CHIP_ERASE, NULL, 0, 0);
1304 +}
1305 +
1306 +static int spi_nor_lock_and_prep(struct spi_nor *nor, enum spi_nor_ops ops)
1307 +{
1308 + int ret = 0;
1309 +
1310 + mutex_lock(&nor->lock);
1311 +
1312 + if (nor->prepare) {
1313 + ret = nor->prepare(nor, ops);
1314 + if (ret) {
1315 + dev_err(nor->dev, "failed in the preparation.\n");
1316 + mutex_unlock(&nor->lock);
1317 + return ret;
1318 + }
1319 + }
1320 + return ret;
1321 +}
1322 +
1323 +static void spi_nor_unlock_and_unprep(struct spi_nor *nor, enum spi_nor_ops ops)
1324 +{
1325 + if (nor->unprepare)
1326 + nor->unprepare(nor, ops);
1327 + mutex_unlock(&nor->lock);
1328 +}
1329 +
1330 +/*
1331 + * Erase an address range on the nor chip. The address range may extend
1332 + * one or more erase sectors. Return an error is there is a problem erasing.
1333 + */
1334 +static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
1335 +{
1336 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
1337 + u32 addr, len;
1338 + uint32_t rem;
1339 + int ret;
1340 +
1341 + dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
1342 + (long long)instr->len);
1343 +
1344 + div_u64_rem(instr->len, mtd->erasesize, &rem);
1345 + if (rem)
1346 + return -EINVAL;
1347 +
1348 + addr = instr->addr;
1349 + len = instr->len;
1350 +
1351 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_ERASE);
1352 + if (ret)
1353 + return ret;
1354 +
1355 + /* whole-chip erase? */
1356 + if (len == mtd->size) {
1357 + if (erase_chip(nor)) {
1358 + ret = -EIO;
1359 + goto erase_err;
1360 + }
1361 +
1362 + /* REVISIT in some cases we could speed up erasing large regions
1363 + * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
1364 + * to use "small sector erase", but that's not always optimal.
1365 + */
1366 +
1367 + /* "sector"-at-a-time erase */
1368 + } else {
1369 + while (len) {
1370 + if (nor->erase(nor, addr)) {
1371 + ret = -EIO;
1372 + goto erase_err;
1373 + }
1374 +
1375 + addr += mtd->erasesize;
1376 + len -= mtd->erasesize;
1377 + }
1378 + }
1379 +
1380 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
1381 +
1382 + instr->state = MTD_ERASE_DONE;
1383 + mtd_erase_callback(instr);
1384 +
1385 + return ret;
1386 +
1387 +erase_err:
1388 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_ERASE);
1389 + instr->state = MTD_ERASE_FAILED;
1390 + return ret;
1391 +}
1392 +
1393 +static int spi_nor_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1394 +{
1395 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
1396 + uint32_t offset = ofs;
1397 + uint8_t status_old, status_new;
1398 + int ret = 0;
1399 +
1400 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_LOCK);
1401 + if (ret)
1402 + return ret;
1403 +
1404 + /* Wait until finished previous command */
1405 + ret = wait_till_ready(nor);
1406 + if (ret)
1407 + goto err;
1408 +
1409 + status_old = read_sr(nor);
1410 +
1411 + if (offset < mtd->size - (mtd->size / 2))
1412 + status_new = status_old | SR_BP2 | SR_BP1 | SR_BP0;
1413 + else if (offset < mtd->size - (mtd->size / 4))
1414 + status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
1415 + else if (offset < mtd->size - (mtd->size / 8))
1416 + status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
1417 + else if (offset < mtd->size - (mtd->size / 16))
1418 + status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
1419 + else if (offset < mtd->size - (mtd->size / 32))
1420 + status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
1421 + else if (offset < mtd->size - (mtd->size / 64))
1422 + status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
1423 + else
1424 + status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
1425 +
1426 + /* Only modify protection if it will not unlock other areas */
1427 + if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) >
1428 + (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
1429 + write_enable(nor);
1430 + ret = write_sr(nor, status_new);
1431 + if (ret)
1432 + goto err;
1433 + }
1434 +
1435 +err:
1436 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_LOCK);
1437 + return ret;
1438 +}
1439 +
1440 +static int spi_nor_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
1441 +{
1442 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
1443 + uint32_t offset = ofs;
1444 + uint8_t status_old, status_new;
1445 + int ret = 0;
1446 +
1447 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_UNLOCK);
1448 + if (ret)
1449 + return ret;
1450 +
1451 + /* Wait until finished previous command */
1452 + ret = wait_till_ready(nor);
1453 + if (ret)
1454 + goto err;
1455 +
1456 + status_old = read_sr(nor);
1457 +
1458 + if (offset+len > mtd->size - (mtd->size / 64))
1459 + status_new = status_old & ~(SR_BP2 | SR_BP1 | SR_BP0);
1460 + else if (offset+len > mtd->size - (mtd->size / 32))
1461 + status_new = (status_old & ~(SR_BP2 | SR_BP1)) | SR_BP0;
1462 + else if (offset+len > mtd->size - (mtd->size / 16))
1463 + status_new = (status_old & ~(SR_BP2 | SR_BP0)) | SR_BP1;
1464 + else if (offset+len > mtd->size - (mtd->size / 8))
1465 + status_new = (status_old & ~SR_BP2) | SR_BP1 | SR_BP0;
1466 + else if (offset+len > mtd->size - (mtd->size / 4))
1467 + status_new = (status_old & ~(SR_BP0 | SR_BP1)) | SR_BP2;
1468 + else if (offset+len > mtd->size - (mtd->size / 2))
1469 + status_new = (status_old & ~SR_BP1) | SR_BP2 | SR_BP0;
1470 + else
1471 + status_new = (status_old & ~SR_BP0) | SR_BP2 | SR_BP1;
1472 +
1473 + /* Only modify protection if it will not lock other areas */
1474 + if ((status_new & (SR_BP2 | SR_BP1 | SR_BP0)) <
1475 + (status_old & (SR_BP2 | SR_BP1 | SR_BP0))) {
1476 + write_enable(nor);
1477 + ret = write_sr(nor, status_new);
1478 + if (ret)
1479 + goto err;
1480 + }
1481 +
1482 +err:
1483 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_UNLOCK);
1484 + return ret;
1485 +}
1486 +
1487 +struct flash_info {
1488 + /* JEDEC id zero means "no ID" (most older chips); otherwise it has
1489 + * a high byte of zero plus three data bytes: the manufacturer id,
1490 + * then a two byte device id.
1491 + */
1492 + u32 jedec_id;
1493 + u16 ext_id;
1494 +
1495 + /* The size listed here is what works with SPINOR_OP_SE, which isn't
1496 + * necessarily called a "sector" by the vendor.
1497 + */
1498 + unsigned sector_size;
1499 + u16 n_sectors;
1500 +
1501 + u16 page_size;
1502 + u16 addr_width;
1503 +
1504 + u16 flags;
1505 +#define SECT_4K 0x01 /* SPINOR_OP_BE_4K works uniformly */
1506 +#define SPI_NOR_NO_ERASE 0x02 /* No erase command needed */
1507 +#define SST_WRITE 0x04 /* use SST byte programming */
1508 +#define SPI_NOR_NO_FR 0x08 /* Can't do fastread */
1509 +#define SECT_4K_PMC 0x10 /* SPINOR_OP_BE_4K_PMC works uniformly */
1510 +#define SPI_NOR_DUAL_READ 0x20 /* Flash supports Dual Read */
1511 +#define SPI_NOR_QUAD_READ 0x40 /* Flash supports Quad Read */
1512 +#define USE_FSR 0x80 /* use flag status register */
1513 +};
1514 +
1515 +#define INFO(_jedec_id, _ext_id, _sector_size, _n_sectors, _flags) \
1516 + ((kernel_ulong_t)&(struct flash_info) { \
1517 + .jedec_id = (_jedec_id), \
1518 + .ext_id = (_ext_id), \
1519 + .sector_size = (_sector_size), \
1520 + .n_sectors = (_n_sectors), \
1521 + .page_size = 256, \
1522 + .flags = (_flags), \
1523 + })
1524 +
1525 +#define CAT25_INFO(_sector_size, _n_sectors, _page_size, _addr_width, _flags) \
1526 + ((kernel_ulong_t)&(struct flash_info) { \
1527 + .sector_size = (_sector_size), \
1528 + .n_sectors = (_n_sectors), \
1529 + .page_size = (_page_size), \
1530 + .addr_width = (_addr_width), \
1531 + .flags = (_flags), \
1532 + })
1533 +
1534 +/* NOTE: double check command sets and memory organization when you add
1535 + * more nor chips. This current list focusses on newer chips, which
1536 + * have been converging on command sets which including JEDEC ID.
1537 + */
1538 +const struct spi_device_id spi_nor_ids[] = {
1539 + /* Atmel -- some are (confusingly) marketed as "DataFlash" */
1540 + { "at25fs010", INFO(0x1f6601, 0, 32 * 1024, 4, SECT_4K) },
1541 + { "at25fs040", INFO(0x1f6604, 0, 64 * 1024, 8, SECT_4K) },
1542 +
1543 + { "at25df041a", INFO(0x1f4401, 0, 64 * 1024, 8, SECT_4K) },
1544 + { "at25df321a", INFO(0x1f4701, 0, 64 * 1024, 64, SECT_4K) },
1545 + { "at25df641", INFO(0x1f4800, 0, 64 * 1024, 128, SECT_4K) },
1546 +
1547 + { "at26f004", INFO(0x1f0400, 0, 64 * 1024, 8, SECT_4K) },
1548 + { "at26df081a", INFO(0x1f4501, 0, 64 * 1024, 16, SECT_4K) },
1549 + { "at26df161a", INFO(0x1f4601, 0, 64 * 1024, 32, SECT_4K) },
1550 + { "at26df321", INFO(0x1f4700, 0, 64 * 1024, 64, SECT_4K) },
1551 +
1552 + { "at45db081d", INFO(0x1f2500, 0, 64 * 1024, 16, SECT_4K) },
1553 +
1554 + /* EON -- en25xxx */
1555 + { "en25f32", INFO(0x1c3116, 0, 64 * 1024, 64, SECT_4K) },
1556 + { "en25p32", INFO(0x1c2016, 0, 64 * 1024, 64, 0) },
1557 + { "en25q32b", INFO(0x1c3016, 0, 64 * 1024, 64, 0) },
1558 + { "en25p64", INFO(0x1c2017, 0, 64 * 1024, 128, 0) },
1559 + { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
1560 + { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
1561 + { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
1562 +
1563 + /* ESMT */
1564 + { "f25l32pa", INFO(0x8c2016, 0, 64 * 1024, 64, SECT_4K) },
1565 +
1566 + /* Everspin */
1567 + { "mr25h256", CAT25_INFO( 32 * 1024, 1, 256, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1568 + { "mr25h10", CAT25_INFO(128 * 1024, 1, 256, 3, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1569 +
1570 + /* GigaDevice */
1571 + { "gd25q32", INFO(0xc84016, 0, 64 * 1024, 64, SECT_4K) },
1572 + { "gd25q64", INFO(0xc84017, 0, 64 * 1024, 128, SECT_4K) },
1573 +
1574 + /* Intel/Numonyx -- xxxs33b */
1575 + { "160s33b", INFO(0x898911, 0, 64 * 1024, 32, 0) },
1576 + { "320s33b", INFO(0x898912, 0, 64 * 1024, 64, 0) },
1577 + { "640s33b", INFO(0x898913, 0, 64 * 1024, 128, 0) },
1578 +
1579 + /* Macronix */
1580 + { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) },
1581 + { "mx25l4005a", INFO(0xc22013, 0, 64 * 1024, 8, SECT_4K) },
1582 + { "mx25l8005", INFO(0xc22014, 0, 64 * 1024, 16, 0) },
1583 + { "mx25l1606e", INFO(0xc22015, 0, 64 * 1024, 32, SECT_4K) },
1584 + { "mx25l3205d", INFO(0xc22016, 0, 64 * 1024, 64, 0) },
1585 + { "mx25l3255e", INFO(0xc29e16, 0, 64 * 1024, 64, SECT_4K) },
1586 + { "mx25l6405d", INFO(0xc22017, 0, 64 * 1024, 128, 0) },
1587 + { "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
1588 + { "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
1589 + { "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512, 0) },
1590 + { "mx25l25655e", INFO(0xc22619, 0, 64 * 1024, 512, 0) },
1591 + { "mx66l51235l", INFO(0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_QUAD_READ) },
1592 + { "mx66l1g55g", INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
1593 +
1594 + /* Micron */
1595 + { "n25q064", INFO(0x20ba17, 0, 64 * 1024, 128, 0) },
1596 + { "n25q128a11", INFO(0x20bb18, 0, 64 * 1024, 256, 0) },
1597 + { "n25q128a13", INFO(0x20ba18, 0, 64 * 1024, 256, 0) },
1598 + { "n25q256a", INFO(0x20ba19, 0, 64 * 1024, 512, SECT_4K) },
1599 + { "n25q512a", INFO(0x20bb20, 0, 64 * 1024, 1024, SECT_4K) },
1600 + { "n25q512ax3", INFO(0x20ba20, 0, 64 * 1024, 1024, USE_FSR) },
1601 + { "n25q00", INFO(0x20ba21, 0, 64 * 1024, 2048, USE_FSR) },
1602 +
1603 + /* PMC */
1604 + { "pm25lv512", INFO(0, 0, 32 * 1024, 2, SECT_4K_PMC) },
1605 + { "pm25lv010", INFO(0, 0, 32 * 1024, 4, SECT_4K_PMC) },
1606 + { "pm25lq032", INFO(0x7f9d46, 0, 64 * 1024, 64, SECT_4K) },
1607 +
1608 + /* Spansion -- single (large) sector size only, at least
1609 + * for the chips listed here (without boot sectors).
1610 + */
1611 + { "s25sl032p", INFO(0x010215, 0x4d00, 64 * 1024, 64, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1612 + { "s25sl064p", INFO(0x010216, 0x4d00, 64 * 1024, 128, 0) },
1613 + { "s25fl256s0", INFO(0x010219, 0x4d00, 256 * 1024, 128, 0) },
1614 + { "s25fl256s1", INFO(0x010219, 0x4d01, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1615 + { "s25fl512s", INFO(0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
1616 + { "s70fl01gs", INFO(0x010221, 0x4d00, 256 * 1024, 256, 0) },
1617 + { "s25sl12800", INFO(0x012018, 0x0300, 256 * 1024, 64, 0) },
1618 + { "s25sl12801", INFO(0x012018, 0x0301, 64 * 1024, 256, 0) },
1619 + { "s25fl129p0", INFO(0x012018, 0x4d00, 256 * 1024, 64, 0) },
1620 + { "s25fl129p1", INFO(0x012018, 0x4d01, 64 * 1024, 256, 0) },
1621 + { "s25sl004a", INFO(0x010212, 0, 64 * 1024, 8, 0) },
1622 + { "s25sl008a", INFO(0x010213, 0, 64 * 1024, 16, 0) },
1623 + { "s25sl016a", INFO(0x010214, 0, 64 * 1024, 32, 0) },
1624 + { "s25sl032a", INFO(0x010215, 0, 64 * 1024, 64, 0) },
1625 + { "s25sl064a", INFO(0x010216, 0, 64 * 1024, 128, 0) },
1626 + { "s25fl008k", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1627 + { "s25fl016k", INFO(0xef4015, 0, 64 * 1024, 32, SECT_4K) },
1628 + { "s25fl064k", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1629 +
1630 + /* SST -- large erase sizes are "overlays", "sectors" are 4K */
1631 + { "sst25vf040b", INFO(0xbf258d, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1632 + { "sst25vf080b", INFO(0xbf258e, 0, 64 * 1024, 16, SECT_4K | SST_WRITE) },
1633 + { "sst25vf016b", INFO(0xbf2541, 0, 64 * 1024, 32, SECT_4K | SST_WRITE) },
1634 + { "sst25vf032b", INFO(0xbf254a, 0, 64 * 1024, 64, SECT_4K | SST_WRITE) },
1635 + { "sst25vf064c", INFO(0xbf254b, 0, 64 * 1024, 128, SECT_4K) },
1636 + { "sst25wf512", INFO(0xbf2501, 0, 64 * 1024, 1, SECT_4K | SST_WRITE) },
1637 + { "sst25wf010", INFO(0xbf2502, 0, 64 * 1024, 2, SECT_4K | SST_WRITE) },
1638 + { "sst25wf020", INFO(0xbf2503, 0, 64 * 1024, 4, SECT_4K | SST_WRITE) },
1639 + { "sst25wf040", INFO(0xbf2504, 0, 64 * 1024, 8, SECT_4K | SST_WRITE) },
1640 +
1641 + /* ST Microelectronics -- newer production may have feature updates */
1642 + { "m25p05", INFO(0x202010, 0, 32 * 1024, 2, 0) },
1643 + { "m25p10", INFO(0x202011, 0, 32 * 1024, 4, 0) },
1644 + { "m25p20", INFO(0x202012, 0, 64 * 1024, 4, 0) },
1645 + { "m25p40", INFO(0x202013, 0, 64 * 1024, 8, 0) },
1646 + { "m25p80", INFO(0x202014, 0, 64 * 1024, 16, 0) },
1647 + { "m25p16", INFO(0x202015, 0, 64 * 1024, 32, 0) },
1648 + { "m25p32", INFO(0x202016, 0, 64 * 1024, 64, 0) },
1649 + { "m25p64", INFO(0x202017, 0, 64 * 1024, 128, 0) },
1650 + { "m25p128", INFO(0x202018, 0, 256 * 1024, 64, 0) },
1651 + { "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64, 0) },
1652 +
1653 + { "m25p05-nonjedec", INFO(0, 0, 32 * 1024, 2, 0) },
1654 + { "m25p10-nonjedec", INFO(0, 0, 32 * 1024, 4, 0) },
1655 + { "m25p20-nonjedec", INFO(0, 0, 64 * 1024, 4, 0) },
1656 + { "m25p40-nonjedec", INFO(0, 0, 64 * 1024, 8, 0) },
1657 + { "m25p80-nonjedec", INFO(0, 0, 64 * 1024, 16, 0) },
1658 + { "m25p16-nonjedec", INFO(0, 0, 64 * 1024, 32, 0) },
1659 + { "m25p32-nonjedec", INFO(0, 0, 64 * 1024, 64, 0) },
1660 + { "m25p64-nonjedec", INFO(0, 0, 64 * 1024, 128, 0) },
1661 + { "m25p128-nonjedec", INFO(0, 0, 256 * 1024, 64, 0) },
1662 +
1663 + { "m45pe10", INFO(0x204011, 0, 64 * 1024, 2, 0) },
1664 + { "m45pe80", INFO(0x204014, 0, 64 * 1024, 16, 0) },
1665 + { "m45pe16", INFO(0x204015, 0, 64 * 1024, 32, 0) },
1666 +
1667 + { "m25pe20", INFO(0x208012, 0, 64 * 1024, 4, 0) },
1668 + { "m25pe80", INFO(0x208014, 0, 64 * 1024, 16, 0) },
1669 + { "m25pe16", INFO(0x208015, 0, 64 * 1024, 32, SECT_4K) },
1670 +
1671 + { "m25px16", INFO(0x207115, 0, 64 * 1024, 32, SECT_4K) },
1672 + { "m25px32", INFO(0x207116, 0, 64 * 1024, 64, SECT_4K) },
1673 + { "m25px32-s0", INFO(0x207316, 0, 64 * 1024, 64, SECT_4K) },
1674 + { "m25px32-s1", INFO(0x206316, 0, 64 * 1024, 64, SECT_4K) },
1675 + { "m25px64", INFO(0x207117, 0, 64 * 1024, 128, 0) },
1676 +
1677 + /* Winbond -- w25x "blocks" are 64K, "sectors" are 4KiB */
1678 + { "w25x10", INFO(0xef3011, 0, 64 * 1024, 2, SECT_4K) },
1679 + { "w25x20", INFO(0xef3012, 0, 64 * 1024, 4, SECT_4K) },
1680 + { "w25x40", INFO(0xef3013, 0, 64 * 1024, 8, SECT_4K) },
1681 + { "w25x80", INFO(0xef3014, 0, 64 * 1024, 16, SECT_4K) },
1682 + { "w25x16", INFO(0xef3015, 0, 64 * 1024, 32, SECT_4K) },
1683 + { "w25x32", INFO(0xef3016, 0, 64 * 1024, 64, SECT_4K) },
1684 + { "w25q32", INFO(0xef4016, 0, 64 * 1024, 64, SECT_4K) },
1685 + { "w25q32dw", INFO(0xef6016, 0, 64 * 1024, 64, SECT_4K) },
1686 + { "w25x64", INFO(0xef3017, 0, 64 * 1024, 128, SECT_4K) },
1687 + { "w25q64", INFO(0xef4017, 0, 64 * 1024, 128, SECT_4K) },
1688 + { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1689 + { "w25q80", INFO(0xef5014, 0, 64 * 1024, 16, SECT_4K) },
1690 + { "w25q80bl", INFO(0xef4014, 0, 64 * 1024, 16, SECT_4K) },
1691 + { "w25q128", INFO(0xef4018, 0, 64 * 1024, 256, SECT_4K) },
1692 + { "w25q256", INFO(0xef4019, 0, 64 * 1024, 512, SECT_4K) },
1693 +
1694 + /* Catalyst / On Semiconductor -- non-JEDEC */
1695 + { "cat25c11", CAT25_INFO( 16, 8, 16, 1, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1696 + { "cat25c03", CAT25_INFO( 32, 8, 16, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1697 + { "cat25c09", CAT25_INFO( 128, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1698 + { "cat25c17", CAT25_INFO( 256, 8, 32, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1699 + { "cat25128", CAT25_INFO(2048, 8, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
1700 + { },
1701 +};
1702 +EXPORT_SYMBOL_GPL(spi_nor_ids);
1703 +
1704 +static const struct spi_device_id *spi_nor_read_id(struct spi_nor *nor)
1705 +{
1706 + int tmp;
1707 + u8 id[5];
1708 + u32 jedec;
1709 + u16 ext_jedec;
1710 + struct flash_info *info;
1711 +
1712 + tmp = nor->read_reg(nor, SPINOR_OP_RDID, id, 5);
1713 + if (tmp < 0) {
1714 + dev_dbg(nor->dev, " error %d reading JEDEC ID\n", tmp);
1715 + return ERR_PTR(tmp);
1716 + }
1717 + jedec = id[0];
1718 + jedec = jedec << 8;
1719 + jedec |= id[1];
1720 + jedec = jedec << 8;
1721 + jedec |= id[2];
1722 +
1723 + ext_jedec = id[3] << 8 | id[4];
1724 +
1725 + for (tmp = 0; tmp < ARRAY_SIZE(spi_nor_ids) - 1; tmp++) {
1726 + info = (void *)spi_nor_ids[tmp].driver_data;
1727 + if (info->jedec_id == jedec) {
1728 + if (info->ext_id == 0 || info->ext_id == ext_jedec)
1729 + return &spi_nor_ids[tmp];
1730 + }
1731 + }
1732 + dev_err(nor->dev, "unrecognized JEDEC id %06x\n", jedec);
1733 + return ERR_PTR(-ENODEV);
1734 +}
1735 +
1736 +static const struct spi_device_id *jedec_probe(struct spi_nor *nor)
1737 +{
1738 + return nor->read_id(nor);
1739 +}
1740 +
1741 +static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
1742 + size_t *retlen, u_char *buf)
1743 +{
1744 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
1745 + int ret;
1746 +
1747 + dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
1748 +
1749 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_READ);
1750 + if (ret)
1751 + return ret;
1752 +
1753 + ret = nor->read(nor, from, len, retlen, buf);
1754 +
1755 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_READ);
1756 + return ret;
1757 +}
1758 +
1759 +static int sst_write(struct mtd_info *mtd, loff_t to, size_t len,
1760 + size_t *retlen, const u_char *buf)
1761 +{
1762 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
1763 + size_t actual;
1764 + int ret;
1765 +
1766 + dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1767 +
1768 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1769 + if (ret)
1770 + return ret;
1771 +
1772 + /* Wait until finished previous write command. */
1773 + ret = wait_till_ready(nor);
1774 + if (ret)
1775 + goto time_out;
1776 +
1777 + write_enable(nor);
1778 +
1779 + nor->sst_write_second = false;
1780 +
1781 + actual = to % 2;
1782 + /* Start write from odd address. */
1783 + if (actual) {
1784 + nor->program_opcode = SPINOR_OP_BP;
1785 +
1786 + /* write one byte. */
1787 + nor->write(nor, to, 1, retlen, buf);
1788 + ret = wait_till_ready(nor);
1789 + if (ret)
1790 + goto time_out;
1791 + }
1792 + to += actual;
1793 +
1794 + /* Write out most of the data here. */
1795 + for (; actual < len - 1; actual += 2) {
1796 + nor->program_opcode = SPINOR_OP_AAI_WP;
1797 +
1798 + /* write two bytes. */
1799 + nor->write(nor, to, 2, retlen, buf + actual);
1800 + ret = wait_till_ready(nor);
1801 + if (ret)
1802 + goto time_out;
1803 + to += 2;
1804 + nor->sst_write_second = true;
1805 + }
1806 + nor->sst_write_second = false;
1807 +
1808 + write_disable(nor);
1809 + ret = wait_till_ready(nor);
1810 + if (ret)
1811 + goto time_out;
1812 +
1813 + /* Write out trailing byte if it exists. */
1814 + if (actual != len) {
1815 + write_enable(nor);
1816 +
1817 + nor->program_opcode = SPINOR_OP_BP;
1818 + nor->write(nor, to, 1, retlen, buf + actual);
1819 +
1820 + ret = wait_till_ready(nor);
1821 + if (ret)
1822 + goto time_out;
1823 + write_disable(nor);
1824 + }
1825 +time_out:
1826 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1827 + return ret;
1828 +}
1829 +
1830 +/*
1831 + * Write an address range to the nor chip. Data must be written in
1832 + * FLASH_PAGESIZE chunks. The address range may be any size provided
1833 + * it is within the physical boundaries.
1834 + */
1835 +static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
1836 + size_t *retlen, const u_char *buf)
1837 +{
1838 + struct spi_nor *nor = mtd_to_spi_nor(mtd);
1839 + u32 page_offset, page_size, i;
1840 + int ret;
1841 +
1842 + dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
1843 +
1844 + ret = spi_nor_lock_and_prep(nor, SPI_NOR_OPS_WRITE);
1845 + if (ret)
1846 + return ret;
1847 +
1848 + /* Wait until finished previous write command. */
1849 + ret = wait_till_ready(nor);
1850 + if (ret)
1851 + goto write_err;
1852 +
1853 + write_enable(nor);
1854 +
1855 + page_offset = to & (nor->page_size - 1);
1856 +
1857 + /* do all the bytes fit onto one page? */
1858 + if (page_offset + len <= nor->page_size) {
1859 + nor->write(nor, to, len, retlen, buf);
1860 + } else {
1861 + /* the size of data remaining on the first page */
1862 + page_size = nor->page_size - page_offset;
1863 + nor->write(nor, to, page_size, retlen, buf);
1864 +
1865 + /* write everything in nor->page_size chunks */
1866 + for (i = page_size; i < len; i += page_size) {
1867 + page_size = len - i;
1868 + if (page_size > nor->page_size)
1869 + page_size = nor->page_size;
1870 +
1871 + wait_till_ready(nor);
1872 + write_enable(nor);
1873 +
1874 + nor->write(nor, to + i, page_size, retlen, buf + i);
1875 + }
1876 + }
1877 +
1878 +write_err:
1879 + spi_nor_unlock_and_unprep(nor, SPI_NOR_OPS_WRITE);
1880 + return 0;
1881 +}
1882 +
1883 +static int macronix_quad_enable(struct spi_nor *nor)
1884 +{
1885 + int ret, val;
1886 +
1887 + val = read_sr(nor);
1888 + write_enable(nor);
1889 +
1890 + nor->cmd_buf[0] = val | SR_QUAD_EN_MX;
1891 + nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 1, 0);
1892 +
1893 + if (wait_till_ready(nor))
1894 + return 1;
1895 +
1896 + ret = read_sr(nor);
1897 + if (!(ret > 0 && (ret & SR_QUAD_EN_MX))) {
1898 + dev_err(nor->dev, "Macronix Quad bit not set\n");
1899 + return -EINVAL;
1900 + }
1901 +
1902 + return 0;
1903 +}
1904 +
1905 +/*
1906 + * Write status Register and configuration register with 2 bytes
1907 + * The first byte will be written to the status register, while the
1908 + * second byte will be written to the configuration register.
1909 + * Return negative if error occured.
1910 + */
1911 +static int write_sr_cr(struct spi_nor *nor, u16 val)
1912 +{
1913 + nor->cmd_buf[0] = val & 0xff;
1914 + nor->cmd_buf[1] = (val >> 8);
1915 +
1916 + return nor->write_reg(nor, SPINOR_OP_WRSR, nor->cmd_buf, 2, 0);
1917 +}
1918 +
1919 +static int spansion_quad_enable(struct spi_nor *nor)
1920 +{
1921 + int ret;
1922 + int quad_en = CR_QUAD_EN_SPAN << 8;
1923 +
1924 + write_enable(nor);
1925 +
1926 + ret = write_sr_cr(nor, quad_en);
1927 + if (ret < 0) {
1928 + dev_err(nor->dev,
1929 + "error while writing configuration register\n");
1930 + return -EINVAL;
1931 + }
1932 +
1933 + /* read back and check it */
1934 + ret = read_cr(nor);
1935 + if (!(ret > 0 && (ret & CR_QUAD_EN_SPAN))) {
1936 + dev_err(nor->dev, "Spansion Quad bit not set\n");
1937 + return -EINVAL;
1938 + }
1939 +
1940 + return 0;
1941 +}
1942 +
1943 +static int set_quad_mode(struct spi_nor *nor, u32 jedec_id)
1944 +{
1945 + int status;
1946 +
1947 + switch (JEDEC_MFR(jedec_id)) {
1948 + case CFI_MFR_MACRONIX:
1949 + status = macronix_quad_enable(nor);
1950 + if (status) {
1951 + dev_err(nor->dev, "Macronix quad-read not enabled\n");
1952 + return -EINVAL;
1953 + }
1954 + return status;
1955 + default:
1956 + status = spansion_quad_enable(nor);
1957 + if (status) {
1958 + dev_err(nor->dev, "Spansion quad-read not enabled\n");
1959 + return -EINVAL;
1960 + }
1961 + return status;
1962 + }
1963 +}
1964 +
1965 +static int spi_nor_check(struct spi_nor *nor)
1966 +{
1967 + if (!nor->dev || !nor->read || !nor->write ||
1968 + !nor->read_reg || !nor->write_reg || !nor->erase) {
1969 + pr_err("spi-nor: please fill all the necessary fields!\n");
1970 + return -EINVAL;
1971 + }
1972 +
1973 + if (!nor->read_id)
1974 + nor->read_id = spi_nor_read_id;
1975 + if (!nor->wait_till_ready)
1976 + nor->wait_till_ready = spi_nor_wait_till_ready;
1977 +
1978 + return 0;
1979 +}
1980 +
1981 +int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
1982 + enum read_mode mode)
1983 +{
1984 + struct flash_info *info;
1985 + struct flash_platform_data *data;
1986 + struct device *dev = nor->dev;
1987 + struct mtd_info *mtd = nor->mtd;
1988 + struct device_node *np = dev->of_node;
1989 + int ret;
1990 + int i;
1991 +
1992 + ret = spi_nor_check(nor);
1993 + if (ret)
1994 + return ret;
1995 +
1996 + /* Platform data helps sort out which chip type we have, as
1997 + * well as how this board partitions it. If we don't have
1998 + * a chip ID, try the JEDEC id commands; they'll work for most
1999 + * newer chips, even if we don't recognize the particular chip.
2000 + */
2001 + data = dev_get_platdata(dev);
2002 + if (data && data->type) {
2003 + const struct spi_device_id *plat_id;
2004 +
2005 + for (i = 0; i < ARRAY_SIZE(spi_nor_ids) - 1; i++) {
2006 + plat_id = &spi_nor_ids[i];
2007 + if (strcmp(data->type, plat_id->name))
2008 + continue;
2009 + break;
2010 + }
2011 +
2012 + if (i < ARRAY_SIZE(spi_nor_ids) - 1)
2013 + id = plat_id;
2014 + else
2015 + dev_warn(dev, "unrecognized id %s\n", data->type);
2016 + }
2017 +
2018 + info = (void *)id->driver_data;
2019 +
2020 + if (info->jedec_id) {
2021 + const struct spi_device_id *jid;
2022 +
2023 + jid = jedec_probe(nor);
2024 + if (IS_ERR(jid)) {
2025 + return PTR_ERR(jid);
2026 + } else if (jid != id) {
2027 + /*
2028 + * JEDEC knows better, so overwrite platform ID. We
2029 + * can't trust partitions any longer, but we'll let
2030 + * mtd apply them anyway, since some partitions may be
2031 + * marked read-only, and we don't want to lose that
2032 + * information, even if it's not 100% accurate.
2033 + */
2034 + dev_warn(dev, "found %s, expected %s\n",
2035 + jid->name, id->name);
2036 + id = jid;
2037 + info = (void *)jid->driver_data;
2038 + }
2039 + }
2040 +
2041 + mutex_init(&nor->lock);
2042 +
2043 + /*
2044 + * Atmel, SST and Intel/Numonyx serial nor tend to power
2045 + * up with the software protection bits set
2046 + */
2047 +
2048 + if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ATMEL ||
2049 + JEDEC_MFR(info->jedec_id) == CFI_MFR_INTEL ||
2050 + JEDEC_MFR(info->jedec_id) == CFI_MFR_SST) {
2051 + write_enable(nor);
2052 + write_sr(nor, 0);
2053 + }
2054 +
2055 + if (data && data->name)
2056 + mtd->name = data->name;
2057 + else
2058 + mtd->name = dev_name(dev);
2059 +
2060 + mtd->type = MTD_NORFLASH;
2061 + mtd->writesize = 1;
2062 + mtd->flags = MTD_CAP_NORFLASH;
2063 + mtd->size = info->sector_size * info->n_sectors;
2064 + mtd->_erase = spi_nor_erase;
2065 + mtd->_read = spi_nor_read;
2066 +
2067 + /* nor protection support for STmicro chips */
2068 + if (JEDEC_MFR(info->jedec_id) == CFI_MFR_ST) {
2069 + mtd->_lock = spi_nor_lock;
2070 + mtd->_unlock = spi_nor_unlock;
2071 + }
2072 +
2073 + /* sst nor chips use AAI word program */
2074 + if (info->flags & SST_WRITE)
2075 + mtd->_write = sst_write;
2076 + else
2077 + mtd->_write = spi_nor_write;
2078 +
2079 + if ((info->flags & USE_FSR) &&
2080 + nor->wait_till_ready == spi_nor_wait_till_ready)
2081 + nor->wait_till_ready = spi_nor_wait_till_fsr_ready;
2082 +
2083 + /* prefer "small sector" erase if possible */
2084 + if (info->flags & SECT_4K) {
2085 + nor->erase_opcode = SPINOR_OP_BE_4K;
2086 + mtd->erasesize = 4096;
2087 + } else if (info->flags & SECT_4K_PMC) {
2088 + nor->erase_opcode = SPINOR_OP_BE_4K_PMC;
2089 + mtd->erasesize = 4096;
2090 + } else {
2091 + nor->erase_opcode = SPINOR_OP_SE;
2092 + mtd->erasesize = info->sector_size;
2093 + }
2094 +
2095 + if (info->flags & SPI_NOR_NO_ERASE)
2096 + mtd->flags |= MTD_NO_ERASE;
2097 +
2098 + mtd->dev.parent = dev;
2099 + nor->page_size = info->page_size;
2100 + mtd->writebufsize = nor->page_size;
2101 +
2102 + if (np) {
2103 + /* If we were instantiated by DT, use it */
2104 + if (of_property_read_bool(np, "m25p,fast-read"))
2105 + nor->flash_read = SPI_NOR_FAST;
2106 + else
2107 + nor->flash_read = SPI_NOR_NORMAL;
2108 + } else {
2109 + /* If we weren't instantiated by DT, default to fast-read */
2110 + nor->flash_read = SPI_NOR_FAST;
2111 + }
2112 +
2113 + /* Some devices cannot do fast-read, no matter what DT tells us */
2114 + if (info->flags & SPI_NOR_NO_FR)
2115 + nor->flash_read = SPI_NOR_NORMAL;
2116 +
2117 + /* Quad/Dual-read mode takes precedence over fast/normal */
2118 + if (mode == SPI_NOR_QUAD && info->flags & SPI_NOR_QUAD_READ) {
2119 + ret = set_quad_mode(nor, info->jedec_id);
2120 + if (ret) {
2121 + dev_err(dev, "quad mode not supported\n");
2122 + return ret;
2123 + }
2124 + nor->flash_read = SPI_NOR_QUAD;
2125 + } else if (mode == SPI_NOR_DUAL && info->flags & SPI_NOR_DUAL_READ) {
2126 + nor->flash_read = SPI_NOR_DUAL;
2127 + }
2128 +
2129 + /* Default commands */
2130 + switch (nor->flash_read) {
2131 + case SPI_NOR_QUAD:
2132 + nor->read_opcode = SPINOR_OP_READ_1_1_4;
2133 + break;
2134 + case SPI_NOR_DUAL:
2135 + nor->read_opcode = SPINOR_OP_READ_1_1_2;
2136 + break;
2137 + case SPI_NOR_FAST:
2138 + nor->read_opcode = SPINOR_OP_READ_FAST;
2139 + break;
2140 + case SPI_NOR_NORMAL:
2141 + nor->read_opcode = SPINOR_OP_READ;
2142 + break;
2143 + default:
2144 + dev_err(dev, "No Read opcode defined\n");
2145 + return -EINVAL;
2146 + }
2147 +
2148 + nor->program_opcode = SPINOR_OP_PP;
2149 +
2150 + if (info->addr_width)
2151 + nor->addr_width = info->addr_width;
2152 + else if (mtd->size > 0x1000000) {
2153 + /* enable 4-byte addressing if the device exceeds 16MiB */
2154 + nor->addr_width = 4;
2155 + if (JEDEC_MFR(info->jedec_id) == CFI_MFR_AMD) {
2156 + /* Dedicated 4-byte command set */
2157 + switch (nor->flash_read) {
2158 + case SPI_NOR_QUAD:
2159 + nor->read_opcode = SPINOR_OP_READ4_1_1_4;
2160 + break;
2161 + case SPI_NOR_DUAL:
2162 + nor->read_opcode = SPINOR_OP_READ4_1_1_2;
2163 + break;
2164 + case SPI_NOR_FAST:
2165 + nor->read_opcode = SPINOR_OP_READ4_FAST;
2166 + break;
2167 + case SPI_NOR_NORMAL:
2168 + nor->read_opcode = SPINOR_OP_READ4;
2169 + break;
2170 + }
2171 + nor->program_opcode = SPINOR_OP_PP_4B;
2172 + /* No small sector erase for 4-byte command set */
2173 + nor->erase_opcode = SPINOR_OP_SE_4B;
2174 + mtd->erasesize = info->sector_size;
2175 + } else
2176 + set_4byte(nor, info->jedec_id, 1);
2177 + } else {
2178 + nor->addr_width = 3;
2179 + }
2180 +
2181 + nor->read_dummy = spi_nor_read_dummy_cycles(nor);
2182 +
2183 + dev_info(dev, "%s (%lld Kbytes)\n", id->name,
2184 + (long long)mtd->size >> 10);
2185 +
2186 + dev_dbg(dev,
2187 + "mtd .name = %s, .size = 0x%llx (%lldMiB), "
2188 + ".erasesize = 0x%.8x (%uKiB) .numeraseregions = %d\n",
2189 + mtd->name, (long long)mtd->size, (long long)(mtd->size >> 20),
2190 + mtd->erasesize, mtd->erasesize / 1024, mtd->numeraseregions);
2191 +
2192 + if (mtd->numeraseregions)
2193 + for (i = 0; i < mtd->numeraseregions; i++)
2194 + dev_dbg(dev,
2195 + "mtd.eraseregions[%d] = { .offset = 0x%llx, "
2196 + ".erasesize = 0x%.8x (%uKiB), "
2197 + ".numblocks = %d }\n",
2198 + i, (long long)mtd->eraseregions[i].offset,
2199 + mtd->eraseregions[i].erasesize,
2200 + mtd->eraseregions[i].erasesize / 1024,
2201 + mtd->eraseregions[i].numblocks);
2202 + return 0;
2203 +}
2204 +EXPORT_SYMBOL_GPL(spi_nor_scan);
2205 +
2206 +const struct spi_device_id *spi_nor_match_id(char *name)
2207 +{
2208 + const struct spi_device_id *id = spi_nor_ids;
2209 +
2210 + while (id->name[0]) {
2211 + if (!strcmp(name, id->name))
2212 + return id;
2213 + id++;
2214 + }
2215 + return NULL;
2216 +}
2217 +EXPORT_SYMBOL_GPL(spi_nor_match_id);
2218 +
2219 +MODULE_LICENSE("GPL");
2220 +MODULE_AUTHOR("Huang Shijie <shijie8@gmail.com>");
2221 +MODULE_AUTHOR("Mike Lavender");
2222 +MODULE_DESCRIPTION("framework for SPI NOR");
2223 --- /dev/null
2224 +++ b/include/linux/mtd/spi-nor.h
2225 @@ -0,0 +1,218 @@
2226 +/*
2227 + * Copyright (C) 2014 Freescale Semiconductor, Inc.
2228 + *
2229 + * This program is free software; you can redistribute it and/or modify
2230 + * it under the terms of the GNU General Public License as published by
2231 + * the Free Software Foundation; either version 2 of the License, or
2232 + * (at your option) any later version.
2233 + */
2234 +
2235 +#ifndef __LINUX_MTD_SPI_NOR_H
2236 +#define __LINUX_MTD_SPI_NOR_H
2237 +
2238 +/*
2239 + * Note on opcode nomenclature: some opcodes have a format like
2240 + * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
2241 + * of I/O lines used for the opcode, address, and data (respectively). The
2242 + * FUNCTION has an optional suffix of '4', to represent an opcode which
2243 + * requires a 4-byte (32-bit) address.
2244 + */
2245 +
2246 +/* Flash opcodes. */
2247 +#define SPINOR_OP_WREN 0x06 /* Write enable */
2248 +#define SPINOR_OP_RDSR 0x05 /* Read status register */
2249 +#define SPINOR_OP_WRSR 0x01 /* Write status register 1 byte */
2250 +#define SPINOR_OP_READ 0x03 /* Read data bytes (low frequency) */
2251 +#define SPINOR_OP_READ_FAST 0x0b /* Read data bytes (high frequency) */
2252 +#define SPINOR_OP_READ_1_1_2 0x3b /* Read data bytes (Dual SPI) */
2253 +#define SPINOR_OP_READ_1_1_4 0x6b /* Read data bytes (Quad SPI) */
2254 +#define SPINOR_OP_PP 0x02 /* Page program (up to 256 bytes) */
2255 +#define SPINOR_OP_BE_4K 0x20 /* Erase 4KiB block */
2256 +#define SPINOR_OP_BE_4K_PMC 0xd7 /* Erase 4KiB block on PMC chips */
2257 +#define SPINOR_OP_BE_32K 0x52 /* Erase 32KiB block */
2258 +#define SPINOR_OP_CHIP_ERASE 0xc7 /* Erase whole flash chip */
2259 +#define SPINOR_OP_SE 0xd8 /* Sector erase (usually 64KiB) */
2260 +#define SPINOR_OP_RDID 0x9f /* Read JEDEC ID */
2261 +#define SPINOR_OP_RDCR 0x35 /* Read configuration register */
2262 +#define SPINOR_OP_RDFSR 0x70 /* Read flag status register */
2263 +
2264 +/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
2265 +#define SPINOR_OP_READ4 0x13 /* Read data bytes (low frequency) */
2266 +#define SPINOR_OP_READ4_FAST 0x0c /* Read data bytes (high frequency) */
2267 +#define SPINOR_OP_READ4_1_1_2 0x3c /* Read data bytes (Dual SPI) */
2268 +#define SPINOR_OP_READ4_1_1_4 0x6c /* Read data bytes (Quad SPI) */
2269 +#define SPINOR_OP_PP_4B 0x12 /* Page program (up to 256 bytes) */
2270 +#define SPINOR_OP_SE_4B 0xdc /* Sector erase (usually 64KiB) */
2271 +
2272 +/* Used for SST flashes only. */
2273 +#define SPINOR_OP_BP 0x02 /* Byte program */
2274 +#define SPINOR_OP_WRDI 0x04 /* Write disable */
2275 +#define SPINOR_OP_AAI_WP 0xad /* Auto address increment word program */
2276 +
2277 +/* Used for Macronix and Winbond flashes. */
2278 +#define SPINOR_OP_EN4B 0xb7 /* Enter 4-byte mode */
2279 +#define SPINOR_OP_EX4B 0xe9 /* Exit 4-byte mode */
2280 +
2281 +/* Used for Spansion flashes only. */
2282 +#define SPINOR_OP_BRWR 0x17 /* Bank register write */
2283 +
2284 +/* Status Register bits. */
2285 +#define SR_WIP 1 /* Write in progress */
2286 +#define SR_WEL 2 /* Write enable latch */
2287 +/* meaning of other SR_* bits may differ between vendors */
2288 +#define SR_BP0 4 /* Block protect 0 */
2289 +#define SR_BP1 8 /* Block protect 1 */
2290 +#define SR_BP2 0x10 /* Block protect 2 */
2291 +#define SR_SRWD 0x80 /* SR write protect */
2292 +
2293 +#define SR_QUAD_EN_MX 0x40 /* Macronix Quad I/O */
2294 +
2295 +/* Flag Status Register bits */
2296 +#define FSR_READY 0x80
2297 +
2298 +/* Configuration Register bits. */
2299 +#define CR_QUAD_EN_SPAN 0x2 /* Spansion Quad I/O */
2300 +
2301 +enum read_mode {
2302 + SPI_NOR_NORMAL = 0,
2303 + SPI_NOR_FAST,
2304 + SPI_NOR_DUAL,
2305 + SPI_NOR_QUAD,
2306 +};
2307 +
2308 +/**
2309 + * struct spi_nor_xfer_cfg - Structure for defining a Serial Flash transfer
2310 + * @wren: command for "Write Enable", or 0x00 for not required
2311 + * @cmd: command for operation
2312 + * @cmd_pins: number of pins to send @cmd (1, 2, 4)
2313 + * @addr: address for operation
2314 + * @addr_pins: number of pins to send @addr (1, 2, 4)
2315 + * @addr_width: number of address bytes
2316 + * (3,4, or 0 for address not required)
2317 + * @mode: mode data
2318 + * @mode_pins: number of pins to send @mode (1, 2, 4)
2319 + * @mode_cycles: number of mode cycles (0 for mode not required)
2320 + * @dummy_cycles: number of dummy cycles (0 for dummy not required)
2321 + */
2322 +struct spi_nor_xfer_cfg {
2323 + u8 wren;
2324 + u8 cmd;
2325 + u8 cmd_pins;
2326 + u32 addr;
2327 + u8 addr_pins;
2328 + u8 addr_width;
2329 + u8 mode;
2330 + u8 mode_pins;
2331 + u8 mode_cycles;
2332 + u8 dummy_cycles;
2333 +};
2334 +
2335 +#define SPI_NOR_MAX_CMD_SIZE 8
2336 +enum spi_nor_ops {
2337 + SPI_NOR_OPS_READ = 0,
2338 + SPI_NOR_OPS_WRITE,
2339 + SPI_NOR_OPS_ERASE,
2340 + SPI_NOR_OPS_LOCK,
2341 + SPI_NOR_OPS_UNLOCK,
2342 +};
2343 +
2344 +/**
2345 + * struct spi_nor - Structure for defining a the SPI NOR layer
2346 + * @mtd: point to a mtd_info structure
2347 + * @lock: the lock for the read/write/erase/lock/unlock operations
2348 + * @dev: point to a spi device, or a spi nor controller device.
2349 + * @page_size: the page size of the SPI NOR
2350 + * @addr_width: number of address bytes
2351 + * @erase_opcode: the opcode for erasing a sector
2352 + * @read_opcode: the read opcode
2353 + * @read_dummy: the dummy needed by the read operation
2354 + * @program_opcode: the program opcode
2355 + * @flash_read: the mode of the read
2356 + * @sst_write_second: used by the SST write operation
2357 + * @cfg: used by the read_xfer/write_xfer
2358 + * @cmd_buf: used by the write_reg
2359 + * @prepare: [OPTIONAL] do some preparations for the
2360 + * read/write/erase/lock/unlock operations
2361 + * @unprepare: [OPTIONAL] do some post work after the
2362 + * read/write/erase/lock/unlock operations
2363 + * @read_xfer: [OPTIONAL] the read fundamental primitive
2364 + * @write_xfer: [OPTIONAL] the writefundamental primitive
2365 + * @read_reg: [DRIVER-SPECIFIC] read out the register
2366 + * @write_reg: [DRIVER-SPECIFIC] write data to the register
2367 + * @read_id: [REPLACEABLE] read out the ID data, and find
2368 + * the proper spi_device_id
2369 + * @wait_till_ready: [REPLACEABLE] wait till the NOR becomes ready
2370 + * @read: [DRIVER-SPECIFIC] read data from the SPI NOR
2371 + * @write: [DRIVER-SPECIFIC] write data to the SPI NOR
2372 + * @erase: [DRIVER-SPECIFIC] erase a sector of the SPI NOR
2373 + * at the offset @offs
2374 + * @priv: the private data
2375 + */
2376 +struct spi_nor {
2377 + struct mtd_info *mtd;
2378 + struct mutex lock;
2379 + struct device *dev;
2380 + u32 page_size;
2381 + u8 addr_width;
2382 + u8 erase_opcode;
2383 + u8 read_opcode;
2384 + u8 read_dummy;
2385 + u8 program_opcode;
2386 + enum read_mode flash_read;
2387 + bool sst_write_second;
2388 + struct spi_nor_xfer_cfg cfg;
2389 + u8 cmd_buf[SPI_NOR_MAX_CMD_SIZE];
2390 +
2391 + int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
2392 + void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
2393 + int (*read_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
2394 + u8 *buf, size_t len);
2395 + int (*write_xfer)(struct spi_nor *nor, struct spi_nor_xfer_cfg *cfg,
2396 + u8 *buf, size_t len);
2397 + int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
2398 + int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len,
2399 + int write_enable);
2400 + const struct spi_device_id *(*read_id)(struct spi_nor *nor);
2401 + int (*wait_till_ready)(struct spi_nor *nor);
2402 +
2403 + int (*read)(struct spi_nor *nor, loff_t from,
2404 + size_t len, size_t *retlen, u_char *read_buf);
2405 + void (*write)(struct spi_nor *nor, loff_t to,
2406 + size_t len, size_t *retlen, const u_char *write_buf);
2407 + int (*erase)(struct spi_nor *nor, loff_t offs);
2408 +
2409 + void *priv;
2410 +};
2411 +
2412 +/**
2413 + * spi_nor_scan() - scan the SPI NOR
2414 + * @nor: the spi_nor structure
2415 + * @id: the spi_device_id provided by the driver
2416 + * @mode: the read mode supported by the driver
2417 + *
2418 + * The drivers can use this fuction to scan the SPI NOR.
2419 + * In the scanning, it will try to get all the necessary information to
2420 + * fill the mtd_info{} and the spi_nor{}.
2421 + *
2422 + * The board may assigns a spi_device_id with @id which be used to compared with
2423 + * the spi_device_id detected by the scanning.
2424 + *
2425 + * Return: 0 for success, others for failure.
2426 + */
2427 +int spi_nor_scan(struct spi_nor *nor, const struct spi_device_id *id,
2428 + enum read_mode mode);
2429 +extern const struct spi_device_id spi_nor_ids[];
2430 +
2431 +/**
2432 + * spi_nor_match_id() - find the spi_device_id by the name
2433 + * @name: the name of the spi_device_id
2434 + *
2435 + * The drivers use this function to find the spi_device_id
2436 + * specified by the @name.
2437 + *
2438 + * Return: returns the right spi_device_id pointer on success,
2439 + * and returns NULL on failure.
2440 + */
2441 +const struct spi_device_id *spi_nor_match_id(char *name);
2442 +
2443 +#endif
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