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ixp4xx: remove linux 3.10 support
[openwrt/svn-archive/archive.git] / target / linux / brcm2708 / patches-3.10 / 0001-Main-bcm2708-linux-port.patch
1 From 8775cd3a02a2eb38e20465b0ca5db05de1f75125 Mon Sep 17 00:00:00 2001
2 From: popcornmix <popcornmix@gmail.com>
3 Date: Sun, 12 May 2013 12:24:19 +0100
4 Subject: [PATCH 001/196] Main bcm2708 linux port
5
6 Signed-off-by: popcornmix <popcornmix@gmail.com>
7 ---
8 arch/arm/Kconfig | 16 +
9 arch/arm/Kconfig.debug | 8 +
10 arch/arm/Makefile | 1 +
11 arch/arm/configs/bcmrpi_cutdown_defconfig | 474 +++++++
12 arch/arm/configs/bcmrpi_defconfig | 510 ++++++++
13 arch/arm/configs/bcmrpi_emergency_defconfig | 532 ++++++++
14 arch/arm/kernel/process.c | 2 +-
15 arch/arm/mach-bcm2708/Kconfig | 34 +
16 arch/arm/mach-bcm2708/Makefile | 8 +
17 arch/arm/mach-bcm2708/Makefile.boot | 3 +
18 arch/arm/mach-bcm2708/armctrl.c | 208 ++++
19 arch/arm/mach-bcm2708/armctrl.h | 27 +
20 arch/arm/mach-bcm2708/bcm2708.c | 695 +++++++++++
21 arch/arm/mach-bcm2708/bcm2708.h | 51 +
22 arch/arm/mach-bcm2708/bcm2708_gpio.c | 339 +++++
23 arch/arm/mach-bcm2708/clock.c | 61 +
24 arch/arm/mach-bcm2708/clock.h | 24 +
25 arch/arm/mach-bcm2708/dma.c | 399 ++++++
26 arch/arm/mach-bcm2708/include/mach/arm_control.h | 419 +++++++
27 arch/arm/mach-bcm2708/include/mach/arm_power.h | 60 +
28 arch/arm/mach-bcm2708/include/mach/clkdev.h | 7 +
29 arch/arm/mach-bcm2708/include/mach/debug-macro.S | 22 +
30 arch/arm/mach-bcm2708/include/mach/dma.h | 86 ++
31 arch/arm/mach-bcm2708/include/mach/entry-macro.S | 69 ++
32 arch/arm/mach-bcm2708/include/mach/frc.h | 38 +
33 arch/arm/mach-bcm2708/include/mach/gpio.h | 18 +
34 arch/arm/mach-bcm2708/include/mach/hardware.h | 28 +
35 arch/arm/mach-bcm2708/include/mach/io.h | 27 +
36 arch/arm/mach-bcm2708/include/mach/irqs.h | 196 +++
37 arch/arm/mach-bcm2708/include/mach/memory.h | 57 +
38 arch/arm/mach-bcm2708/include/mach/platform.h | 220 ++++
39 arch/arm/mach-bcm2708/include/mach/power.h | 26 +
40 arch/arm/mach-bcm2708/include/mach/system.h | 38 +
41 arch/arm/mach-bcm2708/include/mach/timex.h | 23 +
42 arch/arm/mach-bcm2708/include/mach/uncompress.h | 85 ++
43 arch/arm/mach-bcm2708/include/mach/vc_mem.h | 36 +
44 arch/arm/mach-bcm2708/include/mach/vcio.h | 141 +++
45 arch/arm/mach-bcm2708/include/mach/vmalloc.h | 20 +
46 arch/arm/mach-bcm2708/power.c | 194 +++
47 arch/arm/mach-bcm2708/vc_mem.c | 462 +++++++
48 arch/arm/mach-bcm2708/vcio.c | 474 +++++++
49 arch/arm/mm/Kconfig | 2 +-
50 arch/arm/mm/proc-v6.S | 15 +-
51 arch/arm/tools/mach-types | 1 +
52 drivers/mmc/host/Kconfig | 21 +
53 drivers/mmc/host/Makefile | 1 +
54 drivers/mmc/host/sdhci-bcm2708.c | 1425 ++++++++++++++++++++++
55 drivers/mmc/host/sdhci.c | 209 +++-
56 drivers/mmc/host/sdhci.h | 37 +
57 include/linux/mmc/sdhci.h | 2 +
58 50 files changed, 7779 insertions(+), 72 deletions(-)
59 create mode 100644 arch/arm/configs/bcmrpi_cutdown_defconfig
60 create mode 100644 arch/arm/configs/bcmrpi_defconfig
61 create mode 100644 arch/arm/configs/bcmrpi_emergency_defconfig
62 create mode 100644 arch/arm/mach-bcm2708/Kconfig
63 create mode 100644 arch/arm/mach-bcm2708/Makefile
64 create mode 100644 arch/arm/mach-bcm2708/Makefile.boot
65 create mode 100644 arch/arm/mach-bcm2708/armctrl.c
66 create mode 100644 arch/arm/mach-bcm2708/armctrl.h
67 create mode 100644 arch/arm/mach-bcm2708/bcm2708.c
68 create mode 100644 arch/arm/mach-bcm2708/bcm2708.h
69 create mode 100644 arch/arm/mach-bcm2708/bcm2708_gpio.c
70 create mode 100644 arch/arm/mach-bcm2708/clock.c
71 create mode 100644 arch/arm/mach-bcm2708/clock.h
72 create mode 100644 arch/arm/mach-bcm2708/dma.c
73 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_control.h
74 create mode 100644 arch/arm/mach-bcm2708/include/mach/arm_power.h
75 create mode 100644 arch/arm/mach-bcm2708/include/mach/clkdev.h
76 create mode 100644 arch/arm/mach-bcm2708/include/mach/debug-macro.S
77 create mode 100644 arch/arm/mach-bcm2708/include/mach/dma.h
78 create mode 100644 arch/arm/mach-bcm2708/include/mach/entry-macro.S
79 create mode 100644 arch/arm/mach-bcm2708/include/mach/frc.h
80 create mode 100644 arch/arm/mach-bcm2708/include/mach/gpio.h
81 create mode 100644 arch/arm/mach-bcm2708/include/mach/hardware.h
82 create mode 100644 arch/arm/mach-bcm2708/include/mach/io.h
83 create mode 100644 arch/arm/mach-bcm2708/include/mach/irqs.h
84 create mode 100644 arch/arm/mach-bcm2708/include/mach/memory.h
85 create mode 100644 arch/arm/mach-bcm2708/include/mach/platform.h
86 create mode 100644 arch/arm/mach-bcm2708/include/mach/power.h
87 create mode 100644 arch/arm/mach-bcm2708/include/mach/system.h
88 create mode 100644 arch/arm/mach-bcm2708/include/mach/timex.h
89 create mode 100644 arch/arm/mach-bcm2708/include/mach/uncompress.h
90 create mode 100644 arch/arm/mach-bcm2708/include/mach/vc_mem.h
91 create mode 100644 arch/arm/mach-bcm2708/include/mach/vcio.h
92 create mode 100644 arch/arm/mach-bcm2708/include/mach/vmalloc.h
93 create mode 100644 arch/arm/mach-bcm2708/power.c
94 create mode 100644 arch/arm/mach-bcm2708/vc_mem.c
95 create mode 100644 arch/arm/mach-bcm2708/vcio.c
96 create mode 100644 drivers/mmc/host/sdhci-bcm2708.c
97
98 diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
99 index 18a9f5e..eb291c7 100644
100 --- a/arch/arm/Kconfig
101 +++ b/arch/arm/Kconfig
102 @@ -361,6 +361,21 @@ config ARCH_AT91
103 This enables support for systems based on Atmel
104 AT91RM9200 and AT91SAM9* processors.
105
106 +config ARCH_BCM2708
107 + bool "Broadcom BCM2708 family"
108 + select CPU_V6
109 + select ARM_AMBA
110 + select HAVE_CLK
111 + select HAVE_SCHED_CLOCK
112 + select NEED_MACH_MEMORY_H
113 + select CLKDEV_LOOKUP
114 + select GENERIC_CLOCKEVENTS
115 + select ARM_ERRATA_411920
116 + select MACH_BCM2708
117 + select VC4
118 + help
119 + This enables support for Broadcom BCM2708 boards.
120 +
121 config ARCH_CLPS711X
122 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
123 select ARCH_REQUIRE_GPIOLIB
124 @@ -1025,6 +1040,7 @@ source "arch/arm/mach-virt/Kconfig"
125 source "arch/arm/mach-vt8500/Kconfig"
126
127 source "arch/arm/mach-w90x900/Kconfig"
128 +source "arch/arm/mach-bcm2708/Kconfig"
129
130 source "arch/arm/mach-zynq/Kconfig"
131
132 diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
133 index 1d41908..52377c9 100644
134 --- a/arch/arm/Kconfig.debug
135 +++ b/arch/arm/Kconfig.debug
136 @@ -519,6 +519,14 @@ choice
137 For more details about semihosting, please see
138 chapter 8 of DUI0203I_rvct_developer_guide.pdf from ARM Ltd.
139
140 + config DEBUG_BCM2708_UART0
141 + bool "Broadcom BCM2708 UART0 (PL011)"
142 + depends on MACH_BCM2708
143 + help
144 + Say Y here if you want the debug print routines to direct
145 + their output to UART 0. The port must have been initialised
146 + by the boot-loader before use.
147 +
148 endchoice
149
150 config DEBUG_EXYNOS_UART
151 diff --git a/arch/arm/Makefile b/arch/arm/Makefile
152 index 1ba358b..fb73cf0 100644
153 --- a/arch/arm/Makefile
154 +++ b/arch/arm/Makefile
155 @@ -139,6 +139,7 @@ textofs-$(CONFIG_ARCH_MSM8960) := 0x00208000
156 # by CONFIG_* macro name.
157 machine-$(CONFIG_ARCH_AT91) += at91
158 machine-$(CONFIG_ARCH_BCM) += bcm
159 +machine-$(CONFIG_ARCH_BCM2708) += bcm2708
160 machine-$(CONFIG_ARCH_BCM2835) += bcm2835
161 machine-$(CONFIG_ARCH_CLPS711X) += clps711x
162 machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx
163 diff --git a/arch/arm/configs/bcmrpi_cutdown_defconfig b/arch/arm/configs/bcmrpi_cutdown_defconfig
164 new file mode 100644
165 index 0000000..74f2dc9
166 --- /dev/null
167 +++ b/arch/arm/configs/bcmrpi_cutdown_defconfig
168 @@ -0,0 +1,474 @@
169 +CONFIG_EXPERIMENTAL=y
170 +# CONFIG_LOCALVERSION_AUTO is not set
171 +CONFIG_SYSVIPC=y
172 +CONFIG_POSIX_MQUEUE=y
173 +CONFIG_IKCONFIG=y
174 +CONFIG_IKCONFIG_PROC=y
175 +# CONFIG_UID16 is not set
176 +# CONFIG_KALLSYMS is not set
177 +CONFIG_EMBEDDED=y
178 +# CONFIG_VM_EVENT_COUNTERS is not set
179 +# CONFIG_COMPAT_BRK is not set
180 +CONFIG_SLAB=y
181 +CONFIG_MODULES=y
182 +CONFIG_MODULE_UNLOAD=y
183 +CONFIG_MODVERSIONS=y
184 +CONFIG_MODULE_SRCVERSION_ALL=y
185 +# CONFIG_BLK_DEV_BSG is not set
186 +CONFIG_ARCH_BCM2708=y
187 +CONFIG_NO_HZ=y
188 +CONFIG_HIGH_RES_TIMERS=y
189 +CONFIG_AEABI=y
190 +CONFIG_ZBOOT_ROM_TEXT=0x0
191 +CONFIG_ZBOOT_ROM_BSS=0x0
192 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
193 +CONFIG_CPU_IDLE=y
194 +CONFIG_VFP=y
195 +CONFIG_BINFMT_MISC=m
196 +CONFIG_NET=y
197 +CONFIG_PACKET=y
198 +CONFIG_UNIX=y
199 +CONFIG_XFRM_USER=y
200 +CONFIG_NET_KEY=m
201 +CONFIG_INET=y
202 +CONFIG_IP_MULTICAST=y
203 +CONFIG_IP_PNP=y
204 +CONFIG_IP_PNP_DHCP=y
205 +CONFIG_IP_PNP_RARP=y
206 +CONFIG_SYN_COOKIES=y
207 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
208 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
209 +# CONFIG_INET_XFRM_MODE_BEET is not set
210 +# CONFIG_INET_LRO is not set
211 +# CONFIG_INET_DIAG is not set
212 +# CONFIG_IPV6 is not set
213 +CONFIG_NET_PKTGEN=m
214 +CONFIG_IRDA=m
215 +CONFIG_IRLAN=m
216 +CONFIG_IRCOMM=m
217 +CONFIG_IRDA_ULTRA=y
218 +CONFIG_IRDA_CACHE_LAST_LSAP=y
219 +CONFIG_IRDA_FAST_RR=y
220 +CONFIG_IRTTY_SIR=m
221 +CONFIG_KINGSUN_DONGLE=m
222 +CONFIG_KSDAZZLE_DONGLE=m
223 +CONFIG_KS959_DONGLE=m
224 +CONFIG_USB_IRDA=m
225 +CONFIG_SIGMATEL_FIR=m
226 +CONFIG_MCS_FIR=m
227 +CONFIG_BT=m
228 +CONFIG_BT_L2CAP=y
229 +CONFIG_BT_SCO=y
230 +CONFIG_BT_RFCOMM=m
231 +CONFIG_BT_RFCOMM_TTY=y
232 +CONFIG_BT_BNEP=m
233 +CONFIG_BT_BNEP_MC_FILTER=y
234 +CONFIG_BT_BNEP_PROTO_FILTER=y
235 +CONFIG_BT_HIDP=m
236 +CONFIG_BT_HCIBTUSB=m
237 +CONFIG_BT_HCIBCM203X=m
238 +CONFIG_BT_HCIBPA10X=m
239 +CONFIG_BT_HCIBFUSB=m
240 +CONFIG_BT_HCIVHCI=m
241 +CONFIG_BT_MRVL=m
242 +CONFIG_BT_MRVL_SDIO=m
243 +CONFIG_BT_ATH3K=m
244 +CONFIG_CFG80211=m
245 +CONFIG_MAC80211=m
246 +CONFIG_MAC80211_RC_PID=y
247 +CONFIG_MAC80211_MESH=y
248 +CONFIG_WIMAX=m
249 +CONFIG_NET_9P=m
250 +CONFIG_NFC=m
251 +CONFIG_NFC_PN533=m
252 +CONFIG_DEVTMPFS=y
253 +CONFIG_BLK_DEV_LOOP=y
254 +CONFIG_BLK_DEV_CRYPTOLOOP=m
255 +CONFIG_BLK_DEV_NBD=m
256 +CONFIG_BLK_DEV_RAM=y
257 +CONFIG_CDROM_PKTCDVD=m
258 +CONFIG_MISC_DEVICES=y
259 +CONFIG_SCSI=y
260 +# CONFIG_SCSI_PROC_FS is not set
261 +CONFIG_BLK_DEV_SD=m
262 +CONFIG_BLK_DEV_SR=m
263 +CONFIG_SCSI_MULTI_LUN=y
264 +# CONFIG_SCSI_LOWLEVEL is not set
265 +CONFIG_NETDEVICES=y
266 +CONFIG_TUN=m
267 +CONFIG_PHYLIB=m
268 +CONFIG_MDIO_BITBANG=m
269 +CONFIG_NET_ETHERNET=y
270 +# CONFIG_NETDEV_1000 is not set
271 +# CONFIG_NETDEV_10000 is not set
272 +CONFIG_LIBERTAS_THINFIRM=m
273 +CONFIG_LIBERTAS_THINFIRM_USB=m
274 +CONFIG_AT76C50X_USB=m
275 +CONFIG_USB_ZD1201=m
276 +CONFIG_USB_NET_RNDIS_WLAN=m
277 +CONFIG_RTL8187=m
278 +CONFIG_MAC80211_HWSIM=m
279 +CONFIG_ATH_COMMON=m
280 +CONFIG_ATH9K=m
281 +CONFIG_ATH9K_HTC=m
282 +CONFIG_CARL9170=m
283 +CONFIG_B43=m
284 +CONFIG_B43LEGACY=m
285 +CONFIG_HOSTAP=m
286 +CONFIG_IWM=m
287 +CONFIG_LIBERTAS=m
288 +CONFIG_LIBERTAS_USB=m
289 +CONFIG_LIBERTAS_SDIO=m
290 +CONFIG_P54_COMMON=m
291 +CONFIG_P54_USB=m
292 +CONFIG_RT2X00=m
293 +CONFIG_RT2500USB=m
294 +CONFIG_RT73USB=m
295 +CONFIG_RT2800USB=m
296 +CONFIG_RT2800USB_RT53XX=y
297 +CONFIG_RTL8192CU=m
298 +CONFIG_WL1251=m
299 +CONFIG_WL12XX_MENU=m
300 +CONFIG_ZD1211RW=m
301 +CONFIG_MWIFIEX=m
302 +CONFIG_MWIFIEX_SDIO=m
303 +CONFIG_WIMAX_I2400M_USB=m
304 +CONFIG_USB_CATC=m
305 +CONFIG_USB_KAWETH=m
306 +CONFIG_USB_PEGASUS=m
307 +CONFIG_USB_RTL8150=m
308 +CONFIG_USB_USBNET=y
309 +CONFIG_USB_NET_AX8817X=m
310 +CONFIG_USB_NET_CDCETHER=m
311 +CONFIG_USB_NET_CDC_EEM=m
312 +CONFIG_USB_NET_DM9601=m
313 +CONFIG_USB_NET_SMSC75XX=m
314 +CONFIG_USB_NET_SMSC95XX=y
315 +CONFIG_USB_NET_GL620A=m
316 +CONFIG_USB_NET_NET1080=m
317 +CONFIG_USB_NET_PLUSB=m
318 +CONFIG_USB_NET_MCS7830=m
319 +CONFIG_USB_NET_CDC_SUBSET=m
320 +CONFIG_USB_ALI_M5632=y
321 +CONFIG_USB_AN2720=y
322 +CONFIG_USB_KC2190=y
323 +# CONFIG_USB_NET_ZAURUS is not set
324 +CONFIG_USB_NET_CX82310_ETH=m
325 +CONFIG_USB_NET_KALMIA=m
326 +CONFIG_USB_NET_INT51X1=m
327 +CONFIG_USB_IPHETH=m
328 +CONFIG_USB_SIERRA_NET=m
329 +CONFIG_USB_VL600=m
330 +CONFIG_PPP=m
331 +CONFIG_PPP_ASYNC=m
332 +CONFIG_PPP_SYNC_TTY=m
333 +CONFIG_PPP_DEFLATE=m
334 +CONFIG_PPP_BSDCOMP=m
335 +CONFIG_SLIP=m
336 +CONFIG_SLIP_COMPRESSED=y
337 +CONFIG_NETCONSOLE=m
338 +CONFIG_INPUT_POLLDEV=m
339 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
340 +CONFIG_INPUT_JOYDEV=m
341 +CONFIG_INPUT_EVDEV=m
342 +# CONFIG_INPUT_KEYBOARD is not set
343 +# CONFIG_INPUT_MOUSE is not set
344 +CONFIG_INPUT_MISC=y
345 +CONFIG_INPUT_AD714X=m
346 +CONFIG_INPUT_ATI_REMOTE=m
347 +CONFIG_INPUT_ATI_REMOTE2=m
348 +CONFIG_INPUT_KEYSPAN_REMOTE=m
349 +CONFIG_INPUT_POWERMATE=m
350 +CONFIG_INPUT_YEALINK=m
351 +CONFIG_INPUT_CM109=m
352 +CONFIG_INPUT_UINPUT=m
353 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
354 +CONFIG_INPUT_ADXL34X=m
355 +CONFIG_INPUT_CMA3000=m
356 +CONFIG_SERIO=m
357 +CONFIG_SERIO_RAW=m
358 +CONFIG_GAMEPORT=m
359 +CONFIG_GAMEPORT_NS558=m
360 +CONFIG_GAMEPORT_L4=m
361 +CONFIG_VT_HW_CONSOLE_BINDING=y
362 +# CONFIG_LEGACY_PTYS is not set
363 +# CONFIG_DEVKMEM is not set
364 +CONFIG_SERIAL_AMBA_PL011=y
365 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
366 +# CONFIG_HW_RANDOM is not set
367 +CONFIG_RAW_DRIVER=y
368 +CONFIG_GPIO_SYSFS=y
369 +# CONFIG_HWMON is not set
370 +CONFIG_WATCHDOG=y
371 +CONFIG_BCM2708_WDT=m
372 +# CONFIG_MFD_SUPPORT is not set
373 +CONFIG_FB=y
374 +CONFIG_FB_BCM2708=y
375 +CONFIG_FRAMEBUFFER_CONSOLE=y
376 +CONFIG_LOGO=y
377 +# CONFIG_LOGO_LINUX_MONO is not set
378 +# CONFIG_LOGO_LINUX_VGA16 is not set
379 +CONFIG_HID_PID=y
380 +CONFIG_USB_HIDDEV=y
381 +CONFIG_HID_A4TECH=m
382 +CONFIG_HID_ACRUX=m
383 +CONFIG_HID_APPLE=m
384 +CONFIG_HID_BELKIN=m
385 +CONFIG_HID_CHERRY=m
386 +CONFIG_HID_CHICONY=m
387 +CONFIG_HID_CYPRESS=m
388 +CONFIG_HID_DRAGONRISE=m
389 +CONFIG_HID_EMS_FF=m
390 +CONFIG_HID_ELECOM=m
391 +CONFIG_HID_EZKEY=m
392 +CONFIG_HID_HOLTEK=m
393 +CONFIG_HID_KEYTOUCH=m
394 +CONFIG_HID_KYE=m
395 +CONFIG_HID_UCLOGIC=m
396 +CONFIG_HID_WALTOP=m
397 +CONFIG_HID_GYRATION=m
398 +CONFIG_HID_TWINHAN=m
399 +CONFIG_HID_KENSINGTON=m
400 +CONFIG_HID_LCPOWER=m
401 +CONFIG_HID_LOGITECH=m
402 +CONFIG_HID_MAGICMOUSE=m
403 +CONFIG_HID_MICROSOFT=m
404 +CONFIG_HID_MONTEREY=m
405 +CONFIG_HID_MULTITOUCH=m
406 +CONFIG_HID_NTRIG=m
407 +CONFIG_HID_ORTEK=m
408 +CONFIG_HID_PANTHERLORD=m
409 +CONFIG_HID_PETALYNX=m
410 +CONFIG_HID_PICOLCD=m
411 +CONFIG_HID_QUANTA=m
412 +CONFIG_HID_ROCCAT=m
413 +CONFIG_HID_SAMSUNG=m
414 +CONFIG_HID_SONY=m
415 +CONFIG_HID_SPEEDLINK=m
416 +CONFIG_HID_SUNPLUS=m
417 +CONFIG_HID_GREENASIA=m
418 +CONFIG_HID_SMARTJOYPLUS=m
419 +CONFIG_HID_TOPSEED=m
420 +CONFIG_HID_THRUSTMASTER=m
421 +CONFIG_HID_WACOM=m
422 +CONFIG_HID_WIIMOTE=m
423 +CONFIG_HID_ZEROPLUS=m
424 +CONFIG_HID_ZYDACRON=m
425 +CONFIG_USB=y
426 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
427 +CONFIG_USB_MON=m
428 +CONFIG_USB_DWCOTG=y
429 +CONFIG_USB_STORAGE=y
430 +CONFIG_USB_STORAGE_REALTEK=m
431 +CONFIG_USB_STORAGE_DATAFAB=m
432 +CONFIG_USB_STORAGE_FREECOM=m
433 +CONFIG_USB_STORAGE_ISD200=m
434 +CONFIG_USB_STORAGE_USBAT=m
435 +CONFIG_USB_STORAGE_SDDR09=m
436 +CONFIG_USB_STORAGE_SDDR55=m
437 +CONFIG_USB_STORAGE_JUMPSHOT=m
438 +CONFIG_USB_STORAGE_ALAUDA=m
439 +CONFIG_USB_STORAGE_ONETOUCH=m
440 +CONFIG_USB_STORAGE_KARMA=m
441 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
442 +CONFIG_USB_STORAGE_ENE_UB6250=m
443 +CONFIG_USB_UAS=m
444 +CONFIG_USB_LIBUSUAL=y
445 +CONFIG_USB_MDC800=m
446 +CONFIG_USB_MICROTEK=m
447 +CONFIG_USB_SERIAL=m
448 +CONFIG_USB_SERIAL_GENERIC=y
449 +CONFIG_USB_SERIAL_AIRCABLE=m
450 +CONFIG_USB_SERIAL_ARK3116=m
451 +CONFIG_USB_SERIAL_BELKIN=m
452 +CONFIG_USB_SERIAL_CH341=m
453 +CONFIG_USB_SERIAL_WHITEHEAT=m
454 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
455 +CONFIG_USB_SERIAL_CP210X=m
456 +CONFIG_USB_SERIAL_CYPRESS_M8=m
457 +CONFIG_USB_SERIAL_EMPEG=m
458 +CONFIG_USB_SERIAL_FTDI_SIO=m
459 +CONFIG_USB_SERIAL_FUNSOFT=m
460 +CONFIG_USB_SERIAL_VISOR=m
461 +CONFIG_USB_SERIAL_IPAQ=m
462 +CONFIG_USB_SERIAL_IR=m
463 +CONFIG_USB_SERIAL_EDGEPORT=m
464 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
465 +CONFIG_USB_SERIAL_GARMIN=m
466 +CONFIG_USB_SERIAL_IPW=m
467 +CONFIG_USB_SERIAL_IUU=m
468 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
469 +CONFIG_USB_SERIAL_KEYSPAN=m
470 +CONFIG_USB_SERIAL_KLSI=m
471 +CONFIG_USB_SERIAL_KOBIL_SCT=m
472 +CONFIG_USB_SERIAL_MCT_U232=m
473 +CONFIG_USB_SERIAL_MOS7720=m
474 +CONFIG_USB_SERIAL_MOS7840=m
475 +CONFIG_USB_SERIAL_MOTOROLA=m
476 +CONFIG_USB_SERIAL_NAVMAN=m
477 +CONFIG_USB_SERIAL_PL2303=m
478 +CONFIG_USB_SERIAL_OTI6858=m
479 +CONFIG_USB_SERIAL_QCAUX=m
480 +CONFIG_USB_SERIAL_QUALCOMM=m
481 +CONFIG_USB_SERIAL_SPCP8X5=m
482 +CONFIG_USB_SERIAL_HP4X=m
483 +CONFIG_USB_SERIAL_SAFE=m
484 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
485 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
486 +CONFIG_USB_SERIAL_SYMBOL=m
487 +CONFIG_USB_SERIAL_TI=m
488 +CONFIG_USB_SERIAL_CYBERJACK=m
489 +CONFIG_USB_SERIAL_XIRCOM=m
490 +CONFIG_USB_SERIAL_OPTION=m
491 +CONFIG_USB_SERIAL_OMNINET=m
492 +CONFIG_USB_SERIAL_OPTICON=m
493 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
494 +CONFIG_USB_SERIAL_ZIO=m
495 +CONFIG_USB_SERIAL_SSU100=m
496 +CONFIG_USB_SERIAL_DEBUG=m
497 +CONFIG_USB_EMI62=m
498 +CONFIG_USB_EMI26=m
499 +CONFIG_USB_ADUTUX=m
500 +CONFIG_USB_SEVSEG=m
501 +CONFIG_USB_RIO500=m
502 +CONFIG_USB_LEGOTOWER=m
503 +CONFIG_USB_LCD=m
504 +CONFIG_USB_LED=m
505 +CONFIG_USB_CYPRESS_CY7C63=m
506 +CONFIG_USB_CYTHERM=m
507 +CONFIG_USB_IDMOUSE=m
508 +CONFIG_USB_FTDI_ELAN=m
509 +CONFIG_USB_APPLEDISPLAY=m
510 +CONFIG_USB_LD=m
511 +CONFIG_USB_TRANCEVIBRATOR=m
512 +CONFIG_USB_IOWARRIOR=m
513 +CONFIG_USB_TEST=m
514 +CONFIG_USB_ISIGHTFW=m
515 +CONFIG_USB_YUREX=m
516 +CONFIG_MMC=y
517 +CONFIG_MMC_SDHCI=y
518 +CONFIG_MMC_SDHCI_PLTFM=y
519 +CONFIG_MMC_SDHCI_BCM2708=y
520 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
521 +CONFIG_LEDS_GPIO=y
522 +CONFIG_LEDS_TRIGGER_TIMER=m
523 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
524 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
525 +CONFIG_UIO=m
526 +CONFIG_UIO_PDRV=m
527 +CONFIG_UIO_PDRV_GENIRQ=m
528 +# CONFIG_IOMMU_SUPPORT is not set
529 +CONFIG_EXT4_FS=y
530 +CONFIG_EXT4_FS_POSIX_ACL=y
531 +CONFIG_EXT4_FS_SECURITY=y
532 +CONFIG_REISERFS_FS=m
533 +CONFIG_REISERFS_FS_XATTR=y
534 +CONFIG_REISERFS_FS_POSIX_ACL=y
535 +CONFIG_REISERFS_FS_SECURITY=y
536 +CONFIG_JFS_FS=m
537 +CONFIG_JFS_POSIX_ACL=y
538 +CONFIG_JFS_SECURITY=y
539 +CONFIG_XFS_FS=m
540 +CONFIG_XFS_QUOTA=y
541 +CONFIG_XFS_POSIX_ACL=y
542 +CONFIG_XFS_RT=y
543 +CONFIG_GFS2_FS=m
544 +CONFIG_OCFS2_FS=m
545 +CONFIG_BTRFS_FS=m
546 +CONFIG_BTRFS_FS_POSIX_ACL=y
547 +CONFIG_NILFS2_FS=m
548 +CONFIG_AUTOFS4_FS=y
549 +CONFIG_FUSE_FS=m
550 +CONFIG_CUSE=m
551 +CONFIG_FSCACHE=y
552 +CONFIG_CACHEFILES=y
553 +CONFIG_ISO9660_FS=m
554 +CONFIG_JOLIET=y
555 +CONFIG_ZISOFS=y
556 +CONFIG_UDF_FS=m
557 +CONFIG_MSDOS_FS=y
558 +CONFIG_VFAT_FS=y
559 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
560 +CONFIG_NTFS_FS=m
561 +CONFIG_TMPFS=y
562 +CONFIG_TMPFS_POSIX_ACL=y
563 +CONFIG_CONFIGFS_FS=y
564 +CONFIG_SQUASHFS=m
565 +CONFIG_SQUASHFS_XATTR=y
566 +CONFIG_SQUASHFS_LZO=y
567 +CONFIG_SQUASHFS_XZ=y
568 +CONFIG_NFS_FS=y
569 +CONFIG_NFS_V3=y
570 +CONFIG_NFS_V3_ACL=y
571 +CONFIG_NFS_V4=y
572 +CONFIG_ROOT_NFS=y
573 +CONFIG_NFS_FSCACHE=y
574 +CONFIG_CIFS=m
575 +CONFIG_CIFS_WEAK_PW_HASH=y
576 +CONFIG_CIFS_XATTR=y
577 +CONFIG_CIFS_POSIX=y
578 +CONFIG_9P_FS=m
579 +CONFIG_PARTITION_ADVANCED=y
580 +CONFIG_MAC_PARTITION=y
581 +CONFIG_EFI_PARTITION=y
582 +CONFIG_NLS_DEFAULT="utf8"
583 +CONFIG_NLS_CODEPAGE_437=y
584 +CONFIG_NLS_CODEPAGE_737=m
585 +CONFIG_NLS_CODEPAGE_775=m
586 +CONFIG_NLS_CODEPAGE_850=m
587 +CONFIG_NLS_CODEPAGE_852=m
588 +CONFIG_NLS_CODEPAGE_855=m
589 +CONFIG_NLS_CODEPAGE_857=m
590 +CONFIG_NLS_CODEPAGE_860=m
591 +CONFIG_NLS_CODEPAGE_861=m
592 +CONFIG_NLS_CODEPAGE_862=m
593 +CONFIG_NLS_CODEPAGE_863=m
594 +CONFIG_NLS_CODEPAGE_864=m
595 +CONFIG_NLS_CODEPAGE_865=m
596 +CONFIG_NLS_CODEPAGE_866=m
597 +CONFIG_NLS_CODEPAGE_869=m
598 +CONFIG_NLS_CODEPAGE_936=m
599 +CONFIG_NLS_CODEPAGE_950=m
600 +CONFIG_NLS_CODEPAGE_932=m
601 +CONFIG_NLS_CODEPAGE_949=m
602 +CONFIG_NLS_CODEPAGE_874=m
603 +CONFIG_NLS_ISO8859_8=m
604 +CONFIG_NLS_CODEPAGE_1250=m
605 +CONFIG_NLS_CODEPAGE_1251=m
606 +CONFIG_NLS_ASCII=y
607 +CONFIG_NLS_ISO8859_1=m
608 +CONFIG_NLS_ISO8859_2=m
609 +CONFIG_NLS_ISO8859_3=m
610 +CONFIG_NLS_ISO8859_4=m
611 +CONFIG_NLS_ISO8859_5=m
612 +CONFIG_NLS_ISO8859_6=m
613 +CONFIG_NLS_ISO8859_7=m
614 +CONFIG_NLS_ISO8859_9=m
615 +CONFIG_NLS_ISO8859_13=m
616 +CONFIG_NLS_ISO8859_14=m
617 +CONFIG_NLS_ISO8859_15=m
618 +CONFIG_NLS_KOI8_R=m
619 +CONFIG_NLS_KOI8_U=m
620 +CONFIG_NLS_UTF8=m
621 +# CONFIG_SCHED_DEBUG is not set
622 +# CONFIG_DEBUG_BUGVERBOSE is not set
623 +# CONFIG_FTRACE is not set
624 +# CONFIG_ARM_UNWIND is not set
625 +CONFIG_CRYPTO_AUTHENC=m
626 +CONFIG_CRYPTO_SEQIV=m
627 +CONFIG_CRYPTO_CBC=y
628 +CONFIG_CRYPTO_HMAC=y
629 +CONFIG_CRYPTO_XCBC=m
630 +CONFIG_CRYPTO_MD5=y
631 +CONFIG_CRYPTO_SHA1=y
632 +CONFIG_CRYPTO_SHA256=m
633 +CONFIG_CRYPTO_SHA512=m
634 +CONFIG_CRYPTO_TGR192=m
635 +CONFIG_CRYPTO_WP512=m
636 +CONFIG_CRYPTO_CAST5=m
637 +CONFIG_CRYPTO_DES=y
638 +CONFIG_CRYPTO_DEFLATE=m
639 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
640 +# CONFIG_CRYPTO_HW is not set
641 +CONFIG_CRC_ITU_T=y
642 +CONFIG_LIBCRC32C=y
643 diff --git a/arch/arm/configs/bcmrpi_defconfig b/arch/arm/configs/bcmrpi_defconfig
644 new file mode 100644
645 index 0000000..339aabf
646 --- /dev/null
647 +++ b/arch/arm/configs/bcmrpi_defconfig
648 @@ -0,0 +1,510 @@
649 +CONFIG_EXPERIMENTAL=y
650 +# CONFIG_LOCALVERSION_AUTO is not set
651 +CONFIG_SYSVIPC=y
652 +CONFIG_POSIX_MQUEUE=y
653 +CONFIG_BSD_PROCESS_ACCT=y
654 +CONFIG_BSD_PROCESS_ACCT_V3=y
655 +CONFIG_FHANDLE=y
656 +CONFIG_AUDIT=y
657 +CONFIG_IKCONFIG=y
658 +CONFIG_IKCONFIG_PROC=y
659 +CONFIG_CGROUP_FREEZER=y
660 +CONFIG_CGROUP_DEVICE=y
661 +CONFIG_CGROUP_CPUACCT=y
662 +CONFIG_RESOURCE_COUNTERS=y
663 +CONFIG_BLK_CGROUP=y
664 +CONFIG_NAMESPACES=y
665 +CONFIG_SCHED_AUTOGROUP=y
666 +CONFIG_EMBEDDED=y
667 +# CONFIG_COMPAT_BRK is not set
668 +CONFIG_SLAB=y
669 +CONFIG_PROFILING=y
670 +CONFIG_OPROFILE=m
671 +CONFIG_KPROBES=y
672 +CONFIG_MODULES=y
673 +CONFIG_MODULE_UNLOAD=y
674 +CONFIG_MODVERSIONS=y
675 +CONFIG_MODULE_SRCVERSION_ALL=y
676 +# CONFIG_BLK_DEV_BSG is not set
677 +CONFIG_BLK_DEV_THROTTLING=y
678 +CONFIG_CFQ_GROUP_IOSCHED=y
679 +CONFIG_ARCH_BCM2708=y
680 +CONFIG_NO_HZ=y
681 +CONFIG_HIGH_RES_TIMERS=y
682 +CONFIG_AEABI=y
683 +CONFIG_SECCOMP=y
684 +CONFIG_CC_STACKPROTECTOR=y
685 +CONFIG_ZBOOT_ROM_TEXT=0x0
686 +CONFIG_ZBOOT_ROM_BSS=0x0
687 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
688 +CONFIG_KEXEC=y
689 +CONFIG_CPU_IDLE=y
690 +CONFIG_VFP=y
691 +CONFIG_BINFMT_MISC=m
692 +CONFIG_NET=y
693 +CONFIG_PACKET=y
694 +CONFIG_UNIX=y
695 +CONFIG_XFRM_USER=y
696 +CONFIG_NET_KEY=m
697 +CONFIG_INET=y
698 +CONFIG_IP_MULTICAST=y
699 +CONFIG_IP_PNP=y
700 +CONFIG_IP_PNP_DHCP=y
701 +CONFIG_IP_PNP_RARP=y
702 +CONFIG_SYN_COOKIES=y
703 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
704 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
705 +# CONFIG_INET_XFRM_MODE_BEET is not set
706 +# CONFIG_INET_LRO is not set
707 +# CONFIG_INET_DIAG is not set
708 +# CONFIG_IPV6 is not set
709 +CONFIG_NET_PKTGEN=m
710 +CONFIG_IRDA=m
711 +CONFIG_IRLAN=m
712 +CONFIG_IRCOMM=m
713 +CONFIG_IRDA_ULTRA=y
714 +CONFIG_IRDA_CACHE_LAST_LSAP=y
715 +CONFIG_IRDA_FAST_RR=y
716 +CONFIG_IRTTY_SIR=m
717 +CONFIG_KINGSUN_DONGLE=m
718 +CONFIG_KSDAZZLE_DONGLE=m
719 +CONFIG_KS959_DONGLE=m
720 +CONFIG_USB_IRDA=m
721 +CONFIG_SIGMATEL_FIR=m
722 +CONFIG_MCS_FIR=m
723 +CONFIG_BT=m
724 +CONFIG_BT_L2CAP=y
725 +CONFIG_BT_SCO=y
726 +CONFIG_BT_RFCOMM=m
727 +CONFIG_BT_RFCOMM_TTY=y
728 +CONFIG_BT_BNEP=m
729 +CONFIG_BT_BNEP_MC_FILTER=y
730 +CONFIG_BT_BNEP_PROTO_FILTER=y
731 +CONFIG_BT_HIDP=m
732 +CONFIG_BT_HCIBTUSB=m
733 +CONFIG_BT_HCIBCM203X=m
734 +CONFIG_BT_HCIBPA10X=m
735 +CONFIG_BT_HCIBFUSB=m
736 +CONFIG_BT_HCIVHCI=m
737 +CONFIG_BT_MRVL=m
738 +CONFIG_BT_MRVL_SDIO=m
739 +CONFIG_BT_ATH3K=m
740 +CONFIG_CFG80211=m
741 +CONFIG_MAC80211=m
742 +CONFIG_MAC80211_RC_PID=y
743 +CONFIG_MAC80211_MESH=y
744 +CONFIG_WIMAX=m
745 +CONFIG_NET_9P=m
746 +CONFIG_NFC=m
747 +CONFIG_NFC_PN533=m
748 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
749 +CONFIG_BLK_DEV_LOOP=y
750 +CONFIG_BLK_DEV_CRYPTOLOOP=m
751 +CONFIG_BLK_DEV_NBD=m
752 +CONFIG_BLK_DEV_RAM=y
753 +CONFIG_CDROM_PKTCDVD=m
754 +CONFIG_MISC_DEVICES=y
755 +CONFIG_SCSI=y
756 +# CONFIG_SCSI_PROC_FS is not set
757 +CONFIG_BLK_DEV_SD=m
758 +CONFIG_BLK_DEV_SR=m
759 +CONFIG_SCSI_MULTI_LUN=y
760 +# CONFIG_SCSI_LOWLEVEL is not set
761 +CONFIG_MD=y
762 +CONFIG_NETDEVICES=y
763 +CONFIG_TUN=m
764 +CONFIG_PHYLIB=m
765 +CONFIG_MDIO_BITBANG=m
766 +CONFIG_NET_ETHERNET=y
767 +# CONFIG_NETDEV_1000 is not set
768 +# CONFIG_NETDEV_10000 is not set
769 +CONFIG_LIBERTAS_THINFIRM=m
770 +CONFIG_LIBERTAS_THINFIRM_USB=m
771 +CONFIG_AT76C50X_USB=m
772 +CONFIG_USB_ZD1201=m
773 +CONFIG_USB_NET_RNDIS_WLAN=m
774 +CONFIG_RTL8187=m
775 +CONFIG_MAC80211_HWSIM=m
776 +CONFIG_ATH_COMMON=m
777 +CONFIG_ATH9K=m
778 +CONFIG_ATH9K_HTC=m
779 +CONFIG_CARL9170=m
780 +CONFIG_B43=m
781 +CONFIG_B43LEGACY=m
782 +CONFIG_HOSTAP=m
783 +CONFIG_IWM=m
784 +CONFIG_LIBERTAS=m
785 +CONFIG_LIBERTAS_USB=m
786 +CONFIG_LIBERTAS_SDIO=m
787 +CONFIG_P54_COMMON=m
788 +CONFIG_P54_USB=m
789 +CONFIG_RT2X00=m
790 +CONFIG_RT2500USB=m
791 +CONFIG_RT73USB=m
792 +CONFIG_RT2800USB=m
793 +CONFIG_RT2800USB_RT53XX=y
794 +CONFIG_RTL8192CU=m
795 +CONFIG_WL1251=m
796 +CONFIG_WL12XX_MENU=m
797 +CONFIG_ZD1211RW=m
798 +CONFIG_MWIFIEX=m
799 +CONFIG_MWIFIEX_SDIO=m
800 +CONFIG_WIMAX_I2400M_USB=m
801 +CONFIG_USB_CATC=m
802 +CONFIG_USB_KAWETH=m
803 +CONFIG_USB_PEGASUS=m
804 +CONFIG_USB_RTL8150=m
805 +CONFIG_USB_USBNET=y
806 +CONFIG_USB_NET_AX8817X=m
807 +CONFIG_USB_NET_CDCETHER=m
808 +CONFIG_USB_NET_CDC_EEM=m
809 +CONFIG_USB_NET_DM9601=m
810 +CONFIG_USB_NET_SMSC75XX=m
811 +CONFIG_USB_NET_SMSC95XX=y
812 +CONFIG_USB_NET_GL620A=m
813 +CONFIG_USB_NET_NET1080=m
814 +CONFIG_USB_NET_PLUSB=m
815 +CONFIG_USB_NET_MCS7830=m
816 +CONFIG_USB_NET_CDC_SUBSET=m
817 +CONFIG_USB_ALI_M5632=y
818 +CONFIG_USB_AN2720=y
819 +CONFIG_USB_KC2190=y
820 +# CONFIG_USB_NET_ZAURUS is not set
821 +CONFIG_USB_NET_CX82310_ETH=m
822 +CONFIG_USB_NET_KALMIA=m
823 +CONFIG_USB_NET_INT51X1=m
824 +CONFIG_USB_IPHETH=m
825 +CONFIG_USB_SIERRA_NET=m
826 +CONFIG_USB_VL600=m
827 +CONFIG_PPP=m
828 +CONFIG_PPP_ASYNC=m
829 +CONFIG_PPP_SYNC_TTY=m
830 +CONFIG_PPP_DEFLATE=m
831 +CONFIG_PPP_BSDCOMP=m
832 +CONFIG_SLIP=m
833 +CONFIG_SLIP_COMPRESSED=y
834 +CONFIG_NETCONSOLE=m
835 +CONFIG_INPUT_POLLDEV=m
836 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
837 +CONFIG_INPUT_JOYDEV=m
838 +CONFIG_INPUT_EVDEV=m
839 +# CONFIG_INPUT_KEYBOARD is not set
840 +# CONFIG_INPUT_MOUSE is not set
841 +CONFIG_INPUT_MISC=y
842 +CONFIG_INPUT_AD714X=m
843 +CONFIG_INPUT_ATI_REMOTE=m
844 +CONFIG_INPUT_ATI_REMOTE2=m
845 +CONFIG_INPUT_KEYSPAN_REMOTE=m
846 +CONFIG_INPUT_POWERMATE=m
847 +CONFIG_INPUT_YEALINK=m
848 +CONFIG_INPUT_CM109=m
849 +CONFIG_INPUT_UINPUT=m
850 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
851 +CONFIG_INPUT_ADXL34X=m
852 +CONFIG_INPUT_CMA3000=m
853 +CONFIG_SERIO=m
854 +CONFIG_SERIO_RAW=m
855 +CONFIG_GAMEPORT=m
856 +CONFIG_GAMEPORT_NS558=m
857 +CONFIG_GAMEPORT_L4=m
858 +CONFIG_VT_HW_CONSOLE_BINDING=y
859 +# CONFIG_LEGACY_PTYS is not set
860 +# CONFIG_DEVKMEM is not set
861 +CONFIG_SERIAL_AMBA_PL011=y
862 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
863 +# CONFIG_HW_RANDOM is not set
864 +CONFIG_RAW_DRIVER=y
865 +CONFIG_GPIO_SYSFS=y
866 +# CONFIG_HWMON is not set
867 +CONFIG_WATCHDOG=y
868 +CONFIG_BCM2708_WDT=m
869 +# CONFIG_MFD_SUPPORT is not set
870 +CONFIG_FB=y
871 +CONFIG_FB_BCM2708=y
872 +CONFIG_FRAMEBUFFER_CONSOLE=y
873 +CONFIG_LOGO=y
874 +# CONFIG_LOGO_LINUX_MONO is not set
875 +# CONFIG_LOGO_LINUX_VGA16 is not set
876 +CONFIG_HID_PID=y
877 +CONFIG_USB_HIDDEV=y
878 +CONFIG_HID_A4TECH=m
879 +CONFIG_HID_ACRUX=m
880 +CONFIG_HID_APPLE=m
881 +CONFIG_HID_BELKIN=m
882 +CONFIG_HID_CHERRY=m
883 +CONFIG_HID_CHICONY=m
884 +CONFIG_HID_CYPRESS=m
885 +CONFIG_HID_DRAGONRISE=m
886 +CONFIG_HID_EMS_FF=m
887 +CONFIG_HID_ELECOM=m
888 +CONFIG_HID_EZKEY=m
889 +CONFIG_HID_HOLTEK=m
890 +CONFIG_HID_KEYTOUCH=m
891 +CONFIG_HID_KYE=m
892 +CONFIG_HID_UCLOGIC=m
893 +CONFIG_HID_WALTOP=m
894 +CONFIG_HID_GYRATION=m
895 +CONFIG_HID_TWINHAN=m
896 +CONFIG_HID_KENSINGTON=m
897 +CONFIG_HID_LCPOWER=m
898 +CONFIG_HID_LOGITECH=m
899 +CONFIG_HID_MAGICMOUSE=m
900 +CONFIG_HID_MICROSOFT=m
901 +CONFIG_HID_MONTEREY=m
902 +CONFIG_HID_MULTITOUCH=m
903 +CONFIG_HID_NTRIG=m
904 +CONFIG_HID_ORTEK=m
905 +CONFIG_HID_PANTHERLORD=m
906 +CONFIG_HID_PETALYNX=m
907 +CONFIG_HID_PICOLCD=m
908 +CONFIG_HID_QUANTA=m
909 +CONFIG_HID_ROCCAT=m
910 +CONFIG_HID_SAMSUNG=m
911 +CONFIG_HID_SONY=m
912 +CONFIG_HID_SPEEDLINK=m
913 +CONFIG_HID_SUNPLUS=m
914 +CONFIG_HID_GREENASIA=m
915 +CONFIG_HID_SMARTJOYPLUS=m
916 +CONFIG_HID_TOPSEED=m
917 +CONFIG_HID_THRUSTMASTER=m
918 +CONFIG_HID_WACOM=m
919 +CONFIG_HID_WIIMOTE=m
920 +CONFIG_HID_ZEROPLUS=m
921 +CONFIG_HID_ZYDACRON=m
922 +CONFIG_USB=y
923 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
924 +CONFIG_USB_MON=m
925 +CONFIG_USB_DWCOTG=y
926 +CONFIG_USB_STORAGE=y
927 +CONFIG_USB_STORAGE_REALTEK=m
928 +CONFIG_USB_STORAGE_DATAFAB=m
929 +CONFIG_USB_STORAGE_FREECOM=m
930 +CONFIG_USB_STORAGE_ISD200=m
931 +CONFIG_USB_STORAGE_USBAT=m
932 +CONFIG_USB_STORAGE_SDDR09=m
933 +CONFIG_USB_STORAGE_SDDR55=m
934 +CONFIG_USB_STORAGE_JUMPSHOT=m
935 +CONFIG_USB_STORAGE_ALAUDA=m
936 +CONFIG_USB_STORAGE_ONETOUCH=m
937 +CONFIG_USB_STORAGE_KARMA=m
938 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
939 +CONFIG_USB_STORAGE_ENE_UB6250=m
940 +CONFIG_USB_UAS=m
941 +CONFIG_USB_LIBUSUAL=y
942 +CONFIG_USB_MDC800=m
943 +CONFIG_USB_MICROTEK=m
944 +CONFIG_USB_SERIAL=m
945 +CONFIG_USB_SERIAL_GENERIC=y
946 +CONFIG_USB_SERIAL_AIRCABLE=m
947 +CONFIG_USB_SERIAL_ARK3116=m
948 +CONFIG_USB_SERIAL_BELKIN=m
949 +CONFIG_USB_SERIAL_CH341=m
950 +CONFIG_USB_SERIAL_WHITEHEAT=m
951 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
952 +CONFIG_USB_SERIAL_CP210X=m
953 +CONFIG_USB_SERIAL_CYPRESS_M8=m
954 +CONFIG_USB_SERIAL_EMPEG=m
955 +CONFIG_USB_SERIAL_FTDI_SIO=m
956 +CONFIG_USB_SERIAL_FUNSOFT=m
957 +CONFIG_USB_SERIAL_VISOR=m
958 +CONFIG_USB_SERIAL_IPAQ=m
959 +CONFIG_USB_SERIAL_IR=m
960 +CONFIG_USB_SERIAL_EDGEPORT=m
961 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
962 +CONFIG_USB_SERIAL_GARMIN=m
963 +CONFIG_USB_SERIAL_IPW=m
964 +CONFIG_USB_SERIAL_IUU=m
965 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
966 +CONFIG_USB_SERIAL_KEYSPAN=m
967 +CONFIG_USB_SERIAL_KLSI=m
968 +CONFIG_USB_SERIAL_KOBIL_SCT=m
969 +CONFIG_USB_SERIAL_MCT_U232=m
970 +CONFIG_USB_SERIAL_MOS7720=m
971 +CONFIG_USB_SERIAL_MOS7840=m
972 +CONFIG_USB_SERIAL_MOTOROLA=m
973 +CONFIG_USB_SERIAL_NAVMAN=m
974 +CONFIG_USB_SERIAL_PL2303=m
975 +CONFIG_USB_SERIAL_OTI6858=m
976 +CONFIG_USB_SERIAL_QCAUX=m
977 +CONFIG_USB_SERIAL_QUALCOMM=m
978 +CONFIG_USB_SERIAL_SPCP8X5=m
979 +CONFIG_USB_SERIAL_HP4X=m
980 +CONFIG_USB_SERIAL_SAFE=m
981 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
982 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
983 +CONFIG_USB_SERIAL_SYMBOL=m
984 +CONFIG_USB_SERIAL_TI=m
985 +CONFIG_USB_SERIAL_CYBERJACK=m
986 +CONFIG_USB_SERIAL_XIRCOM=m
987 +CONFIG_USB_SERIAL_OPTION=m
988 +CONFIG_USB_SERIAL_OMNINET=m
989 +CONFIG_USB_SERIAL_OPTICON=m
990 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
991 +CONFIG_USB_SERIAL_ZIO=m
992 +CONFIG_USB_SERIAL_SSU100=m
993 +CONFIG_USB_SERIAL_DEBUG=m
994 +CONFIG_USB_EMI62=m
995 +CONFIG_USB_EMI26=m
996 +CONFIG_USB_ADUTUX=m
997 +CONFIG_USB_SEVSEG=m
998 +CONFIG_USB_RIO500=m
999 +CONFIG_USB_LEGOTOWER=m
1000 +CONFIG_USB_LCD=m
1001 +CONFIG_USB_LED=m
1002 +CONFIG_USB_CYPRESS_CY7C63=m
1003 +CONFIG_USB_CYTHERM=m
1004 +CONFIG_USB_IDMOUSE=m
1005 +CONFIG_USB_FTDI_ELAN=m
1006 +CONFIG_USB_APPLEDISPLAY=m
1007 +CONFIG_USB_LD=m
1008 +CONFIG_USB_TRANCEVIBRATOR=m
1009 +CONFIG_USB_IOWARRIOR=m
1010 +CONFIG_USB_TEST=m
1011 +CONFIG_USB_ISIGHTFW=m
1012 +CONFIG_USB_YUREX=m
1013 +CONFIG_MMC=y
1014 +CONFIG_MMC_SDHCI=y
1015 +CONFIG_MMC_SDHCI_PLTFM=y
1016 +CONFIG_MMC_SDHCI_BCM2708=y
1017 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1018 +CONFIG_LEDS_GPIO=y
1019 +CONFIG_LEDS_TRIGGER_TIMER=m
1020 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1021 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1022 +CONFIG_UIO=m
1023 +CONFIG_UIO_PDRV=m
1024 +CONFIG_UIO_PDRV_GENIRQ=m
1025 +# CONFIG_IOMMU_SUPPORT is not set
1026 +CONFIG_EXT4_FS=y
1027 +CONFIG_EXT4_FS_POSIX_ACL=y
1028 +CONFIG_EXT4_FS_SECURITY=y
1029 +CONFIG_REISERFS_FS=m
1030 +CONFIG_REISERFS_FS_XATTR=y
1031 +CONFIG_REISERFS_FS_POSIX_ACL=y
1032 +CONFIG_REISERFS_FS_SECURITY=y
1033 +CONFIG_JFS_FS=m
1034 +CONFIG_JFS_POSIX_ACL=y
1035 +CONFIG_JFS_SECURITY=y
1036 +CONFIG_JFS_STATISTICS=y
1037 +CONFIG_XFS_FS=m
1038 +CONFIG_XFS_QUOTA=y
1039 +CONFIG_XFS_POSIX_ACL=y
1040 +CONFIG_XFS_RT=y
1041 +CONFIG_GFS2_FS=m
1042 +CONFIG_OCFS2_FS=m
1043 +CONFIG_BTRFS_FS=m
1044 +CONFIG_BTRFS_FS_POSIX_ACL=y
1045 +CONFIG_NILFS2_FS=m
1046 +CONFIG_FANOTIFY=y
1047 +CONFIG_AUTOFS4_FS=y
1048 +CONFIG_FUSE_FS=m
1049 +CONFIG_CUSE=m
1050 +CONFIG_FSCACHE=y
1051 +CONFIG_FSCACHE_STATS=y
1052 +CONFIG_FSCACHE_HISTOGRAM=y
1053 +CONFIG_CACHEFILES=y
1054 +CONFIG_ISO9660_FS=m
1055 +CONFIG_JOLIET=y
1056 +CONFIG_ZISOFS=y
1057 +CONFIG_UDF_FS=m
1058 +CONFIG_MSDOS_FS=y
1059 +CONFIG_VFAT_FS=y
1060 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1061 +CONFIG_NTFS_FS=m
1062 +CONFIG_TMPFS=y
1063 +CONFIG_TMPFS_POSIX_ACL=y
1064 +CONFIG_CONFIGFS_FS=y
1065 +CONFIG_SQUASHFS=m
1066 +CONFIG_SQUASHFS_XATTR=y
1067 +CONFIG_SQUASHFS_LZO=y
1068 +CONFIG_SQUASHFS_XZ=y
1069 +CONFIG_NFS_FS=y
1070 +CONFIG_NFS_V3=y
1071 +CONFIG_NFS_V3_ACL=y
1072 +CONFIG_NFS_V4=y
1073 +CONFIG_ROOT_NFS=y
1074 +CONFIG_NFS_FSCACHE=y
1075 +CONFIG_CIFS=m
1076 +CONFIG_CIFS_WEAK_PW_HASH=y
1077 +CONFIG_CIFS_XATTR=y
1078 +CONFIG_CIFS_POSIX=y
1079 +CONFIG_9P_FS=m
1080 +CONFIG_9P_FS_POSIX_ACL=y
1081 +CONFIG_PARTITION_ADVANCED=y
1082 +CONFIG_MAC_PARTITION=y
1083 +CONFIG_EFI_PARTITION=y
1084 +CONFIG_NLS_DEFAULT="utf8"
1085 +CONFIG_NLS_CODEPAGE_437=y
1086 +CONFIG_NLS_CODEPAGE_737=m
1087 +CONFIG_NLS_CODEPAGE_775=m
1088 +CONFIG_NLS_CODEPAGE_850=m
1089 +CONFIG_NLS_CODEPAGE_852=m
1090 +CONFIG_NLS_CODEPAGE_855=m
1091 +CONFIG_NLS_CODEPAGE_857=m
1092 +CONFIG_NLS_CODEPAGE_860=m
1093 +CONFIG_NLS_CODEPAGE_861=m
1094 +CONFIG_NLS_CODEPAGE_862=m
1095 +CONFIG_NLS_CODEPAGE_863=m
1096 +CONFIG_NLS_CODEPAGE_864=m
1097 +CONFIG_NLS_CODEPAGE_865=m
1098 +CONFIG_NLS_CODEPAGE_866=m
1099 +CONFIG_NLS_CODEPAGE_869=m
1100 +CONFIG_NLS_CODEPAGE_936=m
1101 +CONFIG_NLS_CODEPAGE_950=m
1102 +CONFIG_NLS_CODEPAGE_932=m
1103 +CONFIG_NLS_CODEPAGE_949=m
1104 +CONFIG_NLS_CODEPAGE_874=m
1105 +CONFIG_NLS_ISO8859_8=m
1106 +CONFIG_NLS_CODEPAGE_1250=m
1107 +CONFIG_NLS_CODEPAGE_1251=m
1108 +CONFIG_NLS_ASCII=y
1109 +CONFIG_NLS_ISO8859_1=m
1110 +CONFIG_NLS_ISO8859_2=m
1111 +CONFIG_NLS_ISO8859_3=m
1112 +CONFIG_NLS_ISO8859_4=m
1113 +CONFIG_NLS_ISO8859_5=m
1114 +CONFIG_NLS_ISO8859_6=m
1115 +CONFIG_NLS_ISO8859_7=m
1116 +CONFIG_NLS_ISO8859_9=m
1117 +CONFIG_NLS_ISO8859_13=m
1118 +CONFIG_NLS_ISO8859_14=m
1119 +CONFIG_NLS_ISO8859_15=m
1120 +CONFIG_NLS_KOI8_R=m
1121 +CONFIG_NLS_KOI8_U=m
1122 +CONFIG_NLS_UTF8=m
1123 +CONFIG_PRINTK_TIME=y
1124 +CONFIG_DETECT_HUNG_TASK=y
1125 +CONFIG_TIMER_STATS=y
1126 +CONFIG_DEBUG_STACK_USAGE=y
1127 +CONFIG_DEBUG_INFO=y
1128 +CONFIG_DEBUG_MEMORY_INIT=y
1129 +CONFIG_BOOT_PRINTK_DELAY=y
1130 +CONFIG_LATENCYTOP=y
1131 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1132 +CONFIG_IRQSOFF_TRACER=y
1133 +CONFIG_SCHED_TRACER=y
1134 +CONFIG_STACK_TRACER=y
1135 +CONFIG_BLK_DEV_IO_TRACE=y
1136 +CONFIG_FUNCTION_PROFILER=y
1137 +CONFIG_KGDB=y
1138 +CONFIG_KGDB_KDB=y
1139 +CONFIG_KDB_KEYBOARD=y
1140 +CONFIG_STRICT_DEVMEM=y
1141 +CONFIG_CRYPTO_AUTHENC=m
1142 +CONFIG_CRYPTO_SEQIV=m
1143 +CONFIG_CRYPTO_CBC=y
1144 +CONFIG_CRYPTO_HMAC=y
1145 +CONFIG_CRYPTO_XCBC=m
1146 +CONFIG_CRYPTO_MD5=y
1147 +CONFIG_CRYPTO_SHA1=y
1148 +CONFIG_CRYPTO_SHA256=m
1149 +CONFIG_CRYPTO_SHA512=m
1150 +CONFIG_CRYPTO_TGR192=m
1151 +CONFIG_CRYPTO_WP512=m
1152 +CONFIG_CRYPTO_CAST5=m
1153 +CONFIG_CRYPTO_DES=y
1154 +CONFIG_CRYPTO_DEFLATE=m
1155 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1156 +# CONFIG_CRYPTO_HW is not set
1157 +CONFIG_CRC_ITU_T=y
1158 +CONFIG_LIBCRC32C=y
1159 diff --git a/arch/arm/configs/bcmrpi_emergency_defconfig b/arch/arm/configs/bcmrpi_emergency_defconfig
1160 new file mode 100644
1161 index 0000000..3b40c49
1162 --- /dev/null
1163 +++ b/arch/arm/configs/bcmrpi_emergency_defconfig
1164 @@ -0,0 +1,532 @@
1165 +CONFIG_EXPERIMENTAL=y
1166 +# CONFIG_LOCALVERSION_AUTO is not set
1167 +CONFIG_SYSVIPC=y
1168 +CONFIG_POSIX_MQUEUE=y
1169 +CONFIG_BSD_PROCESS_ACCT=y
1170 +CONFIG_BSD_PROCESS_ACCT_V3=y
1171 +CONFIG_FHANDLE=y
1172 +CONFIG_AUDIT=y
1173 +CONFIG_IKCONFIG=y
1174 +CONFIG_IKCONFIG_PROC=y
1175 +CONFIG_BLK_DEV_INITRD=y
1176 +CONFIG_INITRAMFS_SOURCE="../target_fs"
1177 +CONFIG_CGROUP_FREEZER=y
1178 +CONFIG_CGROUP_DEVICE=y
1179 +CONFIG_CGROUP_CPUACCT=y
1180 +CONFIG_RESOURCE_COUNTERS=y
1181 +CONFIG_BLK_CGROUP=y
1182 +CONFIG_NAMESPACES=y
1183 +CONFIG_SCHED_AUTOGROUP=y
1184 +CONFIG_EMBEDDED=y
1185 +# CONFIG_COMPAT_BRK is not set
1186 +CONFIG_SLAB=y
1187 +CONFIG_PROFILING=y
1188 +CONFIG_OPROFILE=m
1189 +CONFIG_KPROBES=y
1190 +CONFIG_MODULES=y
1191 +CONFIG_MODULE_UNLOAD=y
1192 +CONFIG_MODVERSIONS=y
1193 +CONFIG_MODULE_SRCVERSION_ALL=y
1194 +# CONFIG_BLK_DEV_BSG is not set
1195 +CONFIG_BLK_DEV_THROTTLING=y
1196 +CONFIG_CFQ_GROUP_IOSCHED=y
1197 +CONFIG_ARCH_BCM2708=y
1198 +CONFIG_NO_HZ=y
1199 +CONFIG_HIGH_RES_TIMERS=y
1200 +CONFIG_AEABI=y
1201 +CONFIG_SECCOMP=y
1202 +CONFIG_CC_STACKPROTECTOR=y
1203 +CONFIG_ZBOOT_ROM_TEXT=0x0
1204 +CONFIG_ZBOOT_ROM_BSS=0x0
1205 +CONFIG_CMDLINE="dwc_otg.lpm_enable=0 console=ttyAMA0,115200 kgdboc=ttyAMA0,115200 root=/dev/mmcblk0p2 rootfstype=ext3 rootwait"
1206 +CONFIG_KEXEC=y
1207 +CONFIG_CPU_IDLE=y
1208 +CONFIG_VFP=y
1209 +CONFIG_BINFMT_MISC=m
1210 +CONFIG_NET=y
1211 +CONFIG_PACKET=y
1212 +CONFIG_UNIX=y
1213 +CONFIG_XFRM_USER=y
1214 +CONFIG_NET_KEY=m
1215 +CONFIG_INET=y
1216 +CONFIG_IP_MULTICAST=y
1217 +CONFIG_IP_PNP=y
1218 +CONFIG_IP_PNP_DHCP=y
1219 +CONFIG_IP_PNP_RARP=y
1220 +CONFIG_SYN_COOKIES=y
1221 +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
1222 +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
1223 +# CONFIG_INET_XFRM_MODE_BEET is not set
1224 +# CONFIG_INET_LRO is not set
1225 +# CONFIG_INET_DIAG is not set
1226 +# CONFIG_IPV6 is not set
1227 +CONFIG_NET_PKTGEN=m
1228 +CONFIG_IRDA=m
1229 +CONFIG_IRLAN=m
1230 +CONFIG_IRCOMM=m
1231 +CONFIG_IRDA_ULTRA=y
1232 +CONFIG_IRDA_CACHE_LAST_LSAP=y
1233 +CONFIG_IRDA_FAST_RR=y
1234 +CONFIG_IRTTY_SIR=m
1235 +CONFIG_KINGSUN_DONGLE=m
1236 +CONFIG_KSDAZZLE_DONGLE=m
1237 +CONFIG_KS959_DONGLE=m
1238 +CONFIG_USB_IRDA=m
1239 +CONFIG_SIGMATEL_FIR=m
1240 +CONFIG_MCS_FIR=m
1241 +CONFIG_BT=m
1242 +CONFIG_BT_L2CAP=y
1243 +CONFIG_BT_SCO=y
1244 +CONFIG_BT_RFCOMM=m
1245 +CONFIG_BT_RFCOMM_TTY=y
1246 +CONFIG_BT_BNEP=m
1247 +CONFIG_BT_BNEP_MC_FILTER=y
1248 +CONFIG_BT_BNEP_PROTO_FILTER=y
1249 +CONFIG_BT_HIDP=m
1250 +CONFIG_BT_HCIBTUSB=m
1251 +CONFIG_BT_HCIBCM203X=m
1252 +CONFIG_BT_HCIBPA10X=m
1253 +CONFIG_BT_HCIBFUSB=m
1254 +CONFIG_BT_HCIVHCI=m
1255 +CONFIG_BT_MRVL=m
1256 +CONFIG_BT_MRVL_SDIO=m
1257 +CONFIG_BT_ATH3K=m
1258 +CONFIG_CFG80211=m
1259 +CONFIG_MAC80211=m
1260 +CONFIG_MAC80211_RC_PID=y
1261 +CONFIG_MAC80211_MESH=y
1262 +CONFIG_WIMAX=m
1263 +CONFIG_NET_9P=m
1264 +CONFIG_NFC=m
1265 +CONFIG_NFC_PN533=m
1266 +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
1267 +CONFIG_BLK_DEV_LOOP=y
1268 +CONFIG_BLK_DEV_CRYPTOLOOP=m
1269 +CONFIG_BLK_DEV_NBD=m
1270 +CONFIG_BLK_DEV_RAM=y
1271 +CONFIG_CDROM_PKTCDVD=m
1272 +CONFIG_MISC_DEVICES=y
1273 +CONFIG_SCSI=y
1274 +# CONFIG_SCSI_PROC_FS is not set
1275 +CONFIG_BLK_DEV_SD=y
1276 +CONFIG_BLK_DEV_SR=m
1277 +CONFIG_SCSI_MULTI_LUN=y
1278 +# CONFIG_SCSI_LOWLEVEL is not set
1279 +CONFIG_MD=y
1280 +CONFIG_NETDEVICES=y
1281 +CONFIG_TUN=m
1282 +CONFIG_PHYLIB=m
1283 +CONFIG_MDIO_BITBANG=m
1284 +CONFIG_NET_ETHERNET=y
1285 +# CONFIG_NETDEV_1000 is not set
1286 +# CONFIG_NETDEV_10000 is not set
1287 +CONFIG_LIBERTAS_THINFIRM=m
1288 +CONFIG_LIBERTAS_THINFIRM_USB=m
1289 +CONFIG_AT76C50X_USB=m
1290 +CONFIG_USB_ZD1201=m
1291 +CONFIG_USB_NET_RNDIS_WLAN=m
1292 +CONFIG_RTL8187=m
1293 +CONFIG_MAC80211_HWSIM=m
1294 +CONFIG_ATH_COMMON=m
1295 +CONFIG_ATH9K=m
1296 +CONFIG_ATH9K_HTC=m
1297 +CONFIG_CARL9170=m
1298 +CONFIG_B43=m
1299 +CONFIG_B43LEGACY=m
1300 +CONFIG_HOSTAP=m
1301 +CONFIG_IWM=m
1302 +CONFIG_LIBERTAS=m
1303 +CONFIG_LIBERTAS_USB=m
1304 +CONFIG_LIBERTAS_SDIO=m
1305 +CONFIG_P54_COMMON=m
1306 +CONFIG_P54_USB=m
1307 +CONFIG_RT2X00=m
1308 +CONFIG_RT2500USB=m
1309 +CONFIG_RT73USB=m
1310 +CONFIG_RT2800USB=m
1311 +CONFIG_RT2800USB_RT53XX=y
1312 +CONFIG_RTL8192CU=m
1313 +CONFIG_WL1251=m
1314 +CONFIG_WL12XX_MENU=m
1315 +CONFIG_ZD1211RW=m
1316 +CONFIG_MWIFIEX=m
1317 +CONFIG_MWIFIEX_SDIO=m
1318 +CONFIG_WIMAX_I2400M_USB=m
1319 +CONFIG_USB_CATC=m
1320 +CONFIG_USB_KAWETH=m
1321 +CONFIG_USB_PEGASUS=m
1322 +CONFIG_USB_RTL8150=m
1323 +CONFIG_USB_USBNET=y
1324 +CONFIG_USB_NET_AX8817X=m
1325 +CONFIG_USB_NET_CDCETHER=m
1326 +CONFIG_USB_NET_CDC_EEM=m
1327 +CONFIG_USB_NET_DM9601=m
1328 +CONFIG_USB_NET_SMSC75XX=m
1329 +CONFIG_USB_NET_SMSC95XX=y
1330 +CONFIG_USB_NET_GL620A=m
1331 +CONFIG_USB_NET_NET1080=m
1332 +CONFIG_USB_NET_PLUSB=m
1333 +CONFIG_USB_NET_MCS7830=m
1334 +CONFIG_USB_NET_CDC_SUBSET=m
1335 +CONFIG_USB_ALI_M5632=y
1336 +CONFIG_USB_AN2720=y
1337 +CONFIG_USB_KC2190=y
1338 +# CONFIG_USB_NET_ZAURUS is not set
1339 +CONFIG_USB_NET_CX82310_ETH=m
1340 +CONFIG_USB_NET_KALMIA=m
1341 +CONFIG_USB_NET_INT51X1=m
1342 +CONFIG_USB_IPHETH=m
1343 +CONFIG_USB_SIERRA_NET=m
1344 +CONFIG_USB_VL600=m
1345 +CONFIG_PPP=m
1346 +CONFIG_PPP_ASYNC=m
1347 +CONFIG_PPP_SYNC_TTY=m
1348 +CONFIG_PPP_DEFLATE=m
1349 +CONFIG_PPP_BSDCOMP=m
1350 +CONFIG_SLIP=m
1351 +CONFIG_SLIP_COMPRESSED=y
1352 +CONFIG_NETCONSOLE=m
1353 +CONFIG_INPUT_POLLDEV=m
1354 +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
1355 +CONFIG_INPUT_JOYDEV=m
1356 +CONFIG_INPUT_EVDEV=m
1357 +# CONFIG_INPUT_KEYBOARD is not set
1358 +# CONFIG_INPUT_MOUSE is not set
1359 +CONFIG_INPUT_MISC=y
1360 +CONFIG_INPUT_AD714X=m
1361 +CONFIG_INPUT_ATI_REMOTE=m
1362 +CONFIG_INPUT_ATI_REMOTE2=m
1363 +CONFIG_INPUT_KEYSPAN_REMOTE=m
1364 +CONFIG_INPUT_POWERMATE=m
1365 +CONFIG_INPUT_YEALINK=m
1366 +CONFIG_INPUT_CM109=m
1367 +CONFIG_INPUT_UINPUT=m
1368 +CONFIG_INPUT_GPIO_ROTARY_ENCODER=m
1369 +CONFIG_INPUT_ADXL34X=m
1370 +CONFIG_INPUT_CMA3000=m
1371 +CONFIG_SERIO=m
1372 +CONFIG_SERIO_RAW=m
1373 +CONFIG_GAMEPORT=m
1374 +CONFIG_GAMEPORT_NS558=m
1375 +CONFIG_GAMEPORT_L4=m
1376 +CONFIG_VT_HW_CONSOLE_BINDING=y
1377 +# CONFIG_LEGACY_PTYS is not set
1378 +# CONFIG_DEVKMEM is not set
1379 +CONFIG_SERIAL_AMBA_PL011=y
1380 +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
1381 +# CONFIG_HW_RANDOM is not set
1382 +CONFIG_RAW_DRIVER=y
1383 +CONFIG_GPIO_SYSFS=y
1384 +# CONFIG_HWMON is not set
1385 +CONFIG_WATCHDOG=y
1386 +CONFIG_BCM2708_WDT=m
1387 +# CONFIG_MFD_SUPPORT is not set
1388 +CONFIG_FB=y
1389 +CONFIG_FB_BCM2708=y
1390 +CONFIG_FRAMEBUFFER_CONSOLE=y
1391 +CONFIG_LOGO=y
1392 +# CONFIG_LOGO_LINUX_MONO is not set
1393 +# CONFIG_LOGO_LINUX_VGA16 is not set
1394 +CONFIG_SOUND=y
1395 +CONFIG_SND=m
1396 +CONFIG_SND_SEQUENCER=m
1397 +CONFIG_SND_SEQ_DUMMY=m
1398 +CONFIG_SND_MIXER_OSS=m
1399 +CONFIG_SND_PCM_OSS=m
1400 +CONFIG_SND_SEQUENCER_OSS=y
1401 +CONFIG_SND_HRTIMER=m
1402 +CONFIG_SND_DUMMY=m
1403 +CONFIG_SND_ALOOP=m
1404 +CONFIG_SND_VIRMIDI=m
1405 +CONFIG_SND_MTPAV=m
1406 +CONFIG_SND_SERIAL_U16550=m
1407 +CONFIG_SND_MPU401=m
1408 +CONFIG_SND_BCM2835=m
1409 +CONFIG_SND_USB_AUDIO=m
1410 +CONFIG_SND_USB_UA101=m
1411 +CONFIG_SND_USB_CAIAQ=m
1412 +CONFIG_SND_USB_6FIRE=m
1413 +CONFIG_SOUND_PRIME=m
1414 +CONFIG_HID_PID=y
1415 +CONFIG_USB_HIDDEV=y
1416 +CONFIG_HID_A4TECH=m
1417 +CONFIG_HID_ACRUX=m
1418 +CONFIG_HID_APPLE=m
1419 +CONFIG_HID_BELKIN=m
1420 +CONFIG_HID_CHERRY=m
1421 +CONFIG_HID_CHICONY=m
1422 +CONFIG_HID_CYPRESS=m
1423 +CONFIG_HID_DRAGONRISE=m
1424 +CONFIG_HID_EMS_FF=m
1425 +CONFIG_HID_ELECOM=m
1426 +CONFIG_HID_EZKEY=m
1427 +CONFIG_HID_HOLTEK=m
1428 +CONFIG_HID_KEYTOUCH=m
1429 +CONFIG_HID_KYE=m
1430 +CONFIG_HID_UCLOGIC=m
1431 +CONFIG_HID_WALTOP=m
1432 +CONFIG_HID_GYRATION=m
1433 +CONFIG_HID_TWINHAN=m
1434 +CONFIG_HID_KENSINGTON=m
1435 +CONFIG_HID_LCPOWER=m
1436 +CONFIG_HID_LOGITECH=m
1437 +CONFIG_HID_MAGICMOUSE=m
1438 +CONFIG_HID_MICROSOFT=m
1439 +CONFIG_HID_MONTEREY=m
1440 +CONFIG_HID_MULTITOUCH=m
1441 +CONFIG_HID_NTRIG=m
1442 +CONFIG_HID_ORTEK=m
1443 +CONFIG_HID_PANTHERLORD=m
1444 +CONFIG_HID_PETALYNX=m
1445 +CONFIG_HID_PICOLCD=m
1446 +CONFIG_HID_QUANTA=m
1447 +CONFIG_HID_ROCCAT=m
1448 +CONFIG_HID_SAMSUNG=m
1449 +CONFIG_HID_SONY=m
1450 +CONFIG_HID_SPEEDLINK=m
1451 +CONFIG_HID_SUNPLUS=m
1452 +CONFIG_HID_GREENASIA=m
1453 +CONFIG_HID_SMARTJOYPLUS=m
1454 +CONFIG_HID_TOPSEED=m
1455 +CONFIG_HID_THRUSTMASTER=m
1456 +CONFIG_HID_WACOM=m
1457 +CONFIG_HID_WIIMOTE=m
1458 +CONFIG_HID_ZEROPLUS=m
1459 +CONFIG_HID_ZYDACRON=m
1460 +CONFIG_USB=y
1461 +CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
1462 +CONFIG_USB_MON=m
1463 +CONFIG_USB_DWCOTG=y
1464 +CONFIG_USB_STORAGE=y
1465 +CONFIG_USB_STORAGE_REALTEK=m
1466 +CONFIG_USB_STORAGE_DATAFAB=m
1467 +CONFIG_USB_STORAGE_FREECOM=m
1468 +CONFIG_USB_STORAGE_ISD200=m
1469 +CONFIG_USB_STORAGE_USBAT=m
1470 +CONFIG_USB_STORAGE_SDDR09=m
1471 +CONFIG_USB_STORAGE_SDDR55=m
1472 +CONFIG_USB_STORAGE_JUMPSHOT=m
1473 +CONFIG_USB_STORAGE_ALAUDA=m
1474 +CONFIG_USB_STORAGE_ONETOUCH=m
1475 +CONFIG_USB_STORAGE_KARMA=m
1476 +CONFIG_USB_STORAGE_CYPRESS_ATACB=m
1477 +CONFIG_USB_STORAGE_ENE_UB6250=m
1478 +CONFIG_USB_UAS=y
1479 +CONFIG_USB_LIBUSUAL=y
1480 +CONFIG_USB_MDC800=m
1481 +CONFIG_USB_MICROTEK=m
1482 +CONFIG_USB_SERIAL=m
1483 +CONFIG_USB_SERIAL_GENERIC=y
1484 +CONFIG_USB_SERIAL_AIRCABLE=m
1485 +CONFIG_USB_SERIAL_ARK3116=m
1486 +CONFIG_USB_SERIAL_BELKIN=m
1487 +CONFIG_USB_SERIAL_CH341=m
1488 +CONFIG_USB_SERIAL_WHITEHEAT=m
1489 +CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m
1490 +CONFIG_USB_SERIAL_CP210X=m
1491 +CONFIG_USB_SERIAL_CYPRESS_M8=m
1492 +CONFIG_USB_SERIAL_EMPEG=m
1493 +CONFIG_USB_SERIAL_FTDI_SIO=m
1494 +CONFIG_USB_SERIAL_FUNSOFT=m
1495 +CONFIG_USB_SERIAL_VISOR=m
1496 +CONFIG_USB_SERIAL_IPAQ=m
1497 +CONFIG_USB_SERIAL_IR=m
1498 +CONFIG_USB_SERIAL_EDGEPORT=m
1499 +CONFIG_USB_SERIAL_EDGEPORT_TI=m
1500 +CONFIG_USB_SERIAL_GARMIN=m
1501 +CONFIG_USB_SERIAL_IPW=m
1502 +CONFIG_USB_SERIAL_IUU=m
1503 +CONFIG_USB_SERIAL_KEYSPAN_PDA=m
1504 +CONFIG_USB_SERIAL_KEYSPAN=m
1505 +CONFIG_USB_SERIAL_KLSI=m
1506 +CONFIG_USB_SERIAL_KOBIL_SCT=m
1507 +CONFIG_USB_SERIAL_MCT_U232=m
1508 +CONFIG_USB_SERIAL_MOS7720=m
1509 +CONFIG_USB_SERIAL_MOS7840=m
1510 +CONFIG_USB_SERIAL_MOTOROLA=m
1511 +CONFIG_USB_SERIAL_NAVMAN=m
1512 +CONFIG_USB_SERIAL_PL2303=m
1513 +CONFIG_USB_SERIAL_OTI6858=m
1514 +CONFIG_USB_SERIAL_QCAUX=m
1515 +CONFIG_USB_SERIAL_QUALCOMM=m
1516 +CONFIG_USB_SERIAL_SPCP8X5=m
1517 +CONFIG_USB_SERIAL_HP4X=m
1518 +CONFIG_USB_SERIAL_SAFE=m
1519 +CONFIG_USB_SERIAL_SIEMENS_MPI=m
1520 +CONFIG_USB_SERIAL_SIERRAWIRELESS=m
1521 +CONFIG_USB_SERIAL_SYMBOL=m
1522 +CONFIG_USB_SERIAL_TI=m
1523 +CONFIG_USB_SERIAL_CYBERJACK=m
1524 +CONFIG_USB_SERIAL_XIRCOM=m
1525 +CONFIG_USB_SERIAL_OPTION=m
1526 +CONFIG_USB_SERIAL_OMNINET=m
1527 +CONFIG_USB_SERIAL_OPTICON=m
1528 +CONFIG_USB_SERIAL_VIVOPAY_SERIAL=m
1529 +CONFIG_USB_SERIAL_ZIO=m
1530 +CONFIG_USB_SERIAL_SSU100=m
1531 +CONFIG_USB_SERIAL_DEBUG=m
1532 +CONFIG_USB_EMI62=m
1533 +CONFIG_USB_EMI26=m
1534 +CONFIG_USB_ADUTUX=m
1535 +CONFIG_USB_SEVSEG=m
1536 +CONFIG_USB_RIO500=m
1537 +CONFIG_USB_LEGOTOWER=m
1538 +CONFIG_USB_LCD=m
1539 +CONFIG_USB_LED=m
1540 +CONFIG_USB_CYPRESS_CY7C63=m
1541 +CONFIG_USB_CYTHERM=m
1542 +CONFIG_USB_IDMOUSE=m
1543 +CONFIG_USB_FTDI_ELAN=m
1544 +CONFIG_USB_APPLEDISPLAY=m
1545 +CONFIG_USB_LD=m
1546 +CONFIG_USB_TRANCEVIBRATOR=m
1547 +CONFIG_USB_IOWARRIOR=m
1548 +CONFIG_USB_TEST=m
1549 +CONFIG_USB_ISIGHTFW=m
1550 +CONFIG_USB_YUREX=m
1551 +CONFIG_MMC=y
1552 +CONFIG_MMC_SDHCI=y
1553 +CONFIG_MMC_SDHCI_PLTFM=y
1554 +CONFIG_MMC_SDHCI_BCM2708=y
1555 +CONFIG_MMC_SDHCI_BCM2708_DMA=y
1556 +CONFIG_LEDS_GPIO=y
1557 +CONFIG_LEDS_TRIGGER_TIMER=m
1558 +CONFIG_LEDS_TRIGGER_HEARTBEAT=m
1559 +CONFIG_LEDS_TRIGGER_DEFAULT_ON=m
1560 +CONFIG_UIO=m
1561 +CONFIG_UIO_PDRV=m
1562 +CONFIG_UIO_PDRV_GENIRQ=m
1563 +# CONFIG_IOMMU_SUPPORT is not set
1564 +CONFIG_EXT4_FS=y
1565 +CONFIG_EXT4_FS_POSIX_ACL=y
1566 +CONFIG_EXT4_FS_SECURITY=y
1567 +CONFIG_REISERFS_FS=m
1568 +CONFIG_REISERFS_FS_XATTR=y
1569 +CONFIG_REISERFS_FS_POSIX_ACL=y
1570 +CONFIG_REISERFS_FS_SECURITY=y
1571 +CONFIG_JFS_FS=m
1572 +CONFIG_JFS_POSIX_ACL=y
1573 +CONFIG_JFS_SECURITY=y
1574 +CONFIG_JFS_STATISTICS=y
1575 +CONFIG_XFS_FS=m
1576 +CONFIG_XFS_QUOTA=y
1577 +CONFIG_XFS_POSIX_ACL=y
1578 +CONFIG_XFS_RT=y
1579 +CONFIG_GFS2_FS=m
1580 +CONFIG_OCFS2_FS=m
1581 +CONFIG_BTRFS_FS=m
1582 +CONFIG_BTRFS_FS_POSIX_ACL=y
1583 +CONFIG_NILFS2_FS=m
1584 +CONFIG_FANOTIFY=y
1585 +CONFIG_AUTOFS4_FS=y
1586 +CONFIG_FUSE_FS=m
1587 +CONFIG_CUSE=m
1588 +CONFIG_FSCACHE=y
1589 +CONFIG_FSCACHE_STATS=y
1590 +CONFIG_FSCACHE_HISTOGRAM=y
1591 +CONFIG_CACHEFILES=y
1592 +CONFIG_ISO9660_FS=m
1593 +CONFIG_JOLIET=y
1594 +CONFIG_ZISOFS=y
1595 +CONFIG_UDF_FS=m
1596 +CONFIG_MSDOS_FS=y
1597 +CONFIG_VFAT_FS=y
1598 +CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
1599 +CONFIG_NTFS_FS=m
1600 +CONFIG_TMPFS=y
1601 +CONFIG_TMPFS_POSIX_ACL=y
1602 +CONFIG_CONFIGFS_FS=y
1603 +CONFIG_SQUASHFS=m
1604 +CONFIG_SQUASHFS_XATTR=y
1605 +CONFIG_SQUASHFS_LZO=y
1606 +CONFIG_SQUASHFS_XZ=y
1607 +CONFIG_NFS_FS=y
1608 +CONFIG_NFS_V3=y
1609 +CONFIG_NFS_V3_ACL=y
1610 +CONFIG_NFS_V4=y
1611 +CONFIG_ROOT_NFS=y
1612 +CONFIG_NFS_FSCACHE=y
1613 +CONFIG_CIFS=m
1614 +CONFIG_CIFS_WEAK_PW_HASH=y
1615 +CONFIG_CIFS_XATTR=y
1616 +CONFIG_CIFS_POSIX=y
1617 +CONFIG_9P_FS=m
1618 +CONFIG_9P_FS_POSIX_ACL=y
1619 +CONFIG_PARTITION_ADVANCED=y
1620 +CONFIG_MAC_PARTITION=y
1621 +CONFIG_EFI_PARTITION=y
1622 +CONFIG_NLS_DEFAULT="utf8"
1623 +CONFIG_NLS_CODEPAGE_437=y
1624 +CONFIG_NLS_CODEPAGE_737=m
1625 +CONFIG_NLS_CODEPAGE_775=m
1626 +CONFIG_NLS_CODEPAGE_850=m
1627 +CONFIG_NLS_CODEPAGE_852=m
1628 +CONFIG_NLS_CODEPAGE_855=m
1629 +CONFIG_NLS_CODEPAGE_857=m
1630 +CONFIG_NLS_CODEPAGE_860=m
1631 +CONFIG_NLS_CODEPAGE_861=m
1632 +CONFIG_NLS_CODEPAGE_862=m
1633 +CONFIG_NLS_CODEPAGE_863=m
1634 +CONFIG_NLS_CODEPAGE_864=m
1635 +CONFIG_NLS_CODEPAGE_865=m
1636 +CONFIG_NLS_CODEPAGE_866=m
1637 +CONFIG_NLS_CODEPAGE_869=m
1638 +CONFIG_NLS_CODEPAGE_936=m
1639 +CONFIG_NLS_CODEPAGE_950=m
1640 +CONFIG_NLS_CODEPAGE_932=m
1641 +CONFIG_NLS_CODEPAGE_949=m
1642 +CONFIG_NLS_CODEPAGE_874=m
1643 +CONFIG_NLS_ISO8859_8=m
1644 +CONFIG_NLS_CODEPAGE_1250=m
1645 +CONFIG_NLS_CODEPAGE_1251=m
1646 +CONFIG_NLS_ASCII=y
1647 +CONFIG_NLS_ISO8859_1=m
1648 +CONFIG_NLS_ISO8859_2=m
1649 +CONFIG_NLS_ISO8859_3=m
1650 +CONFIG_NLS_ISO8859_4=m
1651 +CONFIG_NLS_ISO8859_5=m
1652 +CONFIG_NLS_ISO8859_6=m
1653 +CONFIG_NLS_ISO8859_7=m
1654 +CONFIG_NLS_ISO8859_9=m
1655 +CONFIG_NLS_ISO8859_13=m
1656 +CONFIG_NLS_ISO8859_14=m
1657 +CONFIG_NLS_ISO8859_15=m
1658 +CONFIG_NLS_KOI8_R=m
1659 +CONFIG_NLS_KOI8_U=m
1660 +CONFIG_NLS_UTF8=m
1661 +CONFIG_PRINTK_TIME=y
1662 +CONFIG_DETECT_HUNG_TASK=y
1663 +CONFIG_TIMER_STATS=y
1664 +CONFIG_DEBUG_STACK_USAGE=y
1665 +CONFIG_DEBUG_INFO=y
1666 +CONFIG_DEBUG_MEMORY_INIT=y
1667 +CONFIG_BOOT_PRINTK_DELAY=y
1668 +CONFIG_LATENCYTOP=y
1669 +CONFIG_SYSCTL_SYSCALL_CHECK=y
1670 +CONFIG_IRQSOFF_TRACER=y
1671 +CONFIG_SCHED_TRACER=y
1672 +CONFIG_STACK_TRACER=y
1673 +CONFIG_BLK_DEV_IO_TRACE=y
1674 +CONFIG_FUNCTION_PROFILER=y
1675 +CONFIG_KGDB=y
1676 +CONFIG_KGDB_KDB=y
1677 +CONFIG_KDB_KEYBOARD=y
1678 +CONFIG_STRICT_DEVMEM=y
1679 +CONFIG_CRYPTO_AUTHENC=m
1680 +CONFIG_CRYPTO_SEQIV=m
1681 +CONFIG_CRYPTO_CBC=y
1682 +CONFIG_CRYPTO_HMAC=y
1683 +CONFIG_CRYPTO_XCBC=m
1684 +CONFIG_CRYPTO_MD5=y
1685 +CONFIG_CRYPTO_SHA1=y
1686 +CONFIG_CRYPTO_SHA256=m
1687 +CONFIG_CRYPTO_SHA512=m
1688 +CONFIG_CRYPTO_TGR192=m
1689 +CONFIG_CRYPTO_WP512=m
1690 +CONFIG_CRYPTO_CAST5=m
1691 +CONFIG_CRYPTO_DES=y
1692 +CONFIG_CRYPTO_DEFLATE=m
1693 +# CONFIG_CRYPTO_ANSI_CPRNG is not set
1694 +# CONFIG_CRYPTO_HW is not set
1695 +CONFIG_CRC_ITU_T=y
1696 +CONFIG_LIBCRC32C=y
1697 diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
1698 index ac4c2e5..d3a6810 100644
1699 --- a/arch/arm/kernel/process.c
1700 +++ b/arch/arm/kernel/process.c
1701 @@ -174,7 +174,7 @@ void arch_cpu_idle(void)
1702 default_idle();
1703 }
1704
1705 -static char reboot_mode = 'h';
1706 +char reboot_mode = 'h';
1707
1708 int __init reboot_setup(char *str)
1709 {
1710 diff --git a/arch/arm/mach-bcm2708/Kconfig b/arch/arm/mach-bcm2708/Kconfig
1711 new file mode 100644
1712 index 0000000..63bb76c
1713 --- /dev/null
1714 +++ b/arch/arm/mach-bcm2708/Kconfig
1715 @@ -0,0 +1,34 @@
1716 +menu "Broadcom BCM2708 Implementations"
1717 + depends on ARCH_BCM2708
1718 +
1719 +config MACH_BCM2708
1720 + bool "Broadcom BCM2708 Development Platform"
1721 + select NEED_MACH_MEMORY_H
1722 + select NEED_MACH_IO_H
1723 + select CPU_V6
1724 + help
1725 + Include support for the Broadcom(R) BCM2708 platform.
1726 +
1727 +config BCM2708_GPIO
1728 + bool "BCM2708 gpio support"
1729 + depends on MACH_BCM2708
1730 + select ARCH_REQUIRE_GPIOLIB
1731 + default y
1732 + help
1733 + Include support for the Broadcom(R) BCM2708 gpio.
1734 +
1735 +config BCM2708_VCMEM
1736 + bool "Videocore Memory"
1737 + depends on MACH_BCM2708
1738 + default y
1739 + help
1740 + Helper for videocore memory access and total size allocation.
1741 +
1742 +config BCM2708_NOL2CACHE
1743 + bool "Videocore L2 cache disable"
1744 + depends on MACH_BCM2708
1745 + default n
1746 + help
1747 + Do not allow ARM to use GPU's L2 cache. Requires disable_l2cache in config.txt.
1748 +
1749 +endmenu
1750 diff --git a/arch/arm/mach-bcm2708/Makefile b/arch/arm/mach-bcm2708/Makefile
1751 new file mode 100644
1752 index 0000000..164ecb2
1753 --- /dev/null
1754 +++ b/arch/arm/mach-bcm2708/Makefile
1755 @@ -0,0 +1,8 @@
1756 +#
1757 +# Makefile for the linux kernel.
1758 +#
1759 +
1760 +obj-$(CONFIG_MACH_BCM2708) += clock.o bcm2708.o armctrl.o vcio.o power.o dma.o
1761 +obj-$(CONFIG_BCM2708_GPIO) += bcm2708_gpio.o
1762 +obj-$(CONFIG_BCM2708_VCMEM) += vc_mem.o
1763 +
1764 diff --git a/arch/arm/mach-bcm2708/Makefile.boot b/arch/arm/mach-bcm2708/Makefile.boot
1765 new file mode 100644
1766 index 0000000..67039c3
1767 --- /dev/null
1768 +++ b/arch/arm/mach-bcm2708/Makefile.boot
1769 @@ -0,0 +1,3 @@
1770 + zreladdr-y := 0x00008000
1771 +params_phys-y := 0x00000100
1772 +initrd_phys-y := 0x00800000
1773 diff --git a/arch/arm/mach-bcm2708/armctrl.c b/arch/arm/mach-bcm2708/armctrl.c
1774 new file mode 100644
1775 index 0000000..da18725
1776 --- /dev/null
1777 +++ b/arch/arm/mach-bcm2708/armctrl.c
1778 @@ -0,0 +1,208 @@
1779 +/*
1780 + * linux/arch/arm/mach-bcm2708/armctrl.c
1781 + *
1782 + * Copyright (C) 2010 Broadcom
1783 + *
1784 + * This program is free software; you can redistribute it and/or modify
1785 + * it under the terms of the GNU General Public License as published by
1786 + * the Free Software Foundation; either version 2 of the License, or
1787 + * (at your option) any later version.
1788 + *
1789 + * This program is distributed in the hope that it will be useful,
1790 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
1791 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
1792 + * GNU General Public License for more details.
1793 + *
1794 + * You should have received a copy of the GNU General Public License
1795 + * along with this program; if not, write to the Free Software
1796 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
1797 + */
1798 +#include <linux/init.h>
1799 +#include <linux/list.h>
1800 +#include <linux/io.h>
1801 +#include <linux/version.h>
1802 +#include <linux/syscore_ops.h>
1803 +#include <linux/interrupt.h>
1804 +
1805 +#include <asm/mach/irq.h>
1806 +#include <mach/hardware.h>
1807 +#include "armctrl.h"
1808 +
1809 +/* For support of kernels >= 3.0 assume only one VIC for now*/
1810 +static unsigned int remap_irqs[(INTERRUPT_ARASANSDIO + 1) - INTERRUPT_JPEG] = {
1811 + INTERRUPT_VC_JPEG,
1812 + INTERRUPT_VC_USB,
1813 + INTERRUPT_VC_3D,
1814 + INTERRUPT_VC_DMA2,
1815 + INTERRUPT_VC_DMA3,
1816 + INTERRUPT_VC_I2C,
1817 + INTERRUPT_VC_SPI,
1818 + INTERRUPT_VC_I2SPCM,
1819 + INTERRUPT_VC_SDIO,
1820 + INTERRUPT_VC_UART,
1821 + INTERRUPT_VC_ARASANSDIO
1822 +};
1823 +
1824 +static void armctrl_mask_irq(struct irq_data *d)
1825 +{
1826 + static const unsigned int disables[4] = {
1827 + ARM_IRQ_DIBL1,
1828 + ARM_IRQ_DIBL2,
1829 + ARM_IRQ_DIBL3,
1830 + 0
1831 + };
1832 +
1833 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1834 + writel(1 << (data & 0x1f), __io_address(disables[(data >> 5) & 0x3]));
1835 +}
1836 +
1837 +static void armctrl_unmask_irq(struct irq_data *d)
1838 +{
1839 + static const unsigned int enables[4] = {
1840 + ARM_IRQ_ENBL1,
1841 + ARM_IRQ_ENBL2,
1842 + ARM_IRQ_ENBL3,
1843 + 0
1844 + };
1845 +
1846 + unsigned int data = (unsigned int)irq_get_chip_data(d->irq);
1847 + writel(1 << (data & 0x1f), __io_address(enables[(data >> 5) & 0x3]));
1848 +}
1849 +
1850 +#if defined(CONFIG_PM)
1851 +
1852 +/* for kernels 3.xx use the new syscore_ops apis but for older kernels use the sys dev class */
1853 +
1854 +/* Static defines
1855 + * struct armctrl_device - VIC PM device (< 3.xx)
1856 + * @sysdev: The system device which is registered. (< 3.xx)
1857 + * @irq: The IRQ number for the base of the VIC.
1858 + * @base: The register base for the VIC.
1859 + * @resume_sources: A bitmask of interrupts for resume.
1860 + * @resume_irqs: The IRQs enabled for resume.
1861 + * @int_select: Save for VIC_INT_SELECT.
1862 + * @int_enable: Save for VIC_INT_ENABLE.
1863 + * @soft_int: Save for VIC_INT_SOFT.
1864 + * @protect: Save for VIC_PROTECT.
1865 + */
1866 +struct armctrl_info {
1867 + void __iomem *base;
1868 + int irq;
1869 + u32 resume_sources;
1870 + u32 resume_irqs;
1871 + u32 int_select;
1872 + u32 int_enable;
1873 + u32 soft_int;
1874 + u32 protect;
1875 +} armctrl;
1876 +
1877 +static int armctrl_suspend(void)
1878 +{
1879 + return 0;
1880 +}
1881 +
1882 +static void armctrl_resume(void)
1883 +{
1884 + return;
1885 +}
1886 +
1887 +/**
1888 + * armctrl_pm_register - Register a VIC for later power management control
1889 + * @base: The base address of the VIC.
1890 + * @irq: The base IRQ for the VIC.
1891 + * @resume_sources: bitmask of interrupts allowed for resume sources.
1892 + *
1893 + * For older kernels (< 3.xx) do -
1894 + * Register the VIC with the system device tree so that it can be notified
1895 + * of suspend and resume requests and ensure that the correct actions are
1896 + * taken to re-instate the settings on resume.
1897 + */
1898 +static void __init armctrl_pm_register(void __iomem * base, unsigned int irq,
1899 + u32 resume_sources)
1900 +{
1901 + armctrl.base = base;
1902 + armctrl.resume_sources = resume_sources;
1903 + armctrl.irq = irq;
1904 +}
1905 +
1906 +static int armctrl_set_wake(struct irq_data *d, unsigned int on)
1907 +{
1908 + unsigned int off = d->irq & 31;
1909 + u32 bit = 1 << off;
1910 +
1911 + if (!(bit & armctrl.resume_sources))
1912 + return -EINVAL;
1913 +
1914 + if (on)
1915 + armctrl.resume_irqs |= bit;
1916 + else
1917 + armctrl.resume_irqs &= ~bit;
1918 +
1919 + return 0;
1920 +}
1921 +
1922 +#else
1923 +static inline void armctrl_pm_register(void __iomem * base, unsigned int irq,
1924 + u32 arg1)
1925 +{
1926 +}
1927 +
1928 +#define armctrl_suspend NULL
1929 +#define armctrl_resume NULL
1930 +#define armctrl_set_wake NULL
1931 +#endif /* CONFIG_PM */
1932 +
1933 +static struct syscore_ops armctrl_syscore_ops = {
1934 + .suspend = armctrl_suspend,
1935 + .resume = armctrl_resume,
1936 +};
1937 +
1938 +/**
1939 + * armctrl_syscore_init - initicall to register VIC pm functions
1940 + *
1941 + * This is called via late_initcall() to register
1942 + * the resources for the VICs due to the early
1943 + * nature of the VIC's registration.
1944 +*/
1945 +static int __init armctrl_syscore_init(void)
1946 +{
1947 + register_syscore_ops(&armctrl_syscore_ops);
1948 + return 0;
1949 +}
1950 +
1951 +late_initcall(armctrl_syscore_init);
1952 +
1953 +static struct irq_chip armctrl_chip = {
1954 + .name = "ARMCTRL",
1955 + .irq_ack = armctrl_mask_irq,
1956 + .irq_mask = armctrl_mask_irq,
1957 + .irq_unmask = armctrl_unmask_irq,
1958 + .irq_set_wake = armctrl_set_wake,
1959 +};
1960 +
1961 +/**
1962 + * armctrl_init - initialise a vectored interrupt controller
1963 + * @base: iomem base address
1964 + * @irq_start: starting interrupt number, must be muliple of 32
1965 + * @armctrl_sources: bitmask of interrupt sources to allow
1966 + * @resume_sources: bitmask of interrupt sources to allow for resume
1967 + */
1968 +int __init armctrl_init(void __iomem * base, unsigned int irq_start,
1969 + u32 armctrl_sources, u32 resume_sources)
1970 +{
1971 + unsigned int irq;
1972 +
1973 + for (irq = 0; irq < NR_IRQS; irq++) {
1974 + unsigned int data = irq;
1975 + if (irq >= INTERRUPT_JPEG && irq <= INTERRUPT_ARASANSDIO)
1976 + data = remap_irqs[irq - INTERRUPT_JPEG];
1977 +
1978 + irq_set_chip(irq, &armctrl_chip);
1979 + irq_set_chip_data(irq, (void *)data);
1980 + irq_set_handler(irq, handle_level_irq);
1981 + set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_DISABLED);
1982 + }
1983 +
1984 + armctrl_pm_register(base, irq_start, resume_sources);
1985 + return 0;
1986 +}
1987 diff --git a/arch/arm/mach-bcm2708/armctrl.h b/arch/arm/mach-bcm2708/armctrl.h
1988 new file mode 100644
1989 index 0000000..0aa916e
1990 --- /dev/null
1991 +++ b/arch/arm/mach-bcm2708/armctrl.h
1992 @@ -0,0 +1,27 @@
1993 +/*
1994 + * linux/arch/arm/mach-bcm2708/armctrl.h
1995 + *
1996 + * Copyright (C) 2010 Broadcom
1997 + *
1998 + * This program is free software; you can redistribute it and/or modify
1999 + * it under the terms of the GNU General Public License as published by
2000 + * the Free Software Foundation; either version 2 of the License, or
2001 + * (at your option) any later version.
2002 + *
2003 + * This program is distributed in the hope that it will be useful,
2004 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2005 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2006 + * GNU General Public License for more details.
2007 + *
2008 + * You should have received a copy of the GNU General Public License
2009 + * along with this program; if not, write to the Free Software
2010 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2011 + */
2012 +
2013 +#ifndef __BCM2708_ARMCTRL_H
2014 +#define __BCM2708_ARMCTRL_H
2015 +
2016 +extern int __init armctrl_init(void __iomem * base, unsigned int irq_start,
2017 + u32 armctrl_sources, u32 resume_sources);
2018 +
2019 +#endif
2020 diff --git a/arch/arm/mach-bcm2708/bcm2708.c b/arch/arm/mach-bcm2708/bcm2708.c
2021 new file mode 100644
2022 index 0000000..64a2783
2023 --- /dev/null
2024 +++ b/arch/arm/mach-bcm2708/bcm2708.c
2025 @@ -0,0 +1,695 @@
2026 +/*
2027 + * linux/arch/arm/mach-bcm2708/bcm2708.c
2028 + *
2029 + * Copyright (C) 2010 Broadcom
2030 + *
2031 + * This program is free software; you can redistribute it and/or modify
2032 + * it under the terms of the GNU General Public License as published by
2033 + * the Free Software Foundation; either version 2 of the License, or
2034 + * (at your option) any later version.
2035 + *
2036 + * This program is distributed in the hope that it will be useful,
2037 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2038 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2039 + * GNU General Public License for more details.
2040 + *
2041 + * You should have received a copy of the GNU General Public License
2042 + * along with this program; if not, write to the Free Software
2043 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2044 + */
2045 +
2046 +#include <linux/init.h>
2047 +#include <linux/device.h>
2048 +#include <linux/dma-mapping.h>
2049 +#include <linux/serial_8250.h>
2050 +#include <linux/platform_device.h>
2051 +#include <linux/syscore_ops.h>
2052 +#include <linux/interrupt.h>
2053 +#include <linux/amba/bus.h>
2054 +#include <linux/amba/clcd.h>
2055 +#include <linux/clockchips.h>
2056 +#include <linux/cnt32_to_63.h>
2057 +#include <linux/io.h>
2058 +#include <linux/module.h>
2059 +
2060 +#include <linux/version.h>
2061 +#include <linux/clkdev.h>
2062 +#include <asm/system.h>
2063 +#include <mach/hardware.h>
2064 +#include <asm/irq.h>
2065 +#include <linux/leds.h>
2066 +#include <asm/mach-types.h>
2067 +#include <asm/sched_clock.h>
2068 +
2069 +#include <asm/mach/arch.h>
2070 +#include <asm/mach/flash.h>
2071 +#include <asm/mach/irq.h>
2072 +#include <asm/mach/time.h>
2073 +#include <asm/mach/map.h>
2074 +
2075 +#include <mach/timex.h>
2076 +#include <mach/dma.h>
2077 +#include <mach/vcio.h>
2078 +#include <mach/system.h>
2079 +
2080 +#include <linux/delay.h>
2081 +
2082 +#include "bcm2708.h"
2083 +#include "armctrl.h"
2084 +#include "clock.h"
2085 +
2086 +/* Effectively we have an IOMMU (ARM<->VideoCore map) that is set up to
2087 + * give us IO access only to 64Mbytes of physical memory (26 bits). We could
2088 + * represent this window by setting our dmamasks to 26 bits but, in fact
2089 + * we're not going to use addresses outside this range (they're not in real
2090 + * memory) so we don't bother.
2091 + *
2092 + * In the future we might include code to use this IOMMU to remap other
2093 + * physical addresses onto VideoCore memory then the use of 32-bits would be
2094 + * more legitimate.
2095 + */
2096 +#define DMA_MASK_BITS_COMMON 32
2097 +
2098 +/* command line parameters */
2099 +static unsigned boardrev, serial;
2100 +static unsigned uart_clock;
2101 +static unsigned reboot_part = 0;
2102 +
2103 +static void __init bcm2708_init_led(void);
2104 +
2105 +void __init bcm2708_init_irq(void)
2106 +{
2107 + armctrl_init(__io_address(ARMCTRL_IC_BASE), 0, 0, 0);
2108 +}
2109 +
2110 +static struct map_desc bcm2708_io_desc[] __initdata = {
2111 + {
2112 + .virtual = IO_ADDRESS(ARMCTRL_BASE),
2113 + .pfn = __phys_to_pfn(ARMCTRL_BASE),
2114 + .length = SZ_4K,
2115 + .type = MT_DEVICE},
2116 + {
2117 + .virtual = IO_ADDRESS(UART0_BASE),
2118 + .pfn = __phys_to_pfn(UART0_BASE),
2119 + .length = SZ_4K,
2120 + .type = MT_DEVICE},
2121 + {
2122 + .virtual = IO_ADDRESS(UART1_BASE),
2123 + .pfn = __phys_to_pfn(UART1_BASE),
2124 + .length = SZ_4K,
2125 + .type = MT_DEVICE},
2126 + {
2127 + .virtual = IO_ADDRESS(DMA_BASE),
2128 + .pfn = __phys_to_pfn(DMA_BASE),
2129 + .length = SZ_4K,
2130 + .type = MT_DEVICE},
2131 + {
2132 + .virtual = IO_ADDRESS(MCORE_BASE),
2133 + .pfn = __phys_to_pfn(MCORE_BASE),
2134 + .length = SZ_4K,
2135 + .type = MT_DEVICE},
2136 + {
2137 + .virtual = IO_ADDRESS(ST_BASE),
2138 + .pfn = __phys_to_pfn(ST_BASE),
2139 + .length = SZ_4K,
2140 + .type = MT_DEVICE},
2141 + {
2142 + .virtual = IO_ADDRESS(USB_BASE),
2143 + .pfn = __phys_to_pfn(USB_BASE),
2144 + .length = SZ_128K,
2145 + .type = MT_DEVICE},
2146 + {
2147 + .virtual = IO_ADDRESS(PM_BASE),
2148 + .pfn = __phys_to_pfn(PM_BASE),
2149 + .length = SZ_4K,
2150 + .type = MT_DEVICE},
2151 + {
2152 + .virtual = IO_ADDRESS(GPIO_BASE),
2153 + .pfn = __phys_to_pfn(GPIO_BASE),
2154 + .length = SZ_4K,
2155 + .type = MT_DEVICE}
2156 +};
2157 +
2158 +void __init bcm2708_map_io(void)
2159 +{
2160 + iotable_init(bcm2708_io_desc, ARRAY_SIZE(bcm2708_io_desc));
2161 +}
2162 +
2163 +/* The STC is a free running counter that increments at the rate of 1MHz */
2164 +#define STC_FREQ_HZ 1000000
2165 +
2166 +static inline uint32_t timer_read(void)
2167 +{
2168 + /* STC: a free running counter that increments at the rate of 1MHz */
2169 + return readl(__io_address(ST_BASE + 0x04));
2170 +}
2171 +
2172 +static unsigned long bcm2708_read_current_timer(void)
2173 +{
2174 + return timer_read();
2175 +}
2176 +
2177 +static u32 notrace bcm2708_read_sched_clock(void)
2178 +{
2179 + return timer_read();
2180 +}
2181 +
2182 +static cycle_t clksrc_read(struct clocksource *cs)
2183 +{
2184 + return timer_read();
2185 +}
2186 +
2187 +static struct clocksource clocksource_stc = {
2188 + .name = "stc",
2189 + .rating = 300,
2190 + .read = clksrc_read,
2191 + .mask = CLOCKSOURCE_MASK(32),
2192 + .flags = CLOCK_SOURCE_IS_CONTINUOUS,
2193 +};
2194 +
2195 +unsigned long frc_clock_ticks32(void)
2196 +{
2197 + return timer_read();
2198 +}
2199 +
2200 +static void __init bcm2708_clocksource_init(void)
2201 +{
2202 + if (clocksource_register_hz(&clocksource_stc, STC_FREQ_HZ)) {
2203 + printk(KERN_ERR "timer: failed to initialize clock "
2204 + "source %s\n", clocksource_stc.name);
2205 + }
2206 +}
2207 +
2208 +
2209 +/*
2210 + * These are fixed clocks.
2211 + */
2212 +static struct clk ref24_clk = {
2213 + .rate = UART0_CLOCK, /* The UART is clocked at 3MHz via APB_CLK */
2214 +};
2215 +
2216 +static struct clk osc_clk = {
2217 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2218 + .rate = 27000000,
2219 +#else
2220 + .rate = 500000000, /* ARM clock is set from the VideoCore booter */
2221 +#endif
2222 +};
2223 +
2224 +/* warning - the USB needs a clock > 34MHz */
2225 +
2226 +#ifdef CONFIG_MMC_BCM2708
2227 +static struct clk sdhost_clk = {
2228 +#ifdef CONFIG_ARCH_BCM2708_CHIPIT
2229 + .rate = 4000000, /* 4MHz */
2230 +#else
2231 + .rate = 250000000, /* 250MHz */
2232 +#endif
2233 +};
2234 +#endif
2235 +
2236 +static struct clk_lookup lookups[] = {
2237 + { /* UART0 */
2238 + .dev_id = "dev:f1",
2239 + .clk = &ref24_clk,
2240 + },
2241 + { /* USB */
2242 + .dev_id = "bcm2708_usb",
2243 + .clk = &osc_clk,
2244 + }
2245 +};
2246 +
2247 +#define UART0_IRQ { IRQ_UART, 0 /*NO_IRQ*/ }
2248 +#define UART0_DMA { 15, 14 }
2249 +
2250 +AMBA_DEVICE(uart0, "dev:f1", UART0, NULL);
2251 +
2252 +static struct amba_device *amba_devs[] __initdata = {
2253 + &uart0_device,
2254 +};
2255 +
2256 +static struct resource bcm2708_dmaman_resources[] = {
2257 + {
2258 + .start = DMA_BASE,
2259 + .end = DMA_BASE + SZ_4K - 1,
2260 + .flags = IORESOURCE_MEM,
2261 + }
2262 +};
2263 +
2264 +static struct platform_device bcm2708_dmaman_device = {
2265 + .name = BCM_DMAMAN_DRIVER_NAME,
2266 + .id = 0, /* first bcm2708_dma */
2267 + .resource = bcm2708_dmaman_resources,
2268 + .num_resources = ARRAY_SIZE(bcm2708_dmaman_resources),
2269 +};
2270 +
2271 +static u64 fb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2272 +
2273 +static struct platform_device bcm2708_fb_device = {
2274 + .name = "bcm2708_fb",
2275 + .id = -1, /* only one bcm2708_fb */
2276 + .resource = NULL,
2277 + .num_resources = 0,
2278 + .dev = {
2279 + .dma_mask = &fb_dmamask,
2280 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2281 + },
2282 +};
2283 +
2284 +static struct plat_serial8250_port bcm2708_uart1_platform_data[] = {
2285 + {
2286 + .mapbase = UART1_BASE + 0x40,
2287 + .irq = IRQ_AUX,
2288 + .uartclk = 125000000,
2289 + .regshift = 2,
2290 + .iotype = UPIO_MEM,
2291 + .flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_SKIP_TEST,
2292 + .type = PORT_8250,
2293 + },
2294 + {},
2295 +};
2296 +
2297 +static struct platform_device bcm2708_uart1_device = {
2298 + .name = "serial8250",
2299 + .id = PLAT8250_DEV_PLATFORM,
2300 + .dev = {
2301 + .platform_data = bcm2708_uart1_platform_data,
2302 + },
2303 +};
2304 +
2305 +static struct resource bcm2708_usb_resources[] = {
2306 + [0] = {
2307 + .start = USB_BASE,
2308 + .end = USB_BASE + SZ_128K - 1,
2309 + .flags = IORESOURCE_MEM,
2310 + },
2311 + [1] = {
2312 + .start = IRQ_USB,
2313 + .end = IRQ_USB,
2314 + .flags = IORESOURCE_IRQ,
2315 + },
2316 +};
2317 +
2318 +static u64 usb_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2319 +
2320 +static struct platform_device bcm2708_usb_device = {
2321 + .name = "bcm2708_usb",
2322 + .id = -1, /* only one bcm2708_usb */
2323 + .resource = bcm2708_usb_resources,
2324 + .num_resources = ARRAY_SIZE(bcm2708_usb_resources),
2325 + .dev = {
2326 + .dma_mask = &usb_dmamask,
2327 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2328 + },
2329 +};
2330 +
2331 +static struct resource bcm2708_vcio_resources[] = {
2332 + [0] = { /* mailbox/semaphore/doorbell access */
2333 + .start = MCORE_BASE,
2334 + .end = MCORE_BASE + SZ_4K - 1,
2335 + .flags = IORESOURCE_MEM,
2336 + },
2337 +};
2338 +
2339 +static u64 vcio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2340 +
2341 +static struct platform_device bcm2708_vcio_device = {
2342 + .name = BCM_VCIO_DRIVER_NAME,
2343 + .id = -1, /* only one VideoCore I/O area */
2344 + .resource = bcm2708_vcio_resources,
2345 + .num_resources = ARRAY_SIZE(bcm2708_vcio_resources),
2346 + .dev = {
2347 + .dma_mask = &vcio_dmamask,
2348 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2349 + },
2350 +};
2351 +
2352 +#ifdef CONFIG_BCM2708_GPIO
2353 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2354 +
2355 +static struct resource bcm2708_gpio_resources[] = {
2356 + [0] = { /* general purpose I/O */
2357 + .start = GPIO_BASE,
2358 + .end = GPIO_BASE + SZ_4K - 1,
2359 + .flags = IORESOURCE_MEM,
2360 + },
2361 +};
2362 +
2363 +static u64 gpio_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2364 +
2365 +static struct platform_device bcm2708_gpio_device = {
2366 + .name = BCM_GPIO_DRIVER_NAME,
2367 + .id = -1, /* only one VideoCore I/O area */
2368 + .resource = bcm2708_gpio_resources,
2369 + .num_resources = ARRAY_SIZE(bcm2708_gpio_resources),
2370 + .dev = {
2371 + .dma_mask = &gpio_dmamask,
2372 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2373 + },
2374 +};
2375 +#endif
2376 +
2377 +static struct resource bcm2708_systemtimer_resources[] = {
2378 + [0] = { /* system timer access */
2379 + .start = ST_BASE,
2380 + .end = ST_BASE + SZ_4K - 1,
2381 + .flags = IORESOURCE_MEM,
2382 + },
2383 + {
2384 + .start = IRQ_TIMER3,
2385 + .end = IRQ_TIMER3,
2386 + .flags = IORESOURCE_IRQ,
2387 + }
2388 +
2389 +};
2390 +
2391 +static u64 systemtimer_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2392 +
2393 +static struct platform_device bcm2708_systemtimer_device = {
2394 + .name = "bcm2708_systemtimer",
2395 + .id = -1, /* only one VideoCore I/O area */
2396 + .resource = bcm2708_systemtimer_resources,
2397 + .num_resources = ARRAY_SIZE(bcm2708_systemtimer_resources),
2398 + .dev = {
2399 + .dma_mask = &systemtimer_dmamask,
2400 + .coherent_dma_mask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON),
2401 + },
2402 +};
2403 +
2404 +#ifdef CONFIG_MMC_SDHCI_BCM2708 /* Arasan emmc SD */
2405 +static struct resource bcm2708_emmc_resources[] = {
2406 + [0] = {
2407 + .start = EMMC_BASE,
2408 + .end = EMMC_BASE + SZ_256 - 1, /* we only need this area */
2409 + /* the memory map actually makes SZ_4K available */
2410 + .flags = IORESOURCE_MEM,
2411 + },
2412 + [1] = {
2413 + .start = IRQ_ARASANSDIO,
2414 + .end = IRQ_ARASANSDIO,
2415 + .flags = IORESOURCE_IRQ,
2416 + },
2417 +};
2418 +
2419 +static u64 bcm2708_emmc_dmamask = 0xffffffffUL;
2420 +
2421 +struct platform_device bcm2708_emmc_device = {
2422 + .name = "bcm2708_sdhci",
2423 + .id = 0,
2424 + .num_resources = ARRAY_SIZE(bcm2708_emmc_resources),
2425 + .resource = bcm2708_emmc_resources,
2426 + .dev = {
2427 + .dma_mask = &bcm2708_emmc_dmamask,
2428 + .coherent_dma_mask = 0xffffffffUL},
2429 +};
2430 +#endif /* CONFIG_MMC_SDHCI_BCM2708 */
2431 +
2432 +static struct resource bcm2708_powerman_resources[] = {
2433 + [0] = {
2434 + .start = PM_BASE,
2435 + .end = PM_BASE + SZ_256 - 1,
2436 + .flags = IORESOURCE_MEM,
2437 + },
2438 +};
2439 +
2440 +static u64 powerman_dmamask = DMA_BIT_MASK(DMA_MASK_BITS_COMMON);
2441 +
2442 +struct platform_device bcm2708_powerman_device = {
2443 + .name = "bcm2708_powerman",
2444 + .id = 0,
2445 + .num_resources = ARRAY_SIZE(bcm2708_powerman_resources),
2446 + .resource = bcm2708_powerman_resources,
2447 + .dev = {
2448 + .dma_mask = &powerman_dmamask,
2449 + .coherent_dma_mask = 0xffffffffUL},
2450 +};
2451 +
2452 +int __init bcm_register_device(struct platform_device *pdev)
2453 +{
2454 + int ret;
2455 +
2456 + ret = platform_device_register(pdev);
2457 + if (ret)
2458 + pr_debug("Unable to register platform device '%s': %d\n",
2459 + pdev->name, ret);
2460 +
2461 + return ret;
2462 +}
2463 +
2464 +int calc_rsts(int partition)
2465 +{
2466 + return PM_PASSWORD |
2467 + ((partition & (1 << 0)) << 0) |
2468 + ((partition & (1 << 1)) << 1) |
2469 + ((partition & (1 << 2)) << 2) |
2470 + ((partition & (1 << 3)) << 3) |
2471 + ((partition & (1 << 4)) << 4) |
2472 + ((partition & (1 << 5)) << 5);
2473 +}
2474 +
2475 +static void bcm2708_restart(char mode, const char *cmd)
2476 +{
2477 + uint32_t pm_rstc, pm_wdog;
2478 + uint32_t timeout = 10;
2479 + uint32_t pm_rsts = 0;
2480 +
2481 + if(mode == 'q')
2482 + {
2483 + // NOOBS < 1.3 booting with reboot=q
2484 + pm_rsts = readl(__io_address(PM_RSTS));
2485 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRQ_SET;
2486 + }
2487 + else if(mode == 'p')
2488 + {
2489 + // NOOBS < 1.3 halting
2490 + pm_rsts = readl(__io_address(PM_RSTS));
2491 + pm_rsts = PM_PASSWORD | pm_rsts | PM_RSTS_HADWRH_SET;
2492 + }
2493 + else
2494 + {
2495 + pm_rsts = calc_rsts(reboot_part);
2496 + }
2497 +
2498 + writel(pm_rsts, __io_address(PM_RSTS));
2499 +
2500 + /* Setup watchdog for reset */
2501 + pm_rstc = readl(__io_address(PM_RSTC));
2502 +
2503 + pm_wdog = PM_PASSWORD | (timeout & PM_WDOG_TIME_SET); // watchdog timer = timer clock / 16; need password (31:16) + value (11:0)
2504 + pm_rstc = PM_PASSWORD | (pm_rstc & PM_RSTC_WRCFG_CLR) | PM_RSTC_WRCFG_FULL_RESET;
2505 +
2506 + writel(pm_wdog, __io_address(PM_WDOG));
2507 + writel(pm_rstc, __io_address(PM_RSTC));
2508 +}
2509 +
2510 +/* We can't really power off, but if we do the normal reset scheme, and indicate to bootcode.bin not to reboot, then most of the chip will be powered off */
2511 +static void bcm2708_power_off(void)
2512 +{
2513 + extern char reboot_mode;
2514 +
2515 + if(reboot_mode == 'q')
2516 + {
2517 + // NOOBS < v1.3
2518 + bcm2708_restart('p', "");
2519 + }
2520 + else
2521 + {
2522 + /* partition 63 is special code for HALT the bootloader knows not to boot*/
2523 + reboot_part = 63;
2524 + /* continue with normal reset mechanism */
2525 + bcm2708_restart(0, "");
2526 + }
2527 +}
2528 +
2529 +void __init bcm2708_init(void)
2530 +{
2531 + int i;
2532 +
2533 + printk("bcm2708.uart_clock = %d\n", uart_clock);
2534 + pm_power_off = bcm2708_power_off;
2535 +
2536 + if (uart_clock)
2537 + lookups[0].clk->rate = uart_clock;
2538 +
2539 + for (i = 0; i < ARRAY_SIZE(lookups); i++)
2540 + clkdev_add(&lookups[i]);
2541 +
2542 + bcm_register_device(&bcm2708_dmaman_device);
2543 + bcm_register_device(&bcm2708_vcio_device);
2544 +#ifdef CONFIG_BCM2708_GPIO
2545 + bcm_register_device(&bcm2708_gpio_device);
2546 +#endif
2547 + bcm_register_device(&bcm2708_systemtimer_device);
2548 + bcm_register_device(&bcm2708_fb_device);
2549 + bcm_register_device(&bcm2708_usb_device);
2550 + bcm_register_device(&bcm2708_uart1_device);
2551 + bcm_register_device(&bcm2708_powerman_device);
2552 +
2553 +#ifdef CONFIG_MMC_SDHCI_BCM2708
2554 + bcm_register_device(&bcm2708_emmc_device);
2555 +#endif
2556 + bcm2708_init_led();
2557 +
2558 + for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
2559 + struct amba_device *d = amba_devs[i];
2560 + amba_device_register(d, &iomem_resource);
2561 + }
2562 + system_rev = boardrev;
2563 + system_serial_low = serial;
2564 +}
2565 +
2566 +static void timer_set_mode(enum clock_event_mode mode,
2567 + struct clock_event_device *clk)
2568 +{
2569 + switch (mode) {
2570 + case CLOCK_EVT_MODE_ONESHOT: /* Leave the timer disabled, .set_next_event will enable it */
2571 + case CLOCK_EVT_MODE_SHUTDOWN:
2572 + break;
2573 + case CLOCK_EVT_MODE_PERIODIC:
2574 +
2575 + case CLOCK_EVT_MODE_UNUSED:
2576 + case CLOCK_EVT_MODE_RESUME:
2577 +
2578 + default:
2579 + printk(KERN_ERR "timer_set_mode: unhandled mode:%d\n",
2580 + (int)mode);
2581 + break;
2582 + }
2583 +
2584 +}
2585 +
2586 +static int timer_set_next_event(unsigned long cycles,
2587 + struct clock_event_device *unused)
2588 +{
2589 + unsigned long stc;
2590 +
2591 + stc = readl(__io_address(ST_BASE + 0x04));
2592 + writel(stc + cycles, __io_address(ST_BASE + 0x18)); /* stc3 */
2593 + return 0;
2594 +}
2595 +
2596 +static struct clock_event_device timer0_clockevent = {
2597 + .name = "timer0",
2598 + .shift = 32,
2599 + .features = CLOCK_EVT_FEAT_ONESHOT,
2600 + .set_mode = timer_set_mode,
2601 + .set_next_event = timer_set_next_event,
2602 +};
2603 +
2604 +/*
2605 + * IRQ handler for the timer
2606 + */
2607 +static irqreturn_t bcm2708_timer_interrupt(int irq, void *dev_id)
2608 +{
2609 + struct clock_event_device *evt = &timer0_clockevent;
2610 +
2611 + writel(1 << 3, __io_address(ST_BASE + 0x00)); /* stcs clear timer int */
2612 +
2613 + evt->event_handler(evt);
2614 +
2615 + return IRQ_HANDLED;
2616 +}
2617 +
2618 +static struct irqaction bcm2708_timer_irq = {
2619 + .name = "BCM2708 Timer Tick",
2620 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
2621 + .handler = bcm2708_timer_interrupt,
2622 +};
2623 +
2624 +/*
2625 + * Set up timer interrupt, and return the current time in seconds.
2626 + */
2627 +
2628 +static struct delay_timer bcm2708_delay_timer = {
2629 + .read_current_timer = bcm2708_read_current_timer,
2630 + .freq = STC_FREQ_HZ,
2631 +};
2632 +
2633 +static void __init bcm2708_timer_init(void)
2634 +{
2635 + /* init high res timer */
2636 + bcm2708_clocksource_init();
2637 +
2638 + /*
2639 + * Initialise to a known state (all timers off)
2640 + */
2641 + writel(0, __io_address(ARM_T_CONTROL));
2642 + /*
2643 + * Make irqs happen for the system timer
2644 + */
2645 + setup_irq(IRQ_TIMER3, &bcm2708_timer_irq);
2646 +
2647 + setup_sched_clock(bcm2708_read_sched_clock, 32, STC_FREQ_HZ);
2648 +
2649 + timer0_clockevent.mult =
2650 + div_sc(STC_FREQ_HZ, NSEC_PER_SEC, timer0_clockevent.shift);
2651 + timer0_clockevent.max_delta_ns =
2652 + clockevent_delta2ns(0xffffffff, &timer0_clockevent);
2653 + timer0_clockevent.min_delta_ns =
2654 + clockevent_delta2ns(0xf, &timer0_clockevent);
2655 +
2656 + timer0_clockevent.cpumask = cpumask_of(0);
2657 + clockevents_register_device(&timer0_clockevent);
2658 +
2659 + register_current_timer_delay(&bcm2708_delay_timer);
2660 +}
2661 +
2662 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
2663 +#include <linux/leds.h>
2664 +
2665 +static struct gpio_led bcm2708_leds[] = {
2666 + [0] = {
2667 + .gpio = 16,
2668 + .name = "led0",
2669 + .default_trigger = "mmc0",
2670 + .active_low = 1,
2671 + },
2672 +};
2673 +
2674 +static struct gpio_led_platform_data bcm2708_led_pdata = {
2675 + .num_leds = ARRAY_SIZE(bcm2708_leds),
2676 + .leds = bcm2708_leds,
2677 +};
2678 +
2679 +static struct platform_device bcm2708_led_device = {
2680 + .name = "leds-gpio",
2681 + .id = -1,
2682 + .dev = {
2683 + .platform_data = &bcm2708_led_pdata,
2684 + },
2685 +};
2686 +
2687 +static void __init bcm2708_init_led(void)
2688 +{
2689 + platform_device_register(&bcm2708_led_device);
2690 +}
2691 +#else
2692 +static inline void bcm2708_init_led(void)
2693 +{
2694 +}
2695 +#endif
2696 +
2697 +void __init bcm2708_init_early(void)
2698 +{
2699 + /*
2700 + * Some devices allocate their coherent buffers from atomic
2701 + * context. Increase size of atomic coherent pool to make sure such
2702 + * the allocations won't fail.
2703 + */
2704 + init_dma_coherent_pool_size(SZ_4M);
2705 +}
2706 +
2707 +MACHINE_START(BCM2708, "BCM2708")
2708 + /* Maintainer: Broadcom Europe Ltd. */
2709 + .map_io = bcm2708_map_io,
2710 + .init_irq = bcm2708_init_irq,
2711 + .init_time = bcm2708_timer_init,
2712 + .init_machine = bcm2708_init,
2713 + .init_early = bcm2708_init_early,
2714 + .restart = bcm2708_restart,
2715 +MACHINE_END
2716 +
2717 +module_param(boardrev, uint, 0644);
2718 +module_param(serial, uint, 0644);
2719 +module_param(uart_clock, uint, 0644);
2720 +module_param(reboot_part, uint, 0644);
2721 diff --git a/arch/arm/mach-bcm2708/bcm2708.h b/arch/arm/mach-bcm2708/bcm2708.h
2722 new file mode 100644
2723 index 0000000..dfe8700
2724 --- /dev/null
2725 +++ b/arch/arm/mach-bcm2708/bcm2708.h
2726 @@ -0,0 +1,51 @@
2727 +/*
2728 + * linux/arch/arm/mach-bcm2708/bcm2708.h
2729 + *
2730 + * BCM2708 machine support header
2731 + *
2732 + * Copyright (C) 2010 Broadcom
2733 + *
2734 + * This program is free software; you can redistribute it and/or modify
2735 + * it under the terms of the GNU General Public License as published by
2736 + * the Free Software Foundation; either version 2 of the License, or
2737 + * (at your option) any later version.
2738 + *
2739 + * This program is distributed in the hope that it will be useful,
2740 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
2741 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2742 + * GNU General Public License for more details.
2743 + *
2744 + * You should have received a copy of the GNU General Public License
2745 + * along with this program; if not, write to the Free Software
2746 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
2747 + */
2748 +
2749 +#ifndef __BCM2708_BCM2708_H
2750 +#define __BCM2708_BCM2708_H
2751 +
2752 +#include <linux/amba/bus.h>
2753 +
2754 +extern void __init bcm2708_init(void);
2755 +extern void __init bcm2708_init_irq(void);
2756 +extern void __init bcm2708_map_io(void);
2757 +extern struct sys_timer bcm2708_timer;
2758 +extern unsigned int mmc_status(struct device *dev);
2759 +
2760 +#define AMBA_DEVICE(name, busid, base, plat) \
2761 +static struct amba_device name##_device = { \
2762 + .dev = { \
2763 + .coherent_dma_mask = ~0, \
2764 + .init_name = busid, \
2765 + .platform_data = plat, \
2766 + }, \
2767 + .res = { \
2768 + .start = base##_BASE, \
2769 + .end = (base##_BASE) + SZ_4K - 1,\
2770 + .flags = IORESOURCE_MEM, \
2771 + }, \
2772 + .dma_mask = ~0, \
2773 + .irq = base##_IRQ, \
2774 + /* .dma = base##_DMA,*/ \
2775 +}
2776 +
2777 +#endif
2778 diff --git a/arch/arm/mach-bcm2708/bcm2708_gpio.c b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2779 new file mode 100644
2780 index 0000000..d0339eb
2781 --- /dev/null
2782 +++ b/arch/arm/mach-bcm2708/bcm2708_gpio.c
2783 @@ -0,0 +1,339 @@
2784 +/*
2785 + * linux/arch/arm/mach-bcm2708/bcm2708_gpio.c
2786 + *
2787 + * Copyright (C) 2010 Broadcom
2788 + *
2789 + * This program is free software; you can redistribute it and/or modify
2790 + * it under the terms of the GNU General Public License version 2 as
2791 + * published by the Free Software Foundation.
2792 + *
2793 + */
2794 +
2795 +#include <linux/spinlock.h>
2796 +#include <linux/module.h>
2797 +#include <linux/list.h>
2798 +#include <linux/io.h>
2799 +#include <linux/irq.h>
2800 +#include <linux/interrupt.h>
2801 +#include <linux/slab.h>
2802 +#include <mach/gpio.h>
2803 +#include <linux/gpio.h>
2804 +#include <linux/platform_device.h>
2805 +#include <mach/platform.h>
2806 +
2807 +#define BCM_GPIO_DRIVER_NAME "bcm2708_gpio"
2808 +#define DRIVER_NAME BCM_GPIO_DRIVER_NAME
2809 +#define BCM_GPIO_USE_IRQ 1
2810 +
2811 +#define GPIOFSEL(x) (0x00+(x)*4)
2812 +#define GPIOSET(x) (0x1c+(x)*4)
2813 +#define GPIOCLR(x) (0x28+(x)*4)
2814 +#define GPIOLEV(x) (0x34+(x)*4)
2815 +#define GPIOEDS(x) (0x40+(x)*4)
2816 +#define GPIOREN(x) (0x4c+(x)*4)
2817 +#define GPIOFEN(x) (0x58+(x)*4)
2818 +#define GPIOHEN(x) (0x64+(x)*4)
2819 +#define GPIOLEN(x) (0x70+(x)*4)
2820 +#define GPIOAREN(x) (0x7c+(x)*4)
2821 +#define GPIOAFEN(x) (0x88+(x)*4)
2822 +#define GPIOUD(x) (0x94+(x)*4)
2823 +#define GPIOUDCLK(x) (0x98+(x)*4)
2824 +
2825 +enum { GPIO_FSEL_INPUT, GPIO_FSEL_OUTPUT,
2826 + GPIO_FSEL_ALT5, GPIO_FSEL_ALT_4,
2827 + GPIO_FSEL_ALT0, GPIO_FSEL_ALT1,
2828 + GPIO_FSEL_ALT2, GPIO_FSEL_ALT3,
2829 +};
2830 +
2831 + /* Each of the two spinlocks protects a different set of hardware
2832 + * regiters and data structurs. This decouples the code of the IRQ from
2833 + * the GPIO code. This also makes the case of a GPIO routine call from
2834 + * the IRQ code simpler.
2835 + */
2836 +static DEFINE_SPINLOCK(lock); /* GPIO registers */
2837 +
2838 +struct bcm2708_gpio {
2839 + struct list_head list;
2840 + void __iomem *base;
2841 + struct gpio_chip gc;
2842 + unsigned long rising;
2843 + unsigned long falling;
2844 +};
2845 +
2846 +static int bcm2708_set_function(struct gpio_chip *gc, unsigned offset,
2847 + int function)
2848 +{
2849 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2850 + unsigned long flags;
2851 + unsigned gpiodir;
2852 + unsigned gpio_bank = offset / 10;
2853 + unsigned gpio_field_offset = (offset - 10 * gpio_bank) * 3;
2854 +
2855 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set_function %p (%d,%d)\n", gc, offset, function);
2856 + if (offset >= ARCH_NR_GPIOS)
2857 + return -EINVAL;
2858 +
2859 + spin_lock_irqsave(&lock, flags);
2860 +
2861 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2862 + gpiodir &= ~(7 << gpio_field_offset);
2863 + gpiodir |= function << gpio_field_offset;
2864 + writel(gpiodir, gpio->base + GPIOFSEL(gpio_bank));
2865 + spin_unlock_irqrestore(&lock, flags);
2866 + gpiodir = readl(gpio->base + GPIOFSEL(gpio_bank));
2867 +
2868 + return 0;
2869 +}
2870 +
2871 +static int bcm2708_gpio_dir_in(struct gpio_chip *gc, unsigned offset)
2872 +{
2873 + return bcm2708_set_function(gc, offset, GPIO_FSEL_INPUT);
2874 +}
2875 +
2876 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value);
2877 +static int bcm2708_gpio_dir_out(struct gpio_chip *gc, unsigned offset,
2878 + int value)
2879 +{
2880 + int ret;
2881 + ret = bcm2708_set_function(gc, offset, GPIO_FSEL_OUTPUT);
2882 + if (ret >= 0)
2883 + bcm2708_gpio_set(gc, offset, value);
2884 + return ret;
2885 +}
2886 +
2887 +static int bcm2708_gpio_get(struct gpio_chip *gc, unsigned offset)
2888 +{
2889 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2890 + unsigned gpio_bank = offset / 32;
2891 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2892 + unsigned lev;
2893 +
2894 + if (offset >= ARCH_NR_GPIOS)
2895 + return 0;
2896 + lev = readl(gpio->base + GPIOLEV(gpio_bank));
2897 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_get %p (%d)=%d\n", gc, offset, 0x1 & (lev>>gpio_field_offset));
2898 + return 0x1 & (lev >> gpio_field_offset);
2899 +}
2900 +
2901 +static void bcm2708_gpio_set(struct gpio_chip *gc, unsigned offset, int value)
2902 +{
2903 + struct bcm2708_gpio *gpio = container_of(gc, struct bcm2708_gpio, gc);
2904 + unsigned gpio_bank = offset / 32;
2905 + unsigned gpio_field_offset = (offset - 32 * gpio_bank);
2906 +//printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_set %p (%d=%d)\n", gc, offset, value);
2907 + if (offset >= ARCH_NR_GPIOS)
2908 + return;
2909 + if (value)
2910 + writel(1 << gpio_field_offset, gpio->base + GPIOSET(gpio_bank));
2911 + else
2912 + writel(1 << gpio_field_offset, gpio->base + GPIOCLR(gpio_bank));
2913 +}
2914 +
2915 +/*************************************************************************************************************************
2916 + * bcm2708 GPIO IRQ
2917 + */
2918 +
2919 +#if BCM_GPIO_USE_IRQ
2920 +
2921 +static int bcm2708_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2922 +{
2923 + return gpio_to_irq(gpio);
2924 +}
2925 +
2926 +static int bcm2708_gpio_irq_set_type(struct irq_data *d, unsigned type)
2927 +{
2928 + unsigned irq = d->irq;
2929 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2930 +
2931 + if (type & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
2932 + return -EINVAL;
2933 +
2934 + if (type & IRQ_TYPE_EDGE_RISING) {
2935 + gpio->rising |= (1 << irq_to_gpio(irq));
2936 + } else {
2937 + gpio->rising &= ~(1 << irq_to_gpio(irq));
2938 + }
2939 +
2940 + if (type & IRQ_TYPE_EDGE_FALLING) {
2941 + gpio->falling |= (1 << irq_to_gpio(irq));
2942 + } else {
2943 + gpio->falling &= ~(1 << irq_to_gpio(irq));
2944 + }
2945 + return 0;
2946 +}
2947 +
2948 +static void bcm2708_gpio_irq_mask(struct irq_data *d)
2949 +{
2950 + unsigned irq = d->irq;
2951 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2952 + unsigned gn = irq_to_gpio(irq);
2953 + unsigned gb = gn / 32;
2954 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2955 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2956 +
2957 + gn = gn % 32;
2958 +
2959 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2960 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2961 +}
2962 +
2963 +static void bcm2708_gpio_irq_unmask(struct irq_data *d)
2964 +{
2965 + unsigned irq = d->irq;
2966 + struct bcm2708_gpio *gpio = irq_get_chip_data(irq);
2967 + unsigned gn = irq_to_gpio(irq);
2968 + unsigned gb = gn / 32;
2969 + unsigned long rising = readl(gpio->base + GPIOREN(gb));
2970 + unsigned long falling = readl(gpio->base + GPIOFEN(gb));
2971 +
2972 + gn = gn % 32;
2973 +
2974 + writel(1 << gn, gpio->base + GPIOEDS(gb));
2975 +
2976 + if (gpio->rising & (1 << gn)) {
2977 + writel(rising | (1 << gn), gpio->base + GPIOREN(gb));
2978 + } else {
2979 + writel(rising & ~(1 << gn), gpio->base + GPIOREN(gb));
2980 + }
2981 +
2982 + if (gpio->falling & (1 << gn)) {
2983 + writel(falling | (1 << gn), gpio->base + GPIOFEN(gb));
2984 + } else {
2985 + writel(falling & ~(1 << gn), gpio->base + GPIOFEN(gb));
2986 + }
2987 +}
2988 +
2989 +static struct irq_chip bcm2708_irqchip = {
2990 + .name = "GPIO",
2991 + .irq_enable = bcm2708_gpio_irq_unmask,
2992 + .irq_disable = bcm2708_gpio_irq_mask,
2993 + .irq_unmask = bcm2708_gpio_irq_unmask,
2994 + .irq_mask = bcm2708_gpio_irq_mask,
2995 + .irq_set_type = bcm2708_gpio_irq_set_type,
2996 +};
2997 +
2998 +static irqreturn_t bcm2708_gpio_interrupt(int irq, void *dev_id)
2999 +{
3000 + unsigned long edsr;
3001 + unsigned bank;
3002 + int i;
3003 + unsigned gpio;
3004 + for (bank = 0; bank <= 1; bank++) {
3005 + edsr = readl(__io_address(GPIO_BASE) + GPIOEDS(bank));
3006 + for_each_set_bit(i, &edsr, 32) {
3007 + gpio = i + bank * 32;
3008 + generic_handle_irq(gpio_to_irq(gpio));
3009 + }
3010 + writel(0xffffffff, __io_address(GPIO_BASE) + GPIOEDS(bank));
3011 + }
3012 + return IRQ_HANDLED;
3013 +}
3014 +
3015 +static struct irqaction bcm2708_gpio_irq = {
3016 + .name = "BCM2708 GPIO catchall handler",
3017 + .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
3018 + .handler = bcm2708_gpio_interrupt,
3019 +};
3020 +
3021 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3022 +{
3023 + unsigned irq;
3024 +
3025 + ucb->gc.to_irq = bcm2708_gpio_to_irq;
3026 +
3027 + for (irq = GPIO_IRQ_START; irq < (GPIO_IRQ_START + GPIO_IRQS); irq++) {
3028 + irq_set_chip_data(irq, ucb);
3029 + irq_set_chip(irq, &bcm2708_irqchip);
3030 + set_irq_flags(irq, IRQF_VALID);
3031 + }
3032 + setup_irq(IRQ_GPIO3, &bcm2708_gpio_irq);
3033 +}
3034 +
3035 +#else
3036 +
3037 +static void bcm2708_gpio_irq_init(struct bcm2708_gpio *ucb)
3038 +{
3039 +}
3040 +
3041 +#endif /* #if BCM_GPIO_USE_IRQ ***************************************************************************************************************** */
3042 +
3043 +static int bcm2708_gpio_probe(struct platform_device *dev)
3044 +{
3045 + struct bcm2708_gpio *ucb;
3046 + struct resource *res;
3047 + int err = 0;
3048 +
3049 + printk(KERN_INFO DRIVER_NAME ": bcm2708_gpio_probe %p\n", dev);
3050 +
3051 + ucb = kzalloc(sizeof(*ucb), GFP_KERNEL);
3052 + if (NULL == ucb) {
3053 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3054 + "mailbox memory\n");
3055 + err = -ENOMEM;
3056 + goto err;
3057 + }
3058 +
3059 + res = platform_get_resource(dev, IORESOURCE_MEM, 0);
3060 +
3061 + platform_set_drvdata(dev, ucb);
3062 + ucb->base = __io_address(GPIO_BASE);
3063 +
3064 + ucb->gc.label = "bcm2708_gpio";
3065 + ucb->gc.base = 0;
3066 + ucb->gc.ngpio = ARCH_NR_GPIOS;
3067 + ucb->gc.owner = THIS_MODULE;
3068 +
3069 + ucb->gc.direction_input = bcm2708_gpio_dir_in;
3070 + ucb->gc.direction_output = bcm2708_gpio_dir_out;
3071 + ucb->gc.get = bcm2708_gpio_get;
3072 + ucb->gc.set = bcm2708_gpio_set;
3073 + ucb->gc.can_sleep = 0;
3074 +
3075 + bcm2708_gpio_irq_init(ucb);
3076 +
3077 + err = gpiochip_add(&ucb->gc);
3078 + if (err)
3079 + goto err;
3080 +
3081 +err:
3082 + return err;
3083 +
3084 +}
3085 +
3086 +static int bcm2708_gpio_remove(struct platform_device *dev)
3087 +{
3088 + int err = 0;
3089 + struct bcm2708_gpio *ucb = platform_get_drvdata(dev);
3090 +
3091 + printk(KERN_ERR DRIVER_NAME ": bcm2708_gpio_remove %p\n", dev);
3092 +
3093 + err = gpiochip_remove(&ucb->gc);
3094 +
3095 + platform_set_drvdata(dev, NULL);
3096 + kfree(ucb);
3097 +
3098 + return err;
3099 +}
3100 +
3101 +static struct platform_driver bcm2708_gpio_driver = {
3102 + .probe = bcm2708_gpio_probe,
3103 + .remove = bcm2708_gpio_remove,
3104 + .driver = {
3105 + .name = "bcm2708_gpio"},
3106 +};
3107 +
3108 +static int __init bcm2708_gpio_init(void)
3109 +{
3110 + return platform_driver_register(&bcm2708_gpio_driver);
3111 +}
3112 +
3113 +static void __exit bcm2708_gpio_exit(void)
3114 +{
3115 + platform_driver_unregister(&bcm2708_gpio_driver);
3116 +}
3117 +
3118 +module_init(bcm2708_gpio_init);
3119 +module_exit(bcm2708_gpio_exit);
3120 +
3121 +MODULE_DESCRIPTION("Broadcom BCM2708 GPIO driver");
3122 +MODULE_LICENSE("GPL");
3123 diff --git a/arch/arm/mach-bcm2708/clock.c b/arch/arm/mach-bcm2708/clock.c
3124 new file mode 100644
3125 index 0000000..4fc556e
3126 --- /dev/null
3127 +++ b/arch/arm/mach-bcm2708/clock.c
3128 @@ -0,0 +1,61 @@
3129 +/*
3130 + * linux/arch/arm/mach-bcm2708/clock.c
3131 + *
3132 + * Copyright (C) 2010 Broadcom
3133 + *
3134 + * This program is free software; you can redistribute it and/or modify
3135 + * it under the terms of the GNU General Public License as published by
3136 + * the Free Software Foundation; either version 2 of the License, or
3137 + * (at your option) any later version.
3138 + *
3139 + * This program is distributed in the hope that it will be useful,
3140 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3141 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3142 + * GNU General Public License for more details.
3143 + *
3144 + * You should have received a copy of the GNU General Public License
3145 + * along with this program; if not, write to the Free Software
3146 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3147 + */
3148 +#include <linux/module.h>
3149 +#include <linux/kernel.h>
3150 +#include <linux/device.h>
3151 +#include <linux/list.h>
3152 +#include <linux/errno.h>
3153 +#include <linux/err.h>
3154 +#include <linux/string.h>
3155 +#include <linux/clk.h>
3156 +#include <linux/mutex.h>
3157 +
3158 +#include <asm/clkdev.h>
3159 +
3160 +#include "clock.h"
3161 +
3162 +int clk_enable(struct clk *clk)
3163 +{
3164 + return 0;
3165 +}
3166 +EXPORT_SYMBOL(clk_enable);
3167 +
3168 +void clk_disable(struct clk *clk)
3169 +{
3170 +}
3171 +EXPORT_SYMBOL(clk_disable);
3172 +
3173 +unsigned long clk_get_rate(struct clk *clk)
3174 +{
3175 + return clk->rate;
3176 +}
3177 +EXPORT_SYMBOL(clk_get_rate);
3178 +
3179 +long clk_round_rate(struct clk *clk, unsigned long rate)
3180 +{
3181 + return clk->rate;
3182 +}
3183 +EXPORT_SYMBOL(clk_round_rate);
3184 +
3185 +int clk_set_rate(struct clk *clk, unsigned long rate)
3186 +{
3187 + return -EIO;
3188 +}
3189 +EXPORT_SYMBOL(clk_set_rate);
3190 diff --git a/arch/arm/mach-bcm2708/clock.h b/arch/arm/mach-bcm2708/clock.h
3191 new file mode 100644
3192 index 0000000..5f9d725
3193 --- /dev/null
3194 +++ b/arch/arm/mach-bcm2708/clock.h
3195 @@ -0,0 +1,24 @@
3196 +/*
3197 + * linux/arch/arm/mach-bcm2708/clock.h
3198 + *
3199 + * Copyright (C) 2010 Broadcom
3200 + *
3201 + * This program is free software; you can redistribute it and/or modify
3202 + * it under the terms of the GNU General Public License as published by
3203 + * the Free Software Foundation; either version 2 of the License, or
3204 + * (at your option) any later version.
3205 + *
3206 + * This program is distributed in the hope that it will be useful,
3207 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3208 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3209 + * GNU General Public License for more details.
3210 + *
3211 + * You should have received a copy of the GNU General Public License
3212 + * along with this program; if not, write to the Free Software
3213 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3214 + */
3215 +struct module;
3216 +
3217 +struct clk {
3218 + unsigned long rate;
3219 +};
3220 diff --git a/arch/arm/mach-bcm2708/dma.c b/arch/arm/mach-bcm2708/dma.c
3221 new file mode 100644
3222 index 0000000..51d147a
3223 --- /dev/null
3224 +++ b/arch/arm/mach-bcm2708/dma.c
3225 @@ -0,0 +1,399 @@
3226 +/*
3227 + * linux/arch/arm/mach-bcm2708/dma.c
3228 + *
3229 + * Copyright (C) 2010 Broadcom
3230 + *
3231 + * This program is free software; you can redistribute it and/or modify
3232 + * it under the terms of the GNU General Public License version 2 as
3233 + * published by the Free Software Foundation.
3234 + */
3235 +
3236 +#include <linux/slab.h>
3237 +#include <linux/device.h>
3238 +#include <linux/platform_device.h>
3239 +#include <linux/module.h>
3240 +#include <linux/scatterlist.h>
3241 +
3242 +#include <mach/dma.h>
3243 +#include <mach/irqs.h>
3244 +
3245 +/*****************************************************************************\
3246 + * *
3247 + * Configuration *
3248 + * *
3249 +\*****************************************************************************/
3250 +
3251 +#define CACHE_LINE_MASK 31
3252 +#define DRIVER_NAME BCM_DMAMAN_DRIVER_NAME
3253 +#define DEFAULT_DMACHAN_BITMAP 0x10 /* channel 4 only */
3254 +
3255 +/* valid only for channels 0 - 14, 15 has its own base address */
3256 +#define BCM2708_DMA_CHAN(n) ((n)<<8) /* base address */
3257 +#define BCM2708_DMA_CHANIO(dma_base, n) \
3258 + ((void __iomem *)((char *)(dma_base)+BCM2708_DMA_CHAN(n)))
3259 +
3260 +
3261 +/*****************************************************************************\
3262 + * *
3263 + * DMA Auxilliary Functions *
3264 + * *
3265 +\*****************************************************************************/
3266 +
3267 +/* A DMA buffer on an arbitrary boundary may separate a cache line into a
3268 + section inside the DMA buffer and another section outside it.
3269 + Even if we flush DMA buffers from the cache there is always the chance that
3270 + during a DMA someone will access the part of a cache line that is outside
3271 + the DMA buffer - which will then bring in unwelcome data.
3272 + Without being able to dictate our own buffer pools we must insist that
3273 + DMA buffers consist of a whole number of cache lines.
3274 +*/
3275 +
3276 +extern int
3277 +bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len)
3278 +{
3279 + int i;
3280 +
3281 + for (i = 0; i < sg_len; i++) {
3282 + if (sg_ptr[i].offset & CACHE_LINE_MASK ||
3283 + sg_ptr[i].length & CACHE_LINE_MASK)
3284 + return 0;
3285 + }
3286 +
3287 + return 1;
3288 +}
3289 +EXPORT_SYMBOL_GPL(bcm_sg_suitable_for_dma);
3290 +
3291 +extern void
3292 +bcm_dma_start(void __iomem *dma_chan_base, dma_addr_t control_block)
3293 +{
3294 + dsb(); /* ARM data synchronization (push) operation */
3295 +
3296 + writel(control_block, dma_chan_base + BCM2708_DMA_ADDR);
3297 + writel(BCM2708_DMA_ACTIVE, dma_chan_base + BCM2708_DMA_CS);
3298 +}
3299 +
3300 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base)
3301 +{
3302 + dsb();
3303 +
3304 + /* ugly busy wait only option for now */
3305 + while (readl(dma_chan_base + BCM2708_DMA_CS) & BCM2708_DMA_ACTIVE)
3306 + cpu_relax();
3307 +}
3308 +
3309 +EXPORT_SYMBOL_GPL(bcm_dma_start);
3310 +
3311 +/* Complete an ongoing DMA (assuming its results are to be ignored)
3312 + Does nothing if there is no DMA in progress.
3313 + This routine waits for the current AXI transfer to complete before
3314 + terminating the current DMA. If the current transfer is hung on a DREQ used
3315 + by an uncooperative peripheral the AXI transfer may never complete. In this
3316 + case the routine times out and return a non-zero error code.
3317 + Use of this routine doesn't guarantee that the ongoing or aborted DMA
3318 + does not produce an interrupt.
3319 +*/
3320 +extern int
3321 +bcm_dma_abort(void __iomem *dma_chan_base)
3322 +{
3323 + unsigned long int cs;
3324 + int rc = 0;
3325 +
3326 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3327 +
3328 + if (BCM2708_DMA_ACTIVE & cs) {
3329 + long int timeout = 10000;
3330 +
3331 + /* write 0 to the active bit - pause the DMA */
3332 + writel(0, dma_chan_base + BCM2708_DMA_CS);
3333 +
3334 + /* wait for any current AXI transfer to complete */
3335 + while (0 != (cs & BCM2708_DMA_ISPAUSED) && --timeout >= 0)
3336 + cs = readl(dma_chan_base + BCM2708_DMA_CS);
3337 +
3338 + if (0 != (cs & BCM2708_DMA_ISPAUSED)) {
3339 + /* we'll un-pause when we set of our next DMA */
3340 + rc = -ETIMEDOUT;
3341 +
3342 + } else if (BCM2708_DMA_ACTIVE & cs) {
3343 + /* terminate the control block chain */
3344 + writel(0, dma_chan_base + BCM2708_DMA_NEXTCB);
3345 +
3346 + /* abort the whole DMA */
3347 + writel(BCM2708_DMA_ABORT | BCM2708_DMA_ACTIVE,
3348 + dma_chan_base + BCM2708_DMA_CS);
3349 + }
3350 + }
3351 +
3352 + return rc;
3353 +}
3354 +EXPORT_SYMBOL_GPL(bcm_dma_abort);
3355 +
3356 +
3357 +/***************************************************************************** \
3358 + * *
3359 + * DMA Manager Device Methods *
3360 + * *
3361 +\*****************************************************************************/
3362 +
3363 +struct vc_dmaman {
3364 + void __iomem *dma_base;
3365 + u32 chan_available; /* bitmap of available channels */
3366 + u32 has_feature[BCM_DMA_FEATURE_COUNT]; /* bitmap of feature presence */
3367 +};
3368 +
3369 +static void vc_dmaman_init(struct vc_dmaman *dmaman, void __iomem *dma_base,
3370 + u32 chans_available)
3371 +{
3372 + dmaman->dma_base = dma_base;
3373 + dmaman->chan_available = chans_available;
3374 + dmaman->has_feature[BCM_DMA_FEATURE_FAST_ORD] = 0x0c; /* chans 2 & 3 */
3375 + dmaman->has_feature[BCM_DMA_FEATURE_BULK_ORD] = 0x01; /* chan 0 */
3376 +}
3377 +
3378 +static int vc_dmaman_chan_alloc(struct vc_dmaman *dmaman,
3379 + unsigned preferred_feature_set)
3380 +{
3381 + u32 chans;
3382 + int feature;
3383 +
3384 + chans = dmaman->chan_available;
3385 + for (feature = 0; feature < BCM_DMA_FEATURE_COUNT; feature++)
3386 + /* select the subset of available channels with the desired
3387 + feature so long as some of the candidate channels have that
3388 + feature */
3389 + if ((preferred_feature_set & (1 << feature)) &&
3390 + (chans & dmaman->has_feature[feature]))
3391 + chans &= dmaman->has_feature[feature];
3392 +
3393 + if (chans) {
3394 + int chan = 0;
3395 + /* return the ordinal of the first channel in the bitmap */
3396 + while (chans != 0 && (chans & 1) == 0) {
3397 + chans >>= 1;
3398 + chan++;
3399 + }
3400 + /* claim the channel */
3401 + dmaman->chan_available &= ~(1 << chan);
3402 + return chan;
3403 + } else
3404 + return -ENOMEM;
3405 +}
3406 +
3407 +static int vc_dmaman_chan_free(struct vc_dmaman *dmaman, int chan)
3408 +{
3409 + if (chan < 0)
3410 + return -EINVAL;
3411 + else if ((1 << chan) & dmaman->chan_available)
3412 + return -EIDRM;
3413 + else {
3414 + dmaman->chan_available |= (1 << chan);
3415 + return 0;
3416 + }
3417 +}
3418 +
3419 +/*****************************************************************************\
3420 + * *
3421 + * DMA IRQs *
3422 + * *
3423 +\*****************************************************************************/
3424 +
3425 +static unsigned char bcm_dma_irqs[] = {
3426 + IRQ_DMA0,
3427 + IRQ_DMA1,
3428 + IRQ_DMA2,
3429 + IRQ_DMA3,
3430 + IRQ_DMA4,
3431 + IRQ_DMA5,
3432 + IRQ_DMA6,
3433 + IRQ_DMA7,
3434 + IRQ_DMA8,
3435 + IRQ_DMA9,
3436 + IRQ_DMA10,
3437 + IRQ_DMA11,
3438 + IRQ_DMA12
3439 +};
3440 +
3441 +
3442 +/***************************************************************************** \
3443 + * *
3444 + * DMA Manager Monitor *
3445 + * *
3446 +\*****************************************************************************/
3447 +
3448 +static struct device *dmaman_dev; /* we assume there's only one! */
3449 +
3450 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
3451 + void __iomem **out_dma_base, int *out_dma_irq)
3452 +{
3453 + if (!dmaman_dev)
3454 + return -ENODEV;
3455 + else {
3456 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3457 + int rc;
3458 +
3459 + device_lock(dmaman_dev);
3460 + rc = vc_dmaman_chan_alloc(dmaman, preferred_feature_set);
3461 + if (rc >= 0) {
3462 + *out_dma_base = BCM2708_DMA_CHANIO(dmaman->dma_base,
3463 + rc);
3464 + *out_dma_irq = bcm_dma_irqs[rc];
3465 + }
3466 + device_unlock(dmaman_dev);
3467 +
3468 + return rc;
3469 + }
3470 +}
3471 +EXPORT_SYMBOL_GPL(bcm_dma_chan_alloc);
3472 +
3473 +extern int bcm_dma_chan_free(int channel)
3474 +{
3475 + if (dmaman_dev) {
3476 + struct vc_dmaman *dmaman = dev_get_drvdata(dmaman_dev);
3477 + int rc;
3478 +
3479 + device_lock(dmaman_dev);
3480 + rc = vc_dmaman_chan_free(dmaman, channel);
3481 + device_unlock(dmaman_dev);
3482 +
3483 + return rc;
3484 + } else
3485 + return -ENODEV;
3486 +}
3487 +EXPORT_SYMBOL_GPL(bcm_dma_chan_free);
3488 +
3489 +static int dev_dmaman_register(const char *dev_name, struct device *dev)
3490 +{
3491 + int rc = dmaman_dev ? -EINVAL : 0;
3492 + dmaman_dev = dev;
3493 + return rc;
3494 +}
3495 +
3496 +static void dev_dmaman_deregister(const char *dev_name, struct device *dev)
3497 +{
3498 + dmaman_dev = NULL;
3499 +}
3500 +
3501 +/*****************************************************************************\
3502 + * *
3503 + * DMA Device *
3504 + * *
3505 +\*****************************************************************************/
3506 +
3507 +static int dmachans = -1; /* module parameter */
3508 +
3509 +static int bcm_dmaman_probe(struct platform_device *pdev)
3510 +{
3511 + int ret = 0;
3512 + struct vc_dmaman *dmaman;
3513 + struct resource *dma_res = NULL;
3514 + void __iomem *dma_base = NULL;
3515 + int have_dma_region = 0;
3516 +
3517 + dmaman = kzalloc(sizeof(*dmaman), GFP_KERNEL);
3518 + if (NULL == dmaman) {
3519 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
3520 + "DMA management memory\n");
3521 + ret = -ENOMEM;
3522 + } else {
3523 +
3524 + dma_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3525 + if (dma_res == NULL) {
3526 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
3527 + "resource\n");
3528 + ret = -ENODEV;
3529 + } else if (!request_mem_region(dma_res->start,
3530 + resource_size(dma_res),
3531 + DRIVER_NAME)) {
3532 + dev_err(&pdev->dev, "cannot obtain DMA region\n");
3533 + ret = -EBUSY;
3534 + } else {
3535 + have_dma_region = 1;
3536 + dma_base = ioremap(dma_res->start,
3537 + resource_size(dma_res));
3538 + if (!dma_base) {
3539 + dev_err(&pdev->dev, "cannot map DMA region\n");
3540 + ret = -ENOMEM;
3541 + } else {
3542 + /* use module parameter if one was provided */
3543 + if (dmachans > 0)
3544 + vc_dmaman_init(dmaman, dma_base,
3545 + dmachans);
3546 + else
3547 + vc_dmaman_init(dmaman, dma_base,
3548 + DEFAULT_DMACHAN_BITMAP);
3549 +
3550 + platform_set_drvdata(pdev, dmaman);
3551 + dev_dmaman_register(DRIVER_NAME, &pdev->dev);
3552 +
3553 + printk(KERN_INFO DRIVER_NAME ": DMA manager "
3554 + "at %p\n", dma_base);
3555 + }
3556 + }
3557 + }
3558 + if (ret != 0) {
3559 + if (dma_base)
3560 + iounmap(dma_base);
3561 + if (dma_res && have_dma_region)
3562 + release_mem_region(dma_res->start,
3563 + resource_size(dma_res));
3564 + if (dmaman)
3565 + kfree(dmaman);
3566 + }
3567 + return ret;
3568 +}
3569 +
3570 +static int bcm_dmaman_remove(struct platform_device *pdev)
3571 +{
3572 + struct vc_dmaman *dmaman = platform_get_drvdata(pdev);
3573 +
3574 + platform_set_drvdata(pdev, NULL);
3575 + dev_dmaman_deregister(DRIVER_NAME, &pdev->dev);
3576 + kfree(dmaman);
3577 +
3578 + return 0;
3579 +}
3580 +
3581 +static struct platform_driver bcm_dmaman_driver = {
3582 + .probe = bcm_dmaman_probe,
3583 + .remove = bcm_dmaman_remove,
3584 +
3585 + .driver = {
3586 + .name = DRIVER_NAME,
3587 + .owner = THIS_MODULE,
3588 + },
3589 +};
3590 +
3591 +/*****************************************************************************\
3592 + * *
3593 + * Driver init/exit *
3594 + * *
3595 +\*****************************************************************************/
3596 +
3597 +static int __init bcm_dmaman_drv_init(void)
3598 +{
3599 + int ret;
3600 +
3601 + ret = platform_driver_register(&bcm_dmaman_driver);
3602 + if (ret != 0) {
3603 + printk(KERN_ERR DRIVER_NAME ": failed to register "
3604 + "on platform\n");
3605 + }
3606 +
3607 + return ret;
3608 +}
3609 +
3610 +static void __exit bcm_dmaman_drv_exit(void)
3611 +{
3612 + platform_driver_unregister(&bcm_dmaman_driver);
3613 +}
3614 +
3615 +module_init(bcm_dmaman_drv_init);
3616 +module_exit(bcm_dmaman_drv_exit);
3617 +
3618 +module_param(dmachans, int, 0644);
3619 +
3620 +MODULE_AUTHOR("Gray Girling <grayg@broadcom.com>");
3621 +MODULE_DESCRIPTION("DMA channel manager driver");
3622 +MODULE_LICENSE("GPL");
3623 +
3624 +MODULE_PARM_DESC(dmachans, "Bitmap of DMA channels available to the ARM");
3625 diff --git a/arch/arm/mach-bcm2708/include/mach/arm_control.h b/arch/arm/mach-bcm2708/include/mach/arm_control.h
3626 new file mode 100644
3627 index 0000000..a82bb92
3628 --- /dev/null
3629 +++ b/arch/arm/mach-bcm2708/include/mach/arm_control.h
3630 @@ -0,0 +1,419 @@
3631 +/*
3632 + * linux/arch/arm/mach-bcm2708/arm_control.h
3633 + *
3634 + * Copyright (C) 2010 Broadcom
3635 + *
3636 + * This program is free software; you can redistribute it and/or modify
3637 + * it under the terms of the GNU General Public License as published by
3638 + * the Free Software Foundation; either version 2 of the License, or
3639 + * (at your option) any later version.
3640 + *
3641 + * This program is distributed in the hope that it will be useful,
3642 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
3643 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
3644 + * GNU General Public License for more details.
3645 + *
3646 + * You should have received a copy of the GNU General Public License
3647 + * along with this program; if not, write to the Free Software
3648 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
3649 + */
3650 +
3651 +#ifndef __BCM2708_ARM_CONTROL_H
3652 +#define __BCM2708_ARM_CONTROL_H
3653 +
3654 +/*
3655 + * Definitions and addresses for the ARM CONTROL logic
3656 + * This file is manually generated.
3657 + */
3658 +
3659 +#define ARM_BASE 0x7E00B000
3660 +
3661 +/* Basic configuration */
3662 +#define ARM_CONTROL0 HW_REGISTER_RW(ARM_BASE+0x000)
3663 +#define ARM_C0_SIZ128M 0x00000000
3664 +#define ARM_C0_SIZ256M 0x00000001
3665 +#define ARM_C0_SIZ512M 0x00000002
3666 +#define ARM_C0_SIZ1G 0x00000003
3667 +#define ARM_C0_BRESP0 0x00000000
3668 +#define ARM_C0_BRESP1 0x00000004
3669 +#define ARM_C0_BRESP2 0x00000008
3670 +#define ARM_C0_BOOTHI 0x00000010
3671 +#define ARM_C0_UNUSED05 0x00000020 /* free */
3672 +#define ARM_C0_FULLPERI 0x00000040
3673 +#define ARM_C0_UNUSED78 0x00000180 /* free */
3674 +#define ARM_C0_JTAGMASK 0x00000E00
3675 +#define ARM_C0_JTAGOFF 0x00000000
3676 +#define ARM_C0_JTAGBASH 0x00000800 /* Debug on GPIO off */
3677 +#define ARM_C0_JTAGGPIO 0x00000C00 /* Debug on GPIO on */
3678 +#define ARM_C0_APROTMSK 0x0000F000
3679 +#define ARM_C0_DBG0SYNC 0x00010000 /* VPU0 halt sync */
3680 +#define ARM_C0_DBG1SYNC 0x00020000 /* VPU1 halt sync */
3681 +#define ARM_C0_SWDBGREQ 0x00040000 /* HW debug request */
3682 +#define ARM_C0_PASSHALT 0x00080000 /* ARM halt passed to debugger */
3683 +#define ARM_C0_PRIO_PER 0x00F00000 /* per priority mask */
3684 +#define ARM_C0_PRIO_L2 0x0F000000
3685 +#define ARM_C0_PRIO_UC 0xF0000000
3686 +
3687 +#define ARM_C0_APROTPASS 0x0000A000 /* Translate 1:1 */
3688 +#define ARM_C0_APROTUSER 0x00000000 /* Only user mode */
3689 +#define ARM_C0_APROTSYST 0x0000F000 /* Only system mode */
3690 +
3691 +
3692 +#define ARM_CONTROL1 HW_REGISTER_RW(ARM_BASE+0x440)
3693 +#define ARM_C1_TIMER 0x00000001 /* re-route timer IRQ to VC */
3694 +#define ARM_C1_MAIL 0x00000002 /* re-route Mail IRQ to VC */
3695 +#define ARM_C1_BELL0 0x00000004 /* re-route Doorbell 0 to VC */
3696 +#define ARM_C1_BELL1 0x00000008 /* re-route Doorbell 1 to VC */
3697 +#define ARM_C1_PERSON 0x00000100 /* peripherals on */
3698 +#define ARM_C1_REQSTOP 0x00000200 /* ASYNC bridge request stop */
3699 +
3700 +#define ARM_STATUS HW_REGISTER_RW(ARM_BASE+0x444)
3701 +#define ARM_S_ACKSTOP 0x80000000 /* Bridge stopped */
3702 +#define ARM_S_READPEND 0x000003FF /* pending reads counter */
3703 +#define ARM_S_WRITPEND 0x000FFC00 /* pending writes counter */
3704 +
3705 +#define ARM_ERRHALT HW_REGISTER_RW(ARM_BASE+0x448)
3706 +#define ARM_EH_PERIBURST 0x00000001 /* Burst write seen on peri bus */
3707 +#define ARM_EH_ILLADDRS1 0x00000002 /* Address bits 25-27 error */
3708 +#define ARM_EH_ILLADDRS2 0x00000004 /* Address bits 31-28 error */
3709 +#define ARM_EH_VPU0HALT 0x00000008 /* VPU0 halted & in debug mode */
3710 +#define ARM_EH_VPU1HALT 0x00000010 /* VPU1 halted & in debug mode */
3711 +#define ARM_EH_ARMHALT 0x00000020 /* ARM in halted debug mode */
3712 +
3713 +#define ARM_ID_SECURE HW_REGISTER_RW(ARM_BASE+0x00C)
3714 +#define ARM_ID HW_REGISTER_RW(ARM_BASE+0x44C)
3715 +#define ARM_IDVAL 0x364D5241
3716 +
3717 +/* Translation memory */
3718 +#define ARM_TRANSLATE HW_REGISTER_RW(ARM_BASE+0x100)
3719 +/* 32 locations: 0x100.. 0x17F */
3720 +/* 32 spare means we CAN go to 64 pages.... */
3721 +
3722 +
3723 +/* Interrupts */
3724 +#define ARM_IRQ_PEND0 HW_REGISTER_RW(ARM_BASE+0x200) /* Top IRQ bits */
3725 +#define ARM_I0_TIMER 0x00000001 /* timer IRQ */
3726 +#define ARM_I0_MAIL 0x00000002 /* Mail IRQ */
3727 +#define ARM_I0_BELL0 0x00000004 /* Doorbell 0 */
3728 +#define ARM_I0_BELL1 0x00000008 /* Doorbell 1 */
3729 +#define ARM_I0_BANK1 0x00000100 /* Bank1 IRQ */
3730 +#define ARM_I0_BANK2 0x00000200 /* Bank2 IRQ */
3731 +
3732 +#define ARM_IRQ_PEND1 HW_REGISTER_RW(ARM_BASE+0x204) /* All bank1 IRQ bits */
3733 +/* todo: all I1_interrupt sources */
3734 +#define ARM_IRQ_PEND2 HW_REGISTER_RW(ARM_BASE+0x208) /* All bank2 IRQ bits */
3735 +/* todo: all I2_interrupt sources */
3736 +
3737 +#define ARM_IRQ_FAST HW_REGISTER_RW(ARM_BASE+0x20C) /* FIQ control */
3738 +#define ARM_IF_INDEX 0x0000007F /* FIQ select */
3739 +#define ARM_IF_ENABLE 0x00000080 /* FIQ enable */
3740 +#define ARM_IF_VCMASK 0x0000003F /* FIQ = (index from VC source) */
3741 +#define ARM_IF_TIMER 0x00000040 /* FIQ = ARM timer */
3742 +#define ARM_IF_MAIL 0x00000041 /* FIQ = ARM Mail */
3743 +#define ARM_IF_BELL0 0x00000042 /* FIQ = ARM Doorbell 0 */
3744 +#define ARM_IF_BELL1 0x00000043 /* FIQ = ARM Doorbell 1 */
3745 +#define ARM_IF_VP0HALT 0x00000044 /* FIQ = VPU0 Halt seen */
3746 +#define ARM_IF_VP1HALT 0x00000045 /* FIQ = VPU1 Halt seen */
3747 +#define ARM_IF_ILLEGAL 0x00000046 /* FIQ = Illegal access seen */
3748 +
3749 +#define ARM_IRQ_ENBL1 HW_REGISTER_RW(ARM_BASE+0x210) /* Bank1 enable bits */
3750 +#define ARM_IRQ_ENBL2 HW_REGISTER_RW(ARM_BASE+0x214) /* Bank2 enable bits */
3751 +#define ARM_IRQ_ENBL3 HW_REGISTER_RW(ARM_BASE+0x218) /* ARM irqs enable bits */
3752 +#define ARM_IRQ_DIBL1 HW_REGISTER_RW(ARM_BASE+0x21C) /* Bank1 disable bits */
3753 +#define ARM_IRQ_DIBL2 HW_REGISTER_RW(ARM_BASE+0x220) /* Bank2 disable bits */
3754 +#define ARM_IRQ_DIBL3 HW_REGISTER_RW(ARM_BASE+0x224) /* ARM irqs disable bits */
3755 +#define ARM_IE_TIMER 0x00000001 /* Timer IRQ */
3756 +#define ARM_IE_MAIL 0x00000002 /* Mail IRQ */
3757 +#define ARM_IE_BELL0 0x00000004 /* Doorbell 0 */
3758 +#define ARM_IE_BELL1 0x00000008 /* Doorbell 1 */
3759 +#define ARM_IE_VP0HALT 0x00000010 /* VPU0 Halt */
3760 +#define ARM_IE_VP1HALT 0x00000020 /* VPU1 Halt */
3761 +#define ARM_IE_ILLEGAL 0x00000040 /* Illegal access seen */
3762 +
3763 +/* Timer */
3764 +/* For reg. fields see sp804 spec. */
3765 +#define ARM_T_LOAD HW_REGISTER_RW(ARM_BASE+0x400)
3766 +#define ARM_T_VALUE HW_REGISTER_RW(ARM_BASE+0x404)
3767 +#define ARM_T_CONTROL HW_REGISTER_RW(ARM_BASE+0x408)
3768 +#define ARM_T_IRQCNTL HW_REGISTER_RW(ARM_BASE+0x40C)
3769 +#define ARM_T_RAWIRQ HW_REGISTER_RW(ARM_BASE+0x410)
3770 +#define ARM_T_MSKIRQ HW_REGISTER_RW(ARM_BASE+0x414)
3771 +#define ARM_T_RELOAD HW_REGISTER_RW(ARM_BASE+0x418)
3772 +#define ARM_T_PREDIV HW_REGISTER_RW(ARM_BASE+0x41c)
3773 +#define ARM_T_FREECNT HW_REGISTER_RW(ARM_BASE+0x420)
3774 +
3775 +#define TIMER_CTRL_ONESHOT (1 << 0)
3776 +#define TIMER_CTRL_32BIT (1 << 1)
3777 +#define TIMER_CTRL_DIV1 (0 << 2)
3778 +#define TIMER_CTRL_DIV16 (1 << 2)
3779 +#define TIMER_CTRL_DIV256 (2 << 2)
3780 +#define TIMER_CTRL_IE (1 << 5)
3781 +#define TIMER_CTRL_PERIODIC (1 << 6)
3782 +#define TIMER_CTRL_ENABLE (1 << 7)
3783 +#define TIMER_CTRL_DBGHALT (1 << 8)
3784 +#define TIMER_CTRL_ENAFREE (1 << 9)
3785 +#define TIMER_CTRL_FREEDIV_SHIFT 16)
3786 +#define TIMER_CTRL_FREEDIV_MASK 0xff
3787 +
3788 +/* Semaphores, Doorbells, Mailboxes */
3789 +#define ARM_SBM_OWN0 (ARM_BASE+0x800)
3790 +#define ARM_SBM_OWN1 (ARM_BASE+0x900)
3791 +#define ARM_SBM_OWN2 (ARM_BASE+0xA00)
3792 +#define ARM_SBM_OWN3 (ARM_BASE+0xB00)
3793 +
3794 +/* MAILBOXES
3795 + * Register flags are common across all
3796 + * owner registers. See end of this section
3797 + *
3798 + * Semaphores, Doorbells, Mailboxes Owner 0
3799 + *
3800 + */
3801 +
3802 +#define ARM_0_SEMS HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3803 +#define ARM_0_SEM0 HW_REGISTER_RW(ARM_SBM_OWN0+0x00)
3804 +#define ARM_0_SEM1 HW_REGISTER_RW(ARM_SBM_OWN0+0x04)
3805 +#define ARM_0_SEM2 HW_REGISTER_RW(ARM_SBM_OWN0+0x08)
3806 +#define ARM_0_SEM3 HW_REGISTER_RW(ARM_SBM_OWN0+0x0C)
3807 +#define ARM_0_SEM4 HW_REGISTER_RW(ARM_SBM_OWN0+0x10)
3808 +#define ARM_0_SEM5 HW_REGISTER_RW(ARM_SBM_OWN0+0x14)
3809 +#define ARM_0_SEM6 HW_REGISTER_RW(ARM_SBM_OWN0+0x18)
3810 +#define ARM_0_SEM7 HW_REGISTER_RW(ARM_SBM_OWN0+0x1C)
3811 +#define ARM_0_BELL0 HW_REGISTER_RW(ARM_SBM_OWN0+0x40)
3812 +#define ARM_0_BELL1 HW_REGISTER_RW(ARM_SBM_OWN0+0x44)
3813 +#define ARM_0_BELL2 HW_REGISTER_RW(ARM_SBM_OWN0+0x48)
3814 +#define ARM_0_BELL3 HW_REGISTER_RW(ARM_SBM_OWN0+0x4C)
3815 +/* MAILBOX 0 access in Owner 0 area */
3816 +/* Some addresses should ONLY be used by owner 0 */
3817 +#define ARM_0_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) */
3818 +#define ARM_0_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN0+0x80) /* .. 0x8C (4 locations) Normal read */
3819 +#define ARM_0_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN0+0x90) /* none-pop read */
3820 +#define ARM_0_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN0+0x94) /* Sender read (only LS 2 bits) */
3821 +#define ARM_0_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN0+0x98) /* Status read */
3822 +#define ARM_0_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0x9C) /* Config read/write */
3823 +/* MAILBOX 1 access in Owner 0 area */
3824 +/* Owner 0 should only WRITE to this mailbox */
3825 +#define ARM_0_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) /* .. 0xAC (4 locations) */
3826 +/*#define ARM_0_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN0+0xA0) */ /* DO NOT USE THIS !!!!! */
3827 +/*#define ARM_0_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN0+0xB0) */ /* DO NOT USE THIS !!!!! */
3828 +/*#define ARM_0_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN0+0xB4) */ /* DO NOT USE THIS !!!!! */
3829 +#define ARM_0_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN0+0xB8) /* Status read */
3830 +/*#define ARM_0_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN0+0xBC) */ /* DO NOT USE THIS !!!!! */
3831 +/* General SEM, BELL, MAIL config/status */
3832 +#define ARM_0_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE0) /* semaphore clear/debug register */
3833 +#define ARM_0_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN0+0xE4) /* Doorbells clear/debug register */
3834 +#define ARM_0_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xF8) /* ALL interrupts */
3835 +#define ARM_0_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN0+0xFC) /* IRQS pending for owner 0 */
3836 +
3837 +/* Semaphores, Doorbells, Mailboxes Owner 1 */
3838 +#define ARM_1_SEMS HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3839 +#define ARM_1_SEM0 HW_REGISTER_RW(ARM_SBM_OWN1+0x00)
3840 +#define ARM_1_SEM1 HW_REGISTER_RW(ARM_SBM_OWN1+0x04)
3841 +#define ARM_1_SEM2 HW_REGISTER_RW(ARM_SBM_OWN1+0x08)
3842 +#define ARM_1_SEM3 HW_REGISTER_RW(ARM_SBM_OWN1+0x0C)
3843 +#define ARM_1_SEM4 HW_REGISTER_RW(ARM_SBM_OWN1+0x10)
3844 +#define ARM_1_SEM5 HW_REGISTER_RW(ARM_SBM_OWN1+0x14)
3845 +#define ARM_1_SEM6 HW_REGISTER_RW(ARM_SBM_OWN1+0x18)
3846 +#define ARM_1_SEM7 HW_REGISTER_RW(ARM_SBM_OWN1+0x1C)
3847 +#define ARM_1_BELL0 HW_REGISTER_RW(ARM_SBM_OWN1+0x40)
3848 +#define ARM_1_BELL1 HW_REGISTER_RW(ARM_SBM_OWN1+0x44)
3849 +#define ARM_1_BELL2 HW_REGISTER_RW(ARM_SBM_OWN1+0x48)
3850 +#define ARM_1_BELL3 HW_REGISTER_RW(ARM_SBM_OWN1+0x4C)
3851 +/* MAILBOX 0 access in Owner 0 area */
3852 +/* Owner 1 should only WRITE to this mailbox */
3853 +#define ARM_1_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0x80) /* .. 0x8C (4 locations) */
3854 +/*#define ARM_1_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN1+0x80) */ /* DO NOT USE THIS !!!!! */
3855 +/*#define ARM_1_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN1+0x90) */ /* DO NOT USE THIS !!!!! */
3856 +/*#define ARM_1_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN1+0x94) */ /* DO NOT USE THIS !!!!! */
3857 +#define ARM_1_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN1+0x98) /* Status read */
3858 +/*#define ARM_1_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0x9C) */ /* DO NOT USE THIS !!!!! */
3859 +/* MAILBOX 1 access in Owner 0 area */
3860 +#define ARM_1_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) */
3861 +#define ARM_1_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN1+0xA0) /* .. 0xAC (4 locations) Normal read */
3862 +#define ARM_1_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN1+0xB0) /* none-pop read */
3863 +#define ARM_1_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN1+0xB4) /* Sender read (only LS 2 bits) */
3864 +#define ARM_1_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN1+0xB8) /* Status read */
3865 +#define ARM_1_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN1+0xBC)
3866 +/* General SEM, BELL, MAIL config/status */
3867 +#define ARM_1_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE0) /* semaphore clear/debug register */
3868 +#define ARM_1_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN1+0xE4) /* Doorbells clear/debug register */
3869 +#define ARM_1_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xFC) /* IRQS pending for owner 1 */
3870 +#define ARM_1_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN1+0xF8) /* ALL interrupts */
3871 +
3872 +/* Semaphores, Doorbells, Mailboxes Owner 2 */
3873 +#define ARM_2_SEMS HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3874 +#define ARM_2_SEM0 HW_REGISTER_RW(ARM_SBM_OWN2+0x00)
3875 +#define ARM_2_SEM1 HW_REGISTER_RW(ARM_SBM_OWN2+0x04)
3876 +#define ARM_2_SEM2 HW_REGISTER_RW(ARM_SBM_OWN2+0x08)
3877 +#define ARM_2_SEM3 HW_REGISTER_RW(ARM_SBM_OWN2+0x0C)
3878 +#define ARM_2_SEM4 HW_REGISTER_RW(ARM_SBM_OWN2+0x10)
3879 +#define ARM_2_SEM5 HW_REGISTER_RW(ARM_SBM_OWN2+0x14)
3880 +#define ARM_2_SEM6 HW_REGISTER_RW(ARM_SBM_OWN2+0x18)
3881 +#define ARM_2_SEM7 HW_REGISTER_RW(ARM_SBM_OWN2+0x1C)
3882 +#define ARM_2_BELL0 HW_REGISTER_RW(ARM_SBM_OWN2+0x40)
3883 +#define ARM_2_BELL1 HW_REGISTER_RW(ARM_SBM_OWN2+0x44)
3884 +#define ARM_2_BELL2 HW_REGISTER_RW(ARM_SBM_OWN2+0x48)
3885 +#define ARM_2_BELL3 HW_REGISTER_RW(ARM_SBM_OWN2+0x4C)
3886 +/* MAILBOX 0 access in Owner 2 area */
3887 +/* Owner 2 should only WRITE to this mailbox */
3888 +#define ARM_2_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0x80) /* .. 0x8C (4 locations) */
3889 +/*#define ARM_2_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN2+0x80) */ /* DO NOT USE THIS !!!!! */
3890 +/*#define ARM_2_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN2+0x90) */ /* DO NOT USE THIS !!!!! */
3891 +/*#define ARM_2_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN2+0x94) */ /* DO NOT USE THIS !!!!! */
3892 +#define ARM_2_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN2+0x98) /* Status read */
3893 +/*#define ARM_2_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0x9C) */ /* DO NOT USE THIS !!!!! */
3894 +/* MAILBOX 1 access in Owner 2 area */
3895 +/* Owner 2 should only WRITE to this mailbox */
3896 +#define ARM_2_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) /* .. 0xAC (4 locations) */
3897 +/*#define ARM_2_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN2+0xA0) */ /* DO NOT USE THIS !!!!! */
3898 +/*#define ARM_2_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN2+0xB0) */ /* DO NOT USE THIS !!!!! */
3899 +/*#define ARM_2_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN2+0xB4) */ /* DO NOT USE THIS !!!!! */
3900 +#define ARM_2_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN2+0xB8) /* Status read */
3901 +/*#define ARM_2_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN2+0xBC) */ /* DO NOT USE THIS !!!!! */
3902 +/* General SEM, BELL, MAIL config/status */
3903 +#define ARM_2_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE0) /* semaphore clear/debug register */
3904 +#define ARM_2_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN2+0xE4) /* Doorbells clear/debug register */
3905 +#define ARM_2_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xFC) /* IRQS pending for owner 2 */
3906 +#define ARM_2_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN2+0xF8) /* ALL interrupts */
3907 +
3908 +/* Semaphores, Doorbells, Mailboxes Owner 3 */
3909 +#define ARM_3_SEMS HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3910 +#define ARM_3_SEM0 HW_REGISTER_RW(ARM_SBM_OWN3+0x00)
3911 +#define ARM_3_SEM1 HW_REGISTER_RW(ARM_SBM_OWN3+0x04)
3912 +#define ARM_3_SEM2 HW_REGISTER_RW(ARM_SBM_OWN3+0x08)
3913 +#define ARM_3_SEM3 HW_REGISTER_RW(ARM_SBM_OWN3+0x0C)
3914 +#define ARM_3_SEM4 HW_REGISTER_RW(ARM_SBM_OWN3+0x10)
3915 +#define ARM_3_SEM5 HW_REGISTER_RW(ARM_SBM_OWN3+0x14)
3916 +#define ARM_3_SEM6 HW_REGISTER_RW(ARM_SBM_OWN3+0x18)
3917 +#define ARM_3_SEM7 HW_REGISTER_RW(ARM_SBM_OWN3+0x1C)
3918 +#define ARM_3_BELL0 HW_REGISTER_RW(ARM_SBM_OWN3+0x40)
3919 +#define ARM_3_BELL1 HW_REGISTER_RW(ARM_SBM_OWN3+0x44)
3920 +#define ARM_3_BELL2 HW_REGISTER_RW(ARM_SBM_OWN3+0x48)
3921 +#define ARM_3_BELL3 HW_REGISTER_RW(ARM_SBM_OWN3+0x4C)
3922 +/* MAILBOX 0 access in Owner 3 area */
3923 +/* Owner 3 should only WRITE to this mailbox */
3924 +#define ARM_3_MAIL0_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0x80) /* .. 0x8C (4 locations) */
3925 +/*#define ARM_3_MAIL0_RD HW_REGISTER_RW(ARM_SBM_OWN3+0x80) */ /* DO NOT USE THIS !!!!! */
3926 +/*#define ARM_3_MAIL0_POL HW_REGISTER_RW(ARM_SBM_OWN3+0x90) */ /* DO NOT USE THIS !!!!! */
3927 +/*#define ARM_3_MAIL0_SND HW_REGISTER_RW(ARM_SBM_OWN3+0x94) */ /* DO NOT USE THIS !!!!! */
3928 +#define ARM_3_MAIL0_STA HW_REGISTER_RW(ARM_SBM_OWN3+0x98) /* Status read */
3929 +/*#define ARM_3_MAIL0_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0x9C) */ /* DO NOT USE THIS !!!!! */
3930 +/* MAILBOX 1 access in Owner 3 area */
3931 +/* Owner 3 should only WRITE to this mailbox */
3932 +#define ARM_3_MAIL1_WRT HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) /* .. 0xAC (4 locations) */
3933 +/*#define ARM_3_MAIL1_RD HW_REGISTER_RW(ARM_SBM_OWN3+0xA0) */ /* DO NOT USE THIS !!!!! */
3934 +/*#define ARM_3_MAIL1_POL HW_REGISTER_RW(ARM_SBM_OWN3+0xB0) */ /* DO NOT USE THIS !!!!! */
3935 +/*#define ARM_3_MAIL1_SND HW_REGISTER_RW(ARM_SBM_OWN3+0xB4) */ /* DO NOT USE THIS !!!!! */
3936 +#define ARM_3_MAIL1_STA HW_REGISTER_RW(ARM_SBM_OWN3+0xB8) /* Status read */
3937 +/*#define ARM_3_MAIL1_CNF HW_REGISTER_RW(ARM_SBM_OWN3+0xBC) */ /* DO NOT USE THIS !!!!! */
3938 +/* General SEM, BELL, MAIL config/status */
3939 +#define ARM_3_SEMCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE0) /* semaphore clear/debug register */
3940 +#define ARM_3_BELLCLRDBG HW_REGISTER_RW(ARM_SBM_OWN3+0xE4) /* Doorbells clear/debug register */
3941 +#define ARM_3_MY_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xFC) /* IRQS pending for owner 3 */
3942 +#define ARM_3_ALL_IRQS HW_REGISTER_RW(ARM_SBM_OWN3+0xF8) /* ALL interrupts */
3943 +
3944 +
3945 +
3946 +/* Mailbox flags. Valid for all owners */
3947 +
3948 +/* Mailbox status register (...0x98) */
3949 +#define ARM_MS_FULL 0x80000000
3950 +#define ARM_MS_EMPTY 0x40000000
3951 +#define ARM_MS_LEVEL 0x400000FF /* Max. value depdnds on mailbox depth parameter */
3952 +
3953 +/* MAILBOX config/status register (...0x9C) */
3954 +/* ANY write to this register clears the error bits! */
3955 +#define ARM_MC_IHAVEDATAIRQEN 0x00000001 /* mailbox irq enable: has data */
3956 +#define ARM_MC_IHAVESPACEIRQEN 0x00000002 /* mailbox irq enable: has space */
3957 +#define ARM_MC_OPPISEMPTYIRQEN 0x00000004 /* mailbox irq enable: Opp. is empty */
3958 +#define ARM_MC_MAIL_CLEAR 0x00000008 /* mailbox clear write 1, then 0 */
3959 +#define ARM_MC_IHAVEDATAIRQPEND 0x00000010 /* mailbox irq pending: has space */
3960 +#define ARM_MC_IHAVESPACEIRQPEND 0x00000020 /* mailbox irq pending: Opp. is empty */
3961 +#define ARM_MC_OPPISEMPTYIRQPEND 0x00000040 /* mailbox irq pending */
3962 +/* Bit 7 is unused */
3963 +#define ARM_MC_ERRNOOWN 0x00000100 /* error : none owner read from mailbox */
3964 +#define ARM_MC_ERROVERFLW 0x00000200 /* error : write to fill mailbox */
3965 +#define ARM_MC_ERRUNDRFLW 0x00000400 /* error : read from empty mailbox */
3966 +
3967 +/* Semaphore clear/debug register (...0xE0) */
3968 +#define ARM_SD_OWN0 0x00000003 /* Owner of sem 0 */
3969 +#define ARM_SD_OWN1 0x0000000C /* Owner of sem 1 */
3970 +#define ARM_SD_OWN2 0x00000030 /* Owner of sem 2 */
3971 +#define ARM_SD_OWN3 0x000000C0 /* Owner of sem 3 */
3972 +#define ARM_SD_OWN4 0x00000300 /* Owner of sem 4 */
3973 +#define ARM_SD_OWN5 0x00000C00 /* Owner of sem 5 */
3974 +#define ARM_SD_OWN6 0x00003000 /* Owner of sem 6 */
3975 +#define ARM_SD_OWN7 0x0000C000 /* Owner of sem 7 */
3976 +#define ARM_SD_SEM0 0x00010000 /* Status of sem 0 */
3977 +#define ARM_SD_SEM1 0x00020000 /* Status of sem 1 */
3978 +#define ARM_SD_SEM2 0x00040000 /* Status of sem 2 */
3979 +#define ARM_SD_SEM3 0x00080000 /* Status of sem 3 */
3980 +#define ARM_SD_SEM4 0x00100000 /* Status of sem 4 */
3981 +#define ARM_SD_SEM5 0x00200000 /* Status of sem 5 */
3982 +#define ARM_SD_SEM6 0x00400000 /* Status of sem 6 */
3983 +#define ARM_SD_SEM7 0x00800000 /* Status of sem 7 */
3984 +
3985 +/* Doorbells clear/debug register (...0xE4) */
3986 +#define ARM_BD_OWN0 0x00000003 /* Owner of doorbell 0 */
3987 +#define ARM_BD_OWN1 0x0000000C /* Owner of doorbell 1 */
3988 +#define ARM_BD_OWN2 0x00000030 /* Owner of doorbell 2 */
3989 +#define ARM_BD_OWN3 0x000000C0 /* Owner of doorbell 3 */
3990 +#define ARM_BD_BELL0 0x00000100 /* Status of doorbell 0 */
3991 +#define ARM_BD_BELL1 0x00000200 /* Status of doorbell 1 */
3992 +#define ARM_BD_BELL2 0x00000400 /* Status of doorbell 2 */
3993 +#define ARM_BD_BELL3 0x00000800 /* Status of doorbell 3 */
3994 +
3995 +/* MY IRQS register (...0xF8) */
3996 +#define ARM_MYIRQ_BELL 0x00000001 /* This owner has a doorbell IRQ */
3997 +#define ARM_MYIRQ_MAIL 0x00000002 /* This owner has a mailbox IRQ */
3998 +
3999 +/* ALL IRQS register (...0xF8) */
4000 +#define ARM_AIS_BELL0 0x00000001 /* Doorbell 0 IRQ pending */
4001 +#define ARM_AIS_BELL1 0x00000002 /* Doorbell 1 IRQ pending */
4002 +#define ARM_AIS_BELL2 0x00000004 /* Doorbell 2 IRQ pending */
4003 +#define ARM_AIS_BELL3 0x00000008 /* Doorbell 3 IRQ pending */
4004 +#define ARM_AIS0_HAVEDATA 0x00000010 /* MAIL 0 has data IRQ pending */
4005 +#define ARM_AIS0_HAVESPAC 0x00000020 /* MAIL 0 has space IRQ pending */
4006 +#define ARM_AIS0_OPPEMPTY 0x00000040 /* MAIL 0 opposite is empty IRQ */
4007 +#define ARM_AIS1_HAVEDATA 0x00000080 /* MAIL 1 has data IRQ pending */
4008 +#define ARM_AIS1_HAVESPAC 0x00000100 /* MAIL 1 has space IRQ pending */
4009 +#define ARM_AIS1_OPPEMPTY 0x00000200 /* MAIL 1 opposite is empty IRQ */
4010 +/* Note that bell-0, bell-1 and MAIL0 IRQ go only to the ARM */
4011 +/* Whilst that bell-2, bell-3 and MAIL1 IRQ go only to the VC */
4012 +/* */
4013 +/* ARM JTAG BASH */
4014 +/* */
4015 +#define AJB_BASE 0x7e2000c0
4016 +
4017 +#define AJBCONF HW_REGISTER_RW(AJB_BASE+0x00)
4018 +#define AJB_BITS0 0x000000
4019 +#define AJB_BITS4 0x000004
4020 +#define AJB_BITS8 0x000008
4021 +#define AJB_BITS12 0x00000C
4022 +#define AJB_BITS16 0x000010
4023 +#define AJB_BITS20 0x000014
4024 +#define AJB_BITS24 0x000018
4025 +#define AJB_BITS28 0x00001C
4026 +#define AJB_BITS32 0x000020
4027 +#define AJB_BITS34 0x000022
4028 +#define AJB_OUT_MS 0x000040
4029 +#define AJB_OUT_LS 0x000000
4030 +#define AJB_INV_CLK 0x000080
4031 +#define AJB_D0_RISE 0x000100
4032 +#define AJB_D0_FALL 0x000000
4033 +#define AJB_D1_RISE 0x000200
4034 +#define AJB_D1_FALL 0x000000
4035 +#define AJB_IN_RISE 0x000400
4036 +#define AJB_IN_FALL 0x000000
4037 +#define AJB_ENABLE 0x000800
4038 +#define AJB_HOLD0 0x000000
4039 +#define AJB_HOLD1 0x001000
4040 +#define AJB_HOLD2 0x002000
4041 +#define AJB_HOLD3 0x003000
4042 +#define AJB_RESETN 0x004000
4043 +#define AJB_CLKSHFT 16
4044 +#define AJB_BUSY 0x80000000
4045 +#define AJBTMS HW_REGISTER_RW(AJB_BASE+0x04)
4046 +#define AJBTDI HW_REGISTER_RW(AJB_BASE+0x08)
4047 +#define AJBTDO HW_REGISTER_RW(AJB_BASE+0x0c)
4048 +
4049 +#endif
4050 diff --git a/arch/arm/mach-bcm2708/include/mach/arm_power.h b/arch/arm/mach-bcm2708/include/mach/arm_power.h
4051 new file mode 100644
4052 index 0000000..aae9136
4053 --- /dev/null
4054 +++ b/arch/arm/mach-bcm2708/include/mach/arm_power.h
4055 @@ -0,0 +1,60 @@
4056 +/*
4057 + * linux/arch/arm/mach-bcm2708/include/mach/arm_power.h
4058 + *
4059 + * Copyright (C) 2010 Broadcom
4060 + *
4061 + * This program is free software; you can redistribute it and/or modify
4062 + * it under the terms of the GNU General Public License as published by
4063 + * the Free Software Foundation; either version 2 of the License, or
4064 + * (at your option) any later version.
4065 + *
4066 + * This program is distributed in the hope that it will be useful,
4067 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4068 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4069 + * GNU General Public License for more details.
4070 + *
4071 + * You should have received a copy of the GNU General Public License
4072 + * along with this program; if not, write to the Free Software
4073 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4074 + */
4075 +
4076 +#ifndef _ARM_POWER_H
4077 +#define _ARM_POWER_H
4078 +
4079 +/* Use meaningful names on each side */
4080 +#ifdef __VIDEOCORE__
4081 +#define PREFIX(x) ARM_##x
4082 +#else
4083 +#define PREFIX(x) BCM_##x
4084 +#endif
4085 +
4086 +enum {
4087 + PREFIX(POWER_SDCARD_BIT),
4088 + PREFIX(POWER_UART_BIT),
4089 + PREFIX(POWER_MINIUART_BIT),
4090 + PREFIX(POWER_USB_BIT),
4091 + PREFIX(POWER_I2C0_BIT),
4092 + PREFIX(POWER_I2C1_BIT),
4093 + PREFIX(POWER_I2C2_BIT),
4094 + PREFIX(POWER_SPI_BIT),
4095 + PREFIX(POWER_CCP2TX_BIT),
4096 +
4097 + PREFIX(POWER_MAX)
4098 +};
4099 +
4100 +enum {
4101 + PREFIX(POWER_SDCARD) = (1 << PREFIX(POWER_SDCARD_BIT)),
4102 + PREFIX(POWER_UART) = (1 << PREFIX(POWER_UART_BIT)),
4103 + PREFIX(POWER_MINIUART) = (1 << PREFIX(POWER_MINIUART_BIT)),
4104 + PREFIX(POWER_USB) = (1 << PREFIX(POWER_USB_BIT)),
4105 + PREFIX(POWER_I2C0) = (1 << PREFIX(POWER_I2C0_BIT)),
4106 + PREFIX(POWER_I2C1_MASK) = (1 << PREFIX(POWER_I2C1_BIT)),
4107 + PREFIX(POWER_I2C2_MASK) = (1 << PREFIX(POWER_I2C2_BIT)),
4108 + PREFIX(POWER_SPI_MASK) = (1 << PREFIX(POWER_SPI_BIT)),
4109 + PREFIX(POWER_CCP2TX_MASK) = (1 << PREFIX(POWER_CCP2TX_BIT)),
4110 +
4111 + PREFIX(POWER_MASK) = (1 << PREFIX(POWER_MAX)) - 1,
4112 + PREFIX(POWER_NONE) = 0
4113 +};
4114 +
4115 +#endif
4116 diff --git a/arch/arm/mach-bcm2708/include/mach/clkdev.h b/arch/arm/mach-bcm2708/include/mach/clkdev.h
4117 new file mode 100644
4118 index 0000000..04b37a8
4119 --- /dev/null
4120 +++ b/arch/arm/mach-bcm2708/include/mach/clkdev.h
4121 @@ -0,0 +1,7 @@
4122 +#ifndef __ASM_MACH_CLKDEV_H
4123 +#define __ASM_MACH_CLKDEV_H
4124 +
4125 +#define __clk_get(clk) ({ 1; })
4126 +#define __clk_put(clk) do { } while (0)
4127 +
4128 +#endif
4129 diff --git a/arch/arm/mach-bcm2708/include/mach/debug-macro.S b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
4130 new file mode 100644
4131 index 0000000..2d0dc1c
4132 --- /dev/null
4133 +++ b/arch/arm/mach-bcm2708/include/mach/debug-macro.S
4134 @@ -0,0 +1,22 @@
4135 +/* arch/arm/mach-bcm2708/include/mach/debug-macro.S
4136 + *
4137 + * Debugging macro include header
4138 + *
4139 + * Copyright (C) 2010 Broadcom
4140 + * Copyright (C) 1994-1999 Russell King
4141 + * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
4142 + *
4143 + * This program is free software; you can redistribute it and/or modify
4144 + * it under the terms of the GNU General Public License version 2 as
4145 + * published by the Free Software Foundation.
4146 + *
4147 +*/
4148 +
4149 +#include <mach/platform.h>
4150 +
4151 + .macro addruart, rp, rv, tmp
4152 + ldr \rp, =UART0_BASE
4153 + ldr \rv, =IO_ADDRESS(UART0_BASE)
4154 + .endm
4155 +
4156 +#include <asm/hardware/debug-pl01x.S>
4157 diff --git a/arch/arm/mach-bcm2708/include/mach/dma.h b/arch/arm/mach-bcm2708/include/mach/dma.h
4158 new file mode 100644
4159 index 0000000..ac7a4a0
4160 --- /dev/null
4161 +++ b/arch/arm/mach-bcm2708/include/mach/dma.h
4162 @@ -0,0 +1,86 @@
4163 +/*
4164 + * linux/arch/arm/mach-bcm2708/include/mach/dma.h
4165 + *
4166 + * Copyright (C) 2010 Broadcom
4167 + *
4168 + * This program is free software; you can redistribute it and/or modify
4169 + * it under the terms of the GNU General Public License version 2 as
4170 + * published by the Free Software Foundation.
4171 + */
4172 +
4173 +
4174 +#ifndef _MACH_BCM2708_DMA_H
4175 +#define _MACH_BCM2708_DMA_H
4176 +
4177 +#define BCM_DMAMAN_DRIVER_NAME "bcm2708_dma"
4178 +
4179 +/* DMA CS Control and Status bits */
4180 +#define BCM2708_DMA_ACTIVE (1 << 0)
4181 +#define BCM2708_DMA_INT (1 << 2)
4182 +#define BCM2708_DMA_ISPAUSED (1 << 4) /* Pause requested or not active */
4183 +#define BCM2708_DMA_ISHELD (1 << 5) /* Is held by DREQ flow control */
4184 +#define BCM2708_DMA_ERR (1 << 8)
4185 +#define BCM2708_DMA_ABORT (1 << 30) /* stop current CB, go to next, WO */
4186 +#define BCM2708_DMA_RESET (1 << 31) /* WO, self clearing */
4187 +
4188 +/* DMA control block "info" field bits */
4189 +#define BCM2708_DMA_INT_EN (1 << 0)
4190 +#define BCM2708_DMA_TDMODE (1 << 1)
4191 +#define BCM2708_DMA_WAIT_RESP (1 << 3)
4192 +#define BCM2708_DMA_D_INC (1 << 4)
4193 +#define BCM2708_DMA_D_WIDTH (1 << 5)
4194 +#define BCM2708_DMA_D_DREQ (1 << 6)
4195 +#define BCM2708_DMA_S_INC (1 << 8)
4196 +#define BCM2708_DMA_S_WIDTH (1 << 9)
4197 +#define BCM2708_DMA_S_DREQ (1 << 10)
4198 +
4199 +#define BCM2708_DMA_BURST(x) (((x)&0xf) << 12)
4200 +#define BCM2708_DMA_PER_MAP(x) ((x) << 16)
4201 +#define BCM2708_DMA_WAITS(x) (((x)&0x1f) << 21)
4202 +
4203 +#define BCM2708_DMA_DREQ_EMMC 11
4204 +#define BCM2708_DMA_DREQ_SDHOST 13
4205 +
4206 +#define BCM2708_DMA_CS 0x00 /* Control and Status */
4207 +#define BCM2708_DMA_ADDR 0x04
4208 +/* the current control block appears in the following registers - read only */
4209 +#define BCM2708_DMA_INFO 0x08
4210 +#define BCM2708_DMA_NEXTCB 0x1C
4211 +#define BCM2708_DMA_DEBUG 0x20
4212 +
4213 +#define BCM2708_DMA4_CS (BCM2708_DMA_CHAN(4)+BCM2708_DMA_CS)
4214 +#define BCM2708_DMA4_ADDR (BCM2708_DMA_CHAN(4)+BCM2708_DMA_ADDR)
4215 +
4216 +#define BCM2708_DMA_TDMODE_LEN(w, h) ((h) << 16 | (w))
4217 +
4218 +struct bcm2708_dma_cb {
4219 + unsigned long info;
4220 + unsigned long src;
4221 + unsigned long dst;
4222 + unsigned long length;
4223 + unsigned long stride;
4224 + unsigned long next;
4225 + unsigned long pad[2];
4226 +};
4227 +
4228 +extern int bcm_sg_suitable_for_dma(struct scatterlist *sg_ptr, int sg_len);
4229 +extern void bcm_dma_start(void __iomem *dma_chan_base,
4230 + dma_addr_t control_block);
4231 +extern void bcm_dma_wait_idle(void __iomem *dma_chan_base);
4232 +extern int /*rc*/ bcm_dma_abort(void __iomem *dma_chan_base);
4233 +
4234 +/* When listing features we can ask for when allocating DMA channels give
4235 + those with higher priority smaller ordinal numbers */
4236 +#define BCM_DMA_FEATURE_FAST_ORD 0
4237 +#define BCM_DMA_FEATURE_BULK_ORD 1
4238 +#define BCM_DMA_FEATURE_FAST (1<<BCM_DMA_FEATURE_FAST_ORD)
4239 +#define BCM_DMA_FEATURE_BULK (1<<BCM_DMA_FEATURE_BULK_ORD)
4240 +#define BCM_DMA_FEATURE_COUNT 2
4241 +
4242 +/* return channel no or -ve error */
4243 +extern int bcm_dma_chan_alloc(unsigned preferred_feature_set,
4244 + void __iomem **out_dma_base, int *out_dma_irq);
4245 +extern int bcm_dma_chan_free(int channel);
4246 +
4247 +
4248 +#endif /* _MACH_BCM2708_DMA_H */
4249 diff --git a/arch/arm/mach-bcm2708/include/mach/entry-macro.S b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
4250 new file mode 100644
4251 index 0000000..79b62d9
4252 --- /dev/null
4253 +++ b/arch/arm/mach-bcm2708/include/mach/entry-macro.S
4254 @@ -0,0 +1,69 @@
4255 +/*
4256 + * arch/arm/mach-bcm2708/include/mach/entry-macro.S
4257 + *
4258 + * Low-level IRQ helper macros for BCM2708 platforms
4259 + *
4260 + * Copyright (C) 2010 Broadcom
4261 + *
4262 + * This program is free software; you can redistribute it and/or modify
4263 + * it under the terms of the GNU General Public License as published by
4264 + * the Free Software Foundation; either version 2 of the License, or
4265 + * (at your option) any later version.
4266 + *
4267 + * This program is distributed in the hope that it will be useful,
4268 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4269 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4270 + * GNU General Public License for more details.
4271 + *
4272 + * You should have received a copy of the GNU General Public License
4273 + * along with this program; if not, write to the Free Software
4274 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4275 + */
4276 +#include <mach/hardware.h>
4277 +
4278 + .macro disable_fiq
4279 + .endm
4280 +
4281 + .macro get_irqnr_preamble, base, tmp
4282 + ldr \base, =IO_ADDRESS(ARMCTRL_IC_BASE)
4283 + .endm
4284 +
4285 + .macro arch_ret_to_user, tmp1, tmp2
4286 + .endm
4287 +
4288 + .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
4289 + /* get masked status */
4290 + ldr \irqstat, [\base, #(ARM_IRQ_PEND0 - ARMCTRL_IC_BASE)]
4291 + mov \irqnr, #(ARM_IRQ0_BASE + 31)
4292 + and \tmp, \irqstat, #0x300 @ save bits 8 and 9
4293 + /* clear bits 8 and 9, and test */
4294 + bics \irqstat, \irqstat, #0x300
4295 + bne 1010f
4296 +
4297 + tst \tmp, #0x100
4298 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND1 - ARMCTRL_IC_BASE)]
4299 + movne \irqnr, #(ARM_IRQ1_BASE + 31)
4300 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4301 + bicne \irqstat, #((1<<7) | (1<<9) | (1<<10))
4302 + bicne \irqstat, #((1<<18) | (1<<19))
4303 + bne 1010f
4304 +
4305 + tst \tmp, #0x200
4306 + ldrne \irqstat, [\base, #(ARM_IRQ_PEND2 - ARMCTRL_IC_BASE)]
4307 + movne \irqnr, #(ARM_IRQ2_BASE + 31)
4308 + @ Mask out the interrupts also present in PEND0 - see SW-5809
4309 + bicne \irqstat, #((1<<21) | (1<<22) | (1<<23) | (1<<24) | (1<<25))
4310 + bicne \irqstat, #((1<<30))
4311 + beq 1020f
4312 +
4313 +1010:
4314 + @ For non-zero x, LSB(x) = 31 - CLZ(x^(x-1))
4315 + @ N.B. CLZ is an ARM5 instruction.
4316 + sub \tmp, \irqstat, #1
4317 + eor \irqstat, \irqstat, \tmp
4318 + clz \tmp, \irqstat
4319 + sub \irqnr, \tmp
4320 +
4321 +1020: @ EQ will be set if no irqs pending
4322 +
4323 + .endm
4324 diff --git a/arch/arm/mach-bcm2708/include/mach/frc.h b/arch/arm/mach-bcm2708/include/mach/frc.h
4325 new file mode 100644
4326 index 0000000..dd51e07
4327 --- /dev/null
4328 +++ b/arch/arm/mach-bcm2708/include/mach/frc.h
4329 @@ -0,0 +1,38 @@
4330 +/*
4331 + * arch/arm/mach-bcm2708/include/mach/timex.h
4332 + *
4333 + * BCM2708 free running counter (timer)
4334 + *
4335 + * Copyright (C) 2010 Broadcom
4336 + *
4337 + * This program is free software; you can redistribute it and/or modify
4338 + * it under the terms of the GNU General Public License as published by
4339 + * the Free Software Foundation; either version 2 of the License, or
4340 + * (at your option) any later version.
4341 + *
4342 + * This program is distributed in the hope that it will be useful,
4343 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4344 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4345 + * GNU General Public License for more details.
4346 + *
4347 + * You should have received a copy of the GNU General Public License
4348 + * along with this program; if not, write to the Free Software
4349 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4350 + */
4351 +
4352 +#ifndef _MACH_FRC_H
4353 +#define _MACH_FRC_H
4354 +
4355 +#define FRC_TICK_RATE (1000000)
4356 +
4357 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4358 + (slightly faster than frc_clock_ticks63()
4359 + */
4360 +extern unsigned long frc_clock_ticks32(void);
4361 +
4362 +/*! Free running counter incrementing at the CLOCK_TICK_RATE
4363 + * Note - top bit should be ignored (see cnt32_to_63)
4364 + */
4365 +extern unsigned long long frc_clock_ticks63(void);
4366 +
4367 +#endif
4368 diff --git a/arch/arm/mach-bcm2708/include/mach/gpio.h b/arch/arm/mach-bcm2708/include/mach/gpio.h
4369 new file mode 100644
4370 index 0000000..f600bc7
4371 --- /dev/null
4372 +++ b/arch/arm/mach-bcm2708/include/mach/gpio.h
4373 @@ -0,0 +1,18 @@
4374 +/*
4375 + * arch/arm/mach-bcm2708/include/mach/gpio.h
4376 + *
4377 + * This file is licensed under the terms of the GNU General Public
4378 + * License version 2. This program is licensed "as is" without any
4379 + * warranty of any kind, whether express or implied.
4380 + */
4381 +
4382 +#ifndef __ASM_ARCH_GPIO_H
4383 +#define __ASM_ARCH_GPIO_H
4384 +
4385 +#define ARCH_NR_GPIOS 54 // number of gpio lines
4386 +
4387 +#define gpio_to_irq(x) ((x) + GPIO_IRQ_START)
4388 +#define irq_to_gpio(x) ((x) - GPIO_IRQ_START)
4389 +
4390 +#endif
4391 +
4392 diff --git a/arch/arm/mach-bcm2708/include/mach/hardware.h b/arch/arm/mach-bcm2708/include/mach/hardware.h
4393 new file mode 100644
4394 index 0000000..c2954e8
4395 --- /dev/null
4396 +++ b/arch/arm/mach-bcm2708/include/mach/hardware.h
4397 @@ -0,0 +1,28 @@
4398 +/*
4399 + * arch/arm/mach-bcm2708/include/mach/hardware.h
4400 + *
4401 + * This file contains the hardware definitions of the BCM2708 devices.
4402 + *
4403 + * Copyright (C) 2010 Broadcom
4404 + *
4405 + * This program is free software; you can redistribute it and/or modify
4406 + * it under the terms of the GNU General Public License as published by
4407 + * the Free Software Foundation; either version 2 of the License, or
4408 + * (at your option) any later version.
4409 + *
4410 + * This program is distributed in the hope that it will be useful,
4411 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4412 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4413 + * GNU General Public License for more details.
4414 + *
4415 + * You should have received a copy of the GNU General Public License
4416 + * along with this program; if not, write to the Free Software
4417 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4418 + */
4419 +#ifndef __ASM_ARCH_HARDWARE_H
4420 +#define __ASM_ARCH_HARDWARE_H
4421 +
4422 +#include <asm/sizes.h>
4423 +#include <mach/platform.h>
4424 +
4425 +#endif
4426 diff --git a/arch/arm/mach-bcm2708/include/mach/io.h b/arch/arm/mach-bcm2708/include/mach/io.h
4427 new file mode 100644
4428 index 0000000..e6eb84d
4429 --- /dev/null
4430 +++ b/arch/arm/mach-bcm2708/include/mach/io.h
4431 @@ -0,0 +1,27 @@
4432 +/*
4433 + * arch/arm/mach-bcm2708/include/mach/io.h
4434 + *
4435 + * Copyright (C) 2003 ARM Limited
4436 + *
4437 + * This program is free software; you can redistribute it and/or modify
4438 + * it under the terms of the GNU General Public License as published by
4439 + * the Free Software Foundation; either version 2 of the License, or
4440 + * (at your option) any later version.
4441 + *
4442 + * This program is distributed in the hope that it will be useful,
4443 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4444 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4445 + * GNU General Public License for more details.
4446 + *
4447 + * You should have received a copy of the GNU General Public License
4448 + * along with this program; if not, write to the Free Software
4449 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4450 + */
4451 +#ifndef __ASM_ARM_ARCH_IO_H
4452 +#define __ASM_ARM_ARCH_IO_H
4453 +
4454 +#define IO_SPACE_LIMIT 0xffffffff
4455 +
4456 +#define __io(a) __typesafe_io(a)
4457 +
4458 +#endif
4459 diff --git a/arch/arm/mach-bcm2708/include/mach/irqs.h b/arch/arm/mach-bcm2708/include/mach/irqs.h
4460 new file mode 100644
4461 index 0000000..e8bb068
4462 --- /dev/null
4463 +++ b/arch/arm/mach-bcm2708/include/mach/irqs.h
4464 @@ -0,0 +1,196 @@
4465 +/*
4466 + * arch/arm/mach-bcm2708/include/mach/irqs.h
4467 + *
4468 + * Copyright (C) 2010 Broadcom
4469 + * Copyright (C) 2003 ARM Limited
4470 + * Copyright (C) 2000 Deep Blue Solutions Ltd.
4471 + *
4472 + * This program is free software; you can redistribute it and/or modify
4473 + * it under the terms of the GNU General Public License as published by
4474 + * the Free Software Foundation; either version 2 of the License, or
4475 + * (at your option) any later version.
4476 + *
4477 + * This program is distributed in the hope that it will be useful,
4478 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4479 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4480 + * GNU General Public License for more details.
4481 + *
4482 + * You should have received a copy of the GNU General Public License
4483 + * along with this program; if not, write to the Free Software
4484 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4485 + */
4486 +
4487 +#ifndef _BCM2708_IRQS_H_
4488 +#define _BCM2708_IRQS_H_
4489 +
4490 +#include <mach/platform.h>
4491 +
4492 +/*
4493 + * IRQ interrupts definitions are the same as the INT definitions
4494 + * held within platform.h
4495 + */
4496 +#define IRQ_ARMCTRL_START 0
4497 +#define IRQ_TIMER0 (IRQ_ARMCTRL_START + INTERRUPT_TIMER0)
4498 +#define IRQ_TIMER1 (IRQ_ARMCTRL_START + INTERRUPT_TIMER1)
4499 +#define IRQ_TIMER2 (IRQ_ARMCTRL_START + INTERRUPT_TIMER2)
4500 +#define IRQ_TIMER3 (IRQ_ARMCTRL_START + INTERRUPT_TIMER3)
4501 +#define IRQ_CODEC0 (IRQ_ARMCTRL_START + INTERRUPT_CODEC0)
4502 +#define IRQ_CODEC1 (IRQ_ARMCTRL_START + INTERRUPT_CODEC1)
4503 +#define IRQ_CODEC2 (IRQ_ARMCTRL_START + INTERRUPT_CODEC2)
4504 +#define IRQ_JPEG (IRQ_ARMCTRL_START + INTERRUPT_JPEG)
4505 +#define IRQ_ISP (IRQ_ARMCTRL_START + INTERRUPT_ISP)
4506 +#define IRQ_USB (IRQ_ARMCTRL_START + INTERRUPT_USB)
4507 +#define IRQ_3D (IRQ_ARMCTRL_START + INTERRUPT_3D)
4508 +#define IRQ_TRANSPOSER (IRQ_ARMCTRL_START + INTERRUPT_TRANSPOSER)
4509 +#define IRQ_MULTICORESYNC0 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC0)
4510 +#define IRQ_MULTICORESYNC1 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC1)
4511 +#define IRQ_MULTICORESYNC2 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC2)
4512 +#define IRQ_MULTICORESYNC3 (IRQ_ARMCTRL_START + INTERRUPT_MULTICORESYNC3)
4513 +#define IRQ_DMA0 (IRQ_ARMCTRL_START + INTERRUPT_DMA0)
4514 +#define IRQ_DMA1 (IRQ_ARMCTRL_START + INTERRUPT_DMA1)
4515 +#define IRQ_DMA2 (IRQ_ARMCTRL_START + INTERRUPT_DMA2)
4516 +#define IRQ_DMA3 (IRQ_ARMCTRL_START + INTERRUPT_DMA3)
4517 +#define IRQ_DMA4 (IRQ_ARMCTRL_START + INTERRUPT_DMA4)
4518 +#define IRQ_DMA5 (IRQ_ARMCTRL_START + INTERRUPT_DMA5)
4519 +#define IRQ_DMA6 (IRQ_ARMCTRL_START + INTERRUPT_DMA6)
4520 +#define IRQ_DMA7 (IRQ_ARMCTRL_START + INTERRUPT_DMA7)
4521 +#define IRQ_DMA8 (IRQ_ARMCTRL_START + INTERRUPT_DMA8)
4522 +#define IRQ_DMA9 (IRQ_ARMCTRL_START + INTERRUPT_DMA9)
4523 +#define IRQ_DMA10 (IRQ_ARMCTRL_START + INTERRUPT_DMA10)
4524 +#define IRQ_DMA11 (IRQ_ARMCTRL_START + INTERRUPT_DMA11)
4525 +#define IRQ_DMA12 (IRQ_ARMCTRL_START + INTERRUPT_DMA12)
4526 +#define IRQ_AUX (IRQ_ARMCTRL_START + INTERRUPT_AUX)
4527 +#define IRQ_ARM (IRQ_ARMCTRL_START + INTERRUPT_ARM)
4528 +#define IRQ_VPUDMA (IRQ_ARMCTRL_START + INTERRUPT_VPUDMA)
4529 +#define IRQ_HOSTPORT (IRQ_ARMCTRL_START + INTERRUPT_HOSTPORT)
4530 +#define IRQ_VIDEOSCALER (IRQ_ARMCTRL_START + INTERRUPT_VIDEOSCALER)
4531 +#define IRQ_CCP2TX (IRQ_ARMCTRL_START + INTERRUPT_CCP2TX)
4532 +#define IRQ_SDC (IRQ_ARMCTRL_START + INTERRUPT_SDC)
4533 +#define IRQ_DSI0 (IRQ_ARMCTRL_START + INTERRUPT_DSI0)
4534 +#define IRQ_AVE (IRQ_ARMCTRL_START + INTERRUPT_AVE)
4535 +#define IRQ_CAM0 (IRQ_ARMCTRL_START + INTERRUPT_CAM0)
4536 +#define IRQ_CAM1 (IRQ_ARMCTRL_START + INTERRUPT_CAM1)
4537 +#define IRQ_HDMI0 (IRQ_ARMCTRL_START + INTERRUPT_HDMI0)
4538 +#define IRQ_HDMI1 (IRQ_ARMCTRL_START + INTERRUPT_HDMI1)
4539 +#define IRQ_PIXELVALVE1 (IRQ_ARMCTRL_START + INTERRUPT_PIXELVALVE1)
4540 +#define IRQ_I2CSPISLV (IRQ_ARMCTRL_START + INTERRUPT_I2CSPISLV)
4541 +#define IRQ_DSI1 (IRQ_ARMCTRL_START + INTERRUPT_DSI1)
4542 +#define IRQ_PWA0 (IRQ_ARMCTRL_START + INTERRUPT_PWA0)
4543 +#define IRQ_PWA1 (IRQ_ARMCTRL_START + INTERRUPT_PWA1)
4544 +#define IRQ_CPR (IRQ_ARMCTRL_START + INTERRUPT_CPR)
4545 +#define IRQ_SMI (IRQ_ARMCTRL_START + INTERRUPT_SMI)
4546 +#define IRQ_GPIO0 (IRQ_ARMCTRL_START + INTERRUPT_GPIO0)
4547 +#define IRQ_GPIO1 (IRQ_ARMCTRL_START + INTERRUPT_GPIO1)
4548 +#define IRQ_GPIO2 (IRQ_ARMCTRL_START + INTERRUPT_GPIO2)
4549 +#define IRQ_GPIO3 (IRQ_ARMCTRL_START + INTERRUPT_GPIO3)
4550 +#define IRQ_I2C (IRQ_ARMCTRL_START + INTERRUPT_I2C)
4551 +#define IRQ_SPI (IRQ_ARMCTRL_START + INTERRUPT_SPI)
4552 +#define IRQ_I2SPCM (IRQ_ARMCTRL_START + INTERRUPT_I2SPCM)
4553 +#define IRQ_SDIO (IRQ_ARMCTRL_START + INTERRUPT_SDIO)
4554 +#define IRQ_UART (IRQ_ARMCTRL_START + INTERRUPT_UART)
4555 +#define IRQ_SLIMBUS (IRQ_ARMCTRL_START + INTERRUPT_SLIMBUS)
4556 +#define IRQ_VEC (IRQ_ARMCTRL_START + INTERRUPT_VEC)
4557 +#define IRQ_CPG (IRQ_ARMCTRL_START + INTERRUPT_CPG)
4558 +#define IRQ_RNG (IRQ_ARMCTRL_START + INTERRUPT_RNG)
4559 +#define IRQ_ARASANSDIO (IRQ_ARMCTRL_START + INTERRUPT_ARASANSDIO)
4560 +#define IRQ_AVSPMON (IRQ_ARMCTRL_START + INTERRUPT_AVSPMON)
4561 +
4562 +#define IRQ_ARM_TIMER (IRQ_ARMCTRL_START + INTERRUPT_ARM_TIMER)
4563 +#define IRQ_ARM_MAILBOX (IRQ_ARMCTRL_START + INTERRUPT_ARM_MAILBOX)
4564 +#define IRQ_ARM_DOORBELL_0 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_0)
4565 +#define IRQ_ARM_DOORBELL_1 (IRQ_ARMCTRL_START + INTERRUPT_ARM_DOORBELL_1)
4566 +#define IRQ_VPU0_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU0_HALTED)
4567 +#define IRQ_VPU1_HALTED (IRQ_ARMCTRL_START + INTERRUPT_VPU1_HALTED)
4568 +#define IRQ_ILLEGAL_TYPE0 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE0)
4569 +#define IRQ_ILLEGAL_TYPE1 (IRQ_ARMCTRL_START + INTERRUPT_ILLEGAL_TYPE1)
4570 +#define IRQ_PENDING1 (IRQ_ARMCTRL_START + INTERRUPT_PENDING1)
4571 +#define IRQ_PENDING2 (IRQ_ARMCTRL_START + INTERRUPT_PENDING2)
4572 +
4573 +/*
4574 + * FIQ interrupts definitions are the same as the INT definitions.
4575 + */
4576 +#define FIQ_TIMER0 INT_TIMER0
4577 +#define FIQ_TIMER1 INT_TIMER1
4578 +#define FIQ_TIMER2 INT_TIMER2
4579 +#define FIQ_TIMER3 INT_TIMER3
4580 +#define FIQ_CODEC0 INT_CODEC0
4581 +#define FIQ_CODEC1 INT_CODEC1
4582 +#define FIQ_CODEC2 INT_CODEC2
4583 +#define FIQ_JPEG INT_JPEG
4584 +#define FIQ_ISP INT_ISP
4585 +#define FIQ_USB INT_USB
4586 +#define FIQ_3D INT_3D
4587 +#define FIQ_TRANSPOSER INT_TRANSPOSER
4588 +#define FIQ_MULTICORESYNC0 INT_MULTICORESYNC0
4589 +#define FIQ_MULTICORESYNC1 INT_MULTICORESYNC1
4590 +#define FIQ_MULTICORESYNC2 INT_MULTICORESYNC2
4591 +#define FIQ_MULTICORESYNC3 INT_MULTICORESYNC3
4592 +#define FIQ_DMA0 INT_DMA0
4593 +#define FIQ_DMA1 INT_DMA1
4594 +#define FIQ_DMA2 INT_DMA2
4595 +#define FIQ_DMA3 INT_DMA3
4596 +#define FIQ_DMA4 INT_DMA4
4597 +#define FIQ_DMA5 INT_DMA5
4598 +#define FIQ_DMA6 INT_DMA6
4599 +#define FIQ_DMA7 INT_DMA7
4600 +#define FIQ_DMA8 INT_DMA8
4601 +#define FIQ_DMA9 INT_DMA9
4602 +#define FIQ_DMA10 INT_DMA10
4603 +#define FIQ_DMA11 INT_DMA11
4604 +#define FIQ_DMA12 INT_DMA12
4605 +#define FIQ_AUX INT_AUX
4606 +#define FIQ_ARM INT_ARM
4607 +#define FIQ_VPUDMA INT_VPUDMA
4608 +#define FIQ_HOSTPORT INT_HOSTPORT
4609 +#define FIQ_VIDEOSCALER INT_VIDEOSCALER
4610 +#define FIQ_CCP2TX INT_CCP2TX
4611 +#define FIQ_SDC INT_SDC
4612 +#define FIQ_DSI0 INT_DSI0
4613 +#define FIQ_AVE INT_AVE
4614 +#define FIQ_CAM0 INT_CAM0
4615 +#define FIQ_CAM1 INT_CAM1
4616 +#define FIQ_HDMI0 INT_HDMI0
4617 +#define FIQ_HDMI1 INT_HDMI1
4618 +#define FIQ_PIXELVALVE1 INT_PIXELVALVE1
4619 +#define FIQ_I2CSPISLV INT_I2CSPISLV
4620 +#define FIQ_DSI1 INT_DSI1
4621 +#define FIQ_PWA0 INT_PWA0
4622 +#define FIQ_PWA1 INT_PWA1
4623 +#define FIQ_CPR INT_CPR
4624 +#define FIQ_SMI INT_SMI
4625 +#define FIQ_GPIO0 INT_GPIO0
4626 +#define FIQ_GPIO1 INT_GPIO1
4627 +#define FIQ_GPIO2 INT_GPIO2
4628 +#define FIQ_GPIO3 INT_GPIO3
4629 +#define FIQ_I2C INT_I2C
4630 +#define FIQ_SPI INT_SPI
4631 +#define FIQ_I2SPCM INT_I2SPCM
4632 +#define FIQ_SDIO INT_SDIO
4633 +#define FIQ_UART INT_UART
4634 +#define FIQ_SLIMBUS INT_SLIMBUS
4635 +#define FIQ_VEC INT_VEC
4636 +#define FIQ_CPG INT_CPG
4637 +#define FIQ_RNG INT_RNG
4638 +#define FIQ_ARASANSDIO INT_ARASANSDIO
4639 +#define FIQ_AVSPMON INT_AVSPMON
4640 +
4641 +#define FIQ_ARM_TIMER INT_ARM_TIMER
4642 +#define FIQ_ARM_MAILBOX INT_ARM_MAILBOX
4643 +#define FIQ_ARM_DOORBELL_0 INT_ARM_DOORBELL_0
4644 +#define FIQ_ARM_DOORBELL_1 INT_ARM_DOORBELL_1
4645 +#define FIQ_VPU0_HALTED INT_VPU0_HALTED
4646 +#define FIQ_VPU1_HALTED INT_VPU1_HALTED
4647 +#define FIQ_ILLEGAL_TYPE0 INT_ILLEGAL_TYPE0
4648 +#define FIQ_ILLEGAL_TYPE1 INT_ILLEGAL_TYPE1
4649 +#define FIQ_PENDING1 INT_PENDING1
4650 +#define FIQ_PENDING2 INT_PENDING2
4651 +
4652 +#define HARD_IRQS (64 + 21)
4653 +#define GPIO_IRQ_START HARD_IRQS
4654 +
4655 +#define GPIO_IRQS 32*5
4656 +
4657 +#define NR_IRQS HARD_IRQS+GPIO_IRQS
4658 +
4659 +
4660 +#endif /* _BCM2708_IRQS_H_ */
4661 diff --git a/arch/arm/mach-bcm2708/include/mach/memory.h b/arch/arm/mach-bcm2708/include/mach/memory.h
4662 new file mode 100644
4663 index 0000000..521540d
4664 --- /dev/null
4665 +++ b/arch/arm/mach-bcm2708/include/mach/memory.h
4666 @@ -0,0 +1,57 @@
4667 +/*
4668 + * arch/arm/mach-bcm2708/include/mach/memory.h
4669 + *
4670 + * Copyright (C) 2010 Broadcom
4671 + *
4672 + * This program is free software; you can redistribute it and/or modify
4673 + * it under the terms of the GNU General Public License as published by
4674 + * the Free Software Foundation; either version 2 of the License, or
4675 + * (at your option) any later version.
4676 + *
4677 + * This program is distributed in the hope that it will be useful,
4678 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4679 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4680 + * GNU General Public License for more details.
4681 + *
4682 + * You should have received a copy of the GNU General Public License
4683 + * along with this program; if not, write to the Free Software
4684 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4685 + */
4686 +#ifndef __ASM_ARCH_MEMORY_H
4687 +#define __ASM_ARCH_MEMORY_H
4688 +
4689 +/* Memory overview:
4690 +
4691 + [ARMcore] <--virtual addr-->
4692 + [ARMmmu] <--physical addr-->
4693 + [GERTmap] <--bus add-->
4694 + [VCperiph]
4695 +
4696 +*/
4697 +
4698 +/*
4699 + * Physical DRAM offset.
4700 + */
4701 +#define PLAT_PHYS_OFFSET UL(0x00000000)
4702 +#define VC_ARMMEM_OFFSET UL(0x00000000) /* offset in VC of ARM memory */
4703 +
4704 +#ifdef CONFIG_BCM2708_NOL2CACHE
4705 + #define _REAL_BUS_OFFSET UL(0xC0000000) /* don't use L1 or L2 caches */
4706 +#else
4707 + #define _REAL_BUS_OFFSET UL(0x40000000) /* use L2 cache */
4708 +#endif
4709 +
4710 +/* We're using the memory at 64M in the VideoCore for Linux - this adjustment
4711 + * will provide the offset into this area as well as setting the bits that
4712 + * stop the L1 and L2 cache from being used
4713 + *
4714 + * WARNING: this only works because the ARM is given memory at a fixed location
4715 + * (ARMMEM_OFFSET)
4716 + */
4717 +#define BUS_OFFSET (VC_ARMMEM_OFFSET + _REAL_BUS_OFFSET)
4718 +#define __virt_to_bus(x) ((x) + (BUS_OFFSET - PAGE_OFFSET))
4719 +#define __bus_to_virt(x) ((x) - (BUS_OFFSET - PAGE_OFFSET))
4720 +#define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PLAT_PHYS_OFFSET))
4721 +#define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PLAT_PHYS_OFFSET))
4722 +
4723 +#endif
4724 diff --git a/arch/arm/mach-bcm2708/include/mach/platform.h b/arch/arm/mach-bcm2708/include/mach/platform.h
4725 new file mode 100644
4726 index 0000000..110ce07
4727 --- /dev/null
4728 +++ b/arch/arm/mach-bcm2708/include/mach/platform.h
4729 @@ -0,0 +1,220 @@
4730 +/*
4731 + * arch/arm/mach-bcm2708/include/mach/platform.h
4732 + *
4733 + * Copyright (C) 2010 Broadcom
4734 + *
4735 + * This program is free software; you can redistribute it and/or modify
4736 + * it under the terms of the GNU General Public License as published by
4737 + * the Free Software Foundation; either version 2 of the License, or
4738 + * (at your option) any later version.
4739 + *
4740 + * This program is distributed in the hope that it will be useful,
4741 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
4742 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
4743 + * GNU General Public License for more details.
4744 + *
4745 + * You should have received a copy of the GNU General Public License
4746 + * along with this program; if not, write to the Free Software
4747 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
4748 + */
4749 +
4750 +#ifndef _BCM2708_PLATFORM_H
4751 +#define _BCM2708_PLATFORM_H
4752 +
4753 +
4754 +/* macros to get at IO space when running virtually */
4755 +#define IO_ADDRESS(x) (((x) & 0x0fffffff) + (((x) >> 4) & 0x0f000000) + 0xf0000000)
4756 +
4757 +#define __io_address(n) IOMEM(IO_ADDRESS(n))
4758 +
4759 +
4760 +/*
4761 + * SDRAM
4762 + */
4763 +#define BCM2708_SDRAM_BASE 0x00000000
4764 +
4765 +/*
4766 + * Logic expansion modules
4767 + *
4768 + */
4769 +
4770 +
4771 +/* ------------------------------------------------------------------------
4772 + * BCM2708 ARMCTRL Registers
4773 + * ------------------------------------------------------------------------
4774 + */
4775 +
4776 +#define HW_REGISTER_RW(addr) (addr)
4777 +#define HW_REGISTER_RO(addr) (addr)
4778 +
4779 +#include "arm_control.h"
4780 +#undef ARM_BASE
4781 +
4782 +/*
4783 + * Definitions and addresses for the ARM CONTROL logic
4784 + * This file is manually generated.
4785 + */
4786 +
4787 +#define BCM2708_PERI_BASE 0x20000000
4788 +#define ST_BASE (BCM2708_PERI_BASE + 0x3000) /* System Timer */
4789 +#define DMA_BASE (BCM2708_PERI_BASE + 0x7000) /* DMA controller */
4790 +#define ARM_BASE (BCM2708_PERI_BASE + 0xB000) /* BCM2708 ARM control block */
4791 +#define PM_BASE (BCM2708_PERI_BASE + 0x100000) /* Power Management, Reset controller and Watchdog registers */
4792 +#define GPIO_BASE (BCM2708_PERI_BASE + 0x200000) /* GPIO */
4793 +#define UART0_BASE (BCM2708_PERI_BASE + 0x201000) /* Uart 0 */
4794 +#define MMCI0_BASE (BCM2708_PERI_BASE + 0x202000) /* MMC interface */
4795 +#define UART1_BASE (BCM2708_PERI_BASE + 0x215000) /* Uart 1 */
4796 +#define EMMC_BASE (BCM2708_PERI_BASE + 0x300000) /* eMMC interface */
4797 +#define SMI_BASE (BCM2708_PERI_BASE + 0x600000) /* SMI */
4798 +#define USB_BASE (BCM2708_PERI_BASE + 0x980000) /* DTC_OTG USB controller */
4799 +#define MCORE_BASE (BCM2708_PERI_BASE + 0x0000) /* Fake frame buffer device (actually the multicore sync block*/
4800 +
4801 +#define ARMCTRL_BASE (ARM_BASE + 0x000)
4802 +#define ARMCTRL_IC_BASE (ARM_BASE + 0x200) /* ARM interrupt controller */
4803 +#define ARMCTRL_TIMER0_1_BASE (ARM_BASE + 0x400) /* Timer 0 and 1 */
4804 +#define ARMCTRL_0_SBM_BASE (ARM_BASE + 0x800) /* User 0 (ARM)'s Semaphores Doorbells and Mailboxes */
4805 +
4806 +
4807 +/*
4808 + * Interrupt assignments
4809 + */
4810 +
4811 +#define ARM_IRQ1_BASE 0
4812 +#define INTERRUPT_TIMER0 (ARM_IRQ1_BASE + 0)
4813 +#define INTERRUPT_TIMER1 (ARM_IRQ1_BASE + 1)
4814 +#define INTERRUPT_TIMER2 (ARM_IRQ1_BASE + 2)
4815 +#define INTERRUPT_TIMER3 (ARM_IRQ1_BASE + 3)
4816 +#define INTERRUPT_CODEC0 (ARM_IRQ1_BASE + 4)
4817 +#define INTERRUPT_CODEC1 (ARM_IRQ1_BASE + 5)
4818 +#define INTERRUPT_CODEC2 (ARM_IRQ1_BASE + 6)
4819 +#define INTERRUPT_VC_JPEG (ARM_IRQ1_BASE + 7)
4820 +#define INTERRUPT_ISP (ARM_IRQ1_BASE + 8)
4821 +#define INTERRUPT_VC_USB (ARM_IRQ1_BASE + 9)
4822 +#define INTERRUPT_VC_3D (ARM_IRQ1_BASE + 10)
4823 +#define INTERRUPT_TRANSPOSER (ARM_IRQ1_BASE + 11)
4824 +#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
4825 +#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
4826 +#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
4827 +#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
4828 +#define INTERRUPT_DMA0 (ARM_IRQ1_BASE + 16)
4829 +#define INTERRUPT_DMA1 (ARM_IRQ1_BASE + 17)
4830 +#define INTERRUPT_VC_DMA2 (ARM_IRQ1_BASE + 18)
4831 +#define INTERRUPT_VC_DMA3 (ARM_IRQ1_BASE + 19)
4832 +#define INTERRUPT_DMA4 (ARM_IRQ1_BASE + 20)
4833 +#define INTERRUPT_DMA5 (ARM_IRQ1_BASE + 21)
4834 +#define INTERRUPT_DMA6 (ARM_IRQ1_BASE + 22)
4835 +#define INTERRUPT_DMA7 (ARM_IRQ1_BASE + 23)
4836 +#define INTERRUPT_DMA8 (ARM_IRQ1_BASE + 24)
4837 +#define INTERRUPT_DMA9 (ARM_IRQ1_BASE + 25)
4838 +#define INTERRUPT_DMA10 (ARM_IRQ1_BASE + 26)
4839 +#define INTERRUPT_DMA11 (ARM_IRQ1_BASE + 27)
4840 +#define INTERRUPT_DMA12 (ARM_IRQ1_BASE + 28)
4841 +#define INTERRUPT_AUX (ARM_IRQ1_BASE + 29)
4842 +#define INTERRUPT_ARM (ARM_IRQ1_BASE + 30)
4843 +#define INTERRUPT_VPUDMA (ARM_IRQ1_BASE + 31)
4844 +
4845 +#define ARM_IRQ2_BASE 32
4846 +#define INTERRUPT_HOSTPORT (ARM_IRQ2_BASE + 0)
4847 +#define INTERRUPT_VIDEOSCALER (ARM_IRQ2_BASE + 1)
4848 +#define INTERRUPT_CCP2TX (ARM_IRQ2_BASE + 2)
4849 +#define INTERRUPT_SDC (ARM_IRQ2_BASE + 3)
4850 +#define INTERRUPT_DSI0 (ARM_IRQ2_BASE + 4)
4851 +#define INTERRUPT_AVE (ARM_IRQ2_BASE + 5)
4852 +#define INTERRUPT_CAM0 (ARM_IRQ2_BASE + 6)
4853 +#define INTERRUPT_CAM1 (ARM_IRQ2_BASE + 7)
4854 +#define INTERRUPT_HDMI0 (ARM_IRQ2_BASE + 8)
4855 +#define INTERRUPT_HDMI1 (ARM_IRQ2_BASE + 9)
4856 +#define INTERRUPT_PIXELVALVE1 (ARM_IRQ2_BASE + 10)
4857 +#define INTERRUPT_I2CSPISLV (ARM_IRQ2_BASE + 11)
4858 +#define INTERRUPT_DSI1 (ARM_IRQ2_BASE + 12)
4859 +#define INTERRUPT_PWA0 (ARM_IRQ2_BASE + 13)
4860 +#define INTERRUPT_PWA1 (ARM_IRQ2_BASE + 14)
4861 +#define INTERRUPT_CPR (ARM_IRQ2_BASE + 15)
4862 +#define INTERRUPT_SMI (ARM_IRQ2_BASE + 16)
4863 +#define INTERRUPT_GPIO0 (ARM_IRQ2_BASE + 17)
4864 +#define INTERRUPT_GPIO1 (ARM_IRQ2_BASE + 18)
4865 +#define INTERRUPT_GPIO2 (ARM_IRQ2_BASE + 19)
4866 +#define INTERRUPT_GPIO3 (ARM_IRQ2_BASE + 20)
4867 +#define INTERRUPT_VC_I2C (ARM_IRQ2_BASE + 21)
4868 +#define INTERRUPT_VC_SPI (ARM_IRQ2_BASE + 22)
4869 +#define INTERRUPT_VC_I2SPCM (ARM_IRQ2_BASE + 23)
4870 +#define INTERRUPT_VC_SDIO (ARM_IRQ2_BASE + 24)
4871 +#define INTERRUPT_VC_UART (ARM_IRQ2_BASE + 25)
4872 +#define INTERRUPT_SLIMBUS (ARM_IRQ2_BASE + 26)
4873 +#define INTERRUPT_VEC (ARM_IRQ2_BASE + 27)
4874 +#define INTERRUPT_CPG (ARM_IRQ2_BASE + 28)
4875 +#define INTERRUPT_RNG (ARM_IRQ2_BASE + 29)
4876 +#define INTERRUPT_VC_ARASANSDIO (ARM_IRQ2_BASE + 30)
4877 +#define INTERRUPT_AVSPMON (ARM_IRQ2_BASE + 31)
4878 +
4879 +#define ARM_IRQ0_BASE 64
4880 +#define INTERRUPT_ARM_TIMER (ARM_IRQ0_BASE + 0)
4881 +#define INTERRUPT_ARM_MAILBOX (ARM_IRQ0_BASE + 1)
4882 +#define INTERRUPT_ARM_DOORBELL_0 (ARM_IRQ0_BASE + 2)
4883 +#define INTERRUPT_ARM_DOORBELL_1 (ARM_IRQ0_BASE + 3)
4884 +#define INTERRUPT_VPU0_HALTED (ARM_IRQ0_BASE + 4)
4885 +#define INTERRUPT_VPU1_HALTED (ARM_IRQ0_BASE + 5)
4886 +#define INTERRUPT_ILLEGAL_TYPE0 (ARM_IRQ0_BASE + 6)
4887 +#define INTERRUPT_ILLEGAL_TYPE1 (ARM_IRQ0_BASE + 7)
4888 +#define INTERRUPT_PENDING1 (ARM_IRQ0_BASE + 8)
4889 +#define INTERRUPT_PENDING2 (ARM_IRQ0_BASE + 9)
4890 +#define INTERRUPT_JPEG (ARM_IRQ0_BASE + 10)
4891 +#define INTERRUPT_USB (ARM_IRQ0_BASE + 11)
4892 +#define INTERRUPT_3D (ARM_IRQ0_BASE + 12)
4893 +#define INTERRUPT_DMA2 (ARM_IRQ0_BASE + 13)
4894 +#define INTERRUPT_DMA3 (ARM_IRQ0_BASE + 14)
4895 +#define INTERRUPT_I2C (ARM_IRQ0_BASE + 15)
4896 +#define INTERRUPT_SPI (ARM_IRQ0_BASE + 16)
4897 +#define INTERRUPT_I2SPCM (ARM_IRQ0_BASE + 17)
4898 +#define INTERRUPT_SDIO (ARM_IRQ0_BASE + 18)
4899 +#define INTERRUPT_UART (ARM_IRQ0_BASE + 19)
4900 +#define INTERRUPT_ARASANSDIO (ARM_IRQ0_BASE + 20)
4901 +
4902 +#define MAXIRQNUM (32 + 32 + 20)
4903 +#define MAXFIQNUM (32 + 32 + 20)
4904 +
4905 +#define MAX_TIMER 2
4906 +#define MAX_PERIOD 699050
4907 +#define TICKS_PER_uSEC 1
4908 +
4909 +/*
4910 + * These are useconds NOT ticks.
4911 + *
4912 + */
4913 +#define mSEC_1 1000
4914 +#define mSEC_5 (mSEC_1 * 5)
4915 +#define mSEC_10 (mSEC_1 * 10)
4916 +#define mSEC_25 (mSEC_1 * 25)
4917 +#define SEC_1 (mSEC_1 * 1000)
4918 +
4919 +/*
4920 + * Watchdog
4921 + */
4922 +#define PM_RSTC (PM_BASE+0x1c)
4923 +#define PM_RSTS (PM_BASE+0x20)
4924 +#define PM_WDOG (PM_BASE+0x24)
4925 +
4926 +#define PM_WDOG_RESET 0000000000
4927 +#define PM_PASSWORD 0x5a000000
4928 +#define PM_WDOG_TIME_SET 0x000fffff
4929 +#define PM_RSTC_WRCFG_CLR 0xffffffcf
4930 +#define PM_RSTC_WRCFG_SET 0x00000030
4931 +#define PM_RSTC_WRCFG_FULL_RESET 0x00000020
4932 +#define PM_RSTC_RESET 0x00000102
4933 +
4934 +#define PM_RSTS_HADPOR_SET 0x00001000
4935 +#define PM_RSTS_HADSRH_SET 0x00000400
4936 +#define PM_RSTS_HADSRF_SET 0x00000200
4937 +#define PM_RSTS_HADSRQ_SET 0x00000100
4938 +#define PM_RSTS_HADWRH_SET 0x00000040
4939 +#define PM_RSTS_HADWRF_SET 0x00000020
4940 +#define PM_RSTS_HADWRQ_SET 0x00000010
4941 +#define PM_RSTS_HADDRH_SET 0x00000004
4942 +#define PM_RSTS_HADDRF_SET 0x00000002
4943 +#define PM_RSTS_HADDRQ_SET 0x00000001
4944 +
4945 +#define UART0_CLOCK 3000000
4946 +
4947 +#endif
4948 +
4949 +/* END */
4950 diff --git a/arch/arm/mach-bcm2708/include/mach/power.h b/arch/arm/mach-bcm2708/include/mach/power.h
4951 new file mode 100644
4952 index 0000000..52b3b02
4953 --- /dev/null
4954 +++ b/arch/arm/mach-bcm2708/include/mach/power.h
4955 @@ -0,0 +1,26 @@
4956 +/*
4957 + * linux/arch/arm/mach-bcm2708/power.h
4958 + *
4959 + * Copyright (C) 2010 Broadcom
4960 + *
4961 + * This program is free software; you can redistribute it and/or modify
4962 + * it under the terms of the GNU General Public License version 2 as
4963 + * published by the Free Software Foundation.
4964 + *
4965 + * This device provides a shared mechanism for controlling the power to
4966 + * VideoCore subsystems.
4967 + */
4968 +
4969 +#ifndef _MACH_BCM2708_POWER_H
4970 +#define _MACH_BCM2708_POWER_H
4971 +
4972 +#include <linux/types.h>
4973 +#include <mach/arm_power.h>
4974 +
4975 +typedef unsigned int BCM_POWER_HANDLE_T;
4976 +
4977 +extern int bcm_power_open(BCM_POWER_HANDLE_T *handle);
4978 +extern int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request);
4979 +extern int bcm_power_close(BCM_POWER_HANDLE_T handle);
4980 +
4981 +#endif
4982 diff --git a/arch/arm/mach-bcm2708/include/mach/system.h b/arch/arm/mach-bcm2708/include/mach/system.h
4983 new file mode 100644
4984 index 0000000..2d0b821
4985 --- /dev/null
4986 +++ b/arch/arm/mach-bcm2708/include/mach/system.h
4987 @@ -0,0 +1,38 @@
4988 +/*
4989 + * arch/arm/mach-bcm2708/include/mach/system.h
4990 + *
4991 + * Copyright (C) 2010 Broadcom
4992 + * Copyright (C) 2003 ARM Limited
4993 + * Copyright (C) 2000 Deep Blue Solutions Ltd
4994 + *
4995 + * This program is free software; you can redistribute it and/or modify
4996 + * it under the terms of the GNU General Public License as published by
4997 + * the Free Software Foundation; either version 2 of the License, or
4998 + * (at your option) any later version.
4999 + *
5000 + * This program is distributed in the hope that it will be useful,
5001 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5002 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5003 + * GNU General Public License for more details.
5004 + *
5005 + * You should have received a copy of the GNU General Public License
5006 + * along with this program; if not, write to the Free Software
5007 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5008 + */
5009 +#ifndef __ASM_ARCH_SYSTEM_H
5010 +#define __ASM_ARCH_SYSTEM_H
5011 +
5012 +#include <linux/io.h>
5013 +#include <mach/hardware.h>
5014 +#include <mach/platform.h>
5015 +
5016 +static inline void arch_idle(void)
5017 +{
5018 + /*
5019 + * This should do all the clock switching
5020 + * and wait for interrupt tricks
5021 + */
5022 + cpu_do_idle();
5023 +}
5024 +
5025 +#endif
5026 diff --git a/arch/arm/mach-bcm2708/include/mach/timex.h b/arch/arm/mach-bcm2708/include/mach/timex.h
5027 new file mode 100644
5028 index 0000000..64a660c
5029 --- /dev/null
5030 +++ b/arch/arm/mach-bcm2708/include/mach/timex.h
5031 @@ -0,0 +1,23 @@
5032 +/*
5033 + * arch/arm/mach-bcm2708/include/mach/timex.h
5034 + *
5035 + * BCM2708 sysem clock frequency
5036 + *
5037 + * Copyright (C) 2010 Broadcom
5038 + *
5039 + * This program is free software; you can redistribute it and/or modify
5040 + * it under the terms of the GNU General Public License as published by
5041 + * the Free Software Foundation; either version 2 of the License, or
5042 + * (at your option) any later version.
5043 + *
5044 + * This program is distributed in the hope that it will be useful,
5045 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5046 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5047 + * GNU General Public License for more details.
5048 + *
5049 + * You should have received a copy of the GNU General Public License
5050 + * along with this program; if not, write to the Free Software
5051 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5052 + */
5053 +
5054 +#define CLOCK_TICK_RATE (1000000)
5055 diff --git a/arch/arm/mach-bcm2708/include/mach/uncompress.h b/arch/arm/mach-bcm2708/include/mach/uncompress.h
5056 new file mode 100644
5057 index 0000000..6ff8f94
5058 --- /dev/null
5059 +++ b/arch/arm/mach-bcm2708/include/mach/uncompress.h
5060 @@ -0,0 +1,85 @@
5061 +/*
5062 + * arch/arm/mach-bcn2708/include/mach/uncompress.h
5063 + *
5064 + * Copyright (C) 2010 Broadcom
5065 + * Copyright (C) 2003 ARM Limited
5066 + *
5067 + * This program is free software; you can redistribute it and/or modify
5068 + * it under the terms of the GNU General Public License as published by
5069 + * the Free Software Foundation; either version 2 of the License, or
5070 + * (at your option) any later version.
5071 + *
5072 + * This program is distributed in the hope that it will be useful,
5073 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5074 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5075 + * GNU General Public License for more details.
5076 + *
5077 + * You should have received a copy of the GNU General Public License
5078 + * along with this program; if not, write to the Free Software
5079 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5080 + */
5081 +
5082 +#include <linux/io.h>
5083 +#include <linux/amba/serial.h>
5084 +#include <mach/hardware.h>
5085 +
5086 +#define UART_BAUD 115200
5087 +
5088 +#define BCM2708_UART_DR __io(UART0_BASE + UART01x_DR)
5089 +#define BCM2708_UART_FR __io(UART0_BASE + UART01x_FR)
5090 +#define BCM2708_UART_IBRD __io(UART0_BASE + UART011_IBRD)
5091 +#define BCM2708_UART_FBRD __io(UART0_BASE + UART011_FBRD)
5092 +#define BCM2708_UART_LCRH __io(UART0_BASE + UART011_LCRH)
5093 +#define BCM2708_UART_CR __io(UART0_BASE + UART011_CR)
5094 +
5095 +/*
5096 + * This does not append a newline
5097 + */
5098 +static inline void putc(int c)
5099 +{
5100 + while (__raw_readl(BCM2708_UART_FR) & UART01x_FR_TXFF)
5101 + barrier();
5102 +
5103 + __raw_writel(c, BCM2708_UART_DR);
5104 +}
5105 +
5106 +static inline void flush(void)
5107 +{
5108 + int fr;
5109 +
5110 + do {
5111 + fr = __raw_readl(BCM2708_UART_FR);
5112 + barrier();
5113 + } while ((fr & (UART011_FR_TXFE | UART01x_FR_BUSY)) != UART011_FR_TXFE);
5114 +}
5115 +
5116 +static inline void arch_decomp_setup(void)
5117 +{
5118 + int temp, div, rem, frac;
5119 +
5120 + temp = 16 * UART_BAUD;
5121 + div = UART0_CLOCK / temp;
5122 + rem = UART0_CLOCK % temp;
5123 + temp = (8 * rem) / UART_BAUD;
5124 + frac = (temp >> 1) + (temp & 1);
5125 +
5126 + /* Make sure the UART is disabled before we start */
5127 + __raw_writel(0, BCM2708_UART_CR);
5128 +
5129 + /* Set the baud rate */
5130 + __raw_writel(div, BCM2708_UART_IBRD);
5131 + __raw_writel(frac, BCM2708_UART_FBRD);
5132 +
5133 + /* Set the UART to 8n1, FIFO enabled */
5134 + __raw_writel(UART01x_LCRH_WLEN_8 | UART01x_LCRH_FEN, BCM2708_UART_LCRH);
5135 +
5136 + /* Enable the UART */
5137 + __raw_writel(UART01x_CR_UARTEN | UART011_CR_TXE | UART011_CR_RXE,
5138 + BCM2708_UART_CR);
5139 +}
5140 +
5141 +/*
5142 + * nothing to do
5143 + */
5144 +#define arch_decomp_wdog()
5145 +
5146 diff --git a/arch/arm/mach-bcm2708/include/mach/vc_mem.h b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
5147 new file mode 100644
5148 index 0000000..d29125b
5149 --- /dev/null
5150 +++ b/arch/arm/mach-bcm2708/include/mach/vc_mem.h
5151 @@ -0,0 +1,36 @@
5152 +/*****************************************************************************
5153 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5154 +*
5155 +* Unless you and Broadcom execute a separate written software license
5156 +* agreement governing use of this software, this software is licensed to you
5157 +* under the terms of the GNU General Public License version 2, available at
5158 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5159 +*
5160 +* Notwithstanding the above, under no circumstances may you combine this
5161 +* software in any way with any other Broadcom software provided under a
5162 +* license other than the GPL, without Broadcom's express prior written
5163 +* consent.
5164 +*****************************************************************************/
5165 +
5166 +#if !defined( VC_MEM_H )
5167 +#define VC_MEM_H
5168 +
5169 +#include <linux/ioctl.h>
5170 +
5171 +#define VC_MEM_IOC_MAGIC 'v'
5172 +
5173 +#define VC_MEM_IOC_MEM_PHYS_ADDR _IOR( VC_MEM_IOC_MAGIC, 0, unsigned long )
5174 +#define VC_MEM_IOC_MEM_SIZE _IOR( VC_MEM_IOC_MAGIC, 1, unsigned int )
5175 +#define VC_MEM_IOC_MEM_BASE _IOR( VC_MEM_IOC_MAGIC, 2, unsigned int )
5176 +#define VC_MEM_IOC_MEM_LOAD _IOR( VC_MEM_IOC_MAGIC, 3, unsigned int )
5177 +
5178 +#if defined( __KERNEL__ )
5179 +#define VC_MEM_TO_ARM_ADDR_MASK 0x3FFFFFFF
5180 +
5181 +extern unsigned long mm_vc_mem_phys_addr;
5182 +extern unsigned int mm_vc_mem_size;
5183 +extern int vc_mem_get_current_size( void );
5184 +#endif
5185 +
5186 +#endif /* VC_MEM_H */
5187 +
5188 diff --git a/arch/arm/mach-bcm2708/include/mach/vcio.h b/arch/arm/mach-bcm2708/include/mach/vcio.h
5189 new file mode 100644
5190 index 0000000..b522ba9
5191 --- /dev/null
5192 +++ b/arch/arm/mach-bcm2708/include/mach/vcio.h
5193 @@ -0,0 +1,141 @@
5194 +/*
5195 + * arch/arm/mach-bcm2708/include/mach/vcio.h
5196 + *
5197 + * Copyright (C) 2010 Broadcom
5198 + *
5199 + * This program is free software; you can redistribute it and/or modify
5200 + * it under the terms of the GNU General Public License as published by
5201 + * the Free Software Foundation; either version 2 of the License, or
5202 + * (at your option) any later version.
5203 + *
5204 + * This program is distributed in the hope that it will be useful,
5205 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5206 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5207 + * GNU General Public License for more details.
5208 + *
5209 + * You should have received a copy of the GNU General Public License
5210 + * along with this program; if not, write to the Free Software
5211 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5212 + */
5213 +#ifndef _MACH_BCM2708_VCIO_H
5214 +#define _MACH_BCM2708_VCIO_H
5215 +
5216 +/* Routines to handle I/O via the VideoCore "ARM control" registers
5217 + * (semaphores, doorbells, mailboxes)
5218 + */
5219 +
5220 +#define BCM_VCIO_DRIVER_NAME "bcm2708_vcio"
5221 +
5222 +/* Constants shared with the ARM identifying separate mailbox channels */
5223 +#define MBOX_CHAN_POWER 0 /* for use by the power management interface */
5224 +#define MBOX_CHAN_FB 1 /* for use by the frame buffer */
5225 +#define MBOX_CHAN_VCHIQ 3 /* for use by the VCHIQ interface */
5226 +#define MBOX_CHAN_PROPERTY 8 /* for use by the property channel */
5227 +#define MBOX_CHAN_COUNT 9
5228 +
5229 +/* Mailbox property tags */
5230 +enum {
5231 + VCMSG_PROPERTY_END = 0x00000000,
5232 + VCMSG_GET_FIRMWARE_REVISION = 0x00000001,
5233 + VCMSG_GET_BOARD_MODEL = 0x00010001,
5234 + VCMSG_GET_BOARD_REVISION = 0x00020002,
5235 + VCMSG_GET_BOARD_MAC_ADDRESS = 0x00020003,
5236 + VCMSG_GET_BOARD_SERIAL = 0x00020004,
5237 + VCMSG_GET_ARM_MEMORY = 0x00020005,
5238 + VCMSG_GET_VC_MEMORY = 0x00020006,
5239 + VCMSG_GET_CLOCKS = 0x00020007,
5240 + VCMSG_GET_COMMAND_LINE = 0x00050001,
5241 + VCMSG_GET_DMA_CHANNELS = 0x00060001,
5242 + VCMSG_GET_POWER_STATE = 0x00020001,
5243 + VCMSG_GET_TIMING = 0x00020002,
5244 + VCMSG_SET_POWER_STATE = 0x00028001,
5245 + VCMSG_GET_CLOCK_STATE = 0x00030001,
5246 + VCMSG_SET_CLOCK_STATE = 0x00038001,
5247 + VCMSG_GET_CLOCK_RATE = 0x00030002,
5248 + VCMSG_SET_CLOCK_RATE = 0x00038002,
5249 + VCMSG_GET_VOLTAGE = 0x00030003,
5250 + VCMSG_SET_VOLTAGE = 0x00038003,
5251 + VCMSG_GET_MAX_CLOCK = 0x00030004,
5252 + VCMSG_GET_MAX_VOLTAGE = 0x00030005,
5253 + VCMSG_GET_TEMPERATURE = 0x00030006,
5254 + VCMSG_GET_MIN_CLOCK = 0x00030007,
5255 + VCMSG_GET_MIN_VOLTAGE = 0x00030008,
5256 + VCMSG_GET_TURBO = 0x00030009,
5257 + VCMSG_SET_TURBO = 0x00038009,
5258 + VCMSG_SET_ALLOCATE_BUFFER = 0x00040001,
5259 + VCMSG_SET_RELEASE_BUFFER = 0x00048001,
5260 + VCMSG_SET_BLANK_SCREEN = 0x00040002,
5261 + VCMSG_TST_BLANK_SCREEN = 0x00044002,
5262 + VCMSG_GET_PHYSICAL_WIDTH_HEIGHT = 0x00040003,
5263 + VCMSG_TST_PHYSICAL_WIDTH_HEIGHT = 0x00044003,
5264 + VCMSG_SET_PHYSICAL_WIDTH_HEIGHT = 0x00048003,
5265 + VCMSG_GET_VIRTUAL_WIDTH_HEIGHT = 0x00040004,
5266 + VCMSG_TST_VIRTUAL_WIDTH_HEIGHT = 0x00044004,
5267 + VCMSG_SET_VIRTUAL_WIDTH_HEIGHT = 0x00048004,
5268 + VCMSG_GET_DEPTH = 0x00040005,
5269 + VCMSG_TST_DEPTH = 0x00044005,
5270 + VCMSG_SET_DEPTH = 0x00048005,
5271 + VCMSG_GET_PIXEL_ORDER = 0x00040006,
5272 + VCMSG_TST_PIXEL_ORDER = 0x00044006,
5273 + VCMSG_SET_PIXEL_ORDER = 0x00048006,
5274 + VCMSG_GET_ALPHA_MODE = 0x00040007,
5275 + VCMSG_TST_ALPHA_MODE = 0x00044007,
5276 + VCMSG_SET_ALPHA_MODE = 0x00048007,
5277 + VCMSG_GET_PITCH = 0x00040008,
5278 + VCMSG_TST_PITCH = 0x00044008,
5279 + VCMSG_SET_PITCH = 0x00048008,
5280 + VCMSG_GET_VIRTUAL_OFFSET = 0x00040009,
5281 + VCMSG_TST_VIRTUAL_OFFSET = 0x00044009,
5282 + VCMSG_SET_VIRTUAL_OFFSET = 0x00048009,
5283 + VCMSG_GET_OVERSCAN = 0x0004000a,
5284 + VCMSG_TST_OVERSCAN = 0x0004400a,
5285 + VCMSG_SET_OVERSCAN = 0x0004800a,
5286 + VCMSG_GET_PALETTE = 0x0004000b,
5287 + VCMSG_TST_PALETTE = 0x0004400b,
5288 + VCMSG_SET_PALETTE = 0x0004800b,
5289 + VCMSG_GET_LAYER = 0x0004000c,
5290 + VCMSG_TST_LAYER = 0x0004400c,
5291 + VCMSG_SET_LAYER = 0x0004800c,
5292 + VCMSG_GET_TRANSFORM = 0x0004000d,
5293 + VCMSG_TST_TRANSFORM = 0x0004400d,
5294 + VCMSG_SET_TRANSFORM = 0x0004800d,
5295 +};
5296 +
5297 +extern int /*rc*/ bcm_mailbox_read(unsigned chan, uint32_t *data28);
5298 +extern int /*rc*/ bcm_mailbox_write(unsigned chan, uint32_t data28);
5299 +extern int /*rc*/ bcm_mailbox_property(void *data, int size);
5300 +
5301 +#include <linux/ioctl.h>
5302 +
5303 +/*
5304 + * The major device number. We can't rely on dynamic
5305 + * registration any more, because ioctls need to know
5306 + * it.
5307 + */
5308 +#define MAJOR_NUM 100
5309 +
5310 +/*
5311 + * Set the message of the device driver
5312 + */
5313 +#define IOCTL_MBOX_PROPERTY _IOWR(MAJOR_NUM, 0, char *)
5314 +/*
5315 + * _IOWR means that we're creating an ioctl command
5316 + * number for passing information from a user process
5317 + * to the kernel module and from the kernel module to user process
5318 + *
5319 + * The first arguments, MAJOR_NUM, is the major device
5320 + * number we're using.
5321 + *
5322 + * The second argument is the number of the command
5323 + * (there could be several with different meanings).
5324 + *
5325 + * The third argument is the type we want to get from
5326 + * the process to the kernel.
5327 + */
5328 +
5329 +/*
5330 + * The name of the device file
5331 + */
5332 +#define DEVICE_FILE_NAME "char_dev"
5333 +
5334 +#endif
5335 diff --git a/arch/arm/mach-bcm2708/include/mach/vmalloc.h b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
5336 new file mode 100644
5337 index 0000000..502c617
5338 --- /dev/null
5339 +++ b/arch/arm/mach-bcm2708/include/mach/vmalloc.h
5340 @@ -0,0 +1,20 @@
5341 +/*
5342 + * arch/arm/mach-bcm2708/include/mach/vmalloc.h
5343 + *
5344 + * Copyright (C) 2010 Broadcom
5345 + *
5346 + * This program is free software; you can redistribute it and/or modify
5347 + * it under the terms of the GNU General Public License as published by
5348 + * the Free Software Foundation; either version 2 of the License, or
5349 + * (at your option) any later version.
5350 + *
5351 + * This program is distributed in the hope that it will be useful,
5352 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
5353 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
5354 + * GNU General Public License for more details.
5355 + *
5356 + * You should have received a copy of the GNU General Public License
5357 + * along with this program; if not, write to the Free Software
5358 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
5359 + */
5360 +#define VMALLOC_END (0xe8000000)
5361 diff --git a/arch/arm/mach-bcm2708/power.c b/arch/arm/mach-bcm2708/power.c
5362 new file mode 100644
5363 index 0000000..256bf1a
5364 --- /dev/null
5365 +++ b/arch/arm/mach-bcm2708/power.c
5366 @@ -0,0 +1,194 @@
5367 +/*
5368 + * linux/arch/arm/mach-bcm2708/power.c
5369 + *
5370 + * Copyright (C) 2010 Broadcom
5371 + *
5372 + * This program is free software; you can redistribute it and/or modify
5373 + * it under the terms of the GNU General Public License version 2 as
5374 + * published by the Free Software Foundation.
5375 + *
5376 + * This device provides a shared mechanism for controlling the power to
5377 + * VideoCore subsystems.
5378 + */
5379 +
5380 +#include <linux/module.h>
5381 +#include <linux/semaphore.h>
5382 +#include <linux/bug.h>
5383 +#include <mach/power.h>
5384 +#include <mach/vcio.h>
5385 +#include <mach/arm_power.h>
5386 +
5387 +#define DRIVER_NAME "bcm2708_power"
5388 +
5389 +#define BCM_POWER_MAXCLIENTS 4
5390 +#define BCM_POWER_NOCLIENT (1<<31)
5391 +
5392 +/* Some drivers expect there devices to be permanently powered */
5393 +#define BCM_POWER_ALWAYS_ON (BCM_POWER_USB)
5394 +
5395 +#if 1
5396 +#define DPRINTK printk
5397 +#else
5398 +#define DPRINTK if (0) printk
5399 +#endif
5400 +
5401 +struct state_struct {
5402 + uint32_t global_request;
5403 + uint32_t client_request[BCM_POWER_MAXCLIENTS];
5404 + struct semaphore client_mutex;
5405 + struct semaphore mutex;
5406 +} g_state;
5407 +
5408 +int bcm_power_open(BCM_POWER_HANDLE_T *handle)
5409 +{
5410 + BCM_POWER_HANDLE_T i;
5411 + int ret = -EBUSY;
5412 +
5413 + down(&g_state.client_mutex);
5414 +
5415 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5416 + if (g_state.client_request[i] == BCM_POWER_NOCLIENT) {
5417 + g_state.client_request[i] = BCM_POWER_NONE;
5418 + *handle = i;
5419 + ret = 0;
5420 + break;
5421 + }
5422 + }
5423 +
5424 + up(&g_state.client_mutex);
5425 +
5426 + DPRINTK("bcm_power_open() -> %d\n", *handle);
5427 +
5428 + return ret;
5429 +}
5430 +EXPORT_SYMBOL_GPL(bcm_power_open);
5431 +
5432 +int bcm_power_request(BCM_POWER_HANDLE_T handle, uint32_t request)
5433 +{
5434 + int rc = 0;
5435 +
5436 + DPRINTK("bcm_power_request(%d, %x)\n", handle, request);
5437 +
5438 + if ((handle < BCM_POWER_MAXCLIENTS) &&
5439 + (g_state.client_request[handle] != BCM_POWER_NOCLIENT)) {
5440 + if (down_interruptible(&g_state.mutex) != 0) {
5441 + DPRINTK("bcm_power_request -> interrupted\n");
5442 + return -EINTR;
5443 + }
5444 +
5445 + if (request != g_state.client_request[handle]) {
5446 + uint32_t others_request = 0;
5447 + uint32_t global_request;
5448 + BCM_POWER_HANDLE_T i;
5449 +
5450 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++) {
5451 + if (i != handle)
5452 + others_request |=
5453 + g_state.client_request[i];
5454 + }
5455 + others_request &= ~BCM_POWER_NOCLIENT;
5456 +
5457 + global_request = request | others_request;
5458 + if (global_request != g_state.global_request) {
5459 + uint32_t actual;
5460 +
5461 + /* Send a request to VideoCore */
5462 + bcm_mailbox_write(MBOX_CHAN_POWER,
5463 + global_request << 4);
5464 +
5465 + /* Wait for a response during power-up */
5466 + if (global_request & ~g_state.global_request) {
5467 + rc = bcm_mailbox_read(MBOX_CHAN_POWER,
5468 + &actual);
5469 + DPRINTK
5470 + ("bcm_mailbox_read -> %08x, %d\n",
5471 + actual, rc);
5472 + actual >>= 4;
5473 + } else {
5474 + rc = 0;
5475 + actual = global_request;
5476 + }
5477 +
5478 + if (rc == 0) {
5479 + if (actual != global_request) {
5480 + printk(KERN_ERR
5481 + "%s: prev global %x, new global %x, actual %x, request %x, others_request %x\n",
5482 + __func__,
5483 + g_state.global_request,
5484 + global_request, actual, request, others_request);
5485 + /* A failure */
5486 + BUG_ON((others_request & actual)
5487 + != others_request);
5488 + request &= actual;
5489 + rc = -EIO;
5490 + }
5491 +
5492 + g_state.global_request = actual;
5493 + g_state.client_request[handle] =
5494 + request;
5495 + }
5496 + }
5497 + }
5498 + up(&g_state.mutex);
5499 + } else {
5500 + rc = -EINVAL;
5501 + }
5502 + DPRINTK("bcm_power_request -> %d\n", rc);
5503 + return rc;
5504 +}
5505 +EXPORT_SYMBOL_GPL(bcm_power_request);
5506 +
5507 +int bcm_power_close(BCM_POWER_HANDLE_T handle)
5508 +{
5509 + int rc;
5510 +
5511 + DPRINTK("bcm_power_close(%d)\n", handle);
5512 +
5513 + rc = bcm_power_request(handle, BCM_POWER_NONE);
5514 + if (rc == 0)
5515 + g_state.client_request[handle] = BCM_POWER_NOCLIENT;
5516 +
5517 + return rc;
5518 +}
5519 +EXPORT_SYMBOL_GPL(bcm_power_close);
5520 +
5521 +static int __init bcm_power_init(void)
5522 +{
5523 +#if defined(BCM_POWER_ALWAYS_ON)
5524 + BCM_POWER_HANDLE_T always_on_handle;
5525 +#endif
5526 + int rc = 0;
5527 + int i;
5528 +
5529 + printk(KERN_INFO "bcm_power: Broadcom power driver\n");
5530 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5531 +
5532 + for (i = 0; i < BCM_POWER_MAXCLIENTS; i++)
5533 + g_state.client_request[i] = BCM_POWER_NOCLIENT;
5534 +
5535 + sema_init(&g_state.client_mutex, 1);
5536 + sema_init(&g_state.mutex, 1);
5537 +
5538 + g_state.global_request = 0;
5539 +
5540 +#if defined(BCM_POWER_ALWAYS_ON)
5541 + if (BCM_POWER_ALWAYS_ON) {
5542 + bcm_power_open(&always_on_handle);
5543 + bcm_power_request(always_on_handle, BCM_POWER_ALWAYS_ON);
5544 + }
5545 +#endif
5546 +
5547 + return rc;
5548 +}
5549 +
5550 +static void __exit bcm_power_exit(void)
5551 +{
5552 + bcm_mailbox_write(MBOX_CHAN_POWER, 0);
5553 +}
5554 +
5555 +arch_initcall(bcm_power_init); /* Initialize early */
5556 +module_exit(bcm_power_exit);
5557 +
5558 +MODULE_AUTHOR("Phil Elwell");
5559 +MODULE_DESCRIPTION("Interface to BCM2708 power management");
5560 +MODULE_LICENSE("GPL");
5561 diff --git a/arch/arm/mach-bcm2708/vc_mem.c b/arch/arm/mach-bcm2708/vc_mem.c
5562 new file mode 100644
5563 index 0000000..aeae4d5
5564 --- /dev/null
5565 +++ b/arch/arm/mach-bcm2708/vc_mem.c
5566 @@ -0,0 +1,462 @@
5567 +/*****************************************************************************
5568 +* Copyright 2010 - 2011 Broadcom Corporation. All rights reserved.
5569 +*
5570 +* Unless you and Broadcom execute a separate written software license
5571 +* agreement governing use of this software, this software is licensed to you
5572 +* under the terms of the GNU General Public License version 2, available at
5573 +* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
5574 +*
5575 +* Notwithstanding the above, under no circumstances may you combine this
5576 +* software in any way with any other Broadcom software provided under a
5577 +* license other than the GPL, without Broadcom's express prior written
5578 +* consent.
5579 +*****************************************************************************/
5580 +
5581 +#include <linux/kernel.h>
5582 +#include <linux/module.h>
5583 +#include <linux/fs.h>
5584 +#include <linux/device.h>
5585 +#include <linux/cdev.h>
5586 +#include <linux/mm.h>
5587 +#include <linux/slab.h>
5588 +#include <linux/proc_fs.h>
5589 +#include <asm/uaccess.h>
5590 +#include <linux/dma-mapping.h>
5591 +
5592 +#ifdef CONFIG_ARCH_KONA
5593 +#include <chal/chal_ipc.h>
5594 +#elif CONFIG_ARCH_BCM2708
5595 +#else
5596 +#include <csp/chal_ipc.h>
5597 +#endif
5598 +
5599 +#include "mach/vc_mem.h"
5600 +#include <mach/vcio.h>
5601 +
5602 +#define DRIVER_NAME "vc-mem"
5603 +
5604 +// Uncomment to enable debug logging
5605 +// #define ENABLE_DBG
5606 +
5607 +#if defined(ENABLE_DBG)
5608 +#define LOG_DBG( fmt, ... ) printk( KERN_INFO fmt "\n", ##__VA_ARGS__ )
5609 +#else
5610 +#define LOG_DBG( fmt, ... )
5611 +#endif
5612 +#define LOG_ERR( fmt, ... ) printk( KERN_ERR fmt "\n", ##__VA_ARGS__ )
5613 +
5614 +// Device (/dev) related variables
5615 +static dev_t vc_mem_devnum = 0;
5616 +static struct class *vc_mem_class = NULL;
5617 +static struct cdev vc_mem_cdev;
5618 +static int vc_mem_inited = 0;
5619 +
5620 +// Proc entry
5621 +static struct proc_dir_entry *vc_mem_proc_entry;
5622 +
5623 +/*
5624 + * Videocore memory addresses and size
5625 + *
5626 + * Drivers that wish to know the videocore memory addresses and sizes should
5627 + * use these variables instead of the MM_IO_BASE and MM_ADDR_IO defines in
5628 + * headers. This allows the other drivers to not be tied down to a a certain
5629 + * address/size at compile time.
5630 + *
5631 + * In the future, the goal is to have the videocore memory virtual address and
5632 + * size be calculated at boot time rather than at compile time. The decision of
5633 + * where the videocore memory resides and its size would be in the hands of the
5634 + * bootloader (and/or kernel). When that happens, the values of these variables
5635 + * would be calculated and assigned in the init function.
5636 + */
5637 +// in the 2835 VC in mapped above ARM, but ARM has full access to VC space
5638 +unsigned long mm_vc_mem_phys_addr = 0x00000000;
5639 +unsigned int mm_vc_mem_size = 0;
5640 +unsigned int mm_vc_mem_base = 0;
5641 +
5642 +EXPORT_SYMBOL(mm_vc_mem_phys_addr);
5643 +EXPORT_SYMBOL(mm_vc_mem_size);
5644 +EXPORT_SYMBOL(mm_vc_mem_base);
5645 +
5646 +static uint phys_addr = 0;
5647 +static uint mem_size = 0;
5648 +static uint mem_base = 0;
5649 +
5650 +
5651 +/****************************************************************************
5652 +*
5653 +* vc_mem_open
5654 +*
5655 +***************************************************************************/
5656 +
5657 +static int
5658 +vc_mem_open(struct inode *inode, struct file *file)
5659 +{
5660 + (void) inode;
5661 + (void) file;
5662 +
5663 + LOG_DBG("%s: called file = 0x%p", __func__, file);
5664 +
5665 + return 0;
5666 +}
5667 +
5668 +/****************************************************************************
5669 +*
5670 +* vc_mem_release
5671 +*
5672 +***************************************************************************/
5673 +
5674 +static int
5675 +vc_mem_release(struct inode *inode, struct file *file)
5676 +{
5677 + (void) inode;
5678 + (void) file;
5679 +
5680 + LOG_DBG("%s: called file = 0x%p", __func__, file);
5681 +
5682 + return 0;
5683 +}
5684 +
5685 +/****************************************************************************
5686 +*
5687 +* vc_mem_get_size
5688 +*
5689 +***************************************************************************/
5690 +
5691 +static void
5692 +vc_mem_get_size(void)
5693 +{
5694 +}
5695 +
5696 +/****************************************************************************
5697 +*
5698 +* vc_mem_get_base
5699 +*
5700 +***************************************************************************/
5701 +
5702 +static void
5703 +vc_mem_get_base(void)
5704 +{
5705 +}
5706 +
5707 +/****************************************************************************
5708 +*
5709 +* vc_mem_get_current_size
5710 +*
5711 +***************************************************************************/
5712 +
5713 +int
5714 +vc_mem_get_current_size(void)
5715 +{
5716 + return mm_vc_mem_size;
5717 +}
5718 +
5719 +EXPORT_SYMBOL_GPL(vc_mem_get_current_size);
5720 +
5721 +/****************************************************************************
5722 +*
5723 +* vc_mem_ioctl
5724 +*
5725 +***************************************************************************/
5726 +
5727 +static long
5728 +vc_mem_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
5729 +{
5730 + int rc = 0;
5731 +
5732 + (void) cmd;
5733 + (void) arg;
5734 +
5735 + LOG_DBG("%s: called file = 0x%p", __func__, file);
5736 +
5737 + switch (cmd) {
5738 + case VC_MEM_IOC_MEM_PHYS_ADDR:
5739 + {
5740 + LOG_DBG("%s: VC_MEM_IOC_MEM_PHYS_ADDR=0x%p",
5741 + __func__, (void *) mm_vc_mem_phys_addr);
5742 +
5743 + if (copy_to_user((void *) arg, &mm_vc_mem_phys_addr,
5744 + sizeof (mm_vc_mem_phys_addr)) != 0) {
5745 + rc = -EFAULT;
5746 + }
5747 + break;
5748 + }
5749 + case VC_MEM_IOC_MEM_SIZE:
5750 + {
5751 + // Get the videocore memory size first
5752 + vc_mem_get_size();
5753 +
5754 + LOG_DBG("%s: VC_MEM_IOC_MEM_SIZE=%u", __func__,
5755 + mm_vc_mem_size);
5756 +
5757 + if (copy_to_user((void *) arg, &mm_vc_mem_size,
5758 + sizeof (mm_vc_mem_size)) != 0) {
5759 + rc = -EFAULT;
5760 + }
5761 + break;
5762 + }
5763 + case VC_MEM_IOC_MEM_BASE:
5764 + {
5765 + // Get the videocore memory base
5766 + vc_mem_get_base();
5767 +
5768 + LOG_DBG("%s: VC_MEM_IOC_MEM_BASE=%u", __func__,
5769 + mm_vc_mem_base);
5770 +
5771 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
5772 + sizeof (mm_vc_mem_base)) != 0) {
5773 + rc = -EFAULT;
5774 + }
5775 + break;
5776 + }
5777 + case VC_MEM_IOC_MEM_LOAD:
5778 + {
5779 + // Get the videocore memory base
5780 + vc_mem_get_base();
5781 +
5782 + LOG_DBG("%s: VC_MEM_IOC_MEM_LOAD=%u", __func__,
5783 + mm_vc_mem_base);
5784 +
5785 + if (copy_to_user((void *) arg, &mm_vc_mem_base,
5786 + sizeof (mm_vc_mem_base)) != 0) {
5787 + rc = -EFAULT;
5788 + }
5789 + break;
5790 + }
5791 + default:
5792 + {
5793 + return -ENOTTY;
5794 + }
5795 + }
5796 + LOG_DBG("%s: file = 0x%p returning %d", __func__, file, rc);
5797 +
5798 + return rc;
5799 +}
5800 +
5801 +/****************************************************************************
5802 +*
5803 +* vc_mem_mmap
5804 +*
5805 +***************************************************************************/
5806 +
5807 +static int
5808 +vc_mem_mmap(struct file *filp, struct vm_area_struct *vma)
5809 +{
5810 + int rc = 0;
5811 + unsigned long length = vma->vm_end - vma->vm_start;
5812 + unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
5813 +
5814 + LOG_DBG("%s: vm_start = 0x%08lx vm_end = 0x%08lx vm_pgoff = 0x%08lx",
5815 + __func__, (long) vma->vm_start, (long) vma->vm_end,
5816 + (long) vma->vm_pgoff);
5817 +
5818 + if (offset + length > mm_vc_mem_size) {
5819 + LOG_ERR("%s: length %ld is too big", __func__, length);
5820 + return -EINVAL;
5821 + }
5822 + // Do not cache the memory map
5823 + vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
5824 +
5825 + rc = remap_pfn_range(vma, vma->vm_start,
5826 + (mm_vc_mem_phys_addr >> PAGE_SHIFT) +
5827 + vma->vm_pgoff, length, vma->vm_page_prot);
5828 + if (rc != 0) {
5829 + LOG_ERR("%s: remap_pfn_range failed (rc=%d)", __func__, rc);
5830 + }
5831 +
5832 + return rc;
5833 +}
5834 +
5835 +/****************************************************************************
5836 +*
5837 +* File Operations for the driver.
5838 +*
5839 +***************************************************************************/
5840 +
5841 +static const struct file_operations vc_mem_fops = {
5842 + .owner = THIS_MODULE,
5843 + .open = vc_mem_open,
5844 + .release = vc_mem_release,
5845 + .unlocked_ioctl = vc_mem_ioctl,
5846 + .mmap = vc_mem_mmap,
5847 +};
5848 +
5849 +/****************************************************************************
5850 +*
5851 +* vc_mem_proc_read
5852 +*
5853 +***************************************************************************/
5854 +
5855 +static int
5856 +vc_mem_proc_read(char *buf, char **start, off_t offset, int count, int *eof,
5857 + void *data)
5858 +{
5859 + char *p = buf;
5860 +
5861 + (void) start;
5862 + (void) count;
5863 + (void) data;
5864 +
5865 + if (offset > 0) {
5866 + *eof = 1;
5867 + return 0;
5868 + }
5869 + // Get the videocore memory size first
5870 + vc_mem_get_size();
5871 +
5872 + p += sprintf(p, "Videocore memory:\n");
5873 + if (mm_vc_mem_phys_addr != 0)
5874 + p += sprintf(p, " Physical address: 0x%p\n",
5875 + (void *) mm_vc_mem_phys_addr);
5876 + else
5877 + p += sprintf(p, " Physical address: 0x00000000\n");
5878 + p += sprintf(p, " Length (bytes): %u\n", mm_vc_mem_size);
5879 +
5880 + *eof = 1;
5881 + return p - buf;
5882 +}
5883 +
5884 +/****************************************************************************
5885 +*
5886 +* vc_mem_proc_write
5887 +*
5888 +***************************************************************************/
5889 +
5890 +static int
5891 +vc_mem_proc_write(struct file *file, const char __user * buffer,
5892 + unsigned long count, void *data)
5893 +{
5894 + int rc = -EFAULT;
5895 + char input_str[10];
5896 +
5897 + memset(input_str, 0, sizeof (input_str));
5898 +
5899 + if (count > sizeof (input_str)) {
5900 + LOG_ERR("%s: input string length too long", __func__);
5901 + goto out;
5902 + }
5903 +
5904 + if (copy_from_user(input_str, buffer, count - 1)) {
5905 + LOG_ERR("%s: failed to get input string", __func__);
5906 + goto out;
5907 + }
5908 +
5909 + if (strncmp(input_str, "connect", strlen("connect")) == 0) {
5910 + // Get the videocore memory size from the videocore
5911 + vc_mem_get_size();
5912 + }
5913 +
5914 + out:
5915 + return rc;
5916 +}
5917 +
5918 +/****************************************************************************
5919 +*
5920 +* vc_mem_init
5921 +*
5922 +***************************************************************************/
5923 +
5924 +static int __init
5925 +vc_mem_init(void)
5926 +{
5927 + int rc = -EFAULT;
5928 + struct device *dev;
5929 +
5930 + LOG_DBG("%s: called", __func__);
5931 +
5932 + mm_vc_mem_phys_addr = phys_addr;
5933 + mm_vc_mem_size = mem_size;
5934 + mm_vc_mem_base = mem_base;
5935 +
5936 + vc_mem_get_size();
5937 +
5938 + printk("vc-mem: phys_addr:0x%08lx mem_base=0x%08x mem_size:0x%08x(%u MiB)\n",
5939 + mm_vc_mem_phys_addr, mm_vc_mem_base, mm_vc_mem_size, mm_vc_mem_size / (1024 * 1024));
5940 +
5941 + if ((rc = alloc_chrdev_region(&vc_mem_devnum, 0, 1, DRIVER_NAME)) < 0) {
5942 + LOG_ERR("%s: alloc_chrdev_region failed (rc=%d)", __func__, rc);
5943 + goto out_err;
5944 + }
5945 +
5946 + cdev_init(&vc_mem_cdev, &vc_mem_fops);
5947 + if ((rc = cdev_add(&vc_mem_cdev, vc_mem_devnum, 1)) != 0) {
5948 + LOG_ERR("%s: cdev_add failed (rc=%d)", __func__, rc);
5949 + goto out_unregister;
5950 + }
5951 +
5952 + vc_mem_class = class_create(THIS_MODULE, DRIVER_NAME);
5953 + if (IS_ERR(vc_mem_class)) {
5954 + rc = PTR_ERR(vc_mem_class);
5955 + LOG_ERR("%s: class_create failed (rc=%d)", __func__, rc);
5956 + goto out_cdev_del;
5957 + }
5958 +
5959 + dev = device_create(vc_mem_class, NULL, vc_mem_devnum, NULL,
5960 + DRIVER_NAME);
5961 + if (IS_ERR(dev)) {
5962 + rc = PTR_ERR(dev);
5963 + LOG_ERR("%s: device_create failed (rc=%d)", __func__, rc);
5964 + goto out_class_destroy;
5965 + }
5966 +
5967 +#if 0
5968 + vc_mem_proc_entry = create_proc_entry(DRIVER_NAME, 0444, NULL);
5969 + if (vc_mem_proc_entry == NULL) {
5970 + rc = -EFAULT;
5971 + LOG_ERR("%s: create_proc_entry failed", __func__);
5972 + goto out_device_destroy;
5973 + }
5974 + vc_mem_proc_entry->read_proc = vc_mem_proc_read;
5975 + vc_mem_proc_entry->write_proc = vc_mem_proc_write;
5976 +#endif
5977 +
5978 + vc_mem_inited = 1;
5979 + return 0;
5980 +
5981 + out_device_destroy:
5982 + device_destroy(vc_mem_class, vc_mem_devnum);
5983 +
5984 + out_class_destroy:
5985 + class_destroy(vc_mem_class);
5986 + vc_mem_class = NULL;
5987 +
5988 + out_cdev_del:
5989 + cdev_del(&vc_mem_cdev);
5990 +
5991 + out_unregister:
5992 + unregister_chrdev_region(vc_mem_devnum, 1);
5993 +
5994 + out_err:
5995 + return -1;
5996 +}
5997 +
5998 +/****************************************************************************
5999 +*
6000 +* vc_mem_exit
6001 +*
6002 +***************************************************************************/
6003 +
6004 +static void __exit
6005 +vc_mem_exit(void)
6006 +{
6007 + LOG_DBG("%s: called", __func__);
6008 +
6009 + if (vc_mem_inited) {
6010 +#if 0
6011 + remove_proc_entry(vc_mem_proc_entry->name, NULL);
6012 +#endif
6013 + device_destroy(vc_mem_class, vc_mem_devnum);
6014 + class_destroy(vc_mem_class);
6015 + cdev_del(&vc_mem_cdev);
6016 + unregister_chrdev_region(vc_mem_devnum, 1);
6017 + }
6018 +}
6019 +
6020 +module_init(vc_mem_init);
6021 +module_exit(vc_mem_exit);
6022 +MODULE_LICENSE("GPL");
6023 +MODULE_AUTHOR("Broadcom Corporation");
6024 +
6025 +module_param(phys_addr, uint, 0644);
6026 +module_param(mem_size, uint, 0644);
6027 +module_param(mem_base, uint, 0644);
6028 +
6029 diff --git a/arch/arm/mach-bcm2708/vcio.c b/arch/arm/mach-bcm2708/vcio.c
6030 new file mode 100644
6031 index 0000000..599eb63
6032 --- /dev/null
6033 +++ b/arch/arm/mach-bcm2708/vcio.c
6034 @@ -0,0 +1,474 @@
6035 +/*
6036 + * linux/arch/arm/mach-bcm2708/vcio.c
6037 + *
6038 + * Copyright (C) 2010 Broadcom
6039 + *
6040 + * This program is free software; you can redistribute it and/or modify
6041 + * it under the terms of the GNU General Public License version 2 as
6042 + * published by the Free Software Foundation.
6043 + *
6044 + * This device provides a shared mechanism for writing to the mailboxes,
6045 + * semaphores, doorbells etc. that are shared between the ARM and the
6046 + * VideoCore processor
6047 + */
6048 +
6049 +#if defined(CONFIG_SERIAL_BCM_MBOX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
6050 +#define SUPPORT_SYSRQ
6051 +#endif
6052 +
6053 +#include <linux/module.h>
6054 +#include <linux/console.h>
6055 +#include <linux/serial_core.h>
6056 +#include <linux/serial.h>
6057 +#include <linux/errno.h>
6058 +#include <linux/device.h>
6059 +#include <linux/init.h>
6060 +#include <linux/mm.h>
6061 +#include <linux/dma-mapping.h>
6062 +#include <linux/platform_device.h>
6063 +#include <linux/sysrq.h>
6064 +#include <linux/delay.h>
6065 +#include <linux/slab.h>
6066 +#include <linux/interrupt.h>
6067 +#include <linux/irq.h>
6068 +
6069 +#include <linux/io.h>
6070 +
6071 +#include <mach/vcio.h>
6072 +#include <mach/platform.h>
6073 +
6074 +#include <asm/uaccess.h>
6075 +
6076 +
6077 +#define DRIVER_NAME BCM_VCIO_DRIVER_NAME
6078 +
6079 +/* ----------------------------------------------------------------------
6080 + * Mailbox
6081 + * -------------------------------------------------------------------- */
6082 +
6083 +/* offsets from a mail box base address */
6084 +#define MAIL_WRT 0x00 /* write - and next 4 words */
6085 +#define MAIL_RD 0x00 /* read - and next 4 words */
6086 +#define MAIL_POL 0x10 /* read without popping the fifo */
6087 +#define MAIL_SND 0x14 /* sender ID (bottom two bits) */
6088 +#define MAIL_STA 0x18 /* status */
6089 +#define MAIL_CNF 0x1C /* configuration */
6090 +
6091 +#define MBOX_MSG(chan, data28) (((data28) & ~0xf) | ((chan) & 0xf))
6092 +#define MBOX_MSG_LSB(chan, data28) (((data28) << 4) | ((chan) & 0xf))
6093 +#define MBOX_CHAN(msg) ((msg) & 0xf)
6094 +#define MBOX_DATA28(msg) ((msg) & ~0xf)
6095 +#define MBOX_DATA28_LSB(msg) (((uint32_t)msg) >> 4)
6096 +
6097 +#define MBOX_MAGIC 0xd0d0c0de
6098 +
6099 +struct vc_mailbox {
6100 + struct device *dev; /* parent device */
6101 + void __iomem *status;
6102 + void __iomem *config;
6103 + void __iomem *read;
6104 + void __iomem *write;
6105 + uint32_t msg[MBOX_CHAN_COUNT];
6106 + struct semaphore sema[MBOX_CHAN_COUNT];
6107 + uint32_t magic;
6108 +};
6109 +
6110 +static void mbox_init(struct vc_mailbox *mbox_out, struct device *dev,
6111 + uint32_t addr_mbox)
6112 +{
6113 + int i;
6114 +
6115 + mbox_out->dev = dev;
6116 + mbox_out->status = __io_address(addr_mbox + MAIL_STA);
6117 + mbox_out->config = __io_address(addr_mbox + MAIL_CNF);
6118 + mbox_out->read = __io_address(addr_mbox + MAIL_RD);
6119 + /* Write to the other mailbox */
6120 + mbox_out->write =
6121 + __io_address((addr_mbox ^ ARM_0_MAIL0_WRT ^ ARM_0_MAIL1_WRT) +
6122 + MAIL_WRT);
6123 +
6124 + for (i = 0; i < MBOX_CHAN_COUNT; i++) {
6125 + mbox_out->msg[i] = 0;
6126 + sema_init(&mbox_out->sema[i], 0);
6127 + }
6128 +
6129 + /* Enable the interrupt on data reception */
6130 + writel(ARM_MC_IHAVEDATAIRQEN, mbox_out->config);
6131 +
6132 + mbox_out->magic = MBOX_MAGIC;
6133 +}
6134 +
6135 +static int mbox_write(struct vc_mailbox *mbox, unsigned chan, uint32_t data28)
6136 +{
6137 + int rc;
6138 +
6139 + if (mbox->magic != MBOX_MAGIC)
6140 + rc = -EINVAL;
6141 + else {
6142 + /* wait for the mailbox FIFO to have some space in it */
6143 + while (0 != (readl(mbox->status) & ARM_MS_FULL))
6144 + cpu_relax();
6145 +
6146 + writel(MBOX_MSG(chan, data28), mbox->write);
6147 + rc = 0;
6148 + }
6149 + return rc;
6150 +}
6151 +
6152 +static int mbox_read(struct vc_mailbox *mbox, unsigned chan, uint32_t *data28)
6153 +{
6154 + int rc;
6155 +
6156 + if (mbox->magic != MBOX_MAGIC)
6157 + rc = -EINVAL;
6158 + else {
6159 + down(&mbox->sema[chan]);
6160 + *data28 = MBOX_DATA28(mbox->msg[chan]);
6161 + mbox->msg[chan] = 0;
6162 + rc = 0;
6163 + }
6164 + return rc;
6165 +}
6166 +
6167 +static irqreturn_t mbox_irq(int irq, void *dev_id)
6168 +{
6169 + /* wait for the mailbox FIFO to have some data in it */
6170 + struct vc_mailbox *mbox = (struct vc_mailbox *) dev_id;
6171 + int status = readl(mbox->status);
6172 + int ret = IRQ_NONE;
6173 +
6174 + while (!(status & ARM_MS_EMPTY)) {
6175 + uint32_t msg = readl(mbox->read);
6176 + int chan = MBOX_CHAN(msg);
6177 + if (chan < MBOX_CHAN_COUNT) {
6178 + if (mbox->msg[chan]) {
6179 + /* Overflow */
6180 + printk(KERN_ERR DRIVER_NAME
6181 + ": mbox chan %d overflow - drop %08x\n",
6182 + chan, msg);
6183 + } else {
6184 + mbox->msg[chan] = (msg | 0xf);
6185 + up(&mbox->sema[chan]);
6186 + }
6187 + } else {
6188 + printk(KERN_ERR DRIVER_NAME
6189 + ": invalid channel selector (msg %08x)\n", msg);
6190 + }
6191 + ret = IRQ_HANDLED;
6192 + status = readl(mbox->status);
6193 + }
6194 + return ret;
6195 +}
6196 +
6197 +static struct irqaction mbox_irqaction = {
6198 + .name = "ARM Mailbox IRQ",
6199 + .flags = IRQF_DISABLED | IRQF_IRQPOLL,
6200 + .handler = mbox_irq,
6201 +};
6202 +
6203 +/* ----------------------------------------------------------------------
6204 + * Mailbox Methods
6205 + * -------------------------------------------------------------------- */
6206 +
6207 +static struct device *mbox_dev; /* we assume there's only one! */
6208 +
6209 +static int dev_mbox_write(struct device *dev, unsigned chan, uint32_t data28)
6210 +{
6211 + int rc;
6212 +
6213 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6214 + device_lock(dev);
6215 + rc = mbox_write(mailbox, chan, data28);
6216 + device_unlock(dev);
6217 +
6218 + return rc;
6219 +}
6220 +
6221 +static int dev_mbox_read(struct device *dev, unsigned chan, uint32_t *data28)
6222 +{
6223 + int rc;
6224 +
6225 + struct vc_mailbox *mailbox = dev_get_drvdata(dev);
6226 + device_lock(dev);
6227 + rc = mbox_read(mailbox, chan, data28);
6228 + device_unlock(dev);
6229 +
6230 + return rc;
6231 +}
6232 +
6233 +extern int bcm_mailbox_write(unsigned chan, uint32_t data28)
6234 +{
6235 + if (mbox_dev)
6236 + return dev_mbox_write(mbox_dev, chan, data28);
6237 + else
6238 + return -ENODEV;
6239 +}
6240 +EXPORT_SYMBOL_GPL(bcm_mailbox_write);
6241 +
6242 +extern int bcm_mailbox_read(unsigned chan, uint32_t *data28)
6243 +{
6244 + if (mbox_dev)
6245 + return dev_mbox_read(mbox_dev, chan, data28);
6246 + else
6247 + return -ENODEV;
6248 +}
6249 +EXPORT_SYMBOL_GPL(bcm_mailbox_read);
6250 +
6251 +static void dev_mbox_register(const char *dev_name, struct device *dev)
6252 +{
6253 + mbox_dev = dev;
6254 +}
6255 +
6256 +static int mbox_copy_from_user(void *dst, const void *src, int size)
6257 +{
6258 + if ( (uint32_t)src < TASK_SIZE)
6259 + {
6260 + return copy_from_user(dst, src, size);
6261 + }
6262 + else
6263 + {
6264 + memcpy( dst, src, size );
6265 + return 0;
6266 + }
6267 +}
6268 +
6269 +static int mbox_copy_to_user(void *dst, const void *src, int size)
6270 +{
6271 + if ( (uint32_t)dst < TASK_SIZE)
6272 + {
6273 + return copy_to_user(dst, src, size);
6274 + }
6275 + else
6276 + {
6277 + memcpy( dst, src, size );
6278 + return 0;
6279 + }
6280 +}
6281 +
6282 +static DEFINE_MUTEX(mailbox_lock);
6283 +extern int bcm_mailbox_property(void *data, int size)
6284 +{
6285 + uint32_t success;
6286 + dma_addr_t mem_bus; /* the memory address accessed from videocore */
6287 + void *mem_kern; /* the memory address accessed from driver */
6288 + int s = 0;
6289 +
6290 + mutex_lock(&mailbox_lock);
6291 + /* allocate some memory for the messages communicating with GPU */
6292 + mem_kern = dma_alloc_coherent(NULL, PAGE_ALIGN(size), &mem_bus, GFP_ATOMIC);
6293 + if (mem_kern) {
6294 + /* create the message */
6295 + mbox_copy_from_user(mem_kern, data, size);
6296 +
6297 + /* send the message */
6298 + wmb();
6299 + s = bcm_mailbox_write(MBOX_CHAN_PROPERTY, (uint32_t)mem_bus);
6300 + if (s == 0) {
6301 + s = bcm_mailbox_read(MBOX_CHAN_PROPERTY, &success);
6302 + }
6303 + if (s == 0) {
6304 + /* copy the response */
6305 + rmb();
6306 + mbox_copy_to_user(data, mem_kern, size);
6307 + }
6308 + dma_free_coherent(NULL, PAGE_ALIGN(size), mem_kern, mem_bus);
6309 + } else {
6310 + s = -ENOMEM;
6311 + }
6312 + if (s != 0)
6313 + printk(KERN_ERR DRIVER_NAME ": %s failed (%d)\n", __func__, s);
6314 +
6315 + mutex_unlock(&mailbox_lock);
6316 + return s;
6317 +}
6318 +EXPORT_SYMBOL_GPL(bcm_mailbox_property);
6319 +
6320 +/* ----------------------------------------------------------------------
6321 + * Platform Device for Mailbox
6322 + * -------------------------------------------------------------------- */
6323 +
6324 +/*
6325 + * Is the device open right now? Used to prevent
6326 + * concurent access into the same device
6327 + */
6328 +static int Device_Open = 0;
6329 +
6330 +/*
6331 + * This is called whenever a process attempts to open the device file
6332 + */
6333 +static int device_open(struct inode *inode, struct file *file)
6334 +{
6335 + /*
6336 + * We don't want to talk to two processes at the same time
6337 + */
6338 + if (Device_Open)
6339 + return -EBUSY;
6340 +
6341 + Device_Open++;
6342 + /*
6343 + * Initialize the message
6344 + */
6345 + try_module_get(THIS_MODULE);
6346 + return 0;
6347 +}
6348 +
6349 +static int device_release(struct inode *inode, struct file *file)
6350 +{
6351 + /*
6352 + * We're now ready for our next caller
6353 + */
6354 + Device_Open--;
6355 +
6356 + module_put(THIS_MODULE);
6357 + return 0;
6358 +}
6359 +
6360 +/*
6361 + * This function is called whenever a process tries to do an ioctl on our
6362 + * device file. We get two extra parameters (additional to the inode and file
6363 + * structures, which all device functions get): the number of the ioctl called
6364 + * and the parameter given to the ioctl function.
6365 + *
6366 + * If the ioctl is write or read/write (meaning output is returned to the
6367 + * calling process), the ioctl call returns the output of this function.
6368 + *
6369 + */
6370 +static long device_ioctl(struct file *file, /* see include/linux/fs.h */
6371 + unsigned int ioctl_num, /* number and param for ioctl */
6372 + unsigned long ioctl_param)
6373 +{
6374 + unsigned size;
6375 + /*
6376 + * Switch according to the ioctl called
6377 + */
6378 + switch (ioctl_num) {
6379 + case IOCTL_MBOX_PROPERTY:
6380 + /*
6381 + * Receive a pointer to a message (in user space) and set that
6382 + * to be the device's message. Get the parameter given to
6383 + * ioctl by the process.
6384 + */
6385 + mbox_copy_from_user(&size, (void *)ioctl_param, sizeof size);
6386 + return bcm_mailbox_property((void *)ioctl_param, size);
6387 + break;
6388 + default:
6389 + printk(KERN_ERR DRIVER_NAME "unknown ioctl: %d\n", ioctl_num);
6390 + return -EINVAL;
6391 + }
6392 +
6393 + return 0;
6394 +}
6395 +
6396 +/* Module Declarations */
6397 +
6398 +/*
6399 + * This structure will hold the functions to be called
6400 + * when a process does something to the device we
6401 + * created. Since a pointer to this structure is kept in
6402 + * the devices table, it can't be local to
6403 + * init_module. NULL is for unimplemented functios.
6404 + */
6405 +struct file_operations fops = {
6406 + .unlocked_ioctl = device_ioctl,
6407 + .open = device_open,
6408 + .release = device_release, /* a.k.a. close */
6409 +};
6410 +
6411 +static int bcm_vcio_probe(struct platform_device *pdev)
6412 +{
6413 + int ret = 0;
6414 + struct vc_mailbox *mailbox;
6415 +
6416 + mailbox = kzalloc(sizeof(*mailbox), GFP_KERNEL);
6417 + if (NULL == mailbox) {
6418 + printk(KERN_ERR DRIVER_NAME ": failed to allocate "
6419 + "mailbox memory\n");
6420 + ret = -ENOMEM;
6421 + } else {
6422 + struct resource *res;
6423 +
6424 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6425 + if (res == NULL) {
6426 + printk(KERN_ERR DRIVER_NAME ": failed to obtain memory "
6427 + "resource\n");
6428 + ret = -ENODEV;
6429 + kfree(mailbox);
6430 + } else {
6431 + /* should be based on the registers from res really */
6432 + mbox_init(mailbox, &pdev->dev, ARM_0_MAIL0_RD);
6433 +
6434 + platform_set_drvdata(pdev, mailbox);
6435 + dev_mbox_register(DRIVER_NAME, &pdev->dev);
6436 +
6437 + mbox_irqaction.dev_id = mailbox;
6438 + setup_irq(IRQ_ARM_MAILBOX, &mbox_irqaction);
6439 + printk(KERN_INFO DRIVER_NAME ": mailbox at %p\n",
6440 + __io_address(ARM_0_MAIL0_RD));
6441 + }
6442 + }
6443 +
6444 + if (ret == 0) {
6445 + /*
6446 + * Register the character device
6447 + */
6448 + ret = register_chrdev(MAJOR_NUM, DEVICE_FILE_NAME, &fops);
6449 +
6450 + /*
6451 + * Negative values signify an error
6452 + */
6453 + if (ret < 0) {
6454 + printk(KERN_ERR DRIVER_NAME
6455 + "Failed registering the character device %d\n", ret);
6456 + return ret;
6457 + }
6458 + }
6459 + return ret;
6460 +}
6461 +
6462 +static int bcm_vcio_remove(struct platform_device *pdev)
6463 +{
6464 + struct vc_mailbox *mailbox = platform_get_drvdata(pdev);
6465 +
6466 + platform_set_drvdata(pdev, NULL);
6467 + kfree(mailbox);
6468 +
6469 + return 0;
6470 +}
6471 +
6472 +static struct platform_driver bcm_mbox_driver = {
6473 + .probe = bcm_vcio_probe,
6474 + .remove = bcm_vcio_remove,
6475 +
6476 + .driver = {
6477 + .name = DRIVER_NAME,
6478 + .owner = THIS_MODULE,
6479 + },
6480 +};
6481 +
6482 +static int __init bcm_mbox_init(void)
6483 +{
6484 + int ret;
6485 +
6486 + printk(KERN_INFO "mailbox: Broadcom VideoCore Mailbox driver\n");
6487 +
6488 + ret = platform_driver_register(&bcm_mbox_driver);
6489 + if (ret != 0) {
6490 + printk(KERN_ERR DRIVER_NAME ": failed to register "
6491 + "on platform\n");
6492 + }
6493 +
6494 + return ret;
6495 +}
6496 +
6497 +static void __exit bcm_mbox_exit(void)
6498 +{
6499 + platform_driver_unregister(&bcm_mbox_driver);
6500 +}
6501 +
6502 +arch_initcall(bcm_mbox_init); /* Initialize early */
6503 +module_exit(bcm_mbox_exit);
6504 +
6505 +MODULE_AUTHOR("Gray Girling");
6506 +MODULE_DESCRIPTION("ARM I/O to VideoCore processor");
6507 +MODULE_LICENSE("GPL");
6508 +MODULE_ALIAS("platform:bcm-mbox");
6509 diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
6510 index c21082d..6ae2668 100644
6511 --- a/arch/arm/mm/Kconfig
6512 +++ b/arch/arm/mm/Kconfig
6513 @@ -358,7 +358,7 @@ config CPU_PJ4B
6514
6515 # ARMv6
6516 config CPU_V6
6517 - bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
6518 + bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX || MACH_BCM2708
6519 select CPU_32v6
6520 select CPU_ABRT_EV6
6521 select CPU_CACHE_V6
6522 diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
6523 index d073528..223fc69 100644
6524 --- a/arch/arm/mm/proc-v6.S
6525 +++ b/arch/arm/mm/proc-v6.S
6526 @@ -73,10 +73,19 @@ ENDPROC(cpu_v6_reset)
6527 *
6528 * IRQs are already disabled.
6529 */
6530 +
6531 +/* See jira SW-5991 for details of this workaround */
6532 ENTRY(cpu_v6_do_idle)
6533 - mov r1, #0
6534 - mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6535 - mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt
6536 + .align 5
6537 + mov r1, #2
6538 +1: subs r1, #1
6539 + nop
6540 + mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
6541 + mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
6542 + nop
6543 + nop
6544 + nop
6545 + bne 1b
6546 mov pc, lr
6547
6548 ENTRY(cpu_v6_dcache_clean_area)
6549 diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
6550 index a10297d..c9ddd87 100644
6551 --- a/arch/arm/tools/mach-types
6552 +++ b/arch/arm/tools/mach-types
6553 @@ -522,6 +522,7 @@ torbreck MACH_TORBRECK TORBRECK 3090
6554 prima2_evb MACH_PRIMA2_EVB PRIMA2_EVB 3103
6555 paz00 MACH_PAZ00 PAZ00 3128
6556 acmenetusfoxg20 MACH_ACMENETUSFOXG20 ACMENETUSFOXG20 3129
6557 +bcm2708 MACH_BCM2708 BCM2708 3138
6558 ag5evm MACH_AG5EVM AG5EVM 3189
6559 ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
6560 wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
6561 diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
6562 index 9ab8f8d..74e7543 100644
6563 --- a/drivers/mmc/host/Kconfig
6564 +++ b/drivers/mmc/host/Kconfig
6565 @@ -249,6 +249,27 @@ config MMC_SDHCI_S3C_DMA
6566
6567 YMMV.
6568
6569 +config MMC_SDHCI_BCM2708
6570 + tristate "SDHCI support on BCM2708"
6571 + depends on MMC_SDHCI && MACH_BCM2708
6572 + select MMC_SDHCI_IO_ACCESSORS
6573 + help
6574 + This selects the Secure Digital Host Controller Interface (SDHCI)
6575 + often referrered to as the eMMC block.
6576 +
6577 + If you have a controller with this interface, say Y or M here.
6578 +
6579 + If unsure, say N.
6580 +
6581 +config MMC_SDHCI_BCM2708_DMA
6582 + bool "DMA support on BCM2708 Arasan controller"
6583 + depends on MMC_SDHCI_BCM2708
6584 + help
6585 + Enable DMA support on the Arasan SDHCI controller in Broadcom 2708
6586 + based chips.
6587 +
6588 + If unsure, say N.
6589 +
6590 config MMC_SDHCI_BCM2835
6591 tristate "SDHCI platform support for the BCM2835 SD/MMC Controller"
6592 depends on ARCH_BCM2835
6593 diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
6594 index cd32280..6a7b985 100644
6595 --- a/drivers/mmc/host/Makefile
6596 +++ b/drivers/mmc/host/Makefile
6597 @@ -15,6 +15,7 @@ obj-$(CONFIG_MMC_SDHCI_PXAV2) += sdhci-pxav2.o
6598 obj-$(CONFIG_MMC_SDHCI_S3C) += sdhci-s3c.o
6599 obj-$(CONFIG_MMC_SDHCI_SIRF) += sdhci-sirf.o
6600 obj-$(CONFIG_MMC_SDHCI_SPEAR) += sdhci-spear.o
6601 +obj-$(CONFIG_MMC_SDHCI_BCM2708) += sdhci-bcm2708.o
6602 obj-$(CONFIG_MMC_WBSD) += wbsd.o
6603 obj-$(CONFIG_MMC_AU1X) += au1xmmc.o
6604 obj-$(CONFIG_MMC_OMAP) += omap.o
6605 diff --git a/drivers/mmc/host/sdhci-bcm2708.c b/drivers/mmc/host/sdhci-bcm2708.c
6606 new file mode 100644
6607 index 0000000..e79723d
6608 --- /dev/null
6609 +++ b/drivers/mmc/host/sdhci-bcm2708.c
6610 @@ -0,0 +1,1425 @@
6611 +/*
6612 + * sdhci-bcm2708.c Support for SDHCI device on BCM2708
6613 + * Copyright (c) 2010 Broadcom
6614 + *
6615 + * This program is free software; you can redistribute it and/or modify
6616 + * it under the terms of the GNU General Public License version 2 as
6617 + * published by the Free Software Foundation.
6618 + *
6619 + * This program is distributed in the hope that it will be useful,
6620 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
6621 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6622 + * GNU General Public License for more details.
6623 + *
6624 + * You should have received a copy of the GNU General Public License
6625 + * along with this program; if not, write to the Free Software
6626 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
6627 + */
6628 +
6629 +/* Supports:
6630 + * SDHCI platform device - Arasan SD controller in BCM2708
6631 + *
6632 + * Inspired by sdhci-pci.c, by Pierre Ossman
6633 + */
6634 +
6635 +#include <linux/delay.h>
6636 +#include <linux/highmem.h>
6637 +#include <linux/platform_device.h>
6638 +#include <linux/module.h>
6639 +#include <linux/mmc/mmc.h>
6640 +#include <linux/mmc/host.h>
6641 +#include <linux/mmc/sd.h>
6642 +
6643 +#include <linux/io.h>
6644 +#include <linux/dma-mapping.h>
6645 +#include <mach/dma.h>
6646 +
6647 +#include "sdhci.h"
6648 +
6649 +/*****************************************************************************\
6650 + * *
6651 + * Configuration *
6652 + * *
6653 +\*****************************************************************************/
6654 +
6655 +#define DRIVER_NAME "bcm2708_sdhci"
6656 +
6657 +/* for the time being insist on DMA mode - PIO seems not to work */
6658 +#ifndef CONFIG_MMC_SDHCI_BCM2708_DMA
6659 +#warning Non-DMA (PIO) version of this driver currently unavailable
6660 +#endif
6661 +#undef CONFIG_MMC_SDHCI_BCM2708_DMA
6662 +#define CONFIG_MMC_SDHCI_BCM2708_DMA y
6663 +
6664 +#define USE_SYNC_AFTER_DMA
6665 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
6666 +/* #define CHECK_DMA_USE */
6667 +#endif
6668 +//#define LOG_REGISTERS
6669 +
6670 +#define USE_SCHED_TIME
6671 +#define USE_SPACED_WRITES_2CLK 1 /* space consecutive register writes */
6672 +#define USE_SOFTWARE_TIMEOUTS 1 /* not hardware timeouts */
6673 +#define SOFTWARE_ERASE_TIMEOUT_SEC 30
6674 +
6675 +#define SDHCI_BCM_DMA_CHAN 4 /* this default is normally overriden */
6676 +#define SDHCI_BCM_DMA_WAITS 0 /* delays slowing DMA transfers: 0-31 */
6677 +/* We are worried that SD card DMA use may be blocking the AXI bus for others */
6678 +
6679 +/*! TODO: obtain these from the physical address */
6680 +#define DMA_SDHCI_BASE 0x7e300000 /* EMMC register block on Videocore */
6681 +#define DMA_SDHCI_BUFFER (DMA_SDHCI_BASE + SDHCI_BUFFER)
6682 +
6683 +#define BCM2708_SDHCI_SLEEP_TIMEOUT 1000 /* msecs */
6684 +
6685 +/* Mhz clock that the EMMC core is running at. Should match the platform clockman settings */
6686 +#define BCM2708_EMMC_CLOCK_FREQ 80000000
6687 +
6688 +/*****************************************************************************\
6689 + * *
6690 + * Debug *
6691 + * *
6692 +\*****************************************************************************/
6693 +
6694 +
6695 +
6696 +#define DBG(f, x...) \
6697 + pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
6698 +// printk(KERN_INFO DRIVER_NAME " [%s()]: " f, __func__,## x)//GRAYG
6699 +
6700 +
6701 +/*****************************************************************************\
6702 + * *
6703 + * High Precision Time *
6704 + * *
6705 +\*****************************************************************************/
6706 +
6707 +#ifdef USE_SCHED_TIME
6708 +
6709 +#include <mach/frc.h>
6710 +
6711 +typedef unsigned long hptime_t;
6712 +
6713 +#define FMT_HPT "lu"
6714 +
6715 +static inline hptime_t hptime(void)
6716 +{
6717 + return frc_clock_ticks32();
6718 +}
6719 +
6720 +#define HPTIME_CLK_NS 1000ul
6721 +
6722 +#else
6723 +
6724 +typedef unsigned long hptime_t;
6725 +
6726 +#define FMT_HPT "lu"
6727 +
6728 +static inline hptime_t hptime(void)
6729 +{
6730 + return jiffies;
6731 +}
6732 +
6733 +#define HPTIME_CLK_NS (1000000000ul/HZ)
6734 +
6735 +#endif
6736 +
6737 +static inline unsigned long int since_ns(hptime_t t)
6738 +{
6739 + return (unsigned long)((hptime() - t) * HPTIME_CLK_NS);
6740 +}
6741 +
6742 +#if 0
6743 +static void hptime_test(void)
6744 +{
6745 + hptime_t now;
6746 + hptime_t later;
6747 +
6748 + now = hptime();
6749 + msleep(10);
6750 + later = hptime();
6751 +
6752 + printk(KERN_INFO DRIVER_NAME": 10ms = %"FMT_HPT" clks "
6753 + "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6754 + later-now, now, later,
6755 + (unsigned long)(HPTIME_CLK_NS * (later - now)));
6756 +
6757 + now = hptime();
6758 + msleep(1000);
6759 + later = hptime();
6760 +
6761 + printk(KERN_INFO DRIVER_NAME": 1s = %"FMT_HPT" clks "
6762 + "(from %"FMT_HPT" to %"FMT_HPT") = %luns\n",
6763 + later-now, now, later,
6764 + (unsigned long)(HPTIME_CLK_NS * (later - now)));
6765 +}
6766 +#endif
6767 +
6768 +/*****************************************************************************\
6769 + * *
6770 + * SDHCI core callbacks *
6771 + * *
6772 +\*****************************************************************************/
6773 +
6774 +
6775 +#ifdef CHECK_DMA_USE
6776 +/*#define CHECK_DMA_REG_USE*/
6777 +#endif
6778 +
6779 +#ifdef CHECK_DMA_REG_USE
6780 +/* we don't expect anything to be using these registers during a
6781 + DMA (except the IRQ status) - so check */
6782 +static void check_dma_reg_use(struct sdhci_host *host, int reg);
6783 +#else
6784 +#define check_dma_reg_use(host, reg)
6785 +#endif
6786 +
6787 +
6788 +static inline u32 sdhci_bcm2708_raw_readl(struct sdhci_host *host, int reg)
6789 +{
6790 + return readl(host->ioaddr + reg);
6791 +}
6792 +
6793 +u32 sdhci_bcm2708_readl(struct sdhci_host *host, int reg)
6794 +{
6795 + u32 l = sdhci_bcm2708_raw_readl(host, reg);
6796 +
6797 +#ifdef LOG_REGISTERS
6798 + printk(KERN_ERR "%s: readl from 0x%02x, value 0x%08x\n",
6799 + mmc_hostname(host->mmc), reg, l);
6800 +#endif
6801 + check_dma_reg_use(host, reg);
6802 +
6803 + return l;
6804 +}
6805 +
6806 +u16 sdhci_bcm2708_readw(struct sdhci_host *host, int reg)
6807 +{
6808 + u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6809 + u32 w = l >> (reg << 3 & 0x18) & 0xffff;
6810 +
6811 +#ifdef LOG_REGISTERS
6812 + printk(KERN_ERR "%s: readw from 0x%02x, value 0x%04x\n",
6813 + mmc_hostname(host->mmc), reg, w);
6814 +#endif
6815 + check_dma_reg_use(host, reg);
6816 +
6817 + return (u16)w;
6818 +}
6819 +
6820 +u8 sdhci_bcm2708_readb(struct sdhci_host *host, int reg)
6821 +{
6822 + u32 l = sdhci_bcm2708_raw_readl(host, reg & ~3);
6823 + u32 b = l >> (reg << 3 & 0x18) & 0xff;
6824 +
6825 +#ifdef LOG_REGISTERS
6826 + printk(KERN_ERR "%s: readb from 0x%02x, value 0x%02x\n",
6827 + mmc_hostname(host->mmc), reg, b);
6828 +#endif
6829 + check_dma_reg_use(host, reg);
6830 +
6831 + return (u8)b;
6832 +}
6833 +
6834 +
6835 +static void sdhci_bcm2708_raw_writel(struct sdhci_host *host, u32 val, int reg)
6836 +{
6837 + u32 ier;
6838 +
6839 +#if USE_SPACED_WRITES_2CLK
6840 + static bool timeout_disabled = false;
6841 + unsigned int ns_2clk = 0;
6842 +
6843 + /* The Arasan has a bugette whereby it may lose the content of
6844 + * successive writes to registers that are within two SD-card clock
6845 + * cycles of each other (a clock domain crossing problem).
6846 + * It seems, however, that the data register does not have this problem.
6847 + * (Which is just as well - otherwise we'd have to nobble the DMA engine
6848 + * too)
6849 + */
6850 + if (reg != SDHCI_BUFFER && host->clock != 0) {
6851 + /* host->clock is the clock freq in Hz */
6852 + static hptime_t last_write_hpt;
6853 + hptime_t now = hptime();
6854 + ns_2clk = 2000000000/host->clock;
6855 +
6856 + if (now == last_write_hpt || now == last_write_hpt+1) {
6857 + /* we can't guarantee any significant time has
6858 + * passed - we'll have to wait anyway ! */
6859 + udelay((ns_2clk+1000-1)/1000);
6860 + } else
6861 + {
6862 + /* we must have waited at least this many ns: */
6863 + unsigned int ns_wait = HPTIME_CLK_NS *
6864 + (last_write_hpt - now - 1);
6865 + if (ns_wait < ns_2clk)
6866 + udelay((ns_2clk-ns_wait+500)/1000);
6867 + }
6868 + last_write_hpt = now;
6869 + }
6870 +#if USE_SOFTWARE_TIMEOUTS
6871 + /* The Arasan is clocked for timeouts using the SD clock which is too
6872 + * fast for ERASE commands and causes issues. So we disable timeouts
6873 + * for ERASE */
6874 + if (host->cmd != NULL && host->cmd->opcode == MMC_ERASE &&
6875 + reg == (SDHCI_COMMAND & ~3)) {
6876 + mod_timer(&host->timer,
6877 + jiffies + SOFTWARE_ERASE_TIMEOUT_SEC * HZ);
6878 + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6879 + ier &= ~SDHCI_INT_DATA_TIMEOUT;
6880 + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6881 + timeout_disabled = true;
6882 + udelay((ns_2clk+1000-1)/1000);
6883 + } else if (timeout_disabled) {
6884 + ier = readl(host->ioaddr + SDHCI_SIGNAL_ENABLE);
6885 + ier |= SDHCI_INT_DATA_TIMEOUT;
6886 + writel(ier, host->ioaddr + SDHCI_SIGNAL_ENABLE);
6887 + timeout_disabled = false;
6888 + udelay((ns_2clk+1000-1)/1000);
6889 + }
6890 +#endif
6891 + writel(val, host->ioaddr + reg);
6892 +#else
6893 + void __iomem * regaddr = host->ioaddr + reg;
6894 +
6895 + writel(val, regaddr);
6896 +
6897 + if (reg != SDHCI_BUFFER && reg != SDHCI_INT_STATUS && host->clock != 0)
6898 + {
6899 + int timeout = 100000;
6900 + while (val != readl(regaddr) && --timeout > 0)
6901 + continue;
6902 +
6903 + if (timeout <= 0)
6904 + printk(KERN_ERR "%s: writing 0x%X to reg 0x%X "
6905 + "always gives 0x%X\n",
6906 + mmc_hostname(host->mmc),
6907 + val, reg, readl(regaddr));
6908 + BUG_ON(timeout <= 0);
6909 + }
6910 +#endif
6911 +}
6912 +
6913 +
6914 +void sdhci_bcm2708_writel(struct sdhci_host *host, u32 val, int reg)
6915 +{
6916 +#ifdef LOG_REGISTERS
6917 + printk(KERN_ERR "%s: writel to 0x%02x, value 0x%08x\n",
6918 + mmc_hostname(host->mmc), reg, val);
6919 +#endif
6920 + check_dma_reg_use(host, reg);
6921 +
6922 + sdhci_bcm2708_raw_writel(host, val, reg);
6923 +}
6924 +
6925 +void sdhci_bcm2708_writew(struct sdhci_host *host, u16 val, int reg)
6926 +{
6927 + static u32 shadow = 0;
6928 +
6929 + u32 p = reg == SDHCI_COMMAND ? shadow :
6930 + sdhci_bcm2708_raw_readl(host, reg & ~3);
6931 + u32 s = reg << 3 & 0x18;
6932 + u32 l = val << s;
6933 + u32 m = 0xffff << s;
6934 +
6935 +#ifdef LOG_REGISTERS
6936 + printk(KERN_ERR "%s: writew to 0x%02x, value 0x%04x\n",
6937 + mmc_hostname(host->mmc), reg, val);
6938 +#endif
6939 +
6940 + if (reg == SDHCI_TRANSFER_MODE)
6941 + shadow = (p & ~m) | l;
6942 + else {
6943 + check_dma_reg_use(host, reg);
6944 + sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6945 + }
6946 +}
6947 +
6948 +void sdhci_bcm2708_writeb(struct sdhci_host *host, u8 val, int reg)
6949 +{
6950 + u32 p = sdhci_bcm2708_raw_readl(host, reg & ~3);
6951 + u32 s = reg << 3 & 0x18;
6952 + u32 l = val << s;
6953 + u32 m = 0xff << s;
6954 +
6955 +#ifdef LOG_REGISTERS
6956 + printk(KERN_ERR "%s: writeb to 0x%02x, value 0x%02x\n",
6957 + mmc_hostname(host->mmc), reg, val);
6958 +#endif
6959 +
6960 + check_dma_reg_use(host, reg);
6961 + sdhci_bcm2708_raw_writel(host, (p & ~m) | l, reg & ~3);
6962 +}
6963 +
6964 +static unsigned int sdhci_bcm2708_get_max_clock(struct sdhci_host *host)
6965 +{
6966 + return 20000000; // this value is in Hz (20MHz)
6967 +}
6968 +
6969 +static unsigned int sdhci_bcm2708_get_timeout_clock(struct sdhci_host *host)
6970 +{
6971 + if(host->clock)
6972 + return (host->clock / 1000); // this value is in kHz (100MHz)
6973 + else
6974 + return (sdhci_bcm2708_get_max_clock(host) / 1000);
6975 +}
6976 +
6977 +static void sdhci_bcm2708_set_clock(struct sdhci_host *host, unsigned int clock)
6978 +{
6979 + int div = 0;
6980 + u16 clk = 0;
6981 + unsigned long timeout;
6982 +
6983 + if (clock == host->clock)
6984 + return;
6985 +
6986 + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
6987 +
6988 + if (clock == 0)
6989 + goto out;
6990 +
6991 + if (BCM2708_EMMC_CLOCK_FREQ <= clock)
6992 + div = 1;
6993 + else {
6994 + for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
6995 + if ((BCM2708_EMMC_CLOCK_FREQ / div) <= clock)
6996 + break;
6997 + }
6998 + }
6999 +
7000 + DBG( "desired SD clock: %d, actual: %d\n",
7001 + clock, BCM2708_EMMC_CLOCK_FREQ / div);
7002 +
7003 + clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
7004 + clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
7005 + << SDHCI_DIVIDER_HI_SHIFT;
7006 + clk |= SDHCI_CLOCK_INT_EN;
7007 +
7008 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
7009 +
7010 + timeout = 20;
7011 + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
7012 + & SDHCI_CLOCK_INT_STABLE)) {
7013 + if (timeout == 0) {
7014 + printk(KERN_ERR "%s: Internal clock never "
7015 + "stabilised.\n", mmc_hostname(host->mmc));
7016 + return;
7017 + }
7018 + timeout--;
7019 + mdelay(1);
7020 + }
7021 +
7022 + clk |= SDHCI_CLOCK_CARD_EN;
7023 + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
7024 +out:
7025 + host->clock = clock;
7026 + }
7027 +
7028 +/*****************************************************************************\
7029 + * *
7030 + * DMA Operation *
7031 + * *
7032 +\*****************************************************************************/
7033 +
7034 +struct sdhci_bcm2708_priv {
7035 + int dma_chan;
7036 + int dma_irq;
7037 + void __iomem *dma_chan_base;
7038 + struct bcm2708_dma_cb *cb_base; /* DMA control blocks */
7039 + dma_addr_t cb_handle;
7040 + /* tracking scatter gather progress */
7041 + unsigned sg_ix; /* scatter gather list index */
7042 + unsigned sg_done; /* bytes in current sg_ix done */
7043 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7044 + unsigned char dma_wanted; /* DMA transfer requested */
7045 + unsigned char dma_waits; /* wait states in DMAs */
7046 +#ifdef CHECK_DMA_USE
7047 + unsigned char dmas_pending; /* no of unfinished DMAs */
7048 + hptime_t when_started;
7049 + hptime_t when_reset;
7050 + hptime_t when_stopped;
7051 +#endif
7052 +#endif
7053 + /* signalling the end of a transfer */
7054 + void (*complete)(struct sdhci_host *);
7055 +};
7056 +
7057 +#define SDHCI_HOST_PRIV(host) \
7058 + (struct sdhci_bcm2708_priv *)((struct sdhci_host *)(host)+1)
7059 +
7060 +
7061 +
7062 +#ifdef CHECK_DMA_REG_USE
7063 +static void check_dma_reg_use(struct sdhci_host *host, int reg)
7064 +{
7065 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7066 + if (host_priv->dma_wanted && reg != SDHCI_INT_STATUS) {
7067 + printk(KERN_INFO"%s: accessing register 0x%x during DMA\n",
7068 + mmc_hostname(host->mmc), reg);
7069 + }
7070 +}
7071 +#endif
7072 +
7073 +
7074 +
7075 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7076 +
7077 +static void sdhci_clear_set_irqgen(struct sdhci_host *host, u32 clear, u32 set)
7078 +{
7079 + u32 ier;
7080 +
7081 + ier = sdhci_bcm2708_raw_readl(host, SDHCI_SIGNAL_ENABLE);
7082 + ier &= ~clear;
7083 + ier |= set;
7084 + /* change which requests generate IRQs - makes no difference to
7085 + the content of SDHCI_INT_STATUS, or the need to acknowledge IRQs */
7086 + sdhci_bcm2708_raw_writel(host, ier, SDHCI_SIGNAL_ENABLE);
7087 +}
7088 +
7089 +static void sdhci_signal_irqs(struct sdhci_host *host, u32 irqs)
7090 +{
7091 + sdhci_clear_set_irqgen(host, 0, irqs);
7092 +}
7093 +
7094 +static void sdhci_unsignal_irqs(struct sdhci_host *host, u32 irqs)
7095 +{
7096 + sdhci_clear_set_irqgen(host, irqs, 0);
7097 +}
7098 +
7099 +
7100 +
7101 +static void schci_bcm2708_cb_read(struct sdhci_bcm2708_priv *host,
7102 + int ix,
7103 + dma_addr_t dma_addr, unsigned len,
7104 + int /*bool*/ is_last)
7105 +{
7106 + struct bcm2708_dma_cb *cb = &host->cb_base[ix];
7107 + unsigned char dmawaits = host->dma_waits;
7108 +
7109 + cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
7110 + BCM2708_DMA_WAITS(dmawaits) |
7111 + BCM2708_DMA_S_DREQ |
7112 + BCM2708_DMA_D_WIDTH |
7113 + BCM2708_DMA_D_INC;
7114 + cb->src = DMA_SDHCI_BUFFER; /* DATA register DMA address */
7115 + cb->dst = dma_addr;
7116 + cb->length = len;
7117 + cb->stride = 0;
7118 +
7119 + if (is_last) {
7120 + cb->info |= BCM2708_DMA_INT_EN |
7121 + BCM2708_DMA_WAIT_RESP;
7122 + cb->next = 0;
7123 + } else
7124 + cb->next = host->cb_handle +
7125 + (ix+1)*sizeof(struct bcm2708_dma_cb);
7126 +
7127 + cb->pad[0] = 0;
7128 + cb->pad[1] = 0;
7129 +}
7130 +
7131 +static void schci_bcm2708_cb_write(struct sdhci_bcm2708_priv *host,
7132 + int ix,
7133 + dma_addr_t dma_addr, unsigned len,
7134 + int /*bool*/ is_last)
7135 +{
7136 + struct bcm2708_dma_cb *cb = &host->cb_base[ix];
7137 + unsigned char dmawaits = host->dma_waits;
7138 +
7139 + /* We can make arbitrarily large writes as long as we specify DREQ to
7140 + pace the delivery of bytes to the Arasan hardware */
7141 + cb->info = BCM2708_DMA_PER_MAP(BCM2708_DMA_DREQ_EMMC) |
7142 + BCM2708_DMA_WAITS(dmawaits) |
7143 + BCM2708_DMA_D_DREQ |
7144 + BCM2708_DMA_S_WIDTH |
7145 + BCM2708_DMA_S_INC;
7146 + cb->src = dma_addr;
7147 + cb->dst = DMA_SDHCI_BUFFER; /* DATA register DMA address */
7148 + cb->length = len;
7149 + cb->stride = 0;
7150 +
7151 + if (is_last) {
7152 + cb->info |= BCM2708_DMA_INT_EN |
7153 + BCM2708_DMA_WAIT_RESP;
7154 + cb->next = 0;
7155 + } else
7156 + cb->next = host->cb_handle +
7157 + (ix+1)*sizeof(struct bcm2708_dma_cb);
7158 +
7159 + cb->pad[0] = 0;
7160 + cb->pad[1] = 0;
7161 +}
7162 +
7163 +
7164 +static void schci_bcm2708_dma_go(struct sdhci_host *host)
7165 +{
7166 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7167 + void __iomem *dma_chan_base = host_priv->dma_chan_base;
7168 +
7169 + BUG_ON(host_priv->dma_wanted);
7170 +#ifdef CHECK_DMA_USE
7171 + if (host_priv->dma_wanted)
7172 + printk(KERN_ERR "%s: DMA already in progress - "
7173 + "now %"FMT_HPT", last started %lu "
7174 + "reset %lu stopped %lu\n",
7175 + mmc_hostname(host->mmc),
7176 + hptime(), since_ns(host_priv->when_started),
7177 + since_ns(host_priv->when_reset),
7178 + since_ns(host_priv->when_stopped));
7179 + else if (host_priv->dmas_pending > 0)
7180 + printk(KERN_INFO "%s: note - new DMA when %d reset DMAs "
7181 + "already in progress - "
7182 + "now %"FMT_HPT", started %lu reset %lu stopped %lu\n",
7183 + mmc_hostname(host->mmc),
7184 + host_priv->dmas_pending,
7185 + hptime(), since_ns(host_priv->when_started),
7186 + since_ns(host_priv->when_reset),
7187 + since_ns(host_priv->when_stopped));
7188 + host_priv->dmas_pending += 1;
7189 + host_priv->when_started = hptime();
7190 +#endif
7191 + host_priv->dma_wanted = 1;
7192 + DBG("PDMA go - base %p handle %08X\n", dma_chan_base,
7193 + host_priv->cb_handle);
7194 + bcm_dma_start(dma_chan_base, host_priv->cb_handle);
7195 +}
7196 +
7197 +
7198 +static void
7199 +sdhci_platdma_read(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7200 +{
7201 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7202 +
7203 + DBG("PDMA to read %d bytes\n", len);
7204 + host_priv->sg_done += len;
7205 + schci_bcm2708_cb_read(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7206 + schci_bcm2708_dma_go(host);
7207 +}
7208 +
7209 +
7210 +static void
7211 +sdhci_platdma_write(struct sdhci_host *host, dma_addr_t dma_addr, size_t len)
7212 +{
7213 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7214 +
7215 + DBG("PDMA to write %d bytes\n", len);
7216 + //BUG_ON(0 != (len & 0x1ff));
7217 +
7218 + host_priv->sg_done += len;
7219 + schci_bcm2708_cb_write(host_priv, 0, dma_addr, len, 1/*TRUE*/);
7220 + schci_bcm2708_dma_go(host);
7221 +}
7222 +
7223 +/*! space is avaiable to receive into or data is available to write
7224 + Platform DMA exported function
7225 +*/
7226 +void
7227 +sdhci_bcm2708_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
7228 + void(*completion_callback)(struct sdhci_host *host))
7229 +{
7230 + struct mmc_data *data = host->data;
7231 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7232 + int sg_ix;
7233 + size_t bytes;
7234 + dma_addr_t addr;
7235 +
7236 + BUG_ON(NULL == data);
7237 + BUG_ON(0 == data->blksz);
7238 +
7239 + host_priv->complete = completion_callback;
7240 +
7241 + sg_ix = host_priv->sg_ix;
7242 + BUG_ON(sg_ix >= data->sg_len);
7243 +
7244 + /* we can DMA blocks larger than blksz - it may hang the DMA
7245 + channel but we are its only user */
7246 + bytes = sg_dma_len(&data->sg[sg_ix]) - host_priv->sg_done;
7247 + addr = sg_dma_address(&data->sg[sg_ix]) + host_priv->sg_done;
7248 +
7249 + if (bytes > 0) {
7250 + /* We're going to poll for read/write available state until
7251 + we finish this DMA
7252 + */
7253 +
7254 + if (data->flags & MMC_DATA_READ) {
7255 + if (*ref_intmask & SDHCI_INT_DATA_AVAIL) {
7256 + sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7257 + SDHCI_INT_SPACE_AVAIL);
7258 + sdhci_platdma_read(host, addr, bytes);
7259 + }
7260 + } else {
7261 + if (*ref_intmask & SDHCI_INT_SPACE_AVAIL) {
7262 + sdhci_unsignal_irqs(host, SDHCI_INT_DATA_AVAIL |
7263 + SDHCI_INT_SPACE_AVAIL);
7264 + sdhci_platdma_write(host, addr, bytes);
7265 + }
7266 + }
7267 + }
7268 + /* else:
7269 + we have run out of bytes that need transferring (e.g. we may be in
7270 + the middle of the last DMA transfer), or
7271 + it is also possible that we've been called when another IRQ is
7272 + signalled, even though we've turned off signalling of our own IRQ */
7273 +
7274 + *ref_intmask &= ~SDHCI_INT_DATA_END;
7275 + /* don't let the main sdhci driver act on this .. we'll deal with it
7276 + when we respond to the DMA - if one is currently in progress */
7277 +}
7278 +
7279 +/* is it possible to DMA the given mmc_data structure?
7280 + Platform DMA exported function
7281 +*/
7282 +int /*bool*/
7283 +sdhci_bcm2708_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
7284 +{
7285 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7286 + int ok = bcm_sg_suitable_for_dma(data->sg, data->sg_len);
7287 +
7288 + if (!ok)
7289 + DBG("Reverting to PIO - bad cache alignment\n");
7290 +
7291 + else {
7292 + host_priv->sg_ix = 0; /* first SG index */
7293 + host_priv->sg_done = 0; /* no bytes done */
7294 + }
7295 +
7296 + return ok;
7297 +}
7298 +
7299 +#include <mach/arm_control.h> //GRAYG
7300 +/*! the current SD transacton has been abandonned
7301 + We need to tidy up if we were in the middle of a DMA
7302 + Platform DMA exported function
7303 +*/
7304 +void
7305 +sdhci_bcm2708_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
7306 +{
7307 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7308 + unsigned long flags;
7309 +
7310 + BUG_ON(NULL == host);
7311 +
7312 + spin_lock_irqsave(&host->lock, flags);
7313 +
7314 + if (host_priv->dma_wanted) {
7315 + if (NULL == data) {
7316 + printk(KERN_ERR "%s: ongoing DMA reset - no data!\n",
7317 + mmc_hostname(host->mmc));
7318 + BUG_ON(NULL == data);
7319 + } else {
7320 + struct scatterlist *sg;
7321 + int sg_len;
7322 + int sg_todo;
7323 + int rc;
7324 + unsigned long cs;
7325 +
7326 + sg = data->sg;
7327 + sg_len = data->sg_len;
7328 + sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7329 +
7330 + cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7331 +
7332 + if (!(BCM2708_DMA_ACTIVE & cs))
7333 + printk(KERN_INFO "%s: missed completion of "
7334 + "cmd %d DMA (%d/%d [%d]/[%d]) - "
7335 + "ignoring it\n",
7336 + mmc_hostname(host->mmc),
7337 + host->last_cmdop,
7338 + host_priv->sg_done, sg_todo,
7339 + host_priv->sg_ix+1, sg_len);
7340 + else
7341 + printk(KERN_INFO "%s: resetting ongoing cmd %d"
7342 + "DMA before %d/%d [%d]/[%d] complete\n",
7343 + mmc_hostname(host->mmc),
7344 + host->last_cmdop,
7345 + host_priv->sg_done, sg_todo,
7346 + host_priv->sg_ix+1, sg_len);
7347 +#ifdef CHECK_DMA_USE
7348 + printk(KERN_INFO "%s: now %"FMT_HPT" started %lu "
7349 + "last reset %lu last stopped %lu\n",
7350 + mmc_hostname(host->mmc),
7351 + hptime(), since_ns(host_priv->when_started),
7352 + since_ns(host_priv->when_reset),
7353 + since_ns(host_priv->when_stopped));
7354 + { unsigned long info, debug;
7355 + void __iomem *base;
7356 + unsigned long pend0, pend1, pend2;
7357 +
7358 + base = host_priv->dma_chan_base;
7359 + cs = readl(base + BCM2708_DMA_CS);
7360 + info = readl(base + BCM2708_DMA_INFO);
7361 + debug = readl(base + BCM2708_DMA_DEBUG);
7362 + printk(KERN_INFO "%s: DMA%d CS=%08lX TI=%08lX "
7363 + "DEBUG=%08lX\n",
7364 + mmc_hostname(host->mmc),
7365 + host_priv->dma_chan,
7366 + cs, info, debug);
7367 + pend0 = readl(__io_address(ARM_IRQ_PEND0));
7368 + pend1 = readl(__io_address(ARM_IRQ_PEND1));
7369 + pend2 = readl(__io_address(ARM_IRQ_PEND2));
7370 +
7371 + printk(KERN_INFO "%s: PEND0=%08lX "
7372 + "PEND1=%08lX PEND2=%08lX\n",
7373 + mmc_hostname(host->mmc),
7374 + pend0, pend1, pend2);
7375 +
7376 + //gintsts = readl(__io_address(GINTSTS));
7377 + //gintmsk = readl(__io_address(GINTMSK));
7378 + //printk(KERN_INFO "%s: USB GINTSTS=%08lX"
7379 + // "GINTMSK=%08lX\n",
7380 + // mmc_hostname(host->mmc), gintsts, gintmsk);
7381 + }
7382 +#endif
7383 + rc = bcm_dma_abort(host_priv->dma_chan_base);
7384 + BUG_ON(rc != 0);
7385 + }
7386 + host_priv->dma_wanted = 0;
7387 +#ifdef CHECK_DMA_USE
7388 + host_priv->when_reset = hptime();
7389 +#endif
7390 + }
7391 +
7392 + spin_unlock_irqrestore(&host->lock, flags);
7393 +}
7394 +
7395 +
7396 +static void sdhci_bcm2708_dma_complete_irq(struct sdhci_host *host,
7397 + u32 dma_cs)
7398 +{
7399 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7400 + struct mmc_data *data;
7401 + struct scatterlist *sg;
7402 + int sg_len;
7403 + int sg_ix;
7404 + int sg_todo;
7405 + unsigned long flags;
7406 +
7407 + BUG_ON(NULL == host);
7408 +
7409 + spin_lock_irqsave(&host->lock, flags);
7410 + data = host->data;
7411 +
7412 +#ifdef CHECK_DMA_USE
7413 + if (host_priv->dmas_pending <= 0)
7414 + DBG("on completion no DMA in progress - "
7415 + "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7416 + hptime(), since_ns(host_priv->when_started),
7417 + since_ns(host_priv->when_reset),
7418 + since_ns(host_priv->when_stopped));
7419 + else if (host_priv->dmas_pending > 1)
7420 + DBG("still %d DMA in progress after completion - "
7421 + "now %"FMT_HPT" started %lu reset %lu stopped %lu\n",
7422 + host_priv->dmas_pending - 1,
7423 + hptime(), since_ns(host_priv->when_started),
7424 + since_ns(host_priv->when_reset),
7425 + since_ns(host_priv->when_stopped));
7426 + BUG_ON(host_priv->dmas_pending <= 0);
7427 + host_priv->dmas_pending -= 1;
7428 + host_priv->when_stopped = hptime();
7429 +#endif
7430 + host_priv->dma_wanted = 0;
7431 +
7432 + if (NULL == data) {
7433 + DBG("PDMA unused completion - status 0x%X\n", dma_cs);
7434 + spin_unlock_irqrestore(&host->lock, flags);
7435 + return;
7436 + }
7437 + sg = data->sg;
7438 + sg_len = data->sg_len;
7439 + sg_todo = sg_dma_len(&sg[host_priv->sg_ix]);
7440 +
7441 + DBG("PDMA complete %d/%d [%d]/[%d]..\n",
7442 + host_priv->sg_done, sg_todo,
7443 + host_priv->sg_ix+1, sg_len);
7444 +
7445 + BUG_ON(host_priv->sg_done > sg_todo);
7446 +
7447 + if (host_priv->sg_done >= sg_todo) {
7448 + host_priv->sg_ix++;
7449 + host_priv->sg_done = 0;
7450 + }
7451 +
7452 + sg_ix = host_priv->sg_ix;
7453 + if (sg_ix < sg_len) {
7454 + u32 irq_mask;
7455 + /* Set off next DMA if we've got the capacity */
7456 +
7457 + if (data->flags & MMC_DATA_READ)
7458 + irq_mask = SDHCI_INT_DATA_AVAIL;
7459 + else
7460 + irq_mask = SDHCI_INT_SPACE_AVAIL;
7461 +
7462 + /* We have to use the interrupt status register on the BCM2708
7463 + rather than the SDHCI_PRESENT_STATE register because latency
7464 + in the glue logic means that the information retrieved from
7465 + the latter is not always up-to-date w.r.t the DMA engine -
7466 + it may not indicate that a read or a write is ready yet */
7467 + if (sdhci_bcm2708_raw_readl(host, SDHCI_INT_STATUS) &
7468 + irq_mask) {
7469 + size_t bytes = sg_dma_len(&sg[sg_ix]) -
7470 + host_priv->sg_done;
7471 + dma_addr_t addr = sg_dma_address(&data->sg[sg_ix]) +
7472 + host_priv->sg_done;
7473 +
7474 + /* acknowledge interrupt */
7475 + sdhci_bcm2708_raw_writel(host, irq_mask,
7476 + SDHCI_INT_STATUS);
7477 +
7478 + BUG_ON(0 == bytes);
7479 +
7480 + if (data->flags & MMC_DATA_READ)
7481 + sdhci_platdma_read(host, addr, bytes);
7482 + else
7483 + sdhci_platdma_write(host, addr, bytes);
7484 + } else {
7485 + DBG("PDMA - wait avail\n");
7486 + /* may generate an IRQ if already present */
7487 + sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7488 + SDHCI_INT_SPACE_AVAIL);
7489 + }
7490 + } else {
7491 +#ifdef USE_SYNC_AFTER_DMA
7492 + /* On the Arasan controller the stop command (which will be
7493 + scheduled after this completes) does not seem to work
7494 + properly if we allow it to be issued when we are
7495 + transferring data to/from the SD card.
7496 + We get CRC and DEND errors unless we wait for
7497 + the SD controller to finish reading/writing to the card. */
7498 + u32 state_mask;
7499 + int timeout=1000000;
7500 + hptime_t now = hptime();
7501 +
7502 + DBG("PDMA over - sync card\n");
7503 + if (data->flags & MMC_DATA_READ)
7504 + state_mask = SDHCI_DOING_READ;
7505 + else
7506 + state_mask = SDHCI_DOING_WRITE;
7507 +
7508 + while (0 != (sdhci_bcm2708_raw_readl(host,
7509 + SDHCI_PRESENT_STATE) &
7510 + state_mask) && --timeout > 0)
7511 + continue;
7512 +
7513 + if (1000000-timeout > 4000) /*ave. is about 3250*/
7514 + DBG("%s: note - long %s sync %luns - "
7515 + "%d its.\n",
7516 + mmc_hostname(host->mmc),
7517 + data->flags & MMC_DATA_READ? "read": "write",
7518 + since_ns(now), 1000000-timeout);
7519 + if (timeout <= 0)
7520 + printk(KERN_ERR"%s: final %s to SD card still "
7521 + "running\n",
7522 + mmc_hostname(host->mmc),
7523 + data->flags & MMC_DATA_READ? "read": "write");
7524 +#endif
7525 + if (host_priv->complete) {
7526 + (*host_priv->complete)(host);
7527 + DBG("PDMA %s complete\n",
7528 + data->flags & MMC_DATA_READ?"read":"write");
7529 + sdhci_signal_irqs(host, SDHCI_INT_DATA_AVAIL |
7530 + SDHCI_INT_SPACE_AVAIL);
7531 + }
7532 + }
7533 + spin_unlock_irqrestore(&host->lock, flags);
7534 +}
7535 +
7536 +static irqreturn_t sdhci_bcm2708_dma_irq(int irq, void *dev_id)
7537 +{
7538 + irqreturn_t result = IRQ_NONE;
7539 + struct sdhci_host *host = dev_id;
7540 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7541 + u32 dma_cs; /* control and status register */
7542 + unsigned long flags;
7543 +
7544 + BUG_ON(NULL == dev_id);
7545 + BUG_ON(NULL == host_priv->dma_chan_base);
7546 +
7547 + spin_lock_irqsave(&host->lock, flags);
7548 +
7549 + dma_cs = readl(host_priv->dma_chan_base + BCM2708_DMA_CS);
7550 +
7551 + if (dma_cs & BCM2708_DMA_ERR) {
7552 + unsigned long debug;
7553 + debug = readl(host_priv->dma_chan_base +
7554 + BCM2708_DMA_DEBUG);
7555 + printk(KERN_ERR "%s: DMA error - CS %lX DEBUG %lX\n",
7556 + mmc_hostname(host->mmc), (unsigned long)dma_cs,
7557 + (unsigned long)debug);
7558 + /* reset error */
7559 + writel(debug, host_priv->dma_chan_base +
7560 + BCM2708_DMA_DEBUG);
7561 + }
7562 + if (dma_cs & BCM2708_DMA_INT) {
7563 + /* acknowledge interrupt */
7564 + writel(BCM2708_DMA_INT,
7565 + host_priv->dma_chan_base + BCM2708_DMA_CS);
7566 +
7567 + dsb(); /* ARM data synchronization (push) operation */
7568 +
7569 + if (!host_priv->dma_wanted) {
7570 + /* ignore this interrupt - it was reset */
7571 + printk(KERN_INFO "%s: DMA IRQ %X ignored - "
7572 + "results were reset\n",
7573 + mmc_hostname(host->mmc), dma_cs);
7574 +#ifdef CHECK_DMA_USE
7575 + printk(KERN_INFO "%s: now %"FMT_HPT
7576 + " started %lu reset %lu stopped %lu\n",
7577 + mmc_hostname(host->mmc), hptime(),
7578 + since_ns(host_priv->when_started),
7579 + since_ns(host_priv->when_reset),
7580 + since_ns(host_priv->when_stopped));
7581 + host_priv->dmas_pending--;
7582 +#endif
7583 + } else
7584 + sdhci_bcm2708_dma_complete_irq(host, dma_cs);
7585 +
7586 + result = IRQ_HANDLED;
7587 + }
7588 +
7589 + spin_unlock_irqrestore(&host->lock, flags);
7590 +
7591 + return result;
7592 +}
7593 +#endif /* CONFIG_MMC_SDHCI_BCM2708_DMA */
7594 +
7595 +
7596 +/***************************************************************************** \
7597 + * *
7598 + * Device Attributes *
7599 + * *
7600 +\*****************************************************************************/
7601 +
7602 +
7603 +/**
7604 + * Show the DMA-using status
7605 + */
7606 +static ssize_t attr_dma_show(struct device *_dev,
7607 + struct device_attribute *attr, char *buf)
7608 +{
7609 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7610 +
7611 + if (host) {
7612 + int use_dma = (host->flags & SDHCI_USE_PLATDMA? 1:0);
7613 + return sprintf(buf, "%d\n", use_dma);
7614 + } else
7615 + return -EINVAL;
7616 +}
7617 +
7618 +/**
7619 + * Set the DMA-using status
7620 + */
7621 +static ssize_t attr_dma_store(struct device *_dev,
7622 + struct device_attribute *attr,
7623 + const char *buf, size_t count)
7624 +{
7625 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7626 +
7627 + if (host) {
7628 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7629 + int on = simple_strtol(buf, NULL, 0);
7630 + if (on) {
7631 + host->flags |= SDHCI_USE_PLATDMA;
7632 + printk(KERN_INFO "%s: DMA enabled\n",
7633 + mmc_hostname(host->mmc));
7634 + } else {
7635 + host->flags &= ~(SDHCI_USE_PLATDMA | SDHCI_REQ_USE_DMA);
7636 + printk(KERN_INFO "%s: DMA disabled\n",
7637 + mmc_hostname(host->mmc));
7638 + }
7639 +#endif
7640 + return count;
7641 + } else
7642 + return -EINVAL;
7643 +}
7644 +
7645 +static DEVICE_ATTR(use_dma, S_IRUGO | S_IWUGO, attr_dma_show, attr_dma_store);
7646 +
7647 +
7648 +/**
7649 + * Show the DMA wait states used
7650 + */
7651 +static ssize_t attr_dmawait_show(struct device *_dev,
7652 + struct device_attribute *attr, char *buf)
7653 +{
7654 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7655 +
7656 + if (host) {
7657 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7658 + int dmawait = host_priv->dma_waits;
7659 + return sprintf(buf, "%d\n", dmawait);
7660 + } else
7661 + return -EINVAL;
7662 +}
7663 +
7664 +/**
7665 + * Set the DMA wait state used
7666 + */
7667 +static ssize_t attr_dmawait_store(struct device *_dev,
7668 + struct device_attribute *attr,
7669 + const char *buf, size_t count)
7670 +{
7671 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7672 +
7673 + if (host) {
7674 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7675 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7676 + int dma_waits = simple_strtol(buf, NULL, 0);
7677 + if (dma_waits >= 0 && dma_waits < 32)
7678 + host_priv->dma_waits = dma_waits;
7679 + else
7680 + printk(KERN_ERR "%s: illegal dma_waits value - %d",
7681 + mmc_hostname(host->mmc), dma_waits);
7682 +#endif
7683 + return count;
7684 + } else
7685 + return -EINVAL;
7686 +}
7687 +
7688 +static DEVICE_ATTR(dma_wait, S_IRUGO | S_IWUGO,
7689 + attr_dmawait_show, attr_dmawait_store);
7690 +
7691 +
7692 +/**
7693 + * Show the DMA-using status
7694 + */
7695 +static ssize_t attr_status_show(struct device *_dev,
7696 + struct device_attribute *attr, char *buf)
7697 +{
7698 + struct sdhci_host *host = (struct sdhci_host *)dev_get_drvdata(_dev);
7699 +
7700 + if (host) {
7701 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7702 + return sprintf(buf,
7703 + "present: yes\n"
7704 + "power: %s\n"
7705 + "clock: %u Hz\n"
7706 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7707 + "dma: %s (%d waits)\n",
7708 +#else
7709 + "dma: unconfigured\n",
7710 +#endif
7711 + "always on",
7712 + host->clock
7713 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7714 + , (host->flags & SDHCI_USE_PLATDMA)? "on": "off"
7715 + , host_priv->dma_waits
7716 +#endif
7717 + );
7718 + } else
7719 + return -EINVAL;
7720 +}
7721 +
7722 +static DEVICE_ATTR(status, S_IRUGO, attr_status_show, NULL);
7723 +
7724 +/***************************************************************************** \
7725 + * *
7726 + * Power Management *
7727 + * *
7728 +\*****************************************************************************/
7729 +
7730 +
7731 +#ifdef CONFIG_PM
7732 +static int sdhci_bcm2708_suspend(struct platform_device *dev, pm_message_t state)
7733 +{
7734 + struct sdhci_host *host = (struct sdhci_host *)
7735 + platform_get_drvdata(dev);
7736 + int ret = 0;
7737 +
7738 + if (host->mmc) {
7739 + ret = mmc_suspend_host(host->mmc);
7740 + }
7741 +
7742 + return ret;
7743 +}
7744 +
7745 +static int sdhci_bcm2708_resume(struct platform_device *dev)
7746 +{
7747 + struct sdhci_host *host = (struct sdhci_host *)
7748 + platform_get_drvdata(dev);
7749 + int ret = 0;
7750 +
7751 + if (host->mmc) {
7752 + ret = mmc_resume_host(host->mmc);
7753 + }
7754 +
7755 + return ret;
7756 +}
7757 +#endif
7758 +
7759 +
7760 +/*****************************************************************************\
7761 + * *
7762 + * Device quirk functions. Implemented as local ops because the flags *
7763 + * field is out of space with newer kernels. This implementation can be *
7764 + * back ported to older kernels as well. *
7765 +\****************************************************************************/
7766 +static unsigned int sdhci_bcm2708_quirk_extra_ints(struct sdhci_host *host)
7767 +{
7768 + return 1;
7769 +}
7770 +
7771 +static unsigned int sdhci_bcm2708_quirk_spurious_crc(struct sdhci_host *host)
7772 +{
7773 + return 1;
7774 +}
7775 +
7776 +static unsigned int sdhci_bcm2708_quirk_voltage_broken(struct sdhci_host *host)
7777 +{
7778 + return 1;
7779 +}
7780 +
7781 +static unsigned int sdhci_bcm2708_uhs_broken(struct sdhci_host *host)
7782 +{
7783 + return 1;
7784 +}
7785 +
7786 +/***************************************************************************** \
7787 + * *
7788 + * Device ops *
7789 + * *
7790 +\*****************************************************************************/
7791 +
7792 +static struct sdhci_ops sdhci_bcm2708_ops = {
7793 +#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
7794 + .read_l = sdhci_bcm2708_readl,
7795 + .read_w = sdhci_bcm2708_readw,
7796 + .read_b = sdhci_bcm2708_readb,
7797 + .write_l = sdhci_bcm2708_writel,
7798 + .write_w = sdhci_bcm2708_writew,
7799 + .write_b = sdhci_bcm2708_writeb,
7800 +#else
7801 +#error The BCM2708 SDHCI driver needs CONFIG_MMC_SDHCI_IO_ACCESSORS to be set
7802 +#endif
7803 + //.enable_dma = NULL,
7804 + .set_clock = sdhci_bcm2708_set_clock,
7805 + .get_max_clock = sdhci_bcm2708_get_max_clock,
7806 + //.get_min_clock = NULL,
7807 + .get_timeout_clock = sdhci_bcm2708_get_timeout_clock,
7808 +
7809 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7810 + // Platform DMA operations
7811 + .pdma_able = sdhci_bcm2708_platdma_dmaable,
7812 + .pdma_avail = sdhci_bcm2708_platdma_avail,
7813 + .pdma_reset = sdhci_bcm2708_platdma_reset,
7814 +#endif
7815 + .extra_ints = sdhci_bcm2708_quirk_extra_ints,
7816 + .spurious_crc_acmd51 = sdhci_bcm2708_quirk_spurious_crc,
7817 + .voltage_broken = sdhci_bcm2708_quirk_voltage_broken,
7818 + .uhs_broken = sdhci_bcm2708_uhs_broken,
7819 +};
7820 +
7821 +/*****************************************************************************\
7822 + * *
7823 + * Device probing/removal *
7824 + * *
7825 +\*****************************************************************************/
7826 +
7827 +static int sdhci_bcm2708_probe(struct platform_device *pdev)
7828 +{
7829 + struct sdhci_host *host;
7830 + struct resource *iomem;
7831 + struct sdhci_bcm2708_priv *host_priv;
7832 + int ret;
7833 +
7834 + BUG_ON(pdev == NULL);
7835 +
7836 + iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7837 + if (!iomem) {
7838 + ret = -ENOMEM;
7839 + goto err;
7840 + }
7841 +
7842 + if (resource_size(iomem) != 0x100)
7843 + dev_err(&pdev->dev, "Invalid iomem size. You may "
7844 + "experience problems.\n");
7845 +
7846 + if (pdev->dev.parent)
7847 + host = sdhci_alloc_host(pdev->dev.parent,
7848 + sizeof(struct sdhci_bcm2708_priv));
7849 + else
7850 + host = sdhci_alloc_host(&pdev->dev,
7851 + sizeof(struct sdhci_bcm2708_priv));
7852 +
7853 + if (IS_ERR(host)) {
7854 + ret = PTR_ERR(host);
7855 + goto err;
7856 + }
7857 +
7858 + host->hw_name = "BCM2708_Arasan";
7859 + host->ops = &sdhci_bcm2708_ops;
7860 + host->irq = platform_get_irq(pdev, 0);
7861 +
7862 + host->quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
7863 + SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
7864 + SDHCI_QUIRK_BROKEN_TIMEOUT_VAL |
7865 + SDHCI_QUIRK_NONSTANDARD_CLOCK;
7866 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7867 + host->flags = SDHCI_USE_PLATDMA;
7868 +#endif
7869 +
7870 + if (!request_mem_region(iomem->start, resource_size(iomem),
7871 + mmc_hostname(host->mmc))) {
7872 + dev_err(&pdev->dev, "cannot request region\n");
7873 + ret = -EBUSY;
7874 + goto err_request;
7875 + }
7876 +
7877 + host->ioaddr = ioremap(iomem->start, resource_size(iomem));
7878 + if (!host->ioaddr) {
7879 + dev_err(&pdev->dev, "failed to remap registers\n");
7880 + ret = -ENOMEM;
7881 + goto err_remap;
7882 + }
7883 +
7884 + host_priv = SDHCI_HOST_PRIV(host);
7885 +
7886 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7887 + host_priv->dma_wanted = 0;
7888 +#ifdef CHECK_DMA_USE
7889 + host_priv->dmas_pending = 0;
7890 + host_priv->when_started = 0;
7891 + host_priv->when_reset = 0;
7892 + host_priv->when_stopped = 0;
7893 +#endif
7894 + host_priv->sg_ix = 0;
7895 + host_priv->sg_done = 0;
7896 + host_priv->complete = NULL;
7897 + host_priv->dma_waits = SDHCI_BCM_DMA_WAITS;
7898 +
7899 + host_priv->cb_base = dma_alloc_writecombine(&pdev->dev, SZ_4K,
7900 + &host_priv->cb_handle,
7901 + GFP_KERNEL);
7902 + if (!host_priv->cb_base) {
7903 + dev_err(&pdev->dev, "cannot allocate DMA CBs\n");
7904 + ret = -ENOMEM;
7905 + goto err_alloc_cb;
7906 + }
7907 +
7908 + ret = bcm_dma_chan_alloc(BCM_DMA_FEATURE_FAST,
7909 + &host_priv->dma_chan_base,
7910 + &host_priv->dma_irq);
7911 + if (ret < 0) {
7912 + dev_err(&pdev->dev, "couldn't allocate a DMA channel\n");
7913 + goto err_add_dma;
7914 + }
7915 + host_priv->dma_chan = ret;
7916 +
7917 + ret = request_irq(host_priv->dma_irq, sdhci_bcm2708_dma_irq,
7918 + IRQF_SHARED, DRIVER_NAME " (dma)", host);
7919 + if (ret) {
7920 + dev_err(&pdev->dev, "cannot set DMA IRQ\n");
7921 + goto err_add_dma_irq;
7922 + }
7923 + DBG("DMA CBs %p handle %08X DMA%d %p DMA IRQ %d\n",
7924 + host_priv->cb_base, (unsigned)host_priv->cb_handle,
7925 + host_priv->dma_chan, host_priv->dma_chan_base,
7926 + host_priv->dma_irq);
7927 +
7928 + host->mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
7929 +#endif
7930 +
7931 + ret = sdhci_add_host(host);
7932 + if (ret)
7933 + goto err_add_host;
7934 +
7935 + platform_set_drvdata(pdev, host);
7936 + ret = device_create_file(&pdev->dev, &dev_attr_use_dma);
7937 + ret = device_create_file(&pdev->dev, &dev_attr_dma_wait);
7938 + ret = device_create_file(&pdev->dev, &dev_attr_status);
7939 +
7940 + printk(KERN_INFO "%s: BCM2708 SDHC host at 0x%08llx DMA %d IRQ %d\n",
7941 + mmc_hostname(host->mmc), (unsigned long long)iomem->start,
7942 + host_priv->dma_chan, host_priv->dma_irq);
7943 +
7944 + return 0;
7945 +
7946 +err_add_host:
7947 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7948 + free_irq(host_priv->dma_irq, host);
7949 +err_add_dma_irq:
7950 + bcm_dma_chan_free(host_priv->dma_chan);
7951 +err_add_dma:
7952 + dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7953 + host_priv->cb_handle);
7954 +err_alloc_cb:
7955 +#endif
7956 + iounmap(host->ioaddr);
7957 +err_remap:
7958 + release_mem_region(iomem->start, resource_size(iomem));
7959 +err_request:
7960 + sdhci_free_host(host);
7961 +err:
7962 + dev_err(&pdev->dev, "probe failed, err %d\n", ret);
7963 + return ret;
7964 +}
7965 +
7966 +static int sdhci_bcm2708_remove(struct platform_device *pdev)
7967 +{
7968 + struct sdhci_host *host = platform_get_drvdata(pdev);
7969 + struct resource *iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
7970 + struct sdhci_bcm2708_priv *host_priv = SDHCI_HOST_PRIV(host);
7971 + int dead;
7972 + u32 scratch;
7973 +
7974 + dead = 0;
7975 + scratch = sdhci_bcm2708_readl(host, SDHCI_INT_STATUS);
7976 + if (scratch == (u32)-1)
7977 + dead = 1;
7978 +
7979 + device_remove_file(&pdev->dev, &dev_attr_status);
7980 + device_remove_file(&pdev->dev, &dev_attr_dma_wait);
7981 + device_remove_file(&pdev->dev, &dev_attr_use_dma);
7982 +
7983 +#ifdef CONFIG_MMC_SDHCI_BCM2708_DMA
7984 + free_irq(host_priv->dma_irq, host);
7985 + dma_free_writecombine(&pdev->dev, SZ_4K, host_priv->cb_base,
7986 + host_priv->cb_handle);
7987 +#endif
7988 + sdhci_remove_host(host, dead);
7989 + iounmap(host->ioaddr);
7990 + release_mem_region(iomem->start, resource_size(iomem));
7991 + sdhci_free_host(host);
7992 + platform_set_drvdata(pdev, NULL);
7993 +
7994 + return 0;
7995 +}
7996 +
7997 +static struct platform_driver sdhci_bcm2708_driver = {
7998 + .driver = {
7999 + .name = DRIVER_NAME,
8000 + .owner = THIS_MODULE,
8001 + },
8002 + .probe = sdhci_bcm2708_probe,
8003 + .remove = sdhci_bcm2708_remove,
8004 +
8005 +#ifdef CONFIG_PM
8006 + .suspend = sdhci_bcm2708_suspend,
8007 + .resume = sdhci_bcm2708_resume,
8008 +#endif
8009 +
8010 +};
8011 +
8012 +/*****************************************************************************\
8013 + * *
8014 + * Driver init/exit *
8015 + * *
8016 +\*****************************************************************************/
8017 +
8018 +static int __init sdhci_drv_init(void)
8019 +{
8020 + return platform_driver_register(&sdhci_bcm2708_driver);
8021 +}
8022 +
8023 +static void __exit sdhci_drv_exit(void)
8024 +{
8025 + platform_driver_unregister(&sdhci_bcm2708_driver);
8026 +}
8027 +
8028 +module_init(sdhci_drv_init);
8029 +module_exit(sdhci_drv_exit);
8030 +
8031 +MODULE_DESCRIPTION("Secure Digital Host Controller Interface platform driver");
8032 +MODULE_AUTHOR("Broadcom <info@broadcom.com>");
8033 +MODULE_LICENSE("GPL v2");
8034 +MODULE_ALIAS("platform:"DRIVER_NAME);
8035 +
8036 diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
8037 index 2ea429c..179e83e 100644
8038 --- a/drivers/mmc/host/sdhci.c
8039 +++ b/drivers/mmc/host/sdhci.c
8040 @@ -28,6 +28,7 @@
8041 #include <linux/mmc/mmc.h>
8042 #include <linux/mmc/host.h>
8043 #include <linux/mmc/card.h>
8044 +#include <linux/mmc/sd.h>
8045 #include <linux/mmc/slot-gpio.h>
8046
8047 #include "sdhci.h"
8048 @@ -315,7 +316,7 @@ static void sdhci_read_block_pio(struct sdhci_host *host)
8049 u32 uninitialized_var(scratch);
8050 u8 *buf;
8051
8052 - DBG("PIO reading\n");
8053 + DBG("PIO reading %db\n", host->data->blksz);
8054
8055 blksize = host->data->blksz;
8056 chunk = 0;
8057 @@ -360,7 +361,7 @@ static void sdhci_write_block_pio(struct sdhci_host *host)
8058 u32 scratch;
8059 u8 *buf;
8060
8061 - DBG("PIO writing\n");
8062 + DBG("PIO writing %db\n", host->data->blksz);
8063
8064 blksize = host->data->blksz;
8065 chunk = 0;
8066 @@ -399,19 +400,28 @@ static void sdhci_write_block_pio(struct sdhci_host *host)
8067 local_irq_restore(flags);
8068 }
8069
8070 -static void sdhci_transfer_pio(struct sdhci_host *host)
8071 +static void sdhci_transfer_pio(struct sdhci_host *host, u32 intstate)
8072 {
8073 u32 mask;
8074 + u32 state = 0;
8075 + u32 intmask;
8076 + int available;
8077
8078 BUG_ON(!host->data);
8079
8080 if (host->blocks == 0)
8081 return;
8082
8083 - if (host->data->flags & MMC_DATA_READ)
8084 + if (host->data->flags & MMC_DATA_READ) {
8085 mask = SDHCI_DATA_AVAILABLE;
8086 - else
8087 + intmask = SDHCI_INT_DATA_AVAIL;
8088 + } else {
8089 mask = SDHCI_SPACE_AVAILABLE;
8090 + intmask = SDHCI_INT_SPACE_AVAIL;
8091 + }
8092 +
8093 + /* initially we can see whether we can procede using intstate */
8094 + available = (intstate & intmask);
8095
8096 /*
8097 * Some controllers (JMicron JMB38x) mess up the buffer bits
8098 @@ -422,7 +432,7 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
8099 (host->data->blocks == 1))
8100 mask = ~0;
8101
8102 - while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
8103 + while (available) {
8104 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
8105 udelay(100);
8106
8107 @@ -434,9 +444,11 @@ static void sdhci_transfer_pio(struct sdhci_host *host)
8108 host->blocks--;
8109 if (host->blocks == 0)
8110 break;
8111 + state = sdhci_readl(host, SDHCI_PRESENT_STATE);
8112 + available = state & mask;
8113 }
8114
8115 - DBG("PIO transfer complete.\n");
8116 + DBG("PIO transfer complete - %d blocks left.\n", host->blocks);
8117 }
8118
8119 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
8120 @@ -709,7 +721,9 @@ static void sdhci_set_transfer_irqs(struct sdhci_host *host)
8121 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
8122 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
8123
8124 - if (host->flags & SDHCI_REQ_USE_DMA)
8125 + /* platform DMA will begin on receipt of PIO irqs */
8126 + if ((host->flags & SDHCI_REQ_USE_DMA) &&
8127 + !(host->flags & SDHCI_USE_PLATDMA))
8128 sdhci_clear_set_irqs(host, pio_irqs, dma_irqs);
8129 else
8130 sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
8131 @@ -741,44 +755,25 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
8132 host->data_early = 0;
8133 host->data->bytes_xfered = 0;
8134
8135 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
8136 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA | SDHCI_USE_PLATDMA))
8137 host->flags |= SDHCI_REQ_USE_DMA;
8138
8139 /*
8140 * FIXME: This doesn't account for merging when mapping the
8141 * scatterlist.
8142 */
8143 - if (host->flags & SDHCI_REQ_USE_DMA) {
8144 - int broken, i;
8145 - struct scatterlist *sg;
8146 -
8147 - broken = 0;
8148 - if (host->flags & SDHCI_USE_ADMA) {
8149 - if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
8150 - broken = 1;
8151 - } else {
8152 - if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
8153 - broken = 1;
8154 - }
8155 -
8156 - if (unlikely(broken)) {
8157 - for_each_sg(data->sg, sg, data->sg_len, i) {
8158 - if (sg->length & 0x3) {
8159 - DBG("Reverting to PIO because of "
8160 - "transfer size (%d)\n",
8161 - sg->length);
8162 - host->flags &= ~SDHCI_REQ_USE_DMA;
8163 - break;
8164 - }
8165 - }
8166 - }
8167 - }
8168
8169 /*
8170 * The assumption here being that alignment is the same after
8171 * translation to device address space.
8172 */
8173 - if (host->flags & SDHCI_REQ_USE_DMA) {
8174 + if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) ==
8175 + (SDHCI_REQ_USE_DMA | SDHCI_USE_PLATDMA)) {
8176 +
8177 + if (! sdhci_platdma_dmaable(host, data))
8178 + host->flags &= ~SDHCI_REQ_USE_DMA;
8179 +
8180 + } else if (host->flags & SDHCI_REQ_USE_DMA) {
8181 int broken, i;
8182 struct scatterlist *sg;
8183
8184 @@ -837,7 +832,8 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
8185 */
8186 WARN_ON(1);
8187 host->flags &= ~SDHCI_REQ_USE_DMA;
8188 - } else {
8189 + } else
8190 + if (!(host->flags & SDHCI_USE_PLATDMA)) {
8191 WARN_ON(sg_cnt != 1);
8192 sdhci_writel(host, sg_dma_address(data->sg),
8193 SDHCI_DMA_ADDRESS);
8194 @@ -853,11 +849,13 @@ static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
8195 if (host->version >= SDHCI_SPEC_200) {
8196 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
8197 ctrl &= ~SDHCI_CTRL_DMA_MASK;
8198 + if (! (host->flags & SDHCI_USE_PLATDMA)) {
8199 if ((host->flags & SDHCI_REQ_USE_DMA) &&
8200 (host->flags & SDHCI_USE_ADMA))
8201 ctrl |= SDHCI_CTRL_ADMA32;
8202 else
8203 ctrl |= SDHCI_CTRL_SDMA;
8204 + }
8205 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
8206 }
8207
8208 @@ -909,7 +907,8 @@ static void sdhci_set_transfer_mode(struct sdhci_host *host,
8209
8210 if (data->flags & MMC_DATA_READ)
8211 mode |= SDHCI_TRNS_READ;
8212 - if (host->flags & SDHCI_REQ_USE_DMA)
8213 + if ((host->flags & SDHCI_REQ_USE_DMA) &&
8214 + !(host->flags & SDHCI_USE_PLATDMA))
8215 mode |= SDHCI_TRNS_DMA;
8216
8217 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
8218 @@ -925,13 +924,16 @@ static void sdhci_finish_data(struct sdhci_host *host)
8219 host->data = NULL;
8220
8221 if (host->flags & SDHCI_REQ_USE_DMA) {
8222 - if (host->flags & SDHCI_USE_ADMA)
8223 - sdhci_adma_table_post(host, data);
8224 - else {
8225 + /* we may have to abandon an ongoing platform DMA */
8226 + if (host->flags & SDHCI_USE_PLATDMA)
8227 + sdhci_platdma_reset(host, data);
8228 +
8229 + if (host->flags & (SDHCI_USE_PLATDMA | SDHCI_USE_SDMA)) {
8230 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
8231 data->sg_len, (data->flags & MMC_DATA_READ) ?
8232 DMA_FROM_DEVICE : DMA_TO_DEVICE);
8233 - }
8234 + } else if (host->flags & SDHCI_USE_ADMA)
8235 + sdhci_adma_table_post(host, data);
8236 }
8237
8238 /*
8239 @@ -984,6 +986,12 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
8240 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
8241 mask |= SDHCI_DATA_INHIBIT;
8242
8243 + if(host->ops->missing_status && (cmd->opcode == MMC_SEND_STATUS)) {
8244 + timeout = 5000; // Really obscenely large delay to send the status, due to bug in controller
8245 + // which might cause the STATUS command to get stuck when a data operation is in flow
8246 + mask |= SDHCI_DATA_INHIBIT;
8247 + }
8248 +
8249 /* We shouldn't wait for data inihibit for stop commands, even
8250 though they might use busy signaling */
8251 if (host->mrq->data && (cmd == host->mrq->data->stop))
8252 @@ -1001,10 +1009,16 @@ static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
8253 timeout--;
8254 mdelay(1);
8255 }
8256 + DBG("send cmd %d - wait 0x%X irq 0x%x\n", cmd->opcode, mask,
8257 + sdhci_readl(host, SDHCI_INT_STATUS));
8258
8259 mod_timer(&host->timer, jiffies + 10 * HZ);
8260
8261 host->cmd = cmd;
8262 + if (host->last_cmdop == MMC_APP_CMD)
8263 + host->last_cmdop = -cmd->opcode;
8264 + else
8265 + host->last_cmdop = cmd->opcode;
8266
8267 sdhci_prepare_data(host, cmd);
8268
8269 @@ -1470,7 +1484,7 @@ static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
8270 else
8271 ctrl &= ~SDHCI_CTRL_HISPD;
8272
8273 - if (host->version >= SDHCI_SPEC_300) {
8274 + if (host->version >= SDHCI_SPEC_300 && !(host->ops->uhs_broken)) {
8275 u16 clk, ctrl_2;
8276
8277 /* In case of UHS-I modes, set High Speed Enable */
8278 @@ -2164,7 +2178,7 @@ static void sdhci_timeout_timer(unsigned long data)
8279
8280 if (host->mrq) {
8281 pr_err("%s: Timeout waiting for hardware "
8282 - "interrupt.\n", mmc_hostname(host->mmc));
8283 + "interrupt - cmd%d.\n", mmc_hostname(host->mmc), host->last_cmdop);
8284 sdhci_dumpregs(host);
8285
8286 if (host->data) {
8287 @@ -2209,10 +2223,13 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
8288 BUG_ON(intmask == 0);
8289
8290 if (!host->cmd) {
8291 + if (!(host->ops->extra_ints)) {
8292 pr_err("%s: Got command interrupt 0x%08x even "
8293 "though no command operation was in progress.\n",
8294 mmc_hostname(host->mmc), (unsigned)intmask);
8295 sdhci_dumpregs(host);
8296 + } else
8297 + DBG("cmd irq 0x%08x cmd complete\n", (unsigned)intmask);
8298 return;
8299 }
8300
8301 @@ -2282,6 +2299,19 @@ static void sdhci_show_adma_error(struct sdhci_host *host)
8302 static void sdhci_show_adma_error(struct sdhci_host *host) { }
8303 #endif
8304
8305 +static void sdhci_data_end(struct sdhci_host *host)
8306 +{
8307 + if (host->cmd) {
8308 + /*
8309 + * Data managed to finish before the
8310 + * command completed. Make sure we do
8311 + * things in the proper order.
8312 + */
8313 + host->data_early = 1;
8314 + } else
8315 + sdhci_finish_data(host);
8316 +}
8317 +
8318 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8319 {
8320 u32 command;
8321 @@ -2311,23 +2341,39 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8322 }
8323 }
8324
8325 + if (!(host->ops->extra_ints)) {
8326 pr_err("%s: Got data interrupt 0x%08x even "
8327 "though no data operation was in progress.\n",
8328 mmc_hostname(host->mmc), (unsigned)intmask);
8329 sdhci_dumpregs(host);
8330 + } else
8331 + DBG("data irq 0x%08x but no data\n", (unsigned)intmask);
8332
8333 return;
8334 }
8335
8336 if (intmask & SDHCI_INT_DATA_TIMEOUT)
8337 host->data->error = -ETIMEDOUT;
8338 - else if (intmask & SDHCI_INT_DATA_END_BIT)
8339 + else if (intmask & SDHCI_INT_DATA_END_BIT) {
8340 + DBG("end error in cmd %d\n", host->last_cmdop);
8341 + if (host->ops->spurious_crc_acmd51 &&
8342 + host->last_cmdop == -SD_APP_SEND_SCR) {
8343 + DBG("ignoring spurious data_end_bit error\n");
8344 + intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8345 + } else
8346 host->data->error = -EILSEQ;
8347 - else if ((intmask & SDHCI_INT_DATA_CRC) &&
8348 + } else if ((intmask & SDHCI_INT_DATA_CRC) &&
8349 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
8350 - != MMC_BUS_TEST_R)
8351 + != MMC_BUS_TEST_R) {
8352 + DBG("crc error in cmd %d\n", host->last_cmdop);
8353 + if (host->ops->spurious_crc_acmd51 &&
8354 + host->last_cmdop == -SD_APP_SEND_SCR) {
8355 + DBG("ignoring spurious data_crc_bit error\n");
8356 + intmask = SDHCI_INT_DATA_AVAIL|SDHCI_INT_DATA_END;
8357 + } else {
8358 host->data->error = -EILSEQ;
8359 - else if (intmask & SDHCI_INT_ADMA_ERROR) {
8360 + }
8361 + } else if (intmask & SDHCI_INT_ADMA_ERROR) {
8362 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
8363 sdhci_show_adma_error(host);
8364 host->data->error = -EIO;
8365 @@ -2335,11 +2381,18 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8366 host->ops->adma_workaround(host, intmask);
8367 }
8368
8369 - if (host->data->error)
8370 + if (host->data->error) {
8371 + DBG("finish request early on error %d\n", host->data->error);
8372 sdhci_finish_data(host);
8373 - else {
8374 - if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
8375 - sdhci_transfer_pio(host);
8376 + } else {
8377 + if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) {
8378 + if (host->flags & SDHCI_REQ_USE_DMA) {
8379 + /* possible only in PLATDMA mode */
8380 + sdhci_platdma_avail(host, &intmask,
8381 + &sdhci_data_end);
8382 + } else
8383 + sdhci_transfer_pio(host, intmask);
8384 + }
8385
8386 /*
8387 * We currently don't do anything fancy with DMA
8388 @@ -2368,18 +2421,8 @@ static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
8389 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
8390 }
8391
8392 - if (intmask & SDHCI_INT_DATA_END) {
8393 - if (host->cmd) {
8394 - /*
8395 - * Data managed to finish before the
8396 - * command completed. Make sure we do
8397 - * things in the proper order.
8398 - */
8399 - host->data_early = 1;
8400 - } else {
8401 - sdhci_finish_data(host);
8402 - }
8403 - }
8404 + if (intmask & SDHCI_INT_DATA_END)
8405 + sdhci_data_end(host);
8406 }
8407 }
8408
8409 @@ -2435,6 +2478,22 @@ again:
8410 tasklet_schedule(&host->card_tasklet);
8411 }
8412
8413 + if (intmask & SDHCI_INT_ERROR_MASK & ~SDHCI_INT_ERROR)
8414 + DBG("controller reports error 0x%x -"
8415 + "%s%s%s%s%s%s%s%s%s%s",
8416 + intmask,
8417 + intmask & SDHCI_INT_TIMEOUT? " timeout": "",
8418 + intmask & SDHCI_INT_CRC ? " crc": "",
8419 + intmask & SDHCI_INT_END_BIT? " endbit": "",
8420 + intmask & SDHCI_INT_INDEX? " index": "",
8421 + intmask & SDHCI_INT_DATA_TIMEOUT? " data_timeout": "",
8422 + intmask & SDHCI_INT_DATA_CRC? " data_crc": "",
8423 + intmask & SDHCI_INT_DATA_END_BIT? " data_endbit": "",
8424 + intmask & SDHCI_INT_BUS_POWER? " buspower": "",
8425 + intmask & SDHCI_INT_ACMD12ERR? " acmd12": "",
8426 + intmask & SDHCI_INT_ADMA_ERROR? " adma": ""
8427 + );
8428 +
8429 if (intmask & SDHCI_INT_CMD_MASK) {
8430 sdhci_writel(host, intmask & SDHCI_INT_CMD_MASK,
8431 SDHCI_INT_STATUS);
8432 @@ -2449,7 +2508,13 @@ again:
8433
8434 intmask &= ~(SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK);
8435
8436 - intmask &= ~SDHCI_INT_ERROR;
8437 + if (intmask & SDHCI_INT_ERROR_MASK) {
8438 + /* collect any uncovered errors */
8439 + sdhci_writel(host, intmask & SDHCI_INT_ERROR_MASK,
8440 + SDHCI_INT_STATUS);
8441 + }
8442 +
8443 + intmask &= ~SDHCI_INT_ERROR_MASK;
8444
8445 if (intmask & SDHCI_INT_BUS_POWER) {
8446 pr_err("%s: Card is consuming too much power!\n",
8447 @@ -2569,7 +2634,8 @@ int sdhci_resume_host(struct sdhci_host *host)
8448 {
8449 int ret;
8450
8451 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8452 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8453 + SDHCI_USE_PLATDMA)) {
8454 if (host->ops->enable_dma)
8455 host->ops->enable_dma(host);
8456 }
8457 @@ -2785,14 +2851,16 @@ int sdhci_add_host(struct sdhci_host *host)
8458 host->flags &= ~SDHCI_USE_ADMA;
8459 }
8460
8461 - if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
8462 + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8463 + SDHCI_USE_PLATDMA)) {
8464 if (host->ops->enable_dma) {
8465 if (host->ops->enable_dma(host)) {
8466 pr_warning("%s: No suitable DMA "
8467 "available. Falling back to PIO.\n",
8468 mmc_hostname(mmc));
8469 host->flags &=
8470 - ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
8471 + ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA |
8472 + SDHCI_USE_PLATDMA);
8473 }
8474 }
8475 }
8476 @@ -3080,6 +3148,12 @@ int sdhci_add_host(struct sdhci_host *host)
8477 SDHCI_MAX_CURRENT_MULTIPLIER;
8478 }
8479
8480 + if(host->ops->voltage_broken) {
8481 + ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
8482 + // Cannot support UHS modes if we are stuck at 3.3V;
8483 + mmc->caps &= ~(MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_DDR50);
8484 + }
8485 +
8486 mmc->ocr_avail = ocr_avail;
8487 mmc->ocr_avail_sdio = ocr_avail;
8488 if (host->ocr_avail_sdio)
8489 @@ -3210,6 +3284,7 @@ int sdhci_add_host(struct sdhci_host *host)
8490
8491 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
8492 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
8493 + (host->flags & SDHCI_USE_PLATDMA) ? "platform's DMA" :
8494 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
8495 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
8496
8497 diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
8498 index 379e09d..f90574e 100644
8499 --- a/drivers/mmc/host/sdhci.h
8500 +++ b/drivers/mmc/host/sdhci.h
8501 @@ -289,6 +289,20 @@ struct sdhci_ops {
8502 void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
8503 void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
8504 int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
8505 +
8506 + int (*pdma_able)(struct sdhci_host *host,
8507 + struct mmc_data *data);
8508 + void (*pdma_avail)(struct sdhci_host *host,
8509 + unsigned int *ref_intmask,
8510 + void(*complete)(struct sdhci_host *));
8511 + void (*pdma_reset)(struct sdhci_host *host,
8512 + struct mmc_data *data);
8513 + unsigned int (*extra_ints)(struct sdhci_host *host);
8514 + unsigned int (*spurious_crc_acmd51)(struct sdhci_host *host);
8515 + unsigned int (*voltage_broken)(struct sdhci_host *host);
8516 + unsigned int (*uhs_broken)(struct sdhci_host *host);
8517 + unsigned int (*missing_status)(struct sdhci_host *host);
8518 +
8519 void (*hw_reset)(struct sdhci_host *host);
8520 void (*platform_suspend)(struct sdhci_host *host);
8521 void (*platform_resume)(struct sdhci_host *host);
8522 @@ -399,6 +413,29 @@ extern int sdhci_resume_host(struct sdhci_host *host);
8523 extern void sdhci_enable_irq_wakeups(struct sdhci_host *host);
8524 #endif
8525
8526 +static inline int /*bool*/
8527 +sdhci_platdma_dmaable(struct sdhci_host *host, struct mmc_data *data)
8528 +{
8529 + if (host->ops->pdma_able)
8530 + return host->ops->pdma_able(host, data);
8531 + else
8532 + return 1;
8533 +}
8534 +static inline void
8535 +sdhci_platdma_avail(struct sdhci_host *host, unsigned int *ref_intmask,
8536 + void(*completion_callback)(struct sdhci_host *))
8537 +{
8538 + if (host->ops->pdma_avail)
8539 + host->ops->pdma_avail(host, ref_intmask, completion_callback);
8540 +}
8541 +
8542 +static inline void
8543 +sdhci_platdma_reset(struct sdhci_host *host, struct mmc_data *data)
8544 +{
8545 + if (host->ops->pdma_reset)
8546 + host->ops->pdma_reset(host, data);
8547 +}
8548 +
8549 #ifdef CONFIG_PM_RUNTIME
8550 extern int sdhci_runtime_suspend_host(struct sdhci_host *host);
8551 extern int sdhci_runtime_resume_host(struct sdhci_host *host);
8552 diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
8553 index b838ffc..f3a39c1 100644
8554 --- a/include/linux/mmc/sdhci.h
8555 +++ b/include/linux/mmc/sdhci.h
8556 @@ -128,6 +128,7 @@ struct sdhci_host {
8557 #define SDHCI_SDIO_IRQ_ENABLED (1<<9) /* SDIO irq enabled */
8558 #define SDHCI_HS200_NEEDS_TUNING (1<<10) /* HS200 needs tuning */
8559 #define SDHCI_USING_RETUNING_TIMER (1<<11) /* Host is using a retuning timer for the card */
8560 +#define SDHCI_USE_PLATDMA (1<<12) /* Host uses 3rd party DMA */
8561
8562 unsigned int version; /* SDHCI spec. version */
8563
8564 @@ -142,6 +143,7 @@ struct sdhci_host {
8565
8566 struct mmc_request *mrq; /* Current request */
8567 struct mmc_command *cmd; /* Current command */
8568 + int last_cmdop; /* Opcode of last cmd sent */
8569 struct mmc_data *data; /* Current data request */
8570 unsigned int data_early:1; /* Data finished before cmd */
8571
8572 --
8573 1.9.1
8574
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