target/linux/brcm47xx/patches-3.2/0040-bcma-add-PCIe-host-controller.patch

   1 From 47d0e8c2743729b4248585d33b55b6aaeac008d5 Mon Sep 17 00:00:00 2001
   2 From: Hauke Mehrtens <hauke@hauke-m.de>
   3 Date: Sun, 8 Jan 2012 16:53:15 +0100
   4 Subject: [PATCH 25/34] bcma: add PCIe host controller
   5
   6 Some SoCs have a PCIe host controller to make it possible to attach
   7 some other devices to it, like an other Wifi card.
   8 This code was tested with an Netgear WNDR3400 (bcm4716 based), but
   9 should work with all bcma based SoCs.
  10
  11 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
  12 ---
  13  arch/mips/pci/pci-bcm47xx.c          |   49 +++-
  14  drivers/bcma/bcma_private.h          |    1 +
  15  drivers/bcma/driver_pci.c            |   38 +--
  16  drivers/bcma/driver_pci_host.c       |  576 +++++++++++++++++++++++++++++++++-
  17  include/linux/bcma/bcma_driver_pci.h |   34 ++
  18  include/linux/bcma/bcma_regs.h       |   27 ++
  19  6 files changed, 686 insertions(+), 39 deletions(-)
  20
  21 --- a/arch/mips/pci/pci-bcm47xx.c
  22 +++ b/arch/mips/pci/pci-bcm47xx.c
  23 @@ -25,6 +25,7 @@
  24  #include <linux/types.h>
  25  #include <linux/pci.h>
  26  #include <linux/ssb/ssb.h>
  27 +#include <linux/bcma/bcma.h>
  28  #include <bcm47xx.h>
  29
  30  int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
  31 @@ -32,15 +33,12 @@ int __init pcibios_map_irq(const struct
  32         return 0;
  33  }
  34
  35 -int pcibios_plat_dev_init(struct pci_dev *dev)
  36 -{
  37  #ifdef CONFIG_BCM47XX_SSB
  38 +static int bcm47xx_pcibios_plat_dev_init_ssb(struct pci_dev *dev)
  39 +{
  40         int res;
  41         u8 slot, pin;
  42
  43 -       if (bcm47xx_bus_type !=  BCM47XX_BUS_TYPE_SSB)
  44 -               return 0;
  45 -
  46         res = ssb_pcibios_plat_dev_init(dev);
  47         if (res < 0) {
  48                 printk(KERN_ALERT "PCI: Failed to init device %s\n",
  49 @@ -60,6 +58,47 @@ int pcibios_plat_dev_init(struct pci_dev
  50         }
  51
  52         dev->irq = res;
  53 +       return 0;
  54 +}
  55  #endif
  56 +
  57 +#ifdef CONFIG_BCM47XX_BCMA
  58 +static int bcm47xx_pcibios_plat_dev_init_bcma(struct pci_dev *dev)
  59 +{
  60 +       int res;
  61 +
  62 +       res = bcma_core_pci_plat_dev_init(dev);
  63 +       if (res < 0) {
  64 +               printk(KERN_ALERT "PCI: Failed to init device %s\n",
  65 +                      pci_name(dev));
  66 +               return res;
  67 +       }
  68 +
  69 +       res = bcma_core_pci_pcibios_map_irq(dev);
  70 +
  71 +       /* IRQ-0 and IRQ-1 are software interrupts. */
  72 +       if (res < 2) {
  73 +               printk(KERN_ALERT "PCI: Failed to map IRQ of device %s\n",
  74 +                      pci_name(dev));
  75 +               return res;
  76 +       }
  77 +
  78 +       dev->irq = res;
  79         return 0;
  80  }
  81 +#endif
  82 +
  83 +int pcibios_plat_dev_init(struct pci_dev *dev)
  84 +{
  85 +#ifdef CONFIG_BCM47XX_SSB
  86 +       if (bcm47xx_bus_type ==  BCM47XX_BUS_TYPE_SSB)
  87 +               return bcm47xx_pcibios_plat_dev_init_ssb(dev);
  88 +       else
  89 +#endif
  90 +#ifdef CONFIG_BCM47XX_BCMA
  91 +       if  (bcm47xx_bus_type ==  BCM47XX_BUS_TYPE_BCMA)
  92 +               return bcm47xx_pcibios_plat_dev_init_bcma(dev);
  93 +       else
  94 +#endif
  95 +               return 0;
  96 +}
  97 --- a/drivers/bcma/bcma_private.h
  98 +++ b/drivers/bcma/bcma_private.h
  99 @@ -55,6 +55,7 @@ extern void __exit bcma_host_pci_exit(vo
 100  #endif /* CONFIG_BCMA_HOST_PCI */
 101
 102  #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
 103 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc);
 104  void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc);
 105  #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
 106
 107 --- a/drivers/bcma/driver_pci.c
 108 +++ b/drivers/bcma/driver_pci.c
 109 @@ -2,7 +2,7 @@
 110   * Broadcom specific AMBA
 111   * PCI Core
 112   *
 113 - * Copyright 2005, Broadcom Corporation
 114 + * Copyright 2005, 2011, Broadcom Corporation
 115   * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 116   * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
 117   *
 118 @@ -179,47 +179,19 @@ static void __devinit bcma_core_pci_clie
 119         bcma_pcicore_serdes_workaround(pc);
 120  }
 121
 122 -static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
 123 -{
 124 -       struct bcma_bus *bus = pc->core->bus;
 125 -       u16 chipid_top;
 126 -
 127 -       chipid_top = (bus->chipinfo.id & 0xFF00);
 128 -       if (chipid_top != 0x4700 &&
 129 -           chipid_top != 0x5300)
 130 -               return false;
 131 -
 132 -#ifdef CONFIG_SSB_DRIVER_PCICORE
 133 -       if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI)
 134 -               return false;
 135 -#endif /* CONFIG_SSB_DRIVER_PCICORE */
 136 -
 137 -#if 0
 138 -       /* TODO: on BCMA we use address from EROM instead of magic formula */
 139 -       u32 tmp;
 140 -       return !mips_busprobe32(tmp, (bus->mmio +
 141 -               (pc->core->core_index * BCMA_CORE_SIZE)));
 142 -#endif
 143 -
 144 -       return true;
 145 -}
 146 -
 147  void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc)
 148  {
 149         if (pc->setup_done)
 150                 return;
 151
 152 -       if (bcma_core_pci_is_in_hostmode(pc)) {
 153  #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
 154 +       pc->hostmode = bcma_core_pci_is_in_hostmode(pc);
 155 +       if (pc->hostmode)
 156                 bcma_core_pci_hostmode_init(pc);
 157 -#else
 158 -               pr_err("Driver compiled without support for hostmode PCI\n");
 159  #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */
 160 -       } else {
 161 -               bcma_core_pci_clientmode_init(pc);
 162 -       }
 163
 164 -       pc->setup_done = true;
 165 +       if (!pc->hostmode)
 166 +               bcma_core_pci_clientmode_init(pc);
 167  }
 168
 169  int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
 170 --- a/drivers/bcma/driver_pci_host.c
 171 +++ b/drivers/bcma/driver_pci_host.c
 172 @@ -2,13 +2,587 @@
 173   * Broadcom specific AMBA
 174   * PCI Core in hostmode
 175   *
 176 + * Copyright 2005 - 2011, Broadcom Corporation
 177 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
 178 + * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
 179 + *
 180   * Licensed under the GNU/GPL. See COPYING for details.
 181   */
 182
 183  #include "bcma_private.h"
 184 +#include <linux/export.h>
 185  #include <linux/bcma/bcma.h>
 186 +#include <asm/paccess.h>
 187 +
 188 +/* Probe a 32bit value on the bus and catch bus exceptions.
 189 + * Returns nonzero on a bus exception.
 190 + * This is MIPS specific */
 191 +#define mips_busprobe32(val, addr)     get_dbe((val), ((u32 *)(addr)))
 192 +
 193 +/* Assume one-hot slot wiring */
 194 +#define BCMA_PCI_SLOT_MAX      16
 195 +#define        PCI_CONFIG_SPACE_SIZE   256
 196 +
 197 +bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc)
 198 +{
 199 +       struct bcma_bus *bus = pc->core->bus;
 200 +       u16 chipid_top;
 201 +       u32 tmp;
 202 +
 203 +       chipid_top = (bus->chipinfo.id & 0xFF00);
 204 +       if (chipid_top != 0x4700 &&
 205 +           chipid_top != 0x5300)
 206 +               return false;
 207 +
 208 +       if (bus->sprom.boardflags_lo & BCMA_CORE_PCI_BFL_NOPCI) {
 209 +               pr_info("This PCI core is disabled and not working\n");
 210 +               return false;
 211 +       }
 212 +
 213 +       bcma_core_enable(pc->core, 0);
 214 +
 215 +       return !mips_busprobe32(tmp, pc->core->io_addr);
 216 +}
 217 +
 218 +static u32 bcma_pcie_read_config(struct bcma_drv_pci *pc, u32 address)
 219 +{
 220 +       pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
 221 +       pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
 222 +       return pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_DATA);
 223 +}
 224 +
 225 +static void bcma_pcie_write_config(struct bcma_drv_pci *pc, u32 address,
 226 +                                  u32 data)
 227 +{
 228 +       pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_ADDR, address);
 229 +       pcicore_read32(pc, BCMA_CORE_PCI_CONFIG_ADDR);
 230 +       pcicore_write32(pc, BCMA_CORE_PCI_CONFIG_DATA, data);
 231 +}
 232 +
 233 +static u32 bcma_get_cfgspace_addr(struct bcma_drv_pci *pc, unsigned int dev,
 234 +                            unsigned int func, unsigned int off)
 235 +{
 236 +       u32 addr = 0;
 237 +
 238 +       /* Issue config commands only when the data link is up (atleast
 239 +        * one external pcie device is present).
 240 +        */
 241 +       if (dev >= 2 || !(bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_LSREG)
 242 +                         & BCMA_CORE_PCI_DLLP_LSREG_LINKUP))
 243 +               goto out;
 244 +
 245 +       /* Type 0 transaction */
 246 +       /* Slide the PCI window to the appropriate slot */
 247 +       pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
 248 +       /* Calculate the address */
 249 +       addr = pc->host_controller->host_cfg_addr;
 250 +       addr |= (dev << BCMA_CORE_PCI_CFG_SLOT_SHIFT);
 251 +       addr |= (func << BCMA_CORE_PCI_CFG_FUN_SHIFT);
 252 +       addr |= (off & ~3);
 253 +
 254 +out:
 255 +       return addr;
 256 +}
 257 +
 258 +static int bcma_extpci_read_config(struct bcma_drv_pci *pc, unsigned int dev,
 259 +                                 unsigned int func, unsigned int off,
 260 +                                 void *buf, int len)
 261 +{
 262 +       int err = -EINVAL;
 263 +       u32 addr, val;
 264 +       void __iomem *mmio = 0;
 265 +
 266 +       WARN_ON(!pc->hostmode);
 267 +       if (unlikely(len != 1 && len != 2 && len != 4))
 268 +               goto out;
 269 +       if (dev == 0) {
 270 +               /* we support only two functions on device 0 */
 271 +               if (func > 1)
 272 +                       return -EINVAL;
 273 +
 274 +               /* accesses to config registers with offsets >= 256
 275 +                * requires indirect access.
 276 +                */
 277 +               if (off >= PCI_CONFIG_SPACE_SIZE) {
 278 +                       addr = (func << 12);
 279 +                       addr |= (off & 0x0FFF);
 280 +                       val = bcma_pcie_read_config(pc, addr);
 281 +               } else {
 282 +                       addr = BCMA_CORE_PCI_PCICFG0;
 283 +                       addr |= (func << 8);
 284 +                       addr |= (off & 0xfc);
 285 +                       val = pcicore_read32(pc, addr);
 286 +               }
 287 +       } else {
 288 +               addr = bcma_get_cfgspace_addr(pc, dev, func, off);
 289 +               if (unlikely(!addr))
 290 +                       goto out;
 291 +               err = -ENOMEM;
 292 +               mmio = ioremap_nocache(addr, len);
 293 +               if (!mmio)
 294 +                       goto out;
 295 +
 296 +               if (mips_busprobe32(val, mmio)) {
 297 +                       val = 0xffffffff;
 298 +                       goto unmap;
 299 +               }
 300 +
 301 +               val = readl(mmio);
 302 +       }
 303 +       val >>= (8 * (off & 3));
 304 +
 305 +       switch (len) {
 306 +       case 1:
 307 +               *((u8 *)buf) = (u8)val;
 308 +               break;
 309 +       case 2:
 310 +               *((u16 *)buf) = (u16)val;
 311 +               break;
 312 +       case 4:
 313 +               *((u32 *)buf) = (u32)val;
 314 +               break;
 315 +       }
 316 +       err = 0;
 317 +unmap:
 318 +       if (mmio)
 319 +               iounmap(mmio);
 320 +out:
 321 +       return err;
 322 +}
 323 +
 324 +static int bcma_extpci_write_config(struct bcma_drv_pci *pc, unsigned int dev,
 325 +                                  unsigned int func, unsigned int off,
 326 +                                  const void *buf, int len)
 327 +{
 328 +       int err = -EINVAL;
 329 +       u32 addr = 0, val = 0;
 330 +       void __iomem *mmio = 0;
 331 +       u16 chipid = pc->core->bus->chipinfo.id;
 332 +
 333 +       WARN_ON(!pc->hostmode);
 334 +       if (unlikely(len != 1 && len != 2 && len != 4))
 335 +               goto out;
 336 +       if (dev == 0) {
 337 +               /* accesses to config registers with offsets >= 256
 338 +                * requires indirect access.
 339 +                */
 340 +               if (off < PCI_CONFIG_SPACE_SIZE) {
 341 +                       addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
 342 +                       addr |= (func << 8);
 343 +                       addr |= (off & 0xfc);
 344 +                       mmio = ioremap_nocache(addr, len);
 345 +                       if (!mmio)
 346 +                               goto out;
 347 +               }
 348 +       } else {
 349 +               addr = bcma_get_cfgspace_addr(pc, dev, func, off);
 350 +               if (unlikely(!addr))
 351 +                       goto out;
 352 +               err = -ENOMEM;
 353 +               mmio = ioremap_nocache(addr, len);
 354 +               if (!mmio)
 355 +                       goto out;
 356 +
 357 +               if (mips_busprobe32(val, mmio)) {
 358 +                       val = 0xffffffff;
 359 +                       goto unmap;
 360 +               }
 361 +       }
 362 +
 363 +       switch (len) {
 364 +       case 1:
 365 +               val = readl(mmio);
 366 +               val &= ~(0xFF << (8 * (off & 3)));
 367 +               val |= *((const u8 *)buf) << (8 * (off & 3));
 368 +               break;
 369 +       case 2:
 370 +               val = readl(mmio);
 371 +               val &= ~(0xFFFF << (8 * (off & 3)));
 372 +               val |= *((const u16 *)buf) << (8 * (off & 3));
 373 +               break;
 374 +       case 4:
 375 +               val = *((const u32 *)buf);
 376 +               break;
 377 +       }
 378 +       if (dev == 0 && !addr) {
 379 +               /* accesses to config registers with offsets >= 256
 380 +                * requires indirect access.
 381 +                */
 382 +               addr = (func << 12);
 383 +               addr |= (off & 0x0FFF);
 384 +               bcma_pcie_write_config(pc, addr, val);
 385 +       } else {
 386 +               writel(val, mmio);
 387 +
 388 +               if (chipid == 0x4716 || chipid == 0x4748)
 389 +                       readl(mmio);
 390 +       }
 391 +
 392 +       err = 0;
 393 +unmap:
 394 +       if (mmio)
 395 +               iounmap(mmio);
 396 +out:
 397 +       return err;
 398 +}
 399 +
 400 +static int bcma_core_pci_hostmode_read_config(struct pci_bus *bus,
 401 +                                             unsigned int devfn,
 402 +                                             int reg, int size, u32 *val)
 403 +{
 404 +       unsigned long flags;
 405 +       int err;
 406 +       struct bcma_drv_pci *pc;
 407 +       struct bcma_drv_pci_host *pc_host;
 408 +
 409 +       pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
 410 +       pc = pc_host->pdev;
 411 +
 412 +       spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
 413 +       err = bcma_extpci_read_config(pc, PCI_SLOT(devfn),
 414 +                                    PCI_FUNC(devfn), reg, val, size);
 415 +       spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
 416 +
 417 +       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 418 +}
 419 +
 420 +static int bcma_core_pci_hostmode_write_config(struct pci_bus *bus,
 421 +                                              unsigned int devfn,
 422 +                                              int reg, int size, u32 val)
 423 +{
 424 +       unsigned long flags;
 425 +       int err;
 426 +       struct bcma_drv_pci *pc;
 427 +       struct bcma_drv_pci_host *pc_host;
 428 +
 429 +       pc_host = container_of(bus->ops, struct bcma_drv_pci_host, pci_ops);
 430 +       pc = pc_host->pdev;
 431 +
 432 +       spin_lock_irqsave(&pc_host->cfgspace_lock, flags);
 433 +       err = bcma_extpci_write_config(pc, PCI_SLOT(devfn),
 434 +                                     PCI_FUNC(devfn), reg, &val, size);
 435 +       spin_unlock_irqrestore(&pc_host->cfgspace_lock, flags);
 436 +
 437 +       return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
 438 +}
 439 +
 440 +/* return cap_offset if requested capability exists in the PCI config space */
 441 +static u8 __devinit bcma_find_pci_capability(struct bcma_drv_pci *pc,
 442 +                                            unsigned int dev,
 443 +                                            unsigned int func, u8 req_cap_id,
 444 +                                            unsigned char *buf, u32 *buflen)
 445 +{
 446 +       u8 cap_id;
 447 +       u8 cap_ptr = 0;
 448 +       u32 bufsize;
 449 +       u8 byte_val;
 450 +
 451 +       /* check for Header type 0 */
 452 +       bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
 453 +                               sizeof(u8));
 454 +       if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
 455 +               return cap_ptr;
 456 +
 457 +       /* check if the capability pointer field exists */
 458 +       bcma_extpci_read_config(pc, dev, func, PCI_STATUS, &byte_val,
 459 +                               sizeof(u8));
 460 +       if (!(byte_val & PCI_STATUS_CAP_LIST))
 461 +               return cap_ptr;
 462 +
 463 +       /* check if the capability pointer is 0x00 */
 464 +       bcma_extpci_read_config(pc, dev, func, PCI_CAPABILITY_LIST, &cap_ptr,
 465 +                               sizeof(u8));
 466 +       if (cap_ptr == 0x00)
 467 +               return cap_ptr;
 468 +
 469 +       /* loop thr'u the capability list and see if the requested capabilty
 470 +        * exists */
 471 +       bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id, sizeof(u8));
 472 +       while (cap_id != req_cap_id) {
 473 +               bcma_extpci_read_config(pc, dev, func, cap_ptr + 1, &cap_ptr,
 474 +                                       sizeof(u8));
 475 +               if (cap_ptr == 0x00)
 476 +                       return cap_ptr;
 477 +               bcma_extpci_read_config(pc, dev, func, cap_ptr, &cap_id,
 478 +                                       sizeof(u8));
 479 +       }
 480 +
 481 +       /* found the caller requested capability */
 482 +       if ((buf != NULL) && (buflen != NULL)) {
 483 +               u8 cap_data;
 484 +
 485 +               bufsize = *buflen;
 486 +               if (!bufsize)
 487 +                       return cap_ptr;
 488 +
 489 +               *buflen = 0;
 490 +
 491 +               /* copy the cpability data excluding cap ID and next ptr */
 492 +               cap_data = cap_ptr + 2;
 493 +               if ((bufsize + cap_data)  > PCI_CONFIG_SPACE_SIZE)
 494 +                       bufsize = PCI_CONFIG_SPACE_SIZE - cap_data;
 495 +               *buflen = bufsize;
 496 +               while (bufsize--) {
 497 +                       bcma_extpci_read_config(pc, dev, func, cap_data, buf,
 498 +                                               sizeof(u8));
 499 +                       cap_data++;
 500 +                       buf++;
 501 +               }
 502 +       }
 503 +
 504 +       return cap_ptr;
 505 +}
 506 +
 507 +/* If the root port is capable of returning Config Request
 508 + * Retry Status (CRS) Completion Status to software then
 509 + * enable the feature.
 510 + */
 511 +static void __devinit bcma_core_pci_enable_crs(struct bcma_drv_pci *pc)
 512 +{
 513 +       u8 cap_ptr, root_ctrl, root_cap, dev;
 514 +       u16 val16;
 515 +       int i;
 516 +
 517 +       cap_ptr = bcma_find_pci_capability(pc, 0, 0, PCI_CAP_ID_EXP, NULL,
 518 +                                          NULL);
 519 +       root_cap = cap_ptr + PCI_EXP_RTCAP;
 520 +       bcma_extpci_read_config(pc, 0, 0, root_cap, &val16, sizeof(u16));
 521 +       if (val16 & BCMA_CORE_PCI_RC_CRS_VISIBILITY) {
 522 +               /* Enable CRS software visibility */
 523 +               root_ctrl = cap_ptr + PCI_EXP_RTCTL;
 524 +               val16 = PCI_EXP_RTCTL_CRSSVE;
 525 +               bcma_extpci_read_config(pc, 0, 0, root_ctrl, &val16,
 526 +                                       sizeof(u16));
 527 +
 528 +               /* Initiate a configuration request to read the vendor id
 529 +                * field of the device function's config space header after
 530 +                * 100 ms wait time from the end of Reset. If the device is
 531 +                * not done with its internal initialization, it must at
 532 +                * least return a completion TLP, with a completion status
 533 +                * of "Configuration Request Retry Status (CRS)". The root
 534 +                * complex must complete the request to the host by returning
 535 +                * a read-data value of 0001h for the Vendor ID field and
 536 +                * all 1s for any additional bytes included in the request.
 537 +                * Poll using the config reads for max wait time of 1 sec or
 538 +                * until we receive the successful completion status. Repeat
 539 +                * the procedure for all the devices.
 540 +                */
 541 +               for (dev = 1; dev < BCMA_PCI_SLOT_MAX; dev++) {
 542 +                       for (i = 0; i < 100000; i++) {
 543 +                               bcma_extpci_read_config(pc, dev, 0,
 544 +                                                       PCI_VENDOR_ID, &val16,
 545 +                                                       sizeof(val16));
 546 +                               if (val16 != 0x1)
 547 +                                       break;
 548 +                               udelay(10);
 549 +                       }
 550 +                       if (val16 == 0x1)
 551 +                               pr_err("PCI: Broken device in slot %d\n", dev);
 552 +               }
 553 +       }
 554 +}
 555
 556  void __devinit bcma_core_pci_hostmode_init(struct bcma_drv_pci *pc)
 557  {
 558 -       pr_err("No support for PCI core in hostmode yet\n");
 559 +       struct bcma_bus *bus = pc->core->bus;
 560 +       struct bcma_drv_pci_host *pc_host;
 561 +       u32 tmp;
 562 +       u32 pci_membase_1G;
 563 +       unsigned long io_map_base;
 564 +
 565 +       pr_info("PCIEcore in host mode found\n");
 566 +
 567 +       pc_host = kzalloc(sizeof(*pc_host), GFP_KERNEL);
 568 +       if (!pc_host)  {
 569 +               pr_err("can not allocate memory");
 570 +               return;
 571 +       }
 572 +
 573 +       pc->host_controller = pc_host;
 574 +       pc_host->pci_controller.io_resource = &pc_host->io_resource;
 575 +       pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
 576 +       pc_host->pci_controller.pci_ops = &pc_host->pci_ops;
 577 +       pc_host->pdev = pc;
 578 +
 579 +       pci_membase_1G = BCMA_SOC_PCI_DMA;
 580 +       pc_host->host_cfg_addr = BCMA_SOC_PCI_CFG;
 581 +
 582 +       pc_host->pci_ops.read = bcma_core_pci_hostmode_read_config;
 583 +       pc_host->pci_ops.write = bcma_core_pci_hostmode_write_config;
 584 +
 585 +       pc_host->mem_resource.name = "BCMA PCIcore external memory",
 586 +       pc_host->mem_resource.start = BCMA_SOC_PCI_DMA;
 587 +       pc_host->mem_resource.end = BCMA_SOC_PCI_DMA + BCMA_SOC_PCI_DMA_SZ - 1;
 588 +       pc_host->mem_resource.flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED;
 589 +
 590 +       pc_host->io_resource.name = "BCMA PCIcore external I/O",
 591 +       pc_host->io_resource.start = 0x100;
 592 +       pc_host->io_resource.end = 0x7FF;
 593 +       pc_host->io_resource.flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED;
 594 +
 595 +       /* Reset RC */
 596 +       udelay(3000);
 597 +       pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
 598 +       udelay(1000);
 599 +       pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
 600 +                       BCMA_CORE_PCI_CTL_RST_OE);
 601 +
 602 +       /* 64 MB I/O access window. On 4716, use
 603 +        * sbtopcie0 to access the device registers. We
 604 +        * can't use address match 2 (1 GB window) region
 605 +        * as mips can't generate 64-bit address on the
 606 +        * backplane.
 607 +        */
 608 +       if (bus->chipinfo.id == 0x4716 || bus->chipinfo.id == 0x4748) {
 609 +               pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
 610 +               pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
 611 +                                           BCMA_SOC_PCI_MEM_SZ - 1;
 612 +               pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
 613 +                               BCMA_CORE_PCI_SBTOPCI_MEM | BCMA_SOC_PCI_MEM);
 614 +       } else if (bus->chipinfo.id == 0x5300) {
 615 +               tmp = BCMA_CORE_PCI_SBTOPCI_MEM;
 616 +               tmp |= BCMA_CORE_PCI_SBTOPCI_PREF;
 617 +               tmp |= BCMA_CORE_PCI_SBTOPCI_BURST;
 618 +               if (pc->core->core_unit == 0) {
 619 +                       pc_host->mem_resource.start = BCMA_SOC_PCI_MEM;
 620 +                       pc_host->mem_resource.end = BCMA_SOC_PCI_MEM +
 621 +                                                   BCMA_SOC_PCI_MEM_SZ - 1;
 622 +                       pci_membase_1G = BCMA_SOC_PCIE_DMA_H32;
 623 +                       pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
 624 +                                       tmp | BCMA_SOC_PCI_MEM);
 625 +               } else if (pc->core->core_unit == 1) {
 626 +                       pc_host->mem_resource.start = BCMA_SOC_PCI1_MEM;
 627 +                       pc_host->mem_resource.end = BCMA_SOC_PCI1_MEM +
 628 +                                                   BCMA_SOC_PCI_MEM_SZ - 1;
 629 +                       pci_membase_1G = BCMA_SOC_PCIE1_DMA_H32;
 630 +                       pc_host->host_cfg_addr = BCMA_SOC_PCI1_CFG;
 631 +                       pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
 632 +                                       tmp | BCMA_SOC_PCI1_MEM);
 633 +               }
 634 +       } else
 635 +               pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI0,
 636 +                               BCMA_CORE_PCI_SBTOPCI_IO);
 637 +
 638 +       /* 64 MB configuration access window */
 639 +       pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI1, BCMA_CORE_PCI_SBTOPCI_CFG0);
 640 +
 641 +       /* 1 GB memory access window */
 642 +       pcicore_write32(pc, BCMA_CORE_PCI_SBTOPCI2,
 643 +                       BCMA_CORE_PCI_SBTOPCI_MEM | pci_membase_1G);
 644 +
 645 +
 646 +       /* As per PCI Express Base Spec 1.1 we need to wait for
 647 +        * at least 100 ms from the end of a reset (cold/warm/hot)
 648 +        * before issuing configuration requests to PCI Express
 649 +        * devices.
 650 +        */
 651 +       udelay(100000);
 652 +
 653 +       bcma_core_pci_enable_crs(pc);
 654 +
 655 +       /* Enable PCI bridge BAR0 memory & master access */
 656 +       tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 657 +       bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
 658 +
 659 +       /* Enable PCI interrupts */
 660 +       pcicore_write32(pc, BCMA_CORE_PCI_IMASK, BCMA_CORE_PCI_IMASK_INTA);
 661 +
 662 +       /* Ok, ready to run, register it to the system.
 663 +        * The following needs change, if we want to port hostmode
 664 +        * to non-MIPS platform. */
 665 +       io_map_base = (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM,
 666 +                                                    0x04000000);
 667 +       pc_host->pci_controller.io_map_base = io_map_base;
 668 +       set_io_port_base(pc_host->pci_controller.io_map_base);
 669 +       /* Give some time to the PCI controller to configure itself with the new
 670 +        * values. Not waiting at this point causes crashes of the machine. */
 671 +       mdelay(10);
 672 +       register_pci_controller(&pc_host->pci_controller);
 673 +       return;
 674 +}
 675 +
 676 +/* Early PCI fixup for a device on the PCI-core bridge. */
 677 +static void bcma_core_pci_fixup_pcibridge(struct pci_dev *dev)
 678 +{
 679 +       if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
 680 +               /* This is not a device on the PCI-core bridge. */
 681 +               return;
 682 +       }
 683 +       if (PCI_SLOT(dev->devfn) != 0)
 684 +               return;
 685 +
 686 +       pr_info("PCI: Fixing up bridge %s\n", pci_name(dev));
 687 +
 688 +       /* Enable PCI bridge bus mastering and memory space */
 689 +       pci_set_master(dev);
 690 +       if (pcibios_enable_device(dev, ~0) < 0) {
 691 +               pr_err("PCI: BCMA bridge enable failed\n");
 692 +               return;
 693 +       }
 694 +
 695 +       /* Enable PCI bridge BAR1 prefetch and burst */
 696 +       pci_write_config_dword(dev, BCMA_PCI_BAR1_CONTROL, 3);
 697 +}
 698 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_pcibridge);
 699 +
 700 +/* Early PCI fixup for all PCI-cores to set the correct memory address. */
 701 +static void bcma_core_pci_fixup_addresses(struct pci_dev *dev)
 702 +{
 703 +       struct resource *res;
 704 +       int pos;
 705 +
 706 +       if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
 707 +               /* This is not a device on the PCI-core bridge. */
 708 +               return;
 709 +       }
 710 +       if (PCI_SLOT(dev->devfn) == 0)
 711 +               return;
 712 +
 713 +       pr_info("PCI: Fixing up addresses %s\n", pci_name(dev));
 714 +
 715 +       for (pos = 0; pos < 6; pos++) {
 716 +               res = &dev->resource[pos];
 717 +               if (res->flags & (IORESOURCE_IO | IORESOURCE_MEM))
 718 +                       pci_assign_resource(dev, pos);
 719 +       }
 720 +}
 721 +DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, bcma_core_pci_fixup_addresses);
 722 +
 723 +/* This function is called when doing a pci_enable_device().
 724 + * We must first check if the device is a device on the PCI-core bridge. */
 725 +int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
 726 +{
 727 +       struct bcma_drv_pci_host *pc_host;
 728 +
 729 +       if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
 730 +               /* This is not a device on the PCI-core bridge. */
 731 +               return -ENODEV;
 732 +       }
 733 +       pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
 734 +                              pci_ops);
 735 +
 736 +       pr_info("PCI: Fixing up device %s\n", pci_name(dev));
 737 +
 738 +       /* Fix up interrupt lines */
 739 +       dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
 740 +       pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 741 +
 742 +       return 0;
 743 +}
 744 +EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
 745 +
 746 +/* PCI device IRQ mapping. */
 747 +int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev)
 748 +{
 749 +       struct bcma_drv_pci_host *pc_host;
 750 +
 751 +       if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
 752 +               /* This is not a device on the PCI-core bridge. */
 753 +               return -ENODEV;
 754 +       }
 755 +
 756 +       pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
 757 +                              pci_ops);
 758 +       return bcma_core_mips_irq(pc_host->pdev->core) + 2;
 759  }
 760 +EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
 761 --- a/include/linux/bcma/bcma_driver_pci.h
 762 +++ b/include/linux/bcma/bcma_driver_pci.h
 763 @@ -160,9 +160,40 @@ struct pci_dev;
 764  /* PCIcore specific boardflags */
 765  #define BCMA_CORE_PCI_BFL_NOPCI                        0x00000400 /* Board leaves PCI floating */
 766
 767 +/* PCIE Config space accessing MACROS */
 768 +#define BCMA_CORE_PCI_CFG_BUS_SHIFT            24      /* Bus shift */
 769 +#define BCMA_CORE_PCI_CFG_SLOT_SHIFT           19      /* Slot/Device shift */
 770 +#define BCMA_CORE_PCI_CFG_FUN_SHIFT            16      /* Function shift */
 771 +#define BCMA_CORE_PCI_CFG_OFF_SHIFT            0       /* Register shift */
 772 +
 773 +#define BCMA_CORE_PCI_CFG_BUS_MASK             0xff    /* Bus mask */
 774 +#define BCMA_CORE_PCI_CFG_SLOT_MASK            0x1f    /* Slot/Device mask */
 775 +#define BCMA_CORE_PCI_CFG_FUN_MASK             7       /* Function mask */
 776 +#define BCMA_CORE_PCI_CFG_OFF_MASK             0xfff   /* Register mask */
 777 +
 778 +/* PCIE Root Capability Register bits (Host mode only) */
 779 +#define BCMA_CORE_PCI_RC_CRS_VISIBILITY                0x0001
 780 +
 781 +struct bcma_drv_pci;
 782 +
 783 +struct bcma_drv_pci_host {
 784 +       struct bcma_drv_pci *pdev;
 785 +
 786 +       u32 host_cfg_addr;
 787 +       spinlock_t cfgspace_lock;
 788 +
 789 +       struct pci_controller pci_controller;
 790 +       struct pci_ops pci_ops;
 791 +       struct resource mem_resource;
 792 +       struct resource io_resource;
 793 +};
 794 +
 795  struct bcma_drv_pci {
 796         struct bcma_device *core;
 797         u8 setup_done:1;
 798 +       u8 hostmode:1;
 799 +
 800 +       struct bcma_drv_pci_host *host_controller;
 801  };
 802
 803  /* Register access */
 804 @@ -173,4 +204,7 @@ extern void __devinit bcma_core_pci_init
 805  extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
 806                                  struct bcma_device *core, bool enable);
 807
 808 +extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
 809 +extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
 810 +
 811  #endif /* LINUX_BCMA_DRIVER_PCI_H_ */
 812 --- a/include/linux/bcma/bcma_regs.h
 813 +++ b/include/linux/bcma/bcma_regs.h
 814 @@ -56,4 +56,31 @@
 815  #define  BCMA_PCI_GPIO_XTAL            0x40    /* PCI config space GPIO 14 for Xtal powerup */
 816  #define  BCMA_PCI_GPIO_PLL             0x80    /* PCI config space GPIO 15 for PLL powerdown */
 817
 818 +/* SiliconBackplane Address Map.
 819 + * All regions may not exist on all chips.
 820 + */
 821 +#define BCMA_SOC_SDRAM_BASE            0x00000000U     /* Physical SDRAM */
 822 +#define BCMA_SOC_PCI_MEM               0x08000000U     /* Host Mode sb2pcitranslation0 (64 MB) */
 823 +#define BCMA_SOC_PCI_MEM_SZ            (64 * 1024 * 1024)
 824 +#define BCMA_SOC_PCI_CFG               0x0c000000U     /* Host Mode sb2pcitranslation1 (64 MB) */
 825 +#define BCMA_SOC_SDRAM_SWAPPED         0x10000000U     /* Byteswapped Physical SDRAM */
 826 +#define BCMA_SOC_SDRAM_R2              0x80000000U     /* Region 2 for sdram (512 MB) */
 827 +
 828 +
 829 +#define BCMA_SOC_PCI_DMA               0x40000000U     /* Client Mode sb2pcitranslation2 (1 GB) */
 830 +#define BCMA_SOC_PCI_DMA2              0x80000000U     /* Client Mode sb2pcitranslation2 (1 GB) */
 831 +#define BCMA_SOC_PCI_DMA_SZ            0x40000000U     /* Client Mode sb2pcitranslation2 size in bytes */
 832 +#define BCMA_SOC_PCIE_DMA_L32          0x00000000U     /* PCIE Client Mode sb2pcitranslation2
 833 +                                                        * (2 ZettaBytes), low 32 bits
 834 +                                                        */
 835 +#define BCMA_SOC_PCIE_DMA_H32          0x80000000U     /* PCIE Client Mode sb2pcitranslation2
 836 +                                                        * (2 ZettaBytes), high 32 bits
 837 +                                                        */
 838 +
 839 +#define BCMA_SOC_PCI1_MEM              0x40000000U     /* Host Mode sb2pcitranslation0 (64 MB) */
 840 +#define BCMA_SOC_PCI1_CFG              0x44000000U     /* Host Mode sb2pcitranslation1 (64 MB) */
 841 +#define BCMA_SOC_PCIE1_DMA_H32         0xc0000000U     /* PCIE Client Mode sb2pcitranslation2
 842 +                                                        * (2 ZettaBytes), high 32 bits
 843 +                                                        */
 844 +
 845  #endif /* LINUX_BCMA_REGS_H_ */