target/linux/brcm63xx/patches-3.3/311-MIPS-BCM63XX-add-MISC-register-set-definition.patch

   1 From 48d3ed67982d2d1cecb5b33bf396d21f6fd7b088 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jonas.gorski@gmail.com>
   3 Date: Tue, 14 Jun 2011 21:14:39 +0200
   4 Subject: [PATCH 39/79] MIPS: BCM63XX: add MISC register set definition
   5
   6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
   7 ---
   8  arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h  |   10 +++++++++-
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h   |    2 ++
  10  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |   10 ++++++++++
  11  3 files changed, 21 insertions(+), 1 deletion(-)
  12
  13 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  14 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
  15 @@ -129,7 +129,8 @@ enum bcm63xx_regs_set {
  16         RSET_PCMDMA,
  17         RSET_PCMDMAC,
  18         RSET_PCMDMAS,
  19 -       RSET_TRNG
  20 +       RSET_TRNG,
  21 +       RSET_MISC
  22  };
  23
  24  #define RSET_DSL_LMEM_SIZE             (64 * 1024 * 4)
  25 @@ -198,6 +199,7 @@ enum bcm63xx_regs_set {
  26  #define BCM_6338_PCMDMAC_BASE          (0xdeadbeef)
  27  #define BCM_6338_PCMDMAS_BASE          (0xdeadbeef)
  28  #define BCM_6338_TRNG_BASE             (0xdeadbeef)
  29 +#define BCM_6338_MISC_BASE             (0xdeadbeef)
  30
  31  /*
  32   * 6345 register sets base address
  33 @@ -242,6 +244,7 @@ enum bcm63xx_regs_set {
  34  #define BCM_6345_PCMDMAC_BASE          (0xdeadbeef)
  35  #define BCM_6345_PCMDMAS_BASE          (0xdeadbeef)
  36  #define BCM_6345_TRNG_BASE             (0xdeadbeef)
  37 +#define BCM_6345_MISC_BASE             (0xdeadbeef)
  38
  39  /*
  40   * 6348 register sets base address
  41 @@ -283,6 +286,7 @@ enum bcm63xx_regs_set {
  42  #define BCM_6348_PCMDMAC_BASE          (0xdeadbeef)
  43  #define BCM_6348_PCMDMAS_BASE          (0xdeadbeef)
  44  #define BCM_6348_TRNG_BASE             (0xdeadbeef)
  45 +#define BCM_6348_MISC_BASE             (0xdeadbeef)
  46
  47  /*
  48   * 6358 register sets base address
  49 @@ -324,6 +328,7 @@ enum bcm63xx_regs_set {
  50  #define BCM_6358_PCMDMAC_BASE          (0xfffe1900)
  51  #define BCM_6358_PCMDMAS_BASE          (0xfffe1a00)
  52  #define BCM_6358_TRNG_BASE             (0xdeadbeef)
  53 +#define BCM_6358_MISC_BASE             (0xdeadbeef)
  54
  55
  56  /*
  57 @@ -366,6 +371,7 @@ enum bcm63xx_regs_set {
  58  #define BCM_6368_PCMDMAC_BASE          (0xb0005a00)
  59  #define BCM_6368_PCMDMAS_BASE          (0xb0005c00)
  60  #define BCM_6368_TRNG_BASE             (0xb0004180)
  61 +#define BCM_6368_MISC_BASE             (0xdeadbeef)
  62
  63
  64  extern const unsigned long *bcm63xx_regs_base;
  65 @@ -412,6 +418,7 @@ extern const unsigned long *bcm63xx_regs
  66         __GEN_RSET_BASE(__cpu, PCMDMAC)                                 \
  67         __GEN_RSET_BASE(__cpu, PCMDMAS)                                 \
  68         __GEN_RSET_BASE(__cpu, TRNG)                                    \
  69 +       __GEN_RSET_BASE(__cpu, MISC)                                    \
  70         }
  71
  72  #define __GEN_CPU_REGS_TABLE(__cpu)                                    \
  73 @@ -451,6 +458,7 @@ extern const unsigned long *bcm63xx_regs
  74         [RSET_PCMDMAC]          = BCM_## __cpu ##_PCMDMAC_BASE,         \
  75         [RSET_PCMDMAS]          = BCM_## __cpu ##_PCMDMAS_BASE,         \
  76         [RSET_TRNG]             = BCM_## __cpu ##_TRNG_BASE,            \
  77 +       [RSET_MISC]             = BCM_## __cpu ##_MISC_BASE,            \
  78
  79
  80  static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
  81 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  82 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  83 @@ -91,5 +91,7 @@
  84  #define bcm_memc_writel(v, o)  bcm_rset_writel(RSET_MEMC, (v), (o))
  85  #define bcm_ddr_readl(o)       bcm_rset_readl(RSET_DDR, (o))
  86  #define bcm_ddr_writel(v, o)   bcm_rset_writel(RSET_DDR, (v), (o))
  87 +#define bcm_misc_readl(o)      bcm_rset_readl(RSET_MISC, (o))
  88 +#define bcm_misc_writel(v, o)  bcm_rset_writel(RSET_MISC, (v), (o))
  89
  90  #endif /* ! BCM63XX_IO_H_ */
  91 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  92 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  93 @@ -1116,4 +1116,14 @@
  94  #define TRNG_THRES                     0x0c
  95  #define TRNG_MASK                      0x10
  96
  97 +/*************************************************************************
  98 + * _REG relative to RSET_MISC
  99 + *************************************************************************/
 100 +
 101 +#define MISC_STRAPBUS_6328_REG         0x240
 102 +#define STRAPBUS_6328_FCVO_SHIFT       7
 103 +#define STRAPBUS_6328_FCVO_MASK                (0x1f << STRAPBUS_6328_FCVO_SHIFT)
 104 +#define STRAPBUS_6328_BOOT_SEL_SERIAL  (1 << 28)
 105 +#define STRAPBUS_6328_BOOT_SEL_NAND    (0 << 28)
 106 +
 107  #endif /* BCM63XX_REGS_H_ */