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[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.h
1 /*
2 * ar8216.h: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17 #ifndef __AR8216_H
18 #define __AR8216_H
19
20 #define BITS(_s, _n) (((1UL << (_n)) - 1) << _s)
21
22 #define AR8XXX_CAP_GIGE BIT(0)
23 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
24
25 #define AR8XXX_NUM_PHYS 5
26 #define AR8216_PORT_CPU 0
27 #define AR8216_NUM_PORTS 6
28 #define AR8216_NUM_VLANS 16
29 #define AR8316_NUM_VLANS 4096
30
31 /* size of the vlan table */
32 #define AR8X16_MAX_VLANS 128
33 #define AR8X16_PROBE_RETRIES 10
34 #define AR8X16_MAX_PORTS 8
35
36 /* Atheros specific MII registers */
37 #define MII_ATH_MMD_ADDR 0x0d
38 #define MII_ATH_MMD_DATA 0x0e
39 #define MII_ATH_DBG_ADDR 0x1d
40 #define MII_ATH_DBG_DATA 0x1e
41
42 #define AR8216_REG_CTRL 0x0000
43 #define AR8216_CTRL_REVISION BITS(0, 8)
44 #define AR8216_CTRL_REVISION_S 0
45 #define AR8216_CTRL_VERSION BITS(8, 8)
46 #define AR8216_CTRL_VERSION_S 8
47 #define AR8216_CTRL_RESET BIT(31)
48
49 #define AR8216_REG_FLOOD_MASK 0x002C
50 #define AR8216_FM_UNI_DEST_PORTS BITS(0, 6)
51 #define AR8216_FM_MULTI_DEST_PORTS BITS(16, 6)
52 #define AR8236_FM_CPU_BROADCAST_EN BIT(26)
53 #define AR8236_FM_CPU_BCAST_FWD_EN BIT(25)
54
55 #define AR8216_REG_GLOBAL_CTRL 0x0030
56 #define AR8216_GCTRL_MTU BITS(0, 11)
57 #define AR8236_GCTRL_MTU BITS(0, 14)
58 #define AR8316_GCTRL_MTU BITS(0, 14)
59
60 #define AR8216_REG_VTU 0x0040
61 #define AR8216_VTU_OP BITS(0, 3)
62 #define AR8216_VTU_OP_NOOP 0x0
63 #define AR8216_VTU_OP_FLUSH 0x1
64 #define AR8216_VTU_OP_LOAD 0x2
65 #define AR8216_VTU_OP_PURGE 0x3
66 #define AR8216_VTU_OP_REMOVE_PORT 0x4
67 #define AR8216_VTU_ACTIVE BIT(3)
68 #define AR8216_VTU_FULL BIT(4)
69 #define AR8216_VTU_PORT BITS(8, 4)
70 #define AR8216_VTU_PORT_S 8
71 #define AR8216_VTU_VID BITS(16, 12)
72 #define AR8216_VTU_VID_S 16
73 #define AR8216_VTU_PRIO BITS(28, 3)
74 #define AR8216_VTU_PRIO_S 28
75 #define AR8216_VTU_PRIO_EN BIT(31)
76
77 #define AR8216_REG_VTU_DATA 0x0044
78 #define AR8216_VTUDATA_MEMBER BITS(0, 10)
79 #define AR8236_VTUDATA_MEMBER BITS(0, 7)
80 #define AR8216_VTUDATA_VALID BIT(11)
81
82 #define AR8216_REG_ATU_FUNC0 0x0050
83 #define AR8216_ATU_OP BITS(0, 3)
84 #define AR8216_ATU_OP_NOOP 0x0
85 #define AR8216_ATU_OP_FLUSH 0x1
86 #define AR8216_ATU_OP_LOAD 0x2
87 #define AR8216_ATU_OP_PURGE 0x3
88 #define AR8216_ATU_OP_FLUSH_LOCKED 0x4
89 #define AR8216_ATU_OP_FLUSH_UNICAST 0x5
90 #define AR8216_ATU_OP_GET_NEXT 0x6
91 #define AR8216_ATU_ACTIVE BIT(3)
92 #define AR8216_ATU_PORT_NUM BITS(8, 4)
93 #define AR8216_ATU_FULL_VIO BIT(12)
94 #define AR8216_ATU_ADDR5 BITS(16, 8)
95 #define AR8216_ATU_ADDR5_S 16
96 #define AR8216_ATU_ADDR4 BITS(24, 8)
97 #define AR8216_ATU_ADDR4_S 24
98
99 #define AR8216_REG_ATU_FUNC1 0x0054
100 #define AR8216_ATU_ADDR3 BITS(0, 8)
101 #define AR8216_ATU_ADDR3_S 0
102 #define AR8216_ATU_ADDR2 BITS(8, 8)
103 #define AR8216_ATU_ADDR2_S 8
104 #define AR8216_ATU_ADDR1 BITS(16, 8)
105 #define AR8216_ATU_ADDR1_S 16
106 #define AR8216_ATU_ADDR0 BITS(24, 8)
107 #define AR8216_ATU_ADDR0_S 24
108
109 #define AR8216_REG_ATU_FUNC2 0x0058
110 #define AR8216_ATU_PORTS BITS(0, 6)
111 #define AR8216_ATU_PORT0 BIT(0)
112 #define AR8216_ATU_PORT1 BIT(1)
113 #define AR8216_ATU_PORT2 BIT(2)
114 #define AR8216_ATU_PORT3 BIT(3)
115 #define AR8216_ATU_PORT4 BIT(4)
116 #define AR8216_ATU_PORT5 BIT(5)
117 #define AR8216_ATU_STATUS BITS(16, 4)
118 #define AR8216_ATU_STATUS_S 16
119
120 #define AR8216_REG_ATU_CTRL 0x005C
121 #define AR8216_ATU_CTRL_AGE_EN BIT(17)
122 #define AR8216_ATU_CTRL_AGE_TIME BITS(0, 16)
123 #define AR8216_ATU_CTRL_AGE_TIME_S 0
124 #define AR8236_ATU_CTRL_RES BIT(20)
125
126 #define AR8216_REG_MIB_FUNC 0x0080
127 #define AR8216_MIB_TIMER BITS(0, 16)
128 #define AR8216_MIB_AT_HALF_EN BIT(16)
129 #define AR8216_MIB_BUSY BIT(17)
130 #define AR8216_MIB_FUNC BITS(24, 3)
131 #define AR8216_MIB_FUNC_S 24
132 #define AR8216_MIB_FUNC_NO_OP 0x0
133 #define AR8216_MIB_FUNC_FLUSH 0x1
134 #define AR8216_MIB_FUNC_CAPTURE 0x3
135 #define AR8236_MIB_EN BIT(30)
136
137 #define AR8216_REG_GLOBAL_CPUPORT 0x0078
138 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT BITS(4, 4)
139 #define AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S 4
140
141 #define AR8216_PORT_OFFSET(_i) (0x0100 * (_i + 1))
142 #define AR8216_REG_PORT_STATUS(_i) (AR8216_PORT_OFFSET(_i) + 0x0000)
143 #define AR8216_PORT_STATUS_SPEED BITS(0,2)
144 #define AR8216_PORT_STATUS_SPEED_S 0
145 #define AR8216_PORT_STATUS_TXMAC BIT(2)
146 #define AR8216_PORT_STATUS_RXMAC BIT(3)
147 #define AR8216_PORT_STATUS_TXFLOW BIT(4)
148 #define AR8216_PORT_STATUS_RXFLOW BIT(5)
149 #define AR8216_PORT_STATUS_DUPLEX BIT(6)
150 #define AR8216_PORT_STATUS_LINK_UP BIT(8)
151 #define AR8216_PORT_STATUS_LINK_AUTO BIT(9)
152 #define AR8216_PORT_STATUS_LINK_PAUSE BIT(10)
153
154 #define AR8216_REG_PORT_CTRL(_i) (AR8216_PORT_OFFSET(_i) + 0x0004)
155
156 /* port forwarding state */
157 #define AR8216_PORT_CTRL_STATE BITS(0, 3)
158 #define AR8216_PORT_CTRL_STATE_S 0
159
160 #define AR8216_PORT_CTRL_LEARN_LOCK BIT(7)
161
162 /* egress 802.1q mode */
163 #define AR8216_PORT_CTRL_VLAN_MODE BITS(8, 2)
164 #define AR8216_PORT_CTRL_VLAN_MODE_S 8
165
166 #define AR8216_PORT_CTRL_IGMP_SNOOP BIT(10)
167 #define AR8216_PORT_CTRL_HEADER BIT(11)
168 #define AR8216_PORT_CTRL_MAC_LOOP BIT(12)
169 #define AR8216_PORT_CTRL_SINGLE_VLAN BIT(13)
170 #define AR8216_PORT_CTRL_LEARN BIT(14)
171 #define AR8216_PORT_CTRL_MIRROR_TX BIT(16)
172 #define AR8216_PORT_CTRL_MIRROR_RX BIT(17)
173
174 #define AR8216_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET(_i) + 0x0008)
175
176 #define AR8216_PORT_VLAN_DEFAULT_ID BITS(0, 12)
177 #define AR8216_PORT_VLAN_DEFAULT_ID_S 0
178
179 #define AR8216_PORT_VLAN_DEST_PORTS BITS(16, 9)
180 #define AR8216_PORT_VLAN_DEST_PORTS_S 16
181
182 /* bit0 added to the priority field of egress frames */
183 #define AR8216_PORT_VLAN_TX_PRIO BIT(27)
184
185 /* port default priority */
186 #define AR8216_PORT_VLAN_PRIORITY BITS(28, 2)
187 #define AR8216_PORT_VLAN_PRIORITY_S 28
188
189 /* ingress 802.1q mode */
190 #define AR8216_PORT_VLAN_MODE BITS(30, 2)
191 #define AR8216_PORT_VLAN_MODE_S 30
192
193 #define AR8216_REG_PORT_RATE(_i) (AR8216_PORT_OFFSET(_i) + 0x000c)
194 #define AR8216_REG_PORT_PRIO(_i) (AR8216_PORT_OFFSET(_i) + 0x0010)
195
196 #define AR8216_STATS_RXBROAD 0x00
197 #define AR8216_STATS_RXPAUSE 0x04
198 #define AR8216_STATS_RXMULTI 0x08
199 #define AR8216_STATS_RXFCSERR 0x0c
200 #define AR8216_STATS_RXALIGNERR 0x10
201 #define AR8216_STATS_RXRUNT 0x14
202 #define AR8216_STATS_RXFRAGMENT 0x18
203 #define AR8216_STATS_RX64BYTE 0x1c
204 #define AR8216_STATS_RX128BYTE 0x20
205 #define AR8216_STATS_RX256BYTE 0x24
206 #define AR8216_STATS_RX512BYTE 0x28
207 #define AR8216_STATS_RX1024BYTE 0x2c
208 #define AR8216_STATS_RXMAXBYTE 0x30
209 #define AR8216_STATS_RXTOOLONG 0x34
210 #define AR8216_STATS_RXGOODBYTE 0x38
211 #define AR8216_STATS_RXBADBYTE 0x40
212 #define AR8216_STATS_RXOVERFLOW 0x48
213 #define AR8216_STATS_FILTERED 0x4c
214 #define AR8216_STATS_TXBROAD 0x50
215 #define AR8216_STATS_TXPAUSE 0x54
216 #define AR8216_STATS_TXMULTI 0x58
217 #define AR8216_STATS_TXUNDERRUN 0x5c
218 #define AR8216_STATS_TX64BYTE 0x60
219 #define AR8216_STATS_TX128BYTE 0x64
220 #define AR8216_STATS_TX256BYTE 0x68
221 #define AR8216_STATS_TX512BYTE 0x6c
222 #define AR8216_STATS_TX1024BYTE 0x70
223 #define AR8216_STATS_TXMAXBYTE 0x74
224 #define AR8216_STATS_TXOVERSIZE 0x78
225 #define AR8216_STATS_TXBYTE 0x7c
226 #define AR8216_STATS_TXCOLLISION 0x84
227 #define AR8216_STATS_TXABORTCOL 0x88
228 #define AR8216_STATS_TXMULTICOL 0x8c
229 #define AR8216_STATS_TXSINGLECOL 0x90
230 #define AR8216_STATS_TXEXCDEFER 0x94
231 #define AR8216_STATS_TXDEFER 0x98
232 #define AR8216_STATS_TXLATECOL 0x9c
233
234 #define AR8236_REG_PORT_VLAN(_i) (AR8216_PORT_OFFSET((_i)) + 0x0008)
235 #define AR8236_PORT_VLAN_DEFAULT_ID BITS(16, 12)
236 #define AR8236_PORT_VLAN_DEFAULT_ID_S 16
237 #define AR8236_PORT_VLAN_PRIORITY BITS(29, 3)
238 #define AR8236_PORT_VLAN_PRIORITY_S 28
239
240 #define AR8236_REG_PORT_VLAN2(_i) (AR8216_PORT_OFFSET((_i)) + 0x000c)
241 #define AR8236_PORT_VLAN2_MEMBER BITS(16, 7)
242 #define AR8236_PORT_VLAN2_MEMBER_S 16
243 #define AR8236_PORT_VLAN2_TX_PRIO BIT(23)
244 #define AR8236_PORT_VLAN2_VLAN_MODE BITS(30, 2)
245 #define AR8236_PORT_VLAN2_VLAN_MODE_S 30
246
247 #define AR8236_STATS_RXBROAD 0x00
248 #define AR8236_STATS_RXPAUSE 0x04
249 #define AR8236_STATS_RXMULTI 0x08
250 #define AR8236_STATS_RXFCSERR 0x0c
251 #define AR8236_STATS_RXALIGNERR 0x10
252 #define AR8236_STATS_RXRUNT 0x14
253 #define AR8236_STATS_RXFRAGMENT 0x18
254 #define AR8236_STATS_RX64BYTE 0x1c
255 #define AR8236_STATS_RX128BYTE 0x20
256 #define AR8236_STATS_RX256BYTE 0x24
257 #define AR8236_STATS_RX512BYTE 0x28
258 #define AR8236_STATS_RX1024BYTE 0x2c
259 #define AR8236_STATS_RX1518BYTE 0x30
260 #define AR8236_STATS_RXMAXBYTE 0x34
261 #define AR8236_STATS_RXTOOLONG 0x38
262 #define AR8236_STATS_RXGOODBYTE 0x3c
263 #define AR8236_STATS_RXBADBYTE 0x44
264 #define AR8236_STATS_RXOVERFLOW 0x4c
265 #define AR8236_STATS_FILTERED 0x50
266 #define AR8236_STATS_TXBROAD 0x54
267 #define AR8236_STATS_TXPAUSE 0x58
268 #define AR8236_STATS_TXMULTI 0x5c
269 #define AR8236_STATS_TXUNDERRUN 0x60
270 #define AR8236_STATS_TX64BYTE 0x64
271 #define AR8236_STATS_TX128BYTE 0x68
272 #define AR8236_STATS_TX256BYTE 0x6c
273 #define AR8236_STATS_TX512BYTE 0x70
274 #define AR8236_STATS_TX1024BYTE 0x74
275 #define AR8236_STATS_TX1518BYTE 0x78
276 #define AR8236_STATS_TXMAXBYTE 0x7c
277 #define AR8236_STATS_TXOVERSIZE 0x80
278 #define AR8236_STATS_TXBYTE 0x84
279 #define AR8236_STATS_TXCOLLISION 0x8c
280 #define AR8236_STATS_TXABORTCOL 0x90
281 #define AR8236_STATS_TXMULTICOL 0x94
282 #define AR8236_STATS_TXSINGLECOL 0x98
283 #define AR8236_STATS_TXEXCDEFER 0x9c
284 #define AR8236_STATS_TXDEFER 0xa0
285 #define AR8236_STATS_TXLATECOL 0xa4
286
287 #define AR8316_REG_POSTRIP 0x0008
288 #define AR8316_POSTRIP_MAC0_GMII_EN BIT(0)
289 #define AR8316_POSTRIP_MAC0_RGMII_EN BIT(1)
290 #define AR8316_POSTRIP_PHY4_GMII_EN BIT(2)
291 #define AR8316_POSTRIP_PHY4_RGMII_EN BIT(3)
292 #define AR8316_POSTRIP_MAC0_MAC_MODE BIT(4)
293 #define AR8316_POSTRIP_RTL_MODE BIT(5)
294 #define AR8316_POSTRIP_RGMII_RXCLK_DELAY_EN BIT(6)
295 #define AR8316_POSTRIP_RGMII_TXCLK_DELAY_EN BIT(7)
296 #define AR8316_POSTRIP_SERDES_EN BIT(8)
297 #define AR8316_POSTRIP_SEL_ANA_RST BIT(9)
298 #define AR8316_POSTRIP_GATE_25M_EN BIT(10)
299 #define AR8316_POSTRIP_SEL_CLK25M BIT(11)
300 #define AR8316_POSTRIP_HIB_PULSE_HW BIT(12)
301 #define AR8316_POSTRIP_DBG_MODE_I BIT(13)
302 #define AR8316_POSTRIP_MAC5_MAC_MODE BIT(14)
303 #define AR8316_POSTRIP_MAC5_PHY_MODE BIT(15)
304 #define AR8316_POSTRIP_POWER_DOWN_HW BIT(16)
305 #define AR8316_POSTRIP_LPW_STATE_EN BIT(17)
306 #define AR8316_POSTRIP_MAN_EN BIT(18)
307 #define AR8316_POSTRIP_PHY_PLL_ON BIT(19)
308 #define AR8316_POSTRIP_LPW_EXIT BIT(20)
309 #define AR8316_POSTRIP_TXDELAY_S0 BIT(21)
310 #define AR8316_POSTRIP_TXDELAY_S1 BIT(22)
311 #define AR8316_POSTRIP_RXDELAY_S0 BIT(23)
312 #define AR8316_POSTRIP_LED_OPEN_EN BIT(24)
313 #define AR8316_POSTRIP_SPI_EN BIT(25)
314 #define AR8316_POSTRIP_RXDELAY_S1 BIT(26)
315 #define AR8316_POSTRIP_POWER_ON_SEL BIT(31)
316
317 /* port speed */
318 enum {
319 AR8216_PORT_SPEED_10M = 0,
320 AR8216_PORT_SPEED_100M = 1,
321 AR8216_PORT_SPEED_1000M = 2,
322 AR8216_PORT_SPEED_ERR = 3,
323 };
324
325 /* ingress 802.1q mode */
326 enum {
327 AR8216_IN_PORT_ONLY = 0,
328 AR8216_IN_PORT_FALLBACK = 1,
329 AR8216_IN_VLAN_ONLY = 2,
330 AR8216_IN_SECURE = 3
331 };
332
333 /* egress 802.1q mode */
334 enum {
335 AR8216_OUT_KEEP = 0,
336 AR8216_OUT_STRIP_VLAN = 1,
337 AR8216_OUT_ADD_VLAN = 2
338 };
339
340 /* port forwarding state */
341 enum {
342 AR8216_PORT_STATE_DISABLED = 0,
343 AR8216_PORT_STATE_BLOCK = 1,
344 AR8216_PORT_STATE_LISTEN = 2,
345 AR8216_PORT_STATE_LEARN = 3,
346 AR8216_PORT_STATE_FORWARD = 4
347 };
348
349 enum {
350 AR8XXX_VER_AR8216 = 0x01,
351 AR8XXX_VER_AR8236 = 0x03,
352 AR8XXX_VER_AR8316 = 0x10,
353 AR8XXX_VER_AR8327 = 0x12,
354 AR8XXX_VER_AR8337 = 0x13,
355 };
356
357 #define AR8XXX_NUM_ARL_RECORDS 100
358
359 enum arl_op {
360 AR8XXX_ARL_INITIALIZE,
361 AR8XXX_ARL_GET_NEXT
362 };
363
364 struct arl_entry {
365 u8 port;
366 u8 mac[6];
367 };
368
369 struct ar8xxx_priv;
370
371 struct ar8xxx_mib_desc {
372 unsigned int size;
373 unsigned int offset;
374 const char *name;
375 };
376
377 struct ar8xxx_chip {
378 unsigned long caps;
379 bool config_at_probe;
380 bool mii_lo_first;
381
382 /* parameters to calculate REG_PORT_STATS_BASE */
383 unsigned reg_port_stats_start;
384 unsigned reg_port_stats_length;
385
386 int (*hw_init)(struct ar8xxx_priv *priv);
387 void (*cleanup)(struct ar8xxx_priv *priv);
388
389 const char *name;
390 int vlans;
391 int ports;
392 const struct switch_dev_ops *swops;
393
394 void (*init_globals)(struct ar8xxx_priv *priv);
395 void (*init_port)(struct ar8xxx_priv *priv, int port);
396 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
397 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
398 u32 (*read_port_eee_status)(struct ar8xxx_priv *priv, int port);
399 int (*atu_flush)(struct ar8xxx_priv *priv);
400 void (*vtu_flush)(struct ar8xxx_priv *priv);
401 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
402 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
403 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
404 void (*get_arl_entry)(struct ar8xxx_priv *priv, struct arl_entry *a,
405 u32 *status, enum arl_op op);
406 int (*sw_hw_apply)(struct switch_dev *dev);
407
408 const struct ar8xxx_mib_desc *mib_decs;
409 unsigned num_mibs;
410 unsigned mib_func;
411 };
412
413 struct ar8xxx_priv {
414 struct switch_dev dev;
415 struct mii_bus *mii_bus;
416 struct phy_device *phy;
417
418 int (*get_port_link)(unsigned port);
419
420 const struct net_device_ops *ndo_old;
421 struct net_device_ops ndo;
422 struct mutex reg_mutex;
423 u8 chip_ver;
424 u8 chip_rev;
425 const struct ar8xxx_chip *chip;
426 void *chip_data;
427 bool initialized;
428 bool port4_phy;
429 char buf[2048];
430 struct arl_entry arl_table[AR8XXX_NUM_ARL_RECORDS];
431 char arl_buf[AR8XXX_NUM_ARL_RECORDS * 32 + 256];
432 bool link_up[AR8X16_MAX_PORTS];
433
434 bool init;
435
436 struct mutex mib_lock;
437 struct delayed_work mib_work;
438 int mib_next_port;
439 u64 *mib_stats;
440
441 struct list_head list;
442 unsigned int use_count;
443
444 /* all fields below are cleared on reset */
445 bool vlan;
446 u16 vlan_id[AR8X16_MAX_VLANS];
447 u8 vlan_table[AR8X16_MAX_VLANS];
448 u8 vlan_tagged;
449 u16 pvid[AR8X16_MAX_PORTS];
450
451 /* mirroring */
452 bool mirror_rx;
453 bool mirror_tx;
454 int source_port;
455 int monitor_port;
456 };
457
458 u32
459 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum);
460 void
461 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val);
462 u32
463 ar8xxx_read(struct ar8xxx_priv *priv, int reg);
464 void
465 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val);
466 u32
467 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
468
469 void
470 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
471 u16 dbg_addr, u16 dbg_data);
472 void
473 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data);
474 u16
475 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr);
476 void
477 ar8xxx_phy_init(struct ar8xxx_priv *priv);
478 int
479 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
480 struct switch_val *val);
481 int
482 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
483 struct switch_val *val);
484 int
485 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
486 const struct switch_attr *attr,
487 struct switch_val *val);
488 int
489 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
490 const struct switch_attr *attr,
491 struct switch_val *val);
492 int
493 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
494 const struct switch_attr *attr,
495 struct switch_val *val);
496 int
497 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
498 const struct switch_attr *attr,
499 struct switch_val *val);
500 int
501 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
502 const struct switch_attr *attr,
503 struct switch_val *val);
504 int
505 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
506 const struct switch_attr *attr,
507 struct switch_val *val);
508 int
509 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
510 const struct switch_attr *attr,
511 struct switch_val *val);
512 int
513 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
514 const struct switch_attr *attr,
515 struct switch_val *val);
516 int
517 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
518 const struct switch_attr *attr,
519 struct switch_val *val);
520 int
521 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan);
522 int
523 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan);
524 int
525 ar8xxx_sw_hw_apply(struct switch_dev *dev);
526 int
527 ar8xxx_sw_reset_switch(struct switch_dev *dev);
528 int
529 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
530 struct switch_port_link *link);
531 int
532 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
533 const struct switch_attr *attr,
534 struct switch_val *val);
535 int
536 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
537 const struct switch_attr *attr,
538 struct switch_val *val);
539 int
540 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
541 const struct switch_attr *attr,
542 struct switch_val *val);
543 int
544 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
545
546 static inline struct ar8xxx_priv *
547 swdev_to_ar8xxx(struct switch_dev *swdev)
548 {
549 return container_of(swdev, struct ar8xxx_priv, dev);
550 }
551
552 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
553 {
554 return priv->chip->caps & AR8XXX_CAP_GIGE;
555 }
556
557 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
558 {
559 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
560 }
561
562 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
563 {
564 return priv->chip_ver == AR8XXX_VER_AR8216;
565 }
566
567 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
568 {
569 return priv->chip_ver == AR8XXX_VER_AR8236;
570 }
571
572 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
573 {
574 return priv->chip_ver == AR8XXX_VER_AR8316;
575 }
576
577 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
578 {
579 return priv->chip_ver == AR8XXX_VER_AR8327;
580 }
581
582 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
583 {
584 return priv->chip_ver == AR8XXX_VER_AR8337;
585 }
586
587 static inline void
588 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
589 {
590 ar8xxx_rmw(priv, reg, 0, val);
591 }
592
593 static inline void
594 ar8xxx_reg_clear(struct ar8xxx_priv *priv, int reg, u32 val)
595 {
596 ar8xxx_rmw(priv, reg, val, 0);
597 }
598
599 static inline void
600 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
601 {
602 regaddr >>= 1;
603 *r1 = regaddr & 0x1e;
604
605 regaddr >>= 5;
606 *r2 = regaddr & 0x7;
607
608 regaddr >>= 3;
609 *page = regaddr & 0x1ff;
610 }
611
612 static inline void
613 wait_for_page_switch(void)
614 {
615 udelay(5);
616 }
617
618 #endif
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