projects / openwrt / svn-archive / archive.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
kernel: update bcma and ssb to version master-2011-07-22 from wireless-testing
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.37 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -383,6 +383,35 @@ static int ssb_device_uevent(struct devi
4 ssb_dev->id.revision);
5 }
6
7 +#define ssb_config_attr(attrib, field, format_string) \
8 +static ssize_t \
9 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
10 +{ \
11 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
12 +}
13 +
14 +ssb_config_attr(core_num, core_index, "%u\n")
15 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
16 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
17 +ssb_config_attr(revision, id.revision, "%u\n")
18 +ssb_config_attr(irq, irq, "%u\n")
19 +static ssize_t
20 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
21 +{
22 + return sprintf(buf, "%s\n",
23 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
24 +}
25 +
26 +static struct device_attribute ssb_device_attrs[] = {
27 + __ATTR_RO(name),
28 + __ATTR_RO(core_num),
29 + __ATTR_RO(coreid),
30 + __ATTR_RO(vendor),
31 + __ATTR_RO(revision),
32 + __ATTR_RO(irq),
33 + __ATTR_NULL,
34 +};
35 +
36 static struct bus_type ssb_bustype = {
37 .name = "ssb",
38 .match = ssb_bus_match,
39 @@ -392,6 +421,7 @@ static struct bus_type ssb_bustype = {
40 .suspend = ssb_device_suspend,
41 .resume = ssb_device_resume,
42 .uevent = ssb_device_uevent,
43 + .dev_attrs = ssb_device_attrs,
44 };
45
46 static void ssb_buses_lock(void)
47 @@ -527,7 +557,7 @@ error:
48 }
49
50 /* Needs ssb_buses_lock() */
51 -static int ssb_attach_queued_buses(void)
52 +static int __devinit ssb_attach_queued_buses(void)
53 {
54 struct ssb_bus *bus, *n;
55 int err = 0;
56 @@ -738,9 +768,9 @@ out:
57 return err;
58 }
59
60 -static int ssb_bus_register(struct ssb_bus *bus,
61 - ssb_invariants_func_t get_invariants,
62 - unsigned long baseaddr)
63 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
64 + ssb_invariants_func_t get_invariants,
65 + unsigned long baseaddr)
66 {
67 int err;
68
69 @@ -821,8 +851,8 @@ err_disable_xtal:
70 }
71
72 #ifdef CONFIG_SSB_PCIHOST
73 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
74 - struct pci_dev *host_pci)
75 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
76 + struct pci_dev *host_pci)
77 {
78 int err;
79
80 @@ -845,9 +875,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
81 #endif /* CONFIG_SSB_PCIHOST */
82
83 #ifdef CONFIG_SSB_PCMCIAHOST
84 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
85 - struct pcmcia_device *pcmcia_dev,
86 - unsigned long baseaddr)
87 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
88 + struct pcmcia_device *pcmcia_dev,
89 + unsigned long baseaddr)
90 {
91 int err;
92
93 @@ -867,8 +897,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
94 #endif /* CONFIG_SSB_PCMCIAHOST */
95
96 #ifdef CONFIG_SSB_SDIOHOST
97 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
98 - unsigned int quirks)
99 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
100 + struct sdio_func *func,
101 + unsigned int quirks)
102 {
103 int err;
104
105 @@ -888,9 +919,9 @@ int ssb_bus_sdiobus_register(struct ssb_
106 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
107 #endif /* CONFIG_SSB_PCMCIAHOST */
108
109 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
110 - unsigned long baseaddr,
111 - ssb_invariants_func_t get_invariants)
112 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
113 + unsigned long baseaddr,
114 + ssb_invariants_func_t get_invariants)
115 {
116 int err;
117
118 @@ -971,8 +1002,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
119 switch (plltype) {
120 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
121 if (m & SSB_CHIPCO_CLK_T6_MMASK)
122 - return SSB_CHIPCO_CLK_T6_M0;
123 - return SSB_CHIPCO_CLK_T6_M1;
124 + return SSB_CHIPCO_CLK_T6_M1;
125 + return SSB_CHIPCO_CLK_T6_M0;
126 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
127 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
128 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
129 @@ -1087,23 +1118,22 @@ static u32 ssb_tmslow_reject_bitmask(str
130 {
131 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
132
133 - /* The REJECT bit changed position in TMSLOW between
134 - * Backplane revisions. */
135 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
136 switch (rev) {
137 case SSB_IDLOW_SSBREV_22:
138 - return SSB_TMSLOW_REJECT_22;
139 + case SSB_IDLOW_SSBREV_24:
140 + case SSB_IDLOW_SSBREV_26:
141 + return SSB_TMSLOW_REJECT;
142 case SSB_IDLOW_SSBREV_23:
143 return SSB_TMSLOW_REJECT_23;
144 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
145 - case SSB_IDLOW_SSBREV_25: /* same here */
146 - case SSB_IDLOW_SSBREV_26: /* same here */
147 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
148 case SSB_IDLOW_SSBREV_27: /* same here */
149 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
150 + return SSB_TMSLOW_REJECT; /* this is a guess */
151 default:
152 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
153 WARN_ON(1);
154 }
155 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
156 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
157 }
158
159 int ssb_device_is_enabled(struct ssb_device *dev)
160 @@ -1162,10 +1192,10 @@ void ssb_device_enable(struct ssb_device
161 }
162 EXPORT_SYMBOL(ssb_device_enable);
163
164 -/* Wait for a bit in a register to get set or unset.
165 +/* Wait for bitmask in a register to get set or cleared.
166 * timeout is in units of ten-microseconds */
167 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
168 - int timeout, int set)
169 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
170 + int timeout, int set)
171 {
172 int i;
173 u32 val;
174 @@ -1173,7 +1203,7 @@ static int ssb_wait_bit(struct ssb_devic
175 for (i = 0; i < timeout; i++) {
176 val = ssb_read32(dev, reg);
177 if (set) {
178 - if (val & bitmask)
179 + if ((val & bitmask) == bitmask)
180 return 0;
181 } else {
182 if (!(val & bitmask))
183 @@ -1190,20 +1220,38 @@ static int ssb_wait_bit(struct ssb_devic
184
185 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
186 {
187 - u32 reject;
188 + u32 reject, val;
189
190 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
191 return;
192
193 reject = ssb_tmslow_reject_bitmask(dev);
194 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
195 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
196 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
197 - ssb_write32(dev, SSB_TMSLOW,
198 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
199 - reject | SSB_TMSLOW_RESET |
200 - core_specific_flags);
201 - ssb_flush_tmslow(dev);
202 +
203 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
204 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
205 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
206 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
207 +
208 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
209 + val = ssb_read32(dev, SSB_IMSTATE);
210 + val |= SSB_IMSTATE_REJECT;
211 + ssb_write32(dev, SSB_IMSTATE, val);
212 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
213 + 0);
214 + }
215 +
216 + ssb_write32(dev, SSB_TMSLOW,
217 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
218 + reject | SSB_TMSLOW_RESET |
219 + core_specific_flags);
220 + ssb_flush_tmslow(dev);
221 +
222 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
223 + val = ssb_read32(dev, SSB_IMSTATE);
224 + val &= ~SSB_IMSTATE_REJECT;
225 + ssb_write32(dev, SSB_IMSTATE, val);
226 + }
227 + }
228
229 ssb_write32(dev, SSB_TMSLOW,
230 reject | SSB_TMSLOW_RESET |
231 @@ -1218,7 +1266,10 @@ u32 ssb_dma_translation(struct ssb_devic
232 case SSB_BUSTYPE_SSB:
233 return 0;
234 case SSB_BUSTYPE_PCI:
235 - return SSB_PCI_DMA;
236 + if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
237 + return SSB_PCIE_DMA_H32;
238 + else
239 + return SSB_PCI_DMA;
240 default:
241 __ssb_dma_not_implemented(dev);
242 }
243 @@ -1261,20 +1312,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
244
245 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
246 {
247 - struct ssb_chipcommon *cc;
248 int err;
249 enum ssb_clkmode mode;
250
251 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
252 if (err)
253 goto error;
254 - cc = &bus->chipco;
255 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
256 - ssb_chipco_set_clockmode(cc, mode);
257
258 #ifdef CONFIG_SSB_DEBUG
259 bus->powered_up = 1;
260 #endif
261 +
262 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
263 + ssb_chipco_set_clockmode(&bus->chipco, mode);
264 +
265 return 0;
266 error:
267 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
268 @@ -1282,6 +1333,37 @@ error:
269 }
270 EXPORT_SYMBOL(ssb_bus_powerup);
271
272 +static void ssb_broadcast_value(struct ssb_device *dev,
273 + u32 address, u32 data)
274 +{
275 +#ifdef CONFIG_SSB_DRIVER_PCICORE
276 + /* This is used for both, PCI and ChipCommon core, so be careful. */
277 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
278 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
279 +#endif
280 +
281 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
282 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
283 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
284 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
285 +}
286 +
287 +void ssb_commit_settings(struct ssb_bus *bus)
288 +{
289 + struct ssb_device *dev;
290 +
291 +#ifdef CONFIG_SSB_DRIVER_PCICORE
292 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
293 +#else
294 + dev = bus->chipco.dev;
295 +#endif
296 + if (WARN_ON(!dev))
297 + return;
298 + /* This forces an update of the cached registers. */
299 + ssb_broadcast_value(dev, 0xFD8, 0);
300 +}
301 +EXPORT_SYMBOL(ssb_commit_settings);
302 +
303 u32 ssb_admatch_base(u32 adm)
304 {
305 u32 base = 0;
306 --- a/drivers/ssb/pci.c
307 +++ b/drivers/ssb/pci.c
308 @@ -406,6 +406,46 @@ static void sprom_extract_r123(struct ss
309 out->antenna_gain.ghz5.a3 = gain;
310 }
311
312 +/* Revs 4 5 and 8 have partially shared layout */
313 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
314 +{
315 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
316 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
317 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
318 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
319 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
320 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
321 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
322 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
323 +
324 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
325 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
326 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
327 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
328 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
329 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
330 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
331 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
332 +
333 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
334 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
335 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
336 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
337 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
338 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
339 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
340 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
341 +
342 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
343 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
344 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
345 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
346 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
347 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
348 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
349 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
350 +}
351 +
352 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
353 {
354 int i;
355 @@ -428,10 +468,14 @@ static void sprom_extract_r45(struct ssb
356 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
357 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
358 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
359 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
360 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
361 } else {
362 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
363 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
364 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
365 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
366 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
367 }
368 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
369 SSB_SPROM4_ANTAVAIL_A_SHIFT);
370 @@ -471,6 +515,8 @@ static void sprom_extract_r45(struct ssb
371 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
372 sizeof(out->antenna_gain.ghz5));
373
374 + sprom_extract_r458(out, in);
375 +
376 /* TODO - get remaining rev 4 stuff needed */
377 }
378
379 @@ -561,6 +607,8 @@ static void sprom_extract_r8(struct ssb_
380 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
381 sizeof(out->antenna_gain.ghz5));
382
383 + sprom_extract_r458(out, in);
384 +
385 /* TODO - get remaining rev 8 stuff needed */
386 }
387
388 @@ -573,37 +621,34 @@ static int sprom_extract(struct ssb_bus
389 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
390 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
391 memset(out->et1mac, 0xFF, 6);
392 +
393 if ((bus->chip_id & 0xFF00) == 0x4400) {
394 /* Workaround: The BCM44XX chip has a stupid revision
395 * number stored in the SPROM.
396 * Always extract r1. */
397 out->revision = 1;
398 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
399 + }
400 +
401 + switch (out->revision) {
402 + case 1:
403 + case 2:
404 + case 3:
405 sprom_extract_r123(out, in);
406 - } else if (bus->chip_id == 0x4321) {
407 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
408 - out->revision = 4;
409 + break;
410 + case 4:
411 + case 5:
412 sprom_extract_r45(out, in);
413 - } else {
414 - switch (out->revision) {
415 - case 1:
416 - case 2:
417 - case 3:
418 - sprom_extract_r123(out, in);
419 - break;
420 - case 4:
421 - case 5:
422 - sprom_extract_r45(out, in);
423 - break;
424 - case 8:
425 - sprom_extract_r8(out, in);
426 - break;
427 - default:
428 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
429 - " revision %d detected. Will extract"
430 - " v1\n", out->revision);
431 - out->revision = 1;
432 - sprom_extract_r123(out, in);
433 - }
434 + break;
435 + case 8:
436 + sprom_extract_r8(out, in);
437 + break;
438 + default:
439 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
440 + " revision %d detected. Will extract"
441 + " v1\n", out->revision);
442 + out->revision = 1;
443 + sprom_extract_r123(out, in);
444 }
445
446 if (out->boardflags_lo == 0xFFFF)
447 @@ -617,15 +662,14 @@ static int sprom_extract(struct ssb_bus
448 static int ssb_pci_sprom_get(struct ssb_bus *bus,
449 struct ssb_sprom *sprom)
450 {
451 - const struct ssb_sprom *fallback;
452 - int err = -ENOMEM;
453 + int err;
454 u16 *buf;
455
456 if (!ssb_is_sprom_available(bus)) {
457 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
458 return -ENODEV;
459 }
460 - if (bus->chipco.dev) { /* can be unavailible! */
461 + if (bus->chipco.dev) { /* can be unavailable! */
462 /*
463 * get SPROM offset: SSB_SPROM_BASE1 except for
464 * chipcommon rev >= 31 or chip ID is 0x4312 and
465 @@ -645,7 +689,7 @@ static int ssb_pci_sprom_get(struct ssb_
466
467 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
468 if (!buf)
469 - goto out;
470 + return -ENOMEM;
471 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
472 sprom_do_read(bus, buf);
473 err = sprom_check_crc(buf, bus->sprom_size);
474 @@ -655,17 +699,24 @@ static int ssb_pci_sprom_get(struct ssb_
475 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
476 GFP_KERNEL);
477 if (!buf)
478 - goto out;
479 + return -ENOMEM;
480 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
481 sprom_do_read(bus, buf);
482 err = sprom_check_crc(buf, bus->sprom_size);
483 if (err) {
484 /* All CRC attempts failed.
485 * Maybe there is no SPROM on the device?
486 - * If we have a fallback, use that. */
487 - fallback = ssb_get_fallback_sprom();
488 - if (fallback) {
489 - memcpy(sprom, fallback, sizeof(*sprom));
490 + * Now we ask the arch code if there is some sprom
491 + * available for this device in some other storage */
492 + err = ssb_fill_sprom_with_fallback(bus, sprom);
493 + if (err) {
494 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
495 + " fallback SPROM failed (err %d)\n",
496 + err);
497 + } else {
498 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
499 + " revision %d provided by"
500 + " platform.\n", sprom->revision);
501 err = 0;
502 goto out_free;
503 }
504 @@ -677,19 +728,15 @@ static int ssb_pci_sprom_get(struct ssb_
505
506 out_free:
507 kfree(buf);
508 -out:
509 return err;
510 }
511
512 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
513 struct ssb_boardinfo *bi)
514 {
515 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
516 - &bi->vendor);
517 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
518 - &bi->type);
519 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
520 - &bi->rev);
521 + bi->vendor = bus->host_pci->subsystem_vendor;
522 + bi->type = bus->host_pci->subsystem_device;
523 + bi->rev = bus->host_pci->revision;
524 }
525
526 int ssb_pci_get_invariants(struct ssb_bus *bus,
527 --- a/drivers/ssb/pcihost_wrapper.c
528 +++ b/drivers/ssb/pcihost_wrapper.c
529 @@ -53,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
530 # define ssb_pcihost_resume NULL
531 #endif /* CONFIG_PM */
532
533 -static int ssb_pcihost_probe(struct pci_dev *dev,
534 - const struct pci_device_id *id)
535 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
536 + const struct pci_device_id *id)
537 {
538 struct ssb_bus *ssb;
539 int err = -ENOMEM;
540 const char *name;
541 + u32 val;
542
543 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
544 if (!ssb)
545 @@ -74,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
546 goto err_pci_disable;
547 pci_set_master(dev);
548
549 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
550 + * PCI Tx retries from interfering with C3 CPU state */
551 + pci_read_config_dword(dev, 0x40, &val);
552 + if ((val & 0x0000ff00) != 0)
553 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
554 +
555 err = ssb_bus_pcibus_register(ssb, dev);
556 if (err)
557 goto err_pci_release_regions;
558 @@ -103,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
559 pci_set_drvdata(dev, NULL);
560 }
561
562 -int ssb_pcihost_register(struct pci_driver *driver)
563 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
564 {
565 driver->probe = ssb_pcihost_probe;
566 driver->remove = ssb_pcihost_remove;
567 --- a/drivers/ssb/scan.c
568 +++ b/drivers/ssb/scan.c
569 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
570 #ifdef CONFIG_SSB_PCIHOST
571 if (bus->bustype == SSB_BUSTYPE_PCI) {
572 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
573 - bus->host_pci->device == 0x4324)
574 + ((bus->host_pci->device == 0x4313) ||
575 + (bus->host_pci->device == 0x431A) ||
576 + (bus->host_pci->device == 0x4321) ||
577 + (bus->host_pci->device == 0x4324)))
578 return 1;
579 }
580 #endif /* CONFIG_SSB_PCIHOST */
581 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
582 } else {
583 if (bus->bustype == SSB_BUSTYPE_PCI) {
584 bus->chip_id = pcidev_to_chipid(bus->host_pci);
585 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
586 - &bus->chip_rev);
587 + bus->chip_rev = bus->host_pci->revision;
588 bus->chip_package = 0;
589 } else {
590 bus->chip_id = 0x4710;
591 @@ -405,10 +407,10 @@ int ssb_bus_scan(struct ssb_bus *bus,
592 /* Ignore PCI cores on PCI-E cards.
593 * Ignore PCI-E cores on PCI cards. */
594 if (dev->id.coreid == SSB_DEV_PCI) {
595 - if (bus->host_pci->is_pcie)
596 + if (pci_is_pcie(bus->host_pci))
597 continue;
598 } else {
599 - if (!bus->host_pci->is_pcie)
600 + if (!pci_is_pcie(bus->host_pci))
601 continue;
602 }
603 }
604 @@ -420,6 +422,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
605 bus->pcicore.dev = dev;
606 #endif /* CONFIG_SSB_DRIVER_PCICORE */
607 break;
608 + case SSB_DEV_ETHERNET:
609 + if (bus->bustype == SSB_BUSTYPE_PCI) {
610 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
611 + (bus->host_pci->device & 0xFF00) == 0x4300) {
612 + /* This is a dangling ethernet core on a
613 + * wireless device. Ignore it. */
614 + continue;
615 + }
616 + }
617 + break;
618 default:
619 break;
620 }
621 --- a/include/linux/ssb/ssb.h
622 +++ b/include/linux/ssb/ssb.h
623 @@ -27,6 +27,8 @@ struct ssb_sprom {
624 u8 et1mdcport; /* MDIO for enet1 */
625 u8 board_rev; /* Board revision number from SPROM. */
626 u8 country_code; /* Country Code */
627 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
628 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
629 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
630 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
631 u16 pa0b0;
632 @@ -55,6 +57,10 @@ struct ssb_sprom {
633 u8 tri5gl; /* 5.2GHz TX isolation */
634 u8 tri5g; /* 5.3GHz TX isolation */
635 u8 tri5gh; /* 5.8GHz TX isolation */
636 + u8 txpid2g[4]; /* 2GHz TX power index */
637 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
638 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
639 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
640 u8 rxpo2g; /* 2GHz RX power offset */
641 u8 rxpo5g; /* 5GHz RX power offset */
642 u8 rssisav2g; /* 2GHz RSSI params */
643 @@ -95,7 +101,7 @@ struct ssb_sprom {
644 struct ssb_boardinfo {
645 u16 vendor;
646 u16 type;
647 - u16 rev;
648 + u8 rev;
649 };
650
651
652 @@ -304,7 +310,7 @@ struct ssb_bus {
653
654 /* ID information about the Chip. */
655 u16 chip_id;
656 - u16 chip_rev;
657 + u8 chip_rev;
658 u16 sprom_offset;
659 u16 sprom_size; /* number of words in sprom */
660 u8 chip_package;
661 @@ -400,7 +406,9 @@ extern bool ssb_is_sprom_available(struc
662
663 /* Set a fallback SPROM.
664 * See kdoc at the function definition for complete documentation. */
665 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
666 +extern int ssb_arch_register_fallback_sprom(
667 + int (*sprom_callback)(struct ssb_bus *bus,
668 + struct ssb_sprom *out));
669
670 /* Suspend a SSB bus.
671 * Call this from the parent bus suspend routine. */
672 @@ -514,6 +522,7 @@ extern int ssb_bus_may_powerdown(struct
673 * Otherwise static always-on powercontrol will be used. */
674 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
675
676 +extern void ssb_commit_settings(struct ssb_bus *bus);
677
678 /* Various helper functions */
679 extern u32 ssb_admatch_base(u32 adm);
680 --- a/include/linux/ssb/ssb_regs.h
681 +++ b/include/linux/ssb/ssb_regs.h
682 @@ -85,6 +85,8 @@
683 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
684 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
685 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
686 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
687 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
688 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
689 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
690 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
691 @@ -95,9 +97,8 @@
692 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
693 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
694 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
695 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
696 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
697 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
698 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
699 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
700 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
701 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
702 @@ -268,6 +269,8 @@
703 /* SPROM Revision 4 */
704 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
705 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
706 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
707 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
708 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
709 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
710 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
711 @@ -299,6 +302,46 @@
712 #define SSB_SPROM4_AGAIN2_SHIFT 0
713 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
714 #define SSB_SPROM4_AGAIN3_SHIFT 8
715 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
716 +#define SSB_SPROM4_TXPID2G0 0x00FF
717 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
718 +#define SSB_SPROM4_TXPID2G1 0xFF00
719 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
720 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
721 +#define SSB_SPROM4_TXPID2G2 0x00FF
722 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
723 +#define SSB_SPROM4_TXPID2G3 0xFF00
724 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
725 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
726 +#define SSB_SPROM4_TXPID5G0 0x00FF
727 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
728 +#define SSB_SPROM4_TXPID5G1 0xFF00
729 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
730 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
731 +#define SSB_SPROM4_TXPID5G2 0x00FF
732 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
733 +#define SSB_SPROM4_TXPID5G3 0xFF00
734 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
735 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
736 +#define SSB_SPROM4_TXPID5GL0 0x00FF
737 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
738 +#define SSB_SPROM4_TXPID5GL1 0xFF00
739 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
740 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
741 +#define SSB_SPROM4_TXPID5GL2 0x00FF
742 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
743 +#define SSB_SPROM4_TXPID5GL3 0xFF00
744 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
745 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
746 +#define SSB_SPROM4_TXPID5GH0 0x00FF
747 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
748 +#define SSB_SPROM4_TXPID5GH1 0xFF00
749 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
750 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
751 +#define SSB_SPROM4_TXPID5GH2 0x00FF
752 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
753 +#define SSB_SPROM4_TXPID5GH3 0xFF00
754 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
755 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
756 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
757 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
758 @@ -318,6 +361,8 @@
759 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
760 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
761 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
762 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
763 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
764 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
765 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
766 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
767 --- a/drivers/ssb/driver_chipcommon.c
768 +++ b/drivers/ssb/driver_chipcommon.c
769 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
770 if (!ccdev)
771 return;
772 bus = ccdev->bus;
773 +
774 + /* We support SLOW only on 6..9 */
775 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
776 + mode = SSB_CLKMODE_DYNAMIC;
777 +
778 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
779 + return; /* PMU controls clockmode, separated function needed */
780 + SSB_WARN_ON(ccdev->id.revision >= 20);
781 +
782 /* chipcommon cores prior to rev6 don't support dynamic clock control */
783 if (ccdev->id.revision < 6)
784 return;
785 - /* chipcommon cores rev10 are a whole new ball game */
786 +
787 + /* ChipCommon cores rev10+ need testing */
788 if (ccdev->id.revision >= 10)
789 return;
790 +
791 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
792 return;
793
794 switch (mode) {
795 - case SSB_CLKMODE_SLOW:
796 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
797 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
798 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
799 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
800 break;
801 case SSB_CLKMODE_FAST:
802 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
803 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
804 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
805 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
806 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
807 + if (ccdev->id.revision < 10) {
808 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
809 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
810 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
811 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
812 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
813 + } else {
814 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
815 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
816 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
817 + /* udelay(150); TODO: not available in early init */
818 + }
819 break;
820 case SSB_CLKMODE_DYNAMIC:
821 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
822 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
823 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
824 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
825 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
826 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
827 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
828 -
829 - /* for dynamic control, we have to release our xtal_pu "force on" */
830 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
831 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
832 + if (ccdev->id.revision < 10) {
833 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
834 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
835 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
836 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
837 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
838 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
839 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
840 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
841 +
842 + /* For dynamic control, we have to release our xtal_pu
843 + * "force on" */
844 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
845 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
846 + } else {
847 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
848 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
849 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
850 + }
851 break;
852 default:
853 SSB_WARN_ON(1);
854 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
855 if (cc->dev->id.revision >= 11)
856 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
857 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
858 +
859 + if (cc->dev->id.revision >= 20) {
860 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
861 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
862 + }
863 +
864 ssb_pmu_init(cc);
865 chipco_powercontrol_init(cc);
866 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
867 --- a/drivers/ssb/driver_chipcommon_pmu.c
868 +++ b/drivers/ssb/driver_chipcommon_pmu.c
869 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
870 u32 min_msk = 0, max_msk = 0;
871 unsigned int i;
872 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
873 - unsigned int updown_tab_size;
874 + unsigned int updown_tab_size = 0;
875 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
876 - unsigned int depend_tab_size;
877 + unsigned int depend_tab_size = 0;
878
879 switch (bus->chip_id) {
880 case 0x4312:
881 + min_msk = 0xCBB;
882 + break;
883 case 0x4322:
884 /* We keep the default settings:
885 * min_msk = 0xCBB
886 --- a/drivers/ssb/driver_gige.c
887 +++ b/drivers/ssb/driver_gige.c
888 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
889 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
890 }
891
892 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
893 - int reg, int size, u32 *val)
894 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
895 + unsigned int devfn, int reg,
896 + int size, u32 *val)
897 {
898 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
899 unsigned long flags;
900 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
901 return PCIBIOS_SUCCESSFUL;
902 }
903
904 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
905 - int reg, int size, u32 val)
906 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
907 + unsigned int devfn, int reg,
908 + int size, u32 val)
909 {
910 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
911 unsigned long flags;
912 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
913 return PCIBIOS_SUCCESSFUL;
914 }
915
916 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
917 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
918 + const struct ssb_device_id *id)
919 {
920 struct ssb_gige *dev;
921 u32 base, tmslow, tmshigh;
922 --- a/drivers/ssb/driver_pcicore.c
923 +++ b/drivers/ssb/driver_pcicore.c
924 @@ -15,6 +15,11 @@
925
926 #include "ssb_private.h"
927
928 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
929 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
930 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
931 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
932 + u8 address, u16 data);
933
934 static inline
935 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
936 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
937 return ssb_mips_irq(extpci_core->dev) + 2;
938 }
939
940 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
941 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
942 {
943 u32 val;
944
945 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
946 register_pci_controller(&ssb_pcicore_controller);
947 }
948
949 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
950 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
951 {
952 struct ssb_bus *bus = pc->dev->bus;
953 u16 chipid_top;
954 @@ -403,25 +408,133 @@ static int pcicore_is_in_hostmode(struct
955 }
956 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
957
958 +/**************************************************
959 + * Workarounds.
960 + **************************************************/
961 +
962 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
963 +{
964 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
965 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
966 + tmp &= ~0xF000;
967 + tmp |= (pc->dev->core_index << 12);
968 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
969 + }
970 +}
971 +
972 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
973 +{
974 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
975 +}
976 +
977 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
978 +{
979 + const u8 serdes_pll_device = 0x1D;
980 + const u8 serdes_rx_device = 0x1F;
981 + u16 tmp;
982 +
983 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
984 + ssb_pcicore_polarity_workaround(pc));
985 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
986 + if (tmp & 0x4000)
987 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
988 +}
989 +
990 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
991 +{
992 + struct ssb_device *pdev = pc->dev;
993 + struct ssb_bus *bus = pdev->bus;
994 + u32 tmp;
995 +
996 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
997 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
998 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
999 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1000 +
1001 + if (pdev->id.revision < 5) {
1002 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1003 + tmp &= ~SSB_IMCFGLO_SERTO;
1004 + tmp |= 2;
1005 + tmp &= ~SSB_IMCFGLO_REQTO;
1006 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1007 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1008 + ssb_commit_settings(bus);
1009 + } else if (pdev->id.revision >= 11) {
1010 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1011 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1012 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1013 + }
1014 +}
1015 +
1016 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1017 +{
1018 + u32 tmp;
1019 + u8 rev = pc->dev->id.revision;
1020 +
1021 + if (rev == 0 || rev == 1) {
1022 + /* TLP Workaround register. */
1023 + tmp = ssb_pcie_read(pc, 0x4);
1024 + tmp |= 0x8;
1025 + ssb_pcie_write(pc, 0x4, tmp);
1026 + }
1027 + if (rev == 1) {
1028 + /* DLLP Link Control register. */
1029 + tmp = ssb_pcie_read(pc, 0x100);
1030 + tmp |= 0x40;
1031 + ssb_pcie_write(pc, 0x100, tmp);
1032 + }
1033 +
1034 + if (rev == 0) {
1035 + const u8 serdes_rx_device = 0x1F;
1036 +
1037 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1038 + 2 /* Timer */, 0x8128);
1039 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1040 + 6 /* CDR */, 0x0100);
1041 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1042 + 7 /* CDR BW */, 0x1466);
1043 + } else if (rev == 3 || rev == 4 || rev == 5) {
1044 + /* TODO: DLLP Power Management Threshold */
1045 + ssb_pcicore_serdes_workaround(pc);
1046 + /* TODO: ASPM */
1047 + } else if (rev == 7) {
1048 + /* TODO: No PLL down */
1049 + }
1050 +
1051 + if (rev >= 6) {
1052 + /* Miscellaneous Configuration Fixup */
1053 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1054 + if (!(tmp & 0x8000))
1055 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1056 + tmp | 0x8000);
1057 + }
1058 +}
1059
1060 /**************************************************
1061 * Generic and Clientmode operation code.
1062 **************************************************/
1063
1064 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1065 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1066 {
1067 + ssb_pcicore_fix_sprom_core_index(pc);
1068 +
1069 /* Disable PCI interrupts. */
1070 ssb_write32(pc->dev, SSB_INTVEC, 0);
1071 +
1072 + /* Additional PCIe always once-executed workarounds */
1073 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1074 + ssb_pcicore_serdes_workaround(pc);
1075 + /* TODO: ASPM */
1076 + /* TODO: Clock Request Update */
1077 + }
1078 }
1079
1080 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1081 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1082 {
1083 struct ssb_device *dev = pc->dev;
1084 - struct ssb_bus *bus;
1085
1086 if (!dev)
1087 return;
1088 - bus = dev->bus;
1089 if (!ssb_device_is_enabled(dev))
1090 ssb_device_enable(dev, 0);
1091
1092 @@ -446,11 +559,35 @@ static void ssb_pcie_write(struct ssb_pc
1093 pcicore_write32(pc, 0x134, data);
1094 }
1095
1096 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1097 - u8 address, u16 data)
1098 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1099 +{
1100 + const u16 mdio_control = 0x128;
1101 + const u16 mdio_data = 0x12C;
1102 + u32 v;
1103 + int i;
1104 +
1105 + v = (1 << 30); /* Start of Transaction */
1106 + v |= (1 << 28); /* Write Transaction */
1107 + v |= (1 << 17); /* Turnaround */
1108 + v |= (0x1F << 18);
1109 + v |= (phy << 4);
1110 + pcicore_write32(pc, mdio_data, v);
1111 +
1112 + udelay(10);
1113 + for (i = 0; i < 200; i++) {
1114 + v = pcicore_read32(pc, mdio_control);
1115 + if (v & 0x100 /* Trans complete */)
1116 + break;
1117 + msleep(1);
1118 + }
1119 +}
1120 +
1121 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1122 {
1123 const u16 mdio_control = 0x128;
1124 const u16 mdio_data = 0x12C;
1125 + int max_retries = 10;
1126 + u16 ret = 0;
1127 u32 v;
1128 int i;
1129
1130 @@ -458,46 +595,68 @@ static void ssb_pcie_mdio_write(struct s
1131 v |= 0x2; /* MDIO Clock Divisor */
1132 pcicore_write32(pc, mdio_control, v);
1133
1134 + if (pc->dev->id.revision >= 10) {
1135 + max_retries = 200;
1136 + ssb_pcie_mdio_set_phy(pc, device);
1137 + }
1138 +
1139 v = (1 << 30); /* Start of Transaction */
1140 - v |= (1 << 28); /* Write Transaction */
1141 + v |= (1 << 29); /* Read Transaction */
1142 v |= (1 << 17); /* Turnaround */
1143 - v |= (u32)device << 22;
1144 + if (pc->dev->id.revision < 10)
1145 + v |= (u32)device << 22;
1146 v |= (u32)address << 18;
1147 - v |= data;
1148 pcicore_write32(pc, mdio_data, v);
1149 /* Wait for the device to complete the transaction */
1150 udelay(10);
1151 - for (i = 0; i < 10; i++) {
1152 + for (i = 0; i < max_retries; i++) {
1153 v = pcicore_read32(pc, mdio_control);
1154 - if (v & 0x100 /* Trans complete */)
1155 + if (v & 0x100 /* Trans complete */) {
1156 + udelay(10);
1157 + ret = pcicore_read32(pc, mdio_data);
1158 break;
1159 + }
1160 msleep(1);
1161 }
1162 pcicore_write32(pc, mdio_control, 0);
1163 + return ret;
1164 }
1165
1166 -static void ssb_broadcast_value(struct ssb_device *dev,
1167 - u32 address, u32 data)
1168 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1169 + u8 address, u16 data)
1170 {
1171 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1172 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1173 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1174 + const u16 mdio_control = 0x128;
1175 + const u16 mdio_data = 0x12C;
1176 + int max_retries = 10;
1177 + u32 v;
1178 + int i;
1179
1180 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1181 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1182 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1183 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1184 -}
1185 + v = 0x80; /* Enable Preamble Sequence */
1186 + v |= 0x2; /* MDIO Clock Divisor */
1187 + pcicore_write32(pc, mdio_control, v);
1188
1189 -static void ssb_commit_settings(struct ssb_bus *bus)
1190 -{
1191 - struct ssb_device *dev;
1192 + if (pc->dev->id.revision >= 10) {
1193 + max_retries = 200;
1194 + ssb_pcie_mdio_set_phy(pc, device);
1195 + }
1196
1197 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1198 - if (WARN_ON(!dev))
1199 - return;
1200 - /* This forces an update of the cached registers. */
1201 - ssb_broadcast_value(dev, 0xFD8, 0);
1202 + v = (1 << 30); /* Start of Transaction */
1203 + v |= (1 << 28); /* Write Transaction */
1204 + v |= (1 << 17); /* Turnaround */
1205 + if (pc->dev->id.revision < 10)
1206 + v |= (u32)device << 22;
1207 + v |= (u32)address << 18;
1208 + v |= data;
1209 + pcicore_write32(pc, mdio_data, v);
1210 + /* Wait for the device to complete the transaction */
1211 + udelay(10);
1212 + for (i = 0; i < max_retries; i++) {
1213 + v = pcicore_read32(pc, mdio_control);
1214 + if (v & 0x100 /* Trans complete */)
1215 + break;
1216 + msleep(1);
1217 + }
1218 + pcicore_write32(pc, mdio_control, 0);
1219 }
1220
1221 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1222 @@ -550,48 +709,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1223 if (pc->setup_done)
1224 goto out;
1225 if (pdev->id.coreid == SSB_DEV_PCI) {
1226 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1227 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1228 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1229 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1230 -
1231 - if (pdev->id.revision < 5) {
1232 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1233 - tmp &= ~SSB_IMCFGLO_SERTO;
1234 - tmp |= 2;
1235 - tmp &= ~SSB_IMCFGLO_REQTO;
1236 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1237 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1238 - ssb_commit_settings(bus);
1239 - } else if (pdev->id.revision >= 11) {
1240 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1241 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1242 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1243 - }
1244 + ssb_pcicore_pci_setup_workarounds(pc);
1245 } else {
1246 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1247 - //TODO: Better make defines for all these magic PCIE values.
1248 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1249 - /* TLP Workaround register. */
1250 - tmp = ssb_pcie_read(pc, 0x4);
1251 - tmp |= 0x8;
1252 - ssb_pcie_write(pc, 0x4, tmp);
1253 - }
1254 - if (pdev->id.revision == 0) {
1255 - const u8 serdes_rx_device = 0x1F;
1256 -
1257 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1258 - 2 /* Timer */, 0x8128);
1259 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1260 - 6 /* CDR */, 0x0100);
1261 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1262 - 7 /* CDR BW */, 0x1466);
1263 - } else if (pdev->id.revision == 1) {
1264 - /* DLLP Link Control register. */
1265 - tmp = ssb_pcie_read(pc, 0x100);
1266 - tmp |= 0x40;
1267 - ssb_pcie_write(pc, 0x100, tmp);
1268 - }
1269 + ssb_pcicore_pcie_setup_workarounds(pc);
1270 }
1271 pc->setup_done = 1;
1272 out:
1273 --- a/drivers/ssb/sprom.c
1274 +++ b/drivers/ssb/sprom.c
1275 @@ -17,7 +17,7 @@
1276 #include <linux/slab.h>
1277
1278
1279 -static const struct ssb_sprom *fallback_sprom;
1280 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1281
1282
1283 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1284 @@ -145,36 +145,43 @@ out:
1285 }
1286
1287 /**
1288 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1289 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1290 + * fallback SPROM if no SPROM is found.
1291 *
1292 - * @sprom: The SPROM data structure to register.
1293 + * @sprom_callback: The callback function.
1294 *
1295 - * With this function the architecture implementation may register a fallback
1296 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1297 - * where no valid SPROM can be found in the shadow registers.
1298 + * With this function the architecture implementation may register a
1299 + * callback handler which fills the SPROM data structure. The fallback is
1300 + * only used for PCI based SSB devices, where no valid SPROM can be found
1301 + * in the shadow registers.
1302 *
1303 - * This function is useful for weird architectures that have a half-assed SSB device
1304 - * hardwired to their PCI bus.
1305 + * This function is useful for weird architectures that have a half-assed
1306 + * SSB device hardwired to their PCI bus.
1307 *
1308 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1309 - * don't use this fallback.
1310 - * Architectures must provide the SPROM for native SSB devices anyway,
1311 - * so the fallback also isn't used for native devices.
1312 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1313 + * devices currently don't use this fallback.
1314 + * Architectures must provide the SPROM for native SSB devices anyway, so
1315 + * the fallback also isn't used for native devices.
1316 *
1317 - * This function is available for architecture code, only. So it is not exported.
1318 + * This function is available for architecture code, only. So it is not
1319 + * exported.
1320 */
1321 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1322 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1323 + struct ssb_sprom *out))
1324 {
1325 - if (fallback_sprom)
1326 + if (get_fallback_sprom)
1327 return -EEXIST;
1328 - fallback_sprom = sprom;
1329 + get_fallback_sprom = sprom_callback;
1330
1331 return 0;
1332 }
1333
1334 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1335 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1336 {
1337 - return fallback_sprom;
1338 + if (!get_fallback_sprom)
1339 + return -ENOENT;
1340 +
1341 + return get_fallback_sprom(bus, out);
1342 }
1343
1344 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1345 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1346 /* this routine differs from specs as we do not access SPROM directly
1347 on PCMCIA */
1348 if (bus->bustype == SSB_BUSTYPE_PCI &&
1349 - bus->chipco.dev && /* can be unavailible! */
1350 + bus->chipco.dev && /* can be unavailable! */
1351 bus->chipco.dev->id.revision >= 31)
1352 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1353
1354 --- a/drivers/ssb/ssb_private.h
1355 +++ b/drivers/ssb/ssb_private.h
1356 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1357 const char *buf, size_t count,
1358 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1359 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1360 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1361 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1362 + struct ssb_sprom *out);
1363
1364
1365 /* core.c */
1366 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1367 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1368 @@ -123,6 +123,8 @@
1369 #define SSB_CHIPCO_FLASHDATA 0x0048
1370 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1371 #define SSB_CHIPCO_BCAST_DATA 0x0054
1372 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1373 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1374 #define SSB_CHIPCO_GPIOIN 0x0060
1375 #define SSB_CHIPCO_GPIOOUT 0x0064
1376 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1377 @@ -131,6 +133,9 @@
1378 #define SSB_CHIPCO_GPIOIRQ 0x0074
1379 #define SSB_CHIPCO_WATCHDOG 0x0080
1380 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1381 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1382 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1383 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1384 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1385 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1386 #define SSB_CHIPCO_CLOCK_N 0x0090
1387 @@ -189,8 +194,10 @@
1388 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1389 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1390 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1391 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1392 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1393 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1394 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1395 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1396 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1397 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1398 #define SSB_CHIPCO_UART0_DATA 0x0300
1399 #define SSB_CHIPCO_UART0_IMR 0x0304
OpenWrt SVN history