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kernel: update bcma and ssb to version master-2012-04-12 from wireless-testing
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.1 / 020-ssb_update.patch
1 --- a/drivers/ssb/driver_pcicore.c
2 +++ b/drivers/ssb/driver_pcicore.c
3 @@ -74,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
4 u32 tmp;
5
6 /* We do only have one cardbus device behind the bridge. */
7 - if (pc->cardbusmode && (dev >= 1))
8 + if (pc->cardbusmode && (dev > 1))
9 goto out;
10
11 if (bus == 0) {
12 --- a/drivers/ssb/b43_pci_bridge.c
13 +++ b/drivers/ssb/b43_pci_bridge.c
14 @@ -11,6 +11,7 @@
15 */
16
17 #include <linux/pci.h>
18 +#include <linux/module.h>
19 #include <linux/ssb/ssb.h>
20
21 #include "ssb_private.h"
22 --- a/drivers/ssb/driver_chipcommon_pmu.c
23 +++ b/drivers/ssb/driver_chipcommon_pmu.c
24 @@ -12,6 +12,9 @@
25 #include <linux/ssb/ssb_regs.h>
26 #include <linux/ssb/ssb_driver_chipcommon.h>
27 #include <linux/delay.h>
28 +#ifdef CONFIG_BCM47XX
29 +#include <asm/mach-bcm47xx/nvram.h>
30 +#endif
31
32 #include "ssb_private.h"
33
34 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
35 u32 pmuctl, tmp, pllctl;
36 unsigned int i;
37
38 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
39 - /* The 5354 crystal freq is 25MHz */
40 - crystalfreq = 25000;
41 - }
42 if (crystalfreq)
43 e = pmu0_plltab_find_entry(crystalfreq);
44 if (!e)
45 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
46 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
47
48 if (bus->bustype == SSB_BUSTYPE_SSB) {
49 - /* TODO: The user may override the crystal frequency. */
50 +#ifdef CONFIG_BCM47XX
51 + char buf[20];
52 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
53 + crystalfreq = simple_strtoul(buf, NULL, 0);
54 +#endif
55 }
56
57 switch (bus->chip_id) {
58 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
59 ssb_pmu1_pllinit_r0(cc, crystalfreq);
60 break;
61 case 0x4328:
62 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
63 + break;
64 case 0x5354:
65 + if (crystalfreq == 0)
66 + crystalfreq = 25000;
67 ssb_pmu0_pllinit_r0(cc, crystalfreq);
68 break;
69 case 0x4322:
70 @@ -606,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
71
72 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
73 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
74 +
75 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
76 +{
77 + struct ssb_bus *bus = cc->dev->bus;
78 +
79 + switch (bus->chip_id) {
80 + case 0x5354:
81 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
82 + return 240000000;
83 + default:
84 + ssb_printk(KERN_ERR PFX
85 + "ERROR: PMU cpu clock unknown for device %04X\n",
86 + bus->chip_id);
87 + return 0;
88 + }
89 +}
90 +
91 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
92 +{
93 + struct ssb_bus *bus = cc->dev->bus;
94 +
95 + switch (bus->chip_id) {
96 + case 0x5354:
97 + return 120000000;
98 + default:
99 + ssb_printk(KERN_ERR PFX
100 + "ERROR: PMU controlclock unknown for device %04X\n",
101 + bus->chip_id);
102 + return 0;
103 + }
104 +}
105 --- a/drivers/ssb/driver_mipscore.c
106 +++ b/drivers/ssb/driver_mipscore.c
107 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
108 struct ssb_bus *bus = mcore->dev->bus;
109 u32 pll_type, n, m, rate = 0;
110
111 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
112 + return ssb_pmu_get_cpu_clock(&bus->chipco);
113 +
114 if (bus->extif.dev) {
115 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
116 } else if (bus->chipco.dev) {
117 --- a/drivers/ssb/main.c
118 +++ b/drivers/ssb/main.c
119 @@ -12,6 +12,7 @@
120
121 #include <linux/delay.h>
122 #include <linux/io.h>
123 +#include <linux/module.h>
124 #include <linux/ssb/ssb.h>
125 #include <linux/ssb/ssb_regs.h>
126 #include <linux/ssb/ssb_driver_gige.h>
127 @@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
128 put_device(dev->dev);
129 }
130
131 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
132 -{
133 - if (drv)
134 - get_driver(&drv->drv);
135 - return drv;
136 -}
137 -
138 -static inline void ssb_driver_put(struct ssb_driver *drv)
139 -{
140 - if (drv)
141 - put_driver(&drv->drv);
142 -}
143 -
144 static int ssb_device_resume(struct device *dev)
145 {
146 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
147 @@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
148 ssb_device_put(sdev);
149 continue;
150 }
151 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
152 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
153 - ssb_device_put(sdev);
154 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
155 + if (SSB_WARN_ON(!sdrv->remove))
156 continue;
157 - }
158 sdrv->remove(sdev);
159 ctx->device_frozen[i] = 1;
160 }
161 @@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
162 dev_name(sdev->dev));
163 result = err;
164 }
165 - ssb_driver_put(sdrv);
166 ssb_device_put(sdev);
167 }
168
169 @@ -1093,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
170 u32 plltype;
171 u32 clkctl_n, clkctl_m;
172
173 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
174 + return ssb_pmu_get_controlclock(&bus->chipco);
175 +
176 if (ssb_extif_available(&bus->extif))
177 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
178 &clkctl_n, &clkctl_m);
179 @@ -1260,16 +1248,34 @@ void ssb_device_disable(struct ssb_devic
180 }
181 EXPORT_SYMBOL(ssb_device_disable);
182
183 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
184 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
185 +{
186 + u16 chip_id = dev->bus->chip_id;
187 +
188 + if (dev->id.coreid == SSB_DEV_80211) {
189 + return (chip_id == 0x4322 || chip_id == 43221 ||
190 + chip_id == 43231 || chip_id == 43222);
191 + }
192 +
193 + return 0;
194 +}
195 +
196 u32 ssb_dma_translation(struct ssb_device *dev)
197 {
198 switch (dev->bus->bustype) {
199 case SSB_BUSTYPE_SSB:
200 return 0;
201 case SSB_BUSTYPE_PCI:
202 - if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
203 + if (pci_is_pcie(dev->bus->host_pci) &&
204 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
205 return SSB_PCIE_DMA_H32;
206 - else
207 - return SSB_PCI_DMA;
208 + } else {
209 + if (ssb_dma_translation_special_bit(dev))
210 + return SSB_PCIE_DMA_H32;
211 + else
212 + return SSB_PCI_DMA;
213 + }
214 default:
215 __ssb_dma_not_implemented(dev);
216 }
217 --- a/drivers/ssb/pci.c
218 +++ b/drivers/ssb/pci.c
219 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
220 {
221 int i;
222 u16 v;
223 - s8 gain;
224 u16 loc[3];
225
226 if (out->revision == 3) /* rev 3 moved MAC */
227 @@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
228 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
229
230 /* Extract the antenna gain values. */
231 - gain = r123_extract_antgain(out->revision, in,
232 - SSB_SPROM1_AGAIN_BG,
233 - SSB_SPROM1_AGAIN_BG_SHIFT);
234 - out->antenna_gain.ghz24.a0 = gain;
235 - out->antenna_gain.ghz24.a1 = gain;
236 - out->antenna_gain.ghz24.a2 = gain;
237 - out->antenna_gain.ghz24.a3 = gain;
238 - gain = r123_extract_antgain(out->revision, in,
239 - SSB_SPROM1_AGAIN_A,
240 - SSB_SPROM1_AGAIN_A_SHIFT);
241 - out->antenna_gain.ghz5.a0 = gain;
242 - out->antenna_gain.ghz5.a1 = gain;
243 - out->antenna_gain.ghz5.a2 = gain;
244 - out->antenna_gain.ghz5.a3 = gain;
245 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
246 + SSB_SPROM1_AGAIN_BG,
247 + SSB_SPROM1_AGAIN_BG_SHIFT);
248 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
249 + SSB_SPROM1_AGAIN_A,
250 + SSB_SPROM1_AGAIN_A_SHIFT);
251 }
252
253 /* Revs 4 5 and 8 have partially shared layout */
254 @@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
255 }
256
257 /* Extract the antenna gain values. */
258 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
259 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
260 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
261 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
262 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
263 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
264 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
265 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
266 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
267 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
268 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
269 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
270 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
271 - sizeof(out->antenna_gain.ghz5));
272
273 sprom_extract_r458(out, in);
274
275 @@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
276 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
277 {
278 int i;
279 - u16 v;
280 + u16 v, o;
281 + u16 pwr_info_offset[] = {
282 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
283 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
284 + };
285 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
286 + ARRAY_SIZE(out->core_pwr_info));
287
288 /* extract the MAC address */
289 for (i = 0; i < 3; i++) {
290 @@ -596,16 +591,69 @@ static void sprom_extract_r8(struct ssb_
291 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
292
293 /* Extract the antenna gain values. */
294 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
295 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
296 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
297 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
298 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
299 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
300 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
301 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
302 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
303 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
304 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
305 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
306 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
307 - sizeof(out->antenna_gain.ghz5));
308 +
309 + /* Extract cores power info info */
310 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
311 + o = pwr_info_offset[i];
312 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
313 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
314 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
315 + SSB_SPROM8_2G_MAXP, 0);
316 +
317 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
318 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
319 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
320 +
321 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
322 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
323 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
324 + SSB_SPROM8_5G_MAXP, 0);
325 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
326 + SSB_SPROM8_5GH_MAXP, 0);
327 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
328 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
329 +
330 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
331 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
332 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
333 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
334 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
335 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
336 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
337 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
338 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
339 + }
340 +
341 + /* Extract FEM info */
342 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
343 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
344 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
345 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
346 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
347 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
348 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
349 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
350 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
351 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
352 +
353 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
354 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
355 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
356 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
357 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
358 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
359 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
360 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
361 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
362 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
363
364 sprom_extract_r458(out, in);
365
366 --- a/drivers/ssb/pcmcia.c
367 +++ b/drivers/ssb/pcmcia.c
368 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
369 case SSB_PCMCIA_CIS_ANTGAIN:
370 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
371 "antg tpl size");
372 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
373 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
374 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
375 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
376 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
377 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
378 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
379 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
380 + sprom->antenna_gain.a0 = tuple->TupleData[1];
381 + sprom->antenna_gain.a1 = tuple->TupleData[1];
382 + sprom->antenna_gain.a2 = tuple->TupleData[1];
383 + sprom->antenna_gain.a3 = tuple->TupleData[1];
384 break;
385 case SSB_PCMCIA_CIS_BFLAGS:
386 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
387 --- a/drivers/ssb/scan.c
388 +++ b/drivers/ssb/scan.c
389 @@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
390 bus->chip_package = 0;
391 }
392 }
393 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
394 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
395 + bus->chip_package);
396 if (!bus->nr_devices)
397 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
398 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
399 --- a/drivers/ssb/sdio.c
400 +++ b/drivers/ssb/sdio.c
401 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
402 case SSB_SDIO_CIS_ANTGAIN:
403 GOTO_ERROR_ON(tuple->size != 2,
404 "antg tpl size");
405 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
406 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
407 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
408 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
409 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
410 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
411 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
412 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
413 + sprom->antenna_gain.a0 = tuple->data[1];
414 + sprom->antenna_gain.a1 = tuple->data[1];
415 + sprom->antenna_gain.a2 = tuple->data[1];
416 + sprom->antenna_gain.a3 = tuple->data[1];
417 break;
418 case SSB_SDIO_CIS_BFLAGS:
419 GOTO_ERROR_ON((tuple->size != 3) &&
420 --- a/drivers/ssb/ssb_private.h
421 +++ b/drivers/ssb/ssb_private.h
422 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
423 }
424 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
425
426 +/* driver_chipcommon_pmu.c */
427 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
428 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
429 +
430 #endif /* LINUX_SSB_PRIVATE_H_ */
431 --- a/include/linux/ssb/ssb.h
432 +++ b/include/linux/ssb/ssb.h
433 @@ -16,6 +16,12 @@ struct pcmcia_device;
434 struct ssb_bus;
435 struct ssb_driver;
436
437 +struct ssb_sprom_core_pwr_info {
438 + u8 itssi_2g, itssi_5g;
439 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
440 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
441 +};
442 +
443 struct ssb_sprom {
444 u8 revision;
445 u8 il0mac[6]; /* MAC address for 802.11b/g */
446 @@ -25,10 +31,13 @@ struct ssb_sprom {
447 u8 et1phyaddr; /* MII address for enet1 */
448 u8 et0mdcport; /* MDIO for enet0 */
449 u8 et1mdcport; /* MDIO for enet1 */
450 - u8 board_rev; /* Board revision number from SPROM. */
451 + u16 board_rev; /* Board revision number from SPROM. */
452 + u16 board_num; /* Board number from SPROM. */
453 + u16 board_type; /* Board type from SPROM. */
454 u8 country_code; /* Country Code */
455 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
456 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
457 + char alpha2[2]; /* Country Code as two chars like EU or US */
458 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
459 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
460 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
461 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
462 u16 pa0b0;
463 @@ -47,10 +56,10 @@ struct ssb_sprom {
464 u8 gpio1; /* GPIO pin 1 */
465 u8 gpio2; /* GPIO pin 2 */
466 u8 gpio3; /* GPIO pin 3 */
467 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
468 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
469 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
470 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
471 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
472 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
473 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
474 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
475 u8 itssi_a; /* Idle TSSI Target for A-PHY */
476 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
477 u8 tri2g; /* 2.4GHz TX isolation */
478 @@ -61,8 +70,8 @@ struct ssb_sprom {
479 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
480 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
481 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
482 - u8 rxpo2g; /* 2GHz RX power offset */
483 - u8 rxpo5g; /* 5GHz RX power offset */
484 + s8 rxpo2g; /* 2GHz RX power offset */
485 + s8 rxpo5g; /* 5GHz RX power offset */
486 u8 rssisav2g; /* 2GHz RSSI params */
487 u8 rssismc2g;
488 u8 rssismf2g;
489 @@ -82,19 +91,97 @@ struct ssb_sprom {
490 u16 boardflags2_hi; /* Board flags (bits 48-63) */
491 /* TODO store board flags in a single u64 */
492
493 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
494 +
495 /* Antenna gain values for up to 4 antennas
496 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
497 * loss in the connectors is bigger than the gain. */
498 struct {
499 - struct {
500 - s8 a0, a1, a2, a3;
501 - } ghz24; /* 2.4GHz band */
502 - struct {
503 - s8 a0, a1, a2, a3;
504 - } ghz5; /* 5GHz band */
505 + s8 a0, a1, a2, a3;
506 } antenna_gain;
507
508 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
509 + struct {
510 + struct {
511 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
512 + } ghz2;
513 + struct {
514 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
515 + } ghz5;
516 + } fem;
517 +
518 + u16 mcs2gpo[8];
519 + u16 mcs5gpo[8];
520 + u16 mcs5glpo[8];
521 + u16 mcs5ghpo[8];
522 + u8 opo;
523 +
524 + u8 rxgainerr2ga[3];
525 + u8 rxgainerr5gla[3];
526 + u8 rxgainerr5gma[3];
527 + u8 rxgainerr5gha[3];
528 + u8 rxgainerr5gua[3];
529 +
530 + u8 noiselvl2ga[3];
531 + u8 noiselvl5gla[3];
532 + u8 noiselvl5gma[3];
533 + u8 noiselvl5gha[3];
534 + u8 noiselvl5gua[3];
535 +
536 + u8 regrev;
537 + u8 txchain;
538 + u8 rxchain;
539 + u8 antswitch;
540 + u16 cddpo;
541 + u16 stbcpo;
542 + u16 bw40po;
543 + u16 bwduppo;
544 +
545 + u8 tempthresh;
546 + u8 tempoffset;
547 + u16 rawtempsense;
548 + u8 measpower;
549 + u8 tempsense_slope;
550 + u8 tempcorrx;
551 + u8 tempsense_option;
552 + u8 freqoffset_corr;
553 + u8 iqcal_swp_dis;
554 + u8 hw_iqcal_en;
555 + u8 elna2g;
556 + u8 elna5g;
557 + u8 phycal_tempdelta;
558 + u8 temps_period;
559 + u8 temps_hysteresis;
560 + u8 measpower1;
561 + u8 measpower2;
562 + u8 pcieingress_war;
563 +
564 + /* power per rate from sromrev 9 */
565 + u16 cckbw202gpo;
566 + u16 cckbw20ul2gpo;
567 + u32 legofdmbw202gpo;
568 + u32 legofdmbw20ul2gpo;
569 + u32 legofdmbw205glpo;
570 + u32 legofdmbw20ul5glpo;
571 + u32 legofdmbw205gmpo;
572 + u32 legofdmbw20ul5gmpo;
573 + u32 legofdmbw205ghpo;
574 + u32 legofdmbw20ul5ghpo;
575 + u32 mcsbw202gpo;
576 + u32 mcsbw20ul2gpo;
577 + u32 mcsbw402gpo;
578 + u32 mcsbw205glpo;
579 + u32 mcsbw20ul5glpo;
580 + u32 mcsbw405glpo;
581 + u32 mcsbw205gmpo;
582 + u32 mcsbw20ul5gmpo;
583 + u32 mcsbw405gmpo;
584 + u32 mcsbw205ghpo;
585 + u32 mcsbw20ul5ghpo;
586 + u32 mcsbw405ghpo;
587 + u16 mcs32po;
588 + u16 legofdm40duppo;
589 + u8 sar2g;
590 + u8 sar5g;
591 };
592
593 /* Information about the PCB the circuitry is soldered on. */
594 @@ -231,10 +318,9 @@ struct ssb_driver {
595 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
596
597 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
598 -static inline int ssb_driver_register(struct ssb_driver *drv)
599 -{
600 - return __ssb_driver_register(drv, THIS_MODULE);
601 -}
602 +#define ssb_driver_register(drv) \
603 + __ssb_driver_register(drv, THIS_MODULE)
604 +
605 extern void ssb_driver_unregister(struct ssb_driver *drv);
606
607
608 --- a/include/linux/ssb/ssb_driver_gige.h
609 +++ b/include/linux/ssb/ssb_driver_gige.h
610 @@ -2,6 +2,7 @@
611 #define LINUX_SSB_DRIVER_GIGE_H_
612
613 #include <linux/ssb/ssb.h>
614 +#include <linux/bug.h>
615 #include <linux/pci.h>
616 #include <linux/spinlock.h>
617
618 --- a/include/linux/ssb/ssb_regs.h
619 +++ b/include/linux/ssb/ssb_regs.h
620 @@ -432,6 +432,56 @@
621 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
622 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
623 #define SSB_SPROM8_RXPO5G_SHIFT 8
624 +#define SSB_SPROM8_FEM2G 0x00AE
625 +#define SSB_SPROM8_FEM5G 0x00B0
626 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
627 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
628 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
629 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
630 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
631 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
632 +#define SSB_SROM8_FEM_TR_ISO 0x0700
633 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
634 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
635 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
636 +#define SSB_SPROM8_THERMAL 0x00B2
637 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
638 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
639 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
640 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
641 +
642 +/* There are 4 blocks with power info sharing the same layout */
643 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
644 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
645 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
646 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
647 +
648 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
649 +#define SSB_SPROM8_2G_MAXP 0x00FF
650 +#define SSB_SPROM8_2G_ITSSI 0xFF00
651 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
652 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
653 +#define SSB_SROM8_2G_PA_1 0x04
654 +#define SSB_SROM8_2G_PA_2 0x06
655 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
656 +#define SSB_SPROM8_5G_MAXP 0x00FF
657 +#define SSB_SPROM8_5G_ITSSI 0xFF00
658 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
659 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
660 +#define SSB_SPROM8_5GH_MAXP 0x00FF
661 +#define SSB_SPROM8_5GL_MAXP 0xFF00
662 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
663 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
664 +#define SSB_SROM8_5G_PA_1 0x0E
665 +#define SSB_SROM8_5G_PA_2 0x10
666 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
667 +#define SSB_SROM8_5GL_PA_1 0x14
668 +#define SSB_SROM8_5GL_PA_2 0x16
669 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
670 +#define SSB_SROM8_5GH_PA_1 0x1A
671 +#define SSB_SROM8_5GH_PA_2 0x1C
672 +
673 +/* TODO: Make it deprecated */
674 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
675 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
676 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
677 @@ -456,12 +506,53 @@
678 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
679 #define SSB_SPROM8_PA1HIB1 0x00DA
680 #define SSB_SPROM8_PA1HIB2 0x00DC
681 +
682 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
683 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
684 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
685 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
686 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
687
688 +/* Values for boardflags_lo read from SPROM */
689 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
690 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
691 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
692 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
693 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
694 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
695 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
696 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
697 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
698 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
699 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
700 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
701 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
702 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
703 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
704 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
705 +
706 +/* Values for boardflags_hi read from SPROM */
707 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
708 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
709 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
710 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
711 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
712 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
713 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
714 +
715 +/* Values for boardflags2_lo read from SPROM */
716 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
717 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
718 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
719 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
720 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
721 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
722 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
723 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
724 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
725 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
726 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
727 +
728 /* Values for SSB_SPROM1_BINF_CCODE */
729 enum {
730 SSB_SPROM1CCODE_WORLD = 0,
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