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51b23b03f6aef06a0d76efc707b6cbe5a2b149fe
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 020-ssb_update.patch
1 --- a/arch/mips/bcm47xx/nvram.c
2 +++ b/arch/mips/bcm47xx/nvram.c
3 @@ -43,8 +43,8 @@ static void early_nvram_init(void)
4 #ifdef CONFIG_BCM47XX_SSB
5 case BCM47XX_BUS_TYPE_SSB:
6 mcore_ssb = &bcm47xx_bus.ssb.mipscore;
7 - base = mcore_ssb->flash_window;
8 - lim = mcore_ssb->flash_window_size;
9 + base = mcore_ssb->pflash.window;
10 + lim = mcore_ssb->pflash.window_size;
11 break;
12 #endif
13 #ifdef CONFIG_BCM47XX_BCMA
14 --- a/arch/mips/bcm47xx/wgt634u.c
15 +++ b/arch/mips/bcm47xx/wgt634u.c
16 @@ -156,10 +156,10 @@ static int __init wgt634u_init(void)
17 SSB_CHIPCO_IRQ_GPIO);
18 }
19
20 - wgt634u_flash_data.width = mcore->flash_buswidth;
21 - wgt634u_flash_resource.start = mcore->flash_window;
22 - wgt634u_flash_resource.end = mcore->flash_window
23 - + mcore->flash_window_size
24 + wgt634u_flash_data.width = mcore->pflash.buswidth;
25 + wgt634u_flash_resource.start = mcore->pflash.window;
26 + wgt634u_flash_resource.end = mcore->pflash.window
27 + + mcore->pflash.window_size
28 - 1;
29 return platform_add_devices(wgt634u_devices,
30 ARRAY_SIZE(wgt634u_devices));
31 --- a/drivers/ssb/Kconfig
32 +++ b/drivers/ssb/Kconfig
33 @@ -136,10 +136,15 @@ config SSB_DRIVER_MIPS
34
35 If unsure, say N
36
37 +config SSB_SFLASH
38 + bool "SSB serial flash support"
39 + depends on SSB_DRIVER_MIPS && BROKEN
40 + default y
41 +
42 # Assumption: We are on embedded, if we compile the MIPS core.
43 config SSB_EMBEDDED
44 bool
45 - depends on SSB_DRIVER_MIPS
46 + depends on SSB_DRIVER_MIPS && SSB_PCICORE_HOSTMODE
47 default y
48
49 config SSB_DRIVER_EXTIF
50 @@ -160,4 +165,12 @@ config SSB_DRIVER_GIGE
51
52 If unsure, say N
53
54 +config SSB_DRIVER_GPIO
55 + bool "SSB GPIO driver"
56 + depends on SSB && GPIOLIB
57 + help
58 + Driver to provide access to the GPIO pins on the bus.
59 +
60 + If unsure, say N
61 +
62 endmenu
63 --- a/drivers/ssb/Makefile
64 +++ b/drivers/ssb/Makefile
65 @@ -11,10 +11,12 @@ ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
66 # built-in drivers
67 ssb-y += driver_chipcommon.o
68 ssb-y += driver_chipcommon_pmu.o
69 +ssb-$(CONFIG_SSB_SFLASH) += driver_chipcommon_sflash.o
70 ssb-$(CONFIG_SSB_DRIVER_MIPS) += driver_mipscore.o
71 ssb-$(CONFIG_SSB_DRIVER_EXTIF) += driver_extif.o
72 ssb-$(CONFIG_SSB_DRIVER_PCICORE) += driver_pcicore.o
73 ssb-$(CONFIG_SSB_DRIVER_GIGE) += driver_gige.o
74 +ssb-$(CONFIG_SSB_DRIVER_GPIO) += driver_gpio.o
75
76 # b43 pci-ssb-bridge driver
77 # Not strictly a part of SSB, but kept here for convenience
78 --- a/drivers/ssb/b43_pci_bridge.c
79 +++ b/drivers/ssb/b43_pci_bridge.c
80 @@ -29,11 +29,15 @@ static const struct pci_device_id b43_pc
81 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
82 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
84 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
85 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
86 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
87 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
88 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
89 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
90 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
91 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
92 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4350) },
93 { 0, },
94 };
95 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
96 --- a/drivers/ssb/driver_chipcommon.c
97 +++ b/drivers/ssb/driver_chipcommon.c
98 @@ -4,6 +4,7 @@
99 *
100 * Copyright 2005, Broadcom Corporation
101 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
102 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
103 *
104 * Licensed under the GNU/GPL. See COPYING for details.
105 */
106 @@ -12,6 +13,7 @@
107 #include <linux/ssb/ssb_regs.h>
108 #include <linux/export.h>
109 #include <linux/pci.h>
110 +#include <linux/bcm47xx_wdt.h>
111
112 #include "ssb_private.h"
113
114 @@ -280,13 +282,79 @@ static void calc_fast_powerup_delay(stru
115 cc->fast_pwrup_delay = tmp;
116 }
117
118 +static u32 ssb_chipco_alp_clock(struct ssb_chipcommon *cc)
119 +{
120 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
121 + return ssb_pmu_get_alp_clock(cc);
122 +
123 + return 20000000;
124 +}
125 +
126 +static u32 ssb_chipco_watchdog_get_max_timer(struct ssb_chipcommon *cc)
127 +{
128 + u32 nb;
129 +
130 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
131 + if (cc->dev->id.revision < 26)
132 + nb = 16;
133 + else
134 + nb = (cc->dev->id.revision >= 37) ? 32 : 24;
135 + } else {
136 + nb = 28;
137 + }
138 + if (nb == 32)
139 + return 0xffffffff;
140 + else
141 + return (1 << nb) - 1;
142 +}
143 +
144 +u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
145 +{
146 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
147 +
148 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
149 + return 0;
150 +
151 + return ssb_chipco_watchdog_timer_set(cc, ticks);
152 +}
153 +
154 +u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
155 +{
156 + struct ssb_chipcommon *cc = bcm47xx_wdt_get_drvdata(wdt);
157 + u32 ticks;
158 +
159 + if (cc->dev->bus->bustype != SSB_BUSTYPE_SSB)
160 + return 0;
161 +
162 + ticks = ssb_chipco_watchdog_timer_set(cc, cc->ticks_per_ms * ms);
163 + return ticks / cc->ticks_per_ms;
164 +}
165 +
166 +static int ssb_chipco_watchdog_ticks_per_ms(struct ssb_chipcommon *cc)
167 +{
168 + struct ssb_bus *bus = cc->dev->bus;
169 +
170 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
171 + /* based on 32KHz ILP clock */
172 + return 32;
173 + } else {
174 + if (cc->dev->id.revision < 18)
175 + return ssb_clockspeed(bus) / 1000;
176 + else
177 + return ssb_chipco_alp_clock(cc) / 1000;
178 + }
179 +}
180 +
181 void ssb_chipcommon_init(struct ssb_chipcommon *cc)
182 {
183 if (!cc->dev)
184 return; /* We don't have a ChipCommon */
185 +
186 + spin_lock_init(&cc->gpio_lock);
187 +
188 if (cc->dev->id.revision >= 11)
189 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
190 - ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
191 + ssb_dbg("chipcommon status is 0x%x\n", cc->status);
192
193 if (cc->dev->id.revision >= 20) {
194 chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
195 @@ -297,6 +365,11 @@ void ssb_chipcommon_init(struct ssb_chip
196 chipco_powercontrol_init(cc);
197 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
198 calc_fast_powerup_delay(cc);
199 +
200 + if (cc->dev->bus->bustype == SSB_BUSTYPE_SSB) {
201 + cc->ticks_per_ms = ssb_chipco_watchdog_ticks_per_ms(cc);
202 + cc->max_timer_ms = ssb_chipco_watchdog_get_max_timer(cc) / cc->ticks_per_ms;
203 + }
204 }
205
206 void ssb_chipco_suspend(struct ssb_chipcommon *cc)
207 @@ -395,10 +468,27 @@ void ssb_chipco_timing_init(struct ssb_c
208 }
209
210 /* Set chip watchdog reset timer to fire in 'ticks' backplane cycles */
211 -void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
212 +u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks)
213 {
214 - /* instant NMI */
215 - chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
216 + u32 maxt;
217 + enum ssb_clkmode clkmode;
218 +
219 + maxt = ssb_chipco_watchdog_get_max_timer(cc);
220 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
221 + if (ticks == 1)
222 + ticks = 2;
223 + else if (ticks > maxt)
224 + ticks = maxt;
225 + chipco_write32(cc, SSB_CHIPCO_PMU_WATCHDOG, ticks);
226 + } else {
227 + clkmode = ticks ? SSB_CLKMODE_FAST : SSB_CLKMODE_DYNAMIC;
228 + ssb_chipco_set_clockmode(cc, clkmode);
229 + if (ticks > maxt)
230 + ticks = maxt;
231 + /* instant NMI */
232 + chipco_write32(cc, SSB_CHIPCO_WATCHDOG, ticks);
233 + }
234 + return ticks;
235 }
236
237 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value)
238 @@ -418,28 +508,93 @@ u32 ssb_chipco_gpio_in(struct ssb_chipco
239
240 u32 ssb_chipco_gpio_out(struct ssb_chipcommon *cc, u32 mask, u32 value)
241 {
242 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
243 + unsigned long flags;
244 + u32 res = 0;
245 +
246 + spin_lock_irqsave(&cc->gpio_lock, flags);
247 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUT, mask, value);
248 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
249 +
250 + return res;
251 }
252
253 u32 ssb_chipco_gpio_outen(struct ssb_chipcommon *cc, u32 mask, u32 value)
254 {
255 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
256 + unsigned long flags;
257 + u32 res = 0;
258 +
259 + spin_lock_irqsave(&cc->gpio_lock, flags);
260 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOOUTEN, mask, value);
261 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
262 +
263 + return res;
264 }
265
266 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value)
267 {
268 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
269 + unsigned long flags;
270 + u32 res = 0;
271 +
272 + spin_lock_irqsave(&cc->gpio_lock, flags);
273 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
274 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
275 +
276 + return res;
277 }
278 EXPORT_SYMBOL(ssb_chipco_gpio_control);
279
280 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
281 {
282 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
283 + unsigned long flags;
284 + u32 res = 0;
285 +
286 + spin_lock_irqsave(&cc->gpio_lock, flags);
287 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOIRQ, mask, value);
288 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
289 +
290 + return res;
291 }
292
293 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value)
294 {
295 - return chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
296 + unsigned long flags;
297 + u32 res = 0;
298 +
299 + spin_lock_irqsave(&cc->gpio_lock, flags);
300 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPOL, mask, value);
301 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
302 +
303 + return res;
304 +}
305 +
306 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value)
307 +{
308 + unsigned long flags;
309 + u32 res = 0;
310 +
311 + if (cc->dev->id.revision < 20)
312 + return 0xffffffff;
313 +
314 + spin_lock_irqsave(&cc->gpio_lock, flags);
315 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLUP, mask, value);
316 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
317 +
318 + return res;
319 +}
320 +
321 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value)
322 +{
323 + unsigned long flags;
324 + u32 res = 0;
325 +
326 + if (cc->dev->id.revision < 20)
327 + return 0xffffffff;
328 +
329 + spin_lock_irqsave(&cc->gpio_lock, flags);
330 + res = chipco_write32_masked(cc, SSB_CHIPCO_GPIOPULLDOWN, mask, value);
331 + spin_unlock_irqrestore(&cc->gpio_lock, flags);
332 +
333 + return res;
334 }
335
336 #ifdef CONFIG_SSB_SERIAL
337 @@ -473,12 +628,7 @@ int ssb_chipco_serial_init(struct ssb_ch
338 chipco_read32(cc, SSB_CHIPCO_CORECTL)
339 | SSB_CHIPCO_CORECTL_UARTCLK0);
340 } else if ((ccrev >= 11) && (ccrev != 15)) {
341 - /* Fixed ALP clock */
342 - baud_base = 20000000;
343 - if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
344 - /* FIXME: baud_base is different for devices with a PMU */
345 - SSB_WARN_ON(1);
346 - }
347 + baud_base = ssb_chipco_alp_clock(cc);
348 div = 1;
349 if (ccrev >= 21) {
350 /* Turn off UART clock before switching clocksource. */
351 --- a/drivers/ssb/driver_chipcommon_pmu.c
352 +++ b/drivers/ssb/driver_chipcommon_pmu.c
353 @@ -13,6 +13,9 @@
354 #include <linux/ssb/ssb_driver_chipcommon.h>
355 #include <linux/delay.h>
356 #include <linux/export.h>
357 +#ifdef CONFIG_BCM47XX
358 +#include <asm/mach-bcm47xx/nvram.h>
359 +#endif
360
361 #include "ssb_private.h"
362
363 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
364 u32 pmuctl, tmp, pllctl;
365 unsigned int i;
366
367 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
368 - /* The 5354 crystal freq is 25MHz */
369 - crystalfreq = 25000;
370 - }
371 if (crystalfreq)
372 e = pmu0_plltab_find_entry(crystalfreq);
373 if (!e)
374 @@ -111,8 +110,8 @@ static void ssb_pmu0_pllinit_r0(struct s
375 return;
376 }
377
378 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
379 - (crystalfreq / 1000), (crystalfreq % 1000));
380 + ssb_info("Programming PLL to %u.%03u MHz\n",
381 + crystalfreq / 1000, crystalfreq % 1000);
382
383 /* First turn the PLL off. */
384 switch (bus->chip_id) {
385 @@ -139,7 +138,7 @@ static void ssb_pmu0_pllinit_r0(struct s
386 }
387 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
388 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
389 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
390 + ssb_emerg("Failed to turn the PLL off!\n");
391
392 /* Set PDIV in PLL control 0. */
393 pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
394 @@ -250,8 +249,8 @@ static void ssb_pmu1_pllinit_r0(struct s
395 return;
396 }
397
398 - ssb_printk(KERN_INFO PFX "Programming PLL to %u.%03u MHz\n",
399 - (crystalfreq / 1000), (crystalfreq % 1000));
400 + ssb_info("Programming PLL to %u.%03u MHz\n",
401 + crystalfreq / 1000, crystalfreq % 1000);
402
403 /* First turn the PLL off. */
404 switch (bus->chip_id) {
405 @@ -276,7 +275,7 @@ static void ssb_pmu1_pllinit_r0(struct s
406 }
407 tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
408 if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
409 - ssb_printk(KERN_EMERG PFX "Failed to turn the PLL off!\n");
410 + ssb_emerg("Failed to turn the PLL off!\n");
411
412 /* Set p1div and p2div. */
413 pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
414 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
415 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
416
417 if (bus->bustype == SSB_BUSTYPE_SSB) {
418 - /* TODO: The user may override the crystal frequency. */
419 +#ifdef CONFIG_BCM47XX
420 + char buf[20];
421 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
422 + crystalfreq = simple_strtoul(buf, NULL, 0);
423 +#endif
424 }
425
426 switch (bus->chip_id) {
427 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
428 ssb_pmu1_pllinit_r0(cc, crystalfreq);
429 break;
430 case 0x4328:
431 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
432 + break;
433 case 0x5354:
434 + if (crystalfreq == 0)
435 + crystalfreq = 25000;
436 ssb_pmu0_pllinit_r0(cc, crystalfreq);
437 break;
438 case 0x4322:
439 @@ -339,10 +346,11 @@ static void ssb_pmu_pll_init(struct ssb_
440 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
441 }
442 break;
443 + case 43222:
444 + break;
445 default:
446 - ssb_printk(KERN_ERR PFX
447 - "ERROR: PLL init unknown for device %04X\n",
448 - bus->chip_id);
449 + ssb_err("ERROR: PLL init unknown for device %04X\n",
450 + bus->chip_id);
451 }
452 }
453
454 @@ -427,6 +435,7 @@ static void ssb_pmu_resources_init(struc
455 min_msk = 0xCBB;
456 break;
457 case 0x4322:
458 + case 43222:
459 /* We keep the default settings:
460 * min_msk = 0xCBB
461 * max_msk = 0x7FFFF
462 @@ -462,9 +471,8 @@ static void ssb_pmu_resources_init(struc
463 max_msk = 0xFFFFF;
464 break;
465 default:
466 - ssb_printk(KERN_ERR PFX
467 - "ERROR: PMU resource config unknown for device %04X\n",
468 - bus->chip_id);
469 + ssb_err("ERROR: PMU resource config unknown for device %04X\n",
470 + bus->chip_id);
471 }
472
473 if (updown_tab) {
474 @@ -516,8 +524,8 @@ void ssb_pmu_init(struct ssb_chipcommon
475 pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
476 cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
477
478 - ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
479 - cc->pmu.rev, pmucap);
480 + ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
481 + cc->pmu.rev, pmucap);
482
483 if (cc->pmu.rev == 1)
484 chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
485 @@ -607,3 +615,102 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
486
487 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
488 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
489 +
490 +static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
491 +{
492 + u32 crystalfreq;
493 + const struct pmu0_plltab_entry *e = NULL;
494 +
495 + crystalfreq = chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
496 + SSB_CHIPCO_PMU_CTL_XTALFREQ >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
497 + e = pmu0_plltab_find_entry(crystalfreq);
498 + BUG_ON(!e);
499 + return e->freq * 1000;
500 +}
501 +
502 +u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
503 +{
504 + struct ssb_bus *bus = cc->dev->bus;
505 +
506 + switch (bus->chip_id) {
507 + case 0x5354:
508 + ssb_pmu_get_alp_clock_clk0(cc);
509 + default:
510 + ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
511 + bus->chip_id);
512 + return 0;
513 + }
514 +}
515 +
516 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
517 +{
518 + struct ssb_bus *bus = cc->dev->bus;
519 +
520 + switch (bus->chip_id) {
521 + case 0x5354:
522 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
523 + return 240000000;
524 + default:
525 + ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
526 + bus->chip_id);
527 + return 0;
528 + }
529 +}
530 +
531 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
532 +{
533 + struct ssb_bus *bus = cc->dev->bus;
534 +
535 + switch (bus->chip_id) {
536 + case 0x5354:
537 + return 120000000;
538 + default:
539 + ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
540 + bus->chip_id);
541 + return 0;
542 + }
543 +}
544 +
545 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
546 +{
547 + u32 pmu_ctl = 0;
548 +
549 + switch (cc->dev->bus->chip_id) {
550 + case 0x4322:
551 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
552 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
553 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
554 + if (spuravoid == 1)
555 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
556 + else
557 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
558 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
559 + break;
560 + case 43222:
561 + if (spuravoid == 1) {
562 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
563 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
564 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
565 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
566 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
567 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
568 + } else {
569 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
570 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
571 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
572 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
573 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
574 + ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
575 + }
576 + pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
577 + break;
578 + default:
579 + ssb_printk(KERN_ERR PFX
580 + "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
581 + cc->dev->bus->chip_id);
582 + return;
583 + }
584 +
585 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
586 +}
587 +EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);
588 --- /dev/null
589 +++ b/drivers/ssb/driver_chipcommon_sflash.c
590 @@ -0,0 +1,166 @@
591 +/*
592 + * Sonics Silicon Backplane
593 + * ChipCommon serial flash interface
594 + *
595 + * Licensed under the GNU/GPL. See COPYING for details.
596 + */
597 +
598 +#include <linux/ssb/ssb.h>
599 +
600 +#include "ssb_private.h"
601 +
602 +static struct resource ssb_sflash_resource = {
603 + .name = "ssb_sflash",
604 + .start = SSB_FLASH2,
605 + .end = 0,
606 + .flags = IORESOURCE_MEM | IORESOURCE_READONLY,
607 +};
608 +
609 +struct platform_device ssb_sflash_dev = {
610 + .name = "ssb_sflash",
611 + .resource = &ssb_sflash_resource,
612 + .num_resources = 1,
613 +};
614 +
615 +struct ssb_sflash_tbl_e {
616 + char *name;
617 + u32 id;
618 + u32 blocksize;
619 + u16 numblocks;
620 +};
621 +
622 +static const struct ssb_sflash_tbl_e ssb_sflash_st_tbl[] = {
623 + { "M25P20", 0x11, 0x10000, 4, },
624 + { "M25P40", 0x12, 0x10000, 8, },
625 +
626 + { "M25P16", 0x14, 0x10000, 32, },
627 + { "M25P32", 0x15, 0x10000, 64, },
628 + { "M25P64", 0x16, 0x10000, 128, },
629 + { "M25FL128", 0x17, 0x10000, 256, },
630 + { 0 },
631 +};
632 +
633 +static const struct ssb_sflash_tbl_e ssb_sflash_sst_tbl[] = {
634 + { "SST25WF512", 1, 0x1000, 16, },
635 + { "SST25VF512", 0x48, 0x1000, 16, },
636 + { "SST25WF010", 2, 0x1000, 32, },
637 + { "SST25VF010", 0x49, 0x1000, 32, },
638 + { "SST25WF020", 3, 0x1000, 64, },
639 + { "SST25VF020", 0x43, 0x1000, 64, },
640 + { "SST25WF040", 4, 0x1000, 128, },
641 + { "SST25VF040", 0x44, 0x1000, 128, },
642 + { "SST25VF040B", 0x8d, 0x1000, 128, },
643 + { "SST25WF080", 5, 0x1000, 256, },
644 + { "SST25VF080B", 0x8e, 0x1000, 256, },
645 + { "SST25VF016", 0x41, 0x1000, 512, },
646 + { "SST25VF032", 0x4a, 0x1000, 1024, },
647 + { "SST25VF064", 0x4b, 0x1000, 2048, },
648 + { 0 },
649 +};
650 +
651 +static const struct ssb_sflash_tbl_e ssb_sflash_at_tbl[] = {
652 + { "AT45DB011", 0xc, 256, 512, },
653 + { "AT45DB021", 0x14, 256, 1024, },
654 + { "AT45DB041", 0x1c, 256, 2048, },
655 + { "AT45DB081", 0x24, 256, 4096, },
656 + { "AT45DB161", 0x2c, 512, 4096, },
657 + { "AT45DB321", 0x34, 512, 8192, },
658 + { "AT45DB642", 0x3c, 1024, 8192, },
659 + { 0 },
660 +};
661 +
662 +static void ssb_sflash_cmd(struct ssb_chipcommon *cc, u32 opcode)
663 +{
664 + int i;
665 + chipco_write32(cc, SSB_CHIPCO_FLASHCTL,
666 + SSB_CHIPCO_FLASHCTL_START | opcode);
667 + for (i = 0; i < 1000; i++) {
668 + if (!(chipco_read32(cc, SSB_CHIPCO_FLASHCTL) &
669 + SSB_CHIPCO_FLASHCTL_BUSY))
670 + return;
671 + cpu_relax();
672 + }
673 + pr_err("SFLASH control command failed (timeout)!\n");
674 +}
675 +
676 +/* Initialize serial flash access */
677 +int ssb_sflash_init(struct ssb_chipcommon *cc)
678 +{
679 + struct ssb_sflash *sflash = &cc->dev->bus->mipscore.sflash;
680 + const struct ssb_sflash_tbl_e *e;
681 + u32 id, id2;
682 +
683 + switch (cc->capabilities & SSB_CHIPCO_CAP_FLASHT) {
684 + case SSB_CHIPCO_FLASHT_STSER:
685 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_DP);
686 +
687 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 0);
688 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
689 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
690 +
691 + chipco_write32(cc, SSB_CHIPCO_FLASHADDR, 1);
692 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_ST_RES);
693 + id2 = chipco_read32(cc, SSB_CHIPCO_FLASHDATA);
694 +
695 + switch (id) {
696 + case 0xbf:
697 + for (e = ssb_sflash_sst_tbl; e->name; e++) {
698 + if (e->id == id2)
699 + break;
700 + }
701 + break;
702 + case 0x13:
703 + return -ENOTSUPP;
704 + default:
705 + for (e = ssb_sflash_st_tbl; e->name; e++) {
706 + if (e->id == id)
707 + break;
708 + }
709 + break;
710 + }
711 + if (!e->name) {
712 + pr_err("Unsupported ST serial flash (id: 0x%X, id2: 0x%X)\n",
713 + id, id2);
714 + return -ENOTSUPP;
715 + }
716 +
717 + break;
718 + case SSB_CHIPCO_FLASHT_ATSER:
719 + ssb_sflash_cmd(cc, SSB_CHIPCO_FLASHCTL_AT_STATUS);
720 + id = chipco_read32(cc, SSB_CHIPCO_FLASHDATA) & 0x3c;
721 +
722 + for (e = ssb_sflash_at_tbl; e->name; e++) {
723 + if (e->id == id)
724 + break;
725 + }
726 + if (!e->name) {
727 + pr_err("Unsupported Atmel serial flash (id: 0x%X)\n",
728 + id);
729 + return -ENOTSUPP;
730 + }
731 +
732 + break;
733 + default:
734 + pr_err("Unsupported flash type\n");
735 + return -ENOTSUPP;
736 + }
737 +
738 + sflash->window = SSB_FLASH2;
739 + sflash->blocksize = e->blocksize;
740 + sflash->numblocks = e->numblocks;
741 + sflash->size = sflash->blocksize * sflash->numblocks;
742 + sflash->present = true;
743 +
744 + pr_info("Found %s serial flash (blocksize: 0x%X, blocks: %d)\n",
745 + e->name, e->blocksize, e->numblocks);
746 +
747 + /* Prepare platform device, but don't register it yet. It's too early,
748 + * malloc (required by device_private_init) is not available yet. */
749 + ssb_sflash_dev.resource[0].end = ssb_sflash_dev.resource[0].start +
750 + sflash->size;
751 + ssb_sflash_dev.dev.platform_data = sflash;
752 +
753 + pr_err("Serial flash support is not implemented yet!\n");
754 +
755 + return -ENOTSUPP;
756 +}
757 --- a/drivers/ssb/driver_extif.c
758 +++ b/drivers/ssb/driver_extif.c
759 @@ -112,10 +112,37 @@ void ssb_extif_get_clockcontrol(struct s
760 *m = extif_read32(extif, SSB_EXTIF_CLOCK_SB);
761 }
762
763 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
764 - u32 ticks)
765 +u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks)
766 {
767 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
768 +
769 + return ssb_extif_watchdog_timer_set(extif, ticks);
770 +}
771 +
772 +u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms)
773 +{
774 + struct ssb_extif *extif = bcm47xx_wdt_get_drvdata(wdt);
775 + u32 ticks = (SSB_EXTIF_WATCHDOG_CLK / 1000) * ms;
776 +
777 + ticks = ssb_extif_watchdog_timer_set(extif, ticks);
778 +
779 + return (ticks * 1000) / SSB_EXTIF_WATCHDOG_CLK;
780 +}
781 +
782 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
783 +{
784 + if (ticks > SSB_EXTIF_WATCHDOG_MAX_TIMER)
785 + ticks = SSB_EXTIF_WATCHDOG_MAX_TIMER;
786 extif_write32(extif, SSB_EXTIF_WATCHDOG, ticks);
787 +
788 + return ticks;
789 +}
790 +
791 +void ssb_extif_init(struct ssb_extif *extif)
792 +{
793 + if (!extif->dev)
794 + return; /* We don't have a Extif core */
795 + spin_lock_init(&extif->gpio_lock);
796 }
797
798 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
799 @@ -125,22 +152,50 @@ u32 ssb_extif_gpio_in(struct ssb_extif *
800
801 u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask, u32 value)
802 {
803 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
804 + unsigned long flags;
805 + u32 res = 0;
806 +
807 + spin_lock_irqsave(&extif->gpio_lock, flags);
808 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUT(0),
809 mask, value);
810 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
811 +
812 + return res;
813 }
814
815 u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask, u32 value)
816 {
817 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
818 + unsigned long flags;
819 + u32 res = 0;
820 +
821 + spin_lock_irqsave(&extif->gpio_lock, flags);
822 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_OUTEN(0),
823 mask, value);
824 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
825 +
826 + return res;
827 }
828
829 u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask, u32 value)
830 {
831 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
832 + unsigned long flags;
833 + u32 res = 0;
834 +
835 + spin_lock_irqsave(&extif->gpio_lock, flags);
836 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTPOL, mask, value);
837 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
838 +
839 + return res;
840 }
841
842 u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask, u32 value)
843 {
844 - return extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
845 + unsigned long flags;
846 + u32 res = 0;
847 +
848 + spin_lock_irqsave(&extif->gpio_lock, flags);
849 + res = extif_write32_masked(extif, SSB_EXTIF_GPIO_INTMASK, mask, value);
850 + spin_unlock_irqrestore(&extif->gpio_lock, flags);
851 +
852 + return res;
853 }
854 --- /dev/null
855 +++ b/drivers/ssb/driver_gpio.c
856 @@ -0,0 +1,210 @@
857 +/*
858 + * Sonics Silicon Backplane
859 + * GPIO driver
860 + *
861 + * Copyright 2011, Broadcom Corporation
862 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
863 + *
864 + * Licensed under the GNU/GPL. See COPYING for details.
865 + */
866 +
867 +#include <linux/gpio.h>
868 +#include <linux/export.h>
869 +#include <linux/ssb/ssb.h>
870 +
871 +#include "ssb_private.h"
872 +
873 +static struct ssb_bus *ssb_gpio_get_bus(struct gpio_chip *chip)
874 +{
875 + return container_of(chip, struct ssb_bus, gpio);
876 +}
877 +
878 +static int ssb_gpio_chipco_get_value(struct gpio_chip *chip, unsigned gpio)
879 +{
880 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
881 +
882 + return !!ssb_chipco_gpio_in(&bus->chipco, 1 << gpio);
883 +}
884 +
885 +static void ssb_gpio_chipco_set_value(struct gpio_chip *chip, unsigned gpio,
886 + int value)
887 +{
888 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
889 +
890 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
891 +}
892 +
893 +static int ssb_gpio_chipco_direction_input(struct gpio_chip *chip,
894 + unsigned gpio)
895 +{
896 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
897 +
898 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 0);
899 + return 0;
900 +}
901 +
902 +static int ssb_gpio_chipco_direction_output(struct gpio_chip *chip,
903 + unsigned gpio, int value)
904 +{
905 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
906 +
907 + ssb_chipco_gpio_outen(&bus->chipco, 1 << gpio, 1 << gpio);
908 + ssb_chipco_gpio_out(&bus->chipco, 1 << gpio, value ? 1 << gpio : 0);
909 + return 0;
910 +}
911 +
912 +static int ssb_gpio_chipco_request(struct gpio_chip *chip, unsigned gpio)
913 +{
914 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
915 +
916 + ssb_chipco_gpio_control(&bus->chipco, 1 << gpio, 0);
917 + /* clear pulldown */
918 + ssb_chipco_gpio_pulldown(&bus->chipco, 1 << gpio, 0);
919 + /* Set pullup */
920 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 1 << gpio);
921 +
922 + return 0;
923 +}
924 +
925 +static void ssb_gpio_chipco_free(struct gpio_chip *chip, unsigned gpio)
926 +{
927 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
928 +
929 + /* clear pullup */
930 + ssb_chipco_gpio_pullup(&bus->chipco, 1 << gpio, 0);
931 +}
932 +
933 +static int ssb_gpio_chipco_to_irq(struct gpio_chip *chip, unsigned gpio)
934 +{
935 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
936 +
937 + if (bus->bustype == SSB_BUSTYPE_SSB)
938 + return ssb_mips_irq(bus->chipco.dev) + 2;
939 + else
940 + return -EINVAL;
941 +}
942 +
943 +static int ssb_gpio_chipco_init(struct ssb_bus *bus)
944 +{
945 + struct gpio_chip *chip = &bus->gpio;
946 +
947 + chip->label = "ssb_chipco_gpio";
948 + chip->owner = THIS_MODULE;
949 + chip->request = ssb_gpio_chipco_request;
950 + chip->free = ssb_gpio_chipco_free;
951 + chip->get = ssb_gpio_chipco_get_value;
952 + chip->set = ssb_gpio_chipco_set_value;
953 + chip->direction_input = ssb_gpio_chipco_direction_input;
954 + chip->direction_output = ssb_gpio_chipco_direction_output;
955 + chip->to_irq = ssb_gpio_chipco_to_irq;
956 + chip->ngpio = 16;
957 + /* There is just one SoC in one device and its GPIO addresses should be
958 + * deterministic to address them more easily. The other buses could get
959 + * a random base number. */
960 + if (bus->bustype == SSB_BUSTYPE_SSB)
961 + chip->base = 0;
962 + else
963 + chip->base = -1;
964 +
965 + return gpiochip_add(chip);
966 +}
967 +
968 +#ifdef CONFIG_SSB_DRIVER_EXTIF
969 +
970 +static int ssb_gpio_extif_get_value(struct gpio_chip *chip, unsigned gpio)
971 +{
972 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
973 +
974 + return !!ssb_extif_gpio_in(&bus->extif, 1 << gpio);
975 +}
976 +
977 +static void ssb_gpio_extif_set_value(struct gpio_chip *chip, unsigned gpio,
978 + int value)
979 +{
980 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
981 +
982 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
983 +}
984 +
985 +static int ssb_gpio_extif_direction_input(struct gpio_chip *chip,
986 + unsigned gpio)
987 +{
988 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
989 +
990 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 0);
991 + return 0;
992 +}
993 +
994 +static int ssb_gpio_extif_direction_output(struct gpio_chip *chip,
995 + unsigned gpio, int value)
996 +{
997 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
998 +
999 + ssb_extif_gpio_outen(&bus->extif, 1 << gpio, 1 << gpio);
1000 + ssb_extif_gpio_out(&bus->extif, 1 << gpio, value ? 1 << gpio : 0);
1001 + return 0;
1002 +}
1003 +
1004 +static int ssb_gpio_extif_to_irq(struct gpio_chip *chip, unsigned gpio)
1005 +{
1006 + struct ssb_bus *bus = ssb_gpio_get_bus(chip);
1007 +
1008 + if (bus->bustype == SSB_BUSTYPE_SSB)
1009 + return ssb_mips_irq(bus->extif.dev) + 2;
1010 + else
1011 + return -EINVAL;
1012 +}
1013 +
1014 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
1015 +{
1016 + struct gpio_chip *chip = &bus->gpio;
1017 +
1018 + chip->label = "ssb_extif_gpio";
1019 + chip->owner = THIS_MODULE;
1020 + chip->get = ssb_gpio_extif_get_value;
1021 + chip->set = ssb_gpio_extif_set_value;
1022 + chip->direction_input = ssb_gpio_extif_direction_input;
1023 + chip->direction_output = ssb_gpio_extif_direction_output;
1024 + chip->to_irq = ssb_gpio_extif_to_irq;
1025 + chip->ngpio = 5;
1026 + /* There is just one SoC in one device and its GPIO addresses should be
1027 + * deterministic to address them more easily. The other buses could get
1028 + * a random base number. */
1029 + if (bus->bustype == SSB_BUSTYPE_SSB)
1030 + chip->base = 0;
1031 + else
1032 + chip->base = -1;
1033 +
1034 + return gpiochip_add(chip);
1035 +}
1036 +
1037 +#else
1038 +static int ssb_gpio_extif_init(struct ssb_bus *bus)
1039 +{
1040 + return -ENOTSUPP;
1041 +}
1042 +#endif
1043 +
1044 +int ssb_gpio_init(struct ssb_bus *bus)
1045 +{
1046 + if (ssb_chipco_available(&bus->chipco))
1047 + return ssb_gpio_chipco_init(bus);
1048 + else if (ssb_extif_available(&bus->extif))
1049 + return ssb_gpio_extif_init(bus);
1050 + else
1051 + SSB_WARN_ON(1);
1052 +
1053 + return -1;
1054 +}
1055 +
1056 +int ssb_gpio_unregister(struct ssb_bus *bus)
1057 +{
1058 + if (ssb_chipco_available(&bus->chipco) ||
1059 + ssb_extif_available(&bus->extif)) {
1060 + return gpiochip_remove(&bus->gpio);
1061 + } else {
1062 + SSB_WARN_ON(1);
1063 + }
1064 +
1065 + return -1;
1066 +}
1067 --- a/drivers/ssb/driver_mipscore.c
1068 +++ b/drivers/ssb/driver_mipscore.c
1069 @@ -10,6 +10,7 @@
1070
1071 #include <linux/ssb/ssb.h>
1072
1073 +#include <linux/mtd/physmap.h>
1074 #include <linux/serial.h>
1075 #include <linux/serial_core.h>
1076 #include <linux/serial_reg.h>
1077 @@ -17,6 +18,25 @@
1078
1079 #include "ssb_private.h"
1080
1081 +static const char * const part_probes[] = { "bcm47xxpart", NULL };
1082 +
1083 +static struct physmap_flash_data ssb_pflash_data = {
1084 + .part_probe_types = part_probes,
1085 +};
1086 +
1087 +static struct resource ssb_pflash_resource = {
1088 + .name = "ssb_pflash",
1089 + .flags = IORESOURCE_MEM,
1090 +};
1091 +
1092 +struct platform_device ssb_pflash_dev = {
1093 + .name = "physmap-flash",
1094 + .dev = {
1095 + .platform_data = &ssb_pflash_data,
1096 + },
1097 + .resource = &ssb_pflash_resource,
1098 + .num_resources = 1,
1099 +};
1100
1101 static inline u32 mips_read32(struct ssb_mipscore *mcore,
1102 u16 offset)
1103 @@ -147,21 +167,22 @@ static void set_irq(struct ssb_device *d
1104 irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1105 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1106 }
1107 - ssb_dprintk(KERN_INFO PFX
1108 - "set_irq: core 0x%04x, irq %d => %d\n",
1109 - dev->id.coreid, oldirq+2, irq+2);
1110 + ssb_dbg("set_irq: core 0x%04x, irq %d => %d\n",
1111 + dev->id.coreid, oldirq+2, irq+2);
1112 }
1113
1114 static void print_irq(struct ssb_device *dev, unsigned int irq)
1115 {
1116 - int i;
1117 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1118 - ssb_dprintk(KERN_INFO PFX
1119 - "core 0x%04x, irq :", dev->id.coreid);
1120 - for (i = 0; i <= 6; i++) {
1121 - ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1122 - }
1123 - ssb_dprintk("\n");
1124 + ssb_dbg("core 0x%04x, irq : %s%s %s%s %s%s %s%s %s%s %s%s %s%s\n",
1125 + dev->id.coreid,
1126 + irq_name[0], irq == 0 ? "*" : " ",
1127 + irq_name[1], irq == 1 ? "*" : " ",
1128 + irq_name[2], irq == 2 ? "*" : " ",
1129 + irq_name[3], irq == 3 ? "*" : " ",
1130 + irq_name[4], irq == 4 ? "*" : " ",
1131 + irq_name[5], irq == 5 ? "*" : " ",
1132 + irq_name[6], irq == 6 ? "*" : " ");
1133 }
1134
1135 static void dump_irq(struct ssb_bus *bus)
1136 @@ -178,9 +199,9 @@ static void ssb_mips_serial_init(struct
1137 {
1138 struct ssb_bus *bus = mcore->dev->bus;
1139
1140 - if (bus->extif.dev)
1141 + if (ssb_extif_available(&bus->extif))
1142 mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports);
1143 - else if (bus->chipco.dev)
1144 + else if (ssb_chipco_available(&bus->chipco))
1145 mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports);
1146 else
1147 mcore->nr_serial_ports = 0;
1148 @@ -189,17 +210,42 @@ static void ssb_mips_serial_init(struct
1149 static void ssb_mips_flash_detect(struct ssb_mipscore *mcore)
1150 {
1151 struct ssb_bus *bus = mcore->dev->bus;
1152 + struct ssb_pflash *pflash = &mcore->pflash;
1153
1154 - mcore->flash_buswidth = 2;
1155 - if (bus->chipco.dev) {
1156 - mcore->flash_window = 0x1c000000;
1157 - mcore->flash_window_size = 0x02000000;
1158 + /* When there is no chipcommon on the bus there is 4MB flash */
1159 + if (!ssb_chipco_available(&bus->chipco)) {
1160 + pflash->present = true;
1161 + pflash->buswidth = 2;
1162 + pflash->window = SSB_FLASH1;
1163 + pflash->window_size = SSB_FLASH1_SZ;
1164 + goto ssb_pflash;
1165 + }
1166 +
1167 + /* There is ChipCommon, so use it to read info about flash */
1168 + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
1169 + case SSB_CHIPCO_FLASHT_STSER:
1170 + case SSB_CHIPCO_FLASHT_ATSER:
1171 + pr_debug("Found serial flash\n");
1172 + ssb_sflash_init(&bus->chipco);
1173 + break;
1174 + case SSB_CHIPCO_FLASHT_PARA:
1175 + pr_debug("Found parallel flash\n");
1176 + pflash->present = true;
1177 + pflash->window = SSB_FLASH2;
1178 + pflash->window_size = SSB_FLASH2_SZ;
1179 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
1180 & SSB_CHIPCO_CFG_DS16) == 0)
1181 - mcore->flash_buswidth = 1;
1182 - } else {
1183 - mcore->flash_window = 0x1fc00000;
1184 - mcore->flash_window_size = 0x00400000;
1185 + pflash->buswidth = 1;
1186 + else
1187 + pflash->buswidth = 2;
1188 + break;
1189 + }
1190 +
1191 +ssb_pflash:
1192 + if (pflash->present) {
1193 + ssb_pflash_data.width = pflash->buswidth;
1194 + ssb_pflash_resource.start = pflash->window;
1195 + ssb_pflash_resource.end = pflash->window + pflash->window_size;
1196 }
1197 }
1198
1199 @@ -208,9 +254,12 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1200 struct ssb_bus *bus = mcore->dev->bus;
1201 u32 pll_type, n, m, rate = 0;
1202
1203 - if (bus->extif.dev) {
1204 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1205 + return ssb_pmu_get_cpu_clock(&bus->chipco);
1206 +
1207 + if (ssb_extif_available(&bus->extif)) {
1208 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1209 - } else if (bus->chipco.dev) {
1210 + } else if (ssb_chipco_available(&bus->chipco)) {
1211 ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m);
1212 } else
1213 return 0;
1214 @@ -238,7 +287,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1215 if (!mcore->dev)
1216 return; /* We don't have a MIPS core */
1217
1218 - ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n");
1219 + ssb_dbg("Initializing MIPS core...\n");
1220
1221 bus = mcore->dev->bus;
1222 hz = ssb_clockspeed(bus);
1223 @@ -246,9 +295,9 @@ void ssb_mipscore_init(struct ssb_mipsco
1224 hz = 100000000;
1225 ns = 1000000000 / hz;
1226
1227 - if (bus->extif.dev)
1228 + if (ssb_extif_available(&bus->extif))
1229 ssb_extif_timing_init(&bus->extif, ns);
1230 - else if (bus->chipco.dev)
1231 + else if (ssb_chipco_available(&bus->chipco))
1232 ssb_chipco_timing_init(&bus->chipco, ns);
1233
1234 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1235 @@ -286,7 +335,7 @@ void ssb_mipscore_init(struct ssb_mipsco
1236 break;
1237 }
1238 }
1239 - ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1240 + ssb_dbg("after irq reconfiguration\n");
1241 dump_irq(bus);
1242
1243 ssb_mips_serial_init(mcore);
1244 --- a/drivers/ssb/driver_pcicore.c
1245 +++ b/drivers/ssb/driver_pcicore.c
1246 @@ -263,8 +263,7 @@ int ssb_pcicore_plat_dev_init(struct pci
1247 return -ENODEV;
1248 }
1249
1250 - ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
1251 - pci_name(d));
1252 + ssb_info("PCI: Fixing up device %s\n", pci_name(d));
1253
1254 /* Fix up interrupt lines */
1255 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
1256 @@ -285,12 +284,12 @@ static void ssb_pcicore_fixup_pcibridge(
1257 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
1258 return;
1259
1260 - ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
1261 + ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev));
1262
1263 /* Enable PCI bridge bus mastering and memory space */
1264 pci_set_master(dev);
1265 if (pcibios_enable_device(dev, ~0) < 0) {
1266 - ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n");
1267 + ssb_err("PCI: SSB bridge enable failed\n");
1268 return;
1269 }
1270
1271 @@ -299,8 +298,8 @@ static void ssb_pcicore_fixup_pcibridge(
1272
1273 /* Make sure our latency is high enough to handle the devices behind us */
1274 lat = 168;
1275 - ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
1276 - pci_name(dev), lat);
1277 + ssb_info("PCI: Fixing latency timer of device %s to %u\n",
1278 + pci_name(dev), lat);
1279 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
1280 }
1281 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge);
1282 @@ -323,7 +322,7 @@ static void __devinit ssb_pcicore_init_h
1283 return;
1284 extpci_core = pc;
1285
1286 - ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
1287 + ssb_dbg("PCIcore in host mode found\n");
1288 /* Reset devices on the external PCI bus */
1289 val = SSB_PCICORE_CTL_RST_OE;
1290 val |= SSB_PCICORE_CTL_CLK_OE;
1291 @@ -338,7 +337,7 @@ static void __devinit ssb_pcicore_init_h
1292 udelay(1); /* Assertion time demanded by the PCI standard */
1293
1294 if (pc->dev->bus->has_cardbus_slot) {
1295 - ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
1296 + ssb_dbg("CardBus slot detected\n");
1297 pc->cardbusmode = 1;
1298 /* GPIO 1 resets the bridge */
1299 ssb_gpio_out(pc->dev->bus, 1, 1);
1300 --- a/drivers/ssb/embedded.c
1301 +++ b/drivers/ssb/embedded.c
1302 @@ -4,11 +4,13 @@
1303 *
1304 * Copyright 2005-2008, Broadcom Corporation
1305 * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1306 + * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
1307 *
1308 * Licensed under the GNU/GPL. See COPYING for details.
1309 */
1310
1311 #include <linux/export.h>
1312 +#include <linux/platform_device.h>
1313 #include <linux/ssb/ssb.h>
1314 #include <linux/ssb/ssb_embedded.h>
1315 #include <linux/ssb/ssb_driver_pci.h>
1316 @@ -32,6 +34,38 @@ int ssb_watchdog_timer_set(struct ssb_bu
1317 }
1318 EXPORT_SYMBOL(ssb_watchdog_timer_set);
1319
1320 +int ssb_watchdog_register(struct ssb_bus *bus)
1321 +{
1322 + struct bcm47xx_wdt wdt = {};
1323 + struct platform_device *pdev;
1324 +
1325 + if (ssb_chipco_available(&bus->chipco)) {
1326 + wdt.driver_data = &bus->chipco;
1327 + wdt.timer_set = ssb_chipco_watchdog_timer_set_wdt;
1328 + wdt.timer_set_ms = ssb_chipco_watchdog_timer_set_ms;
1329 + wdt.max_timer_ms = bus->chipco.max_timer_ms;
1330 + } else if (ssb_extif_available(&bus->extif)) {
1331 + wdt.driver_data = &bus->extif;
1332 + wdt.timer_set = ssb_extif_watchdog_timer_set_wdt;
1333 + wdt.timer_set_ms = ssb_extif_watchdog_timer_set_ms;
1334 + wdt.max_timer_ms = SSB_EXTIF_WATCHDOG_MAX_TIMER_MS;
1335 + } else {
1336 + return -ENODEV;
1337 + }
1338 +
1339 + pdev = platform_device_register_data(NULL, "bcm47xx-wdt",
1340 + bus->busnumber, &wdt,
1341 + sizeof(wdt));
1342 + if (IS_ERR(pdev)) {
1343 + ssb_dbg("can not register watchdog device, err: %li\n",
1344 + PTR_ERR(pdev));
1345 + return PTR_ERR(pdev);
1346 + }
1347 +
1348 + bus->watchdog = pdev;
1349 + return 0;
1350 +}
1351 +
1352 u32 ssb_gpio_in(struct ssb_bus *bus, u32 mask)
1353 {
1354 unsigned long flags;
1355 --- a/drivers/ssb/main.c
1356 +++ b/drivers/ssb/main.c
1357 @@ -13,6 +13,7 @@
1358 #include <linux/delay.h>
1359 #include <linux/io.h>
1360 #include <linux/module.h>
1361 +#include <linux/platform_device.h>
1362 #include <linux/ssb/ssb.h>
1363 #include <linux/ssb/ssb_regs.h>
1364 #include <linux/ssb/ssb_driver_gige.h>
1365 @@ -289,8 +290,8 @@ int ssb_devices_thaw(struct ssb_freeze_c
1366
1367 err = sdrv->probe(sdev, &sdev->id);
1368 if (err) {
1369 - ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1370 - dev_name(sdev->dev));
1371 + ssb_err("Failed to thaw device %s\n",
1372 + dev_name(sdev->dev));
1373 result = err;
1374 }
1375 ssb_driver_put(sdrv);
1376 @@ -449,10 +450,23 @@ static void ssb_devices_unregister(struc
1377 if (sdev->dev)
1378 device_unregister(sdev->dev);
1379 }
1380 +
1381 +#ifdef CONFIG_SSB_EMBEDDED
1382 + if (bus->bustype == SSB_BUSTYPE_SSB)
1383 + platform_device_unregister(bus->watchdog);
1384 +#endif
1385 }
1386
1387 void ssb_bus_unregister(struct ssb_bus *bus)
1388 {
1389 + int err;
1390 +
1391 + err = ssb_gpio_unregister(bus);
1392 + if (err == -EBUSY)
1393 + ssb_dbg("Some GPIOs are still in use\n");
1394 + else if (err)
1395 + ssb_dbg("Can not unregister GPIO driver: %i\n", err);
1396 +
1397 ssb_buses_lock();
1398 ssb_devices_unregister(bus);
1399 list_del(&bus->list);
1400 @@ -498,8 +512,7 @@ static int ssb_devices_register(struct s
1401
1402 devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
1403 if (!devwrap) {
1404 - ssb_printk(KERN_ERR PFX
1405 - "Could not allocate device\n");
1406 + ssb_err("Could not allocate device\n");
1407 err = -ENOMEM;
1408 goto error;
1409 }
1410 @@ -538,9 +551,7 @@ static int ssb_devices_register(struct s
1411 sdev->dev = dev;
1412 err = device_register(dev);
1413 if (err) {
1414 - ssb_printk(KERN_ERR PFX
1415 - "Could not register %s\n",
1416 - dev_name(dev));
1417 + ssb_err("Could not register %s\n", dev_name(dev));
1418 /* Set dev to NULL to not unregister
1419 * dev on error unwinding. */
1420 sdev->dev = NULL;
1421 @@ -550,6 +561,22 @@ static int ssb_devices_register(struct s
1422 dev_idx++;
1423 }
1424
1425 +#ifdef CONFIG_SSB_DRIVER_MIPS
1426 + if (bus->mipscore.pflash.present) {
1427 + err = platform_device_register(&ssb_pflash_dev);
1428 + if (err)
1429 + pr_err("Error registering parallel flash\n");
1430 + }
1431 +#endif
1432 +
1433 +#ifdef CONFIG_SSB_SFLASH
1434 + if (bus->mipscore.sflash.present) {
1435 + err = platform_device_register(&ssb_sflash_dev);
1436 + if (err)
1437 + pr_err("Error registering serial flash\n");
1438 + }
1439 +#endif
1440 +
1441 return 0;
1442 error:
1443 /* Unwind the already registered devices. */
1444 @@ -577,6 +604,8 @@ static int __devinit ssb_attach_queued_b
1445 if (err)
1446 goto error;
1447 ssb_pcicore_init(&bus->pcicore);
1448 + if (bus->bustype == SSB_BUSTYPE_SSB)
1449 + ssb_watchdog_register(bus);
1450 ssb_bus_may_powerdown(bus);
1451
1452 err = ssb_devices_register(bus);
1453 @@ -812,7 +841,13 @@ static int __devinit ssb_bus_register(st
1454 if (err)
1455 goto err_pcmcia_exit;
1456 ssb_chipcommon_init(&bus->chipco);
1457 + ssb_extif_init(&bus->extif);
1458 ssb_mipscore_init(&bus->mipscore);
1459 + err = ssb_gpio_init(bus);
1460 + if (err == -ENOTSUPP)
1461 + ssb_dbg("GPIO driver not activated\n");
1462 + else if (err)
1463 + ssb_dbg("Error registering GPIO driver: %i\n", err);
1464 err = ssb_fetch_invariants(bus, get_invariants);
1465 if (err) {
1466 ssb_bus_may_powerdown(bus);
1467 @@ -863,11 +898,11 @@ int __devinit ssb_bus_pcibus_register(st
1468
1469 err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
1470 if (!err) {
1471 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1472 - "PCI device %s\n", dev_name(&host_pci->dev));
1473 + ssb_info("Sonics Silicon Backplane found on PCI device %s\n",
1474 + dev_name(&host_pci->dev));
1475 } else {
1476 - ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1477 - " of SSB with error %d\n", err);
1478 + ssb_err("Failed to register PCI version of SSB with error %d\n",
1479 + err);
1480 }
1481
1482 return err;
1483 @@ -888,8 +923,8 @@ int __devinit ssb_bus_pcmciabus_register
1484
1485 err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
1486 if (!err) {
1487 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1488 - "PCMCIA device %s\n", pcmcia_dev->devname);
1489 + ssb_info("Sonics Silicon Backplane found on PCMCIA device %s\n",
1490 + pcmcia_dev->devname);
1491 }
1492
1493 return err;
1494 @@ -911,8 +946,8 @@ int __devinit ssb_bus_sdiobus_register(s
1495
1496 err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1497 if (!err) {
1498 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1499 - "SDIO device %s\n", sdio_func_id(func));
1500 + ssb_info("Sonics Silicon Backplane found on SDIO device %s\n",
1501 + sdio_func_id(func));
1502 }
1503
1504 return err;
1505 @@ -931,8 +966,8 @@ int __devinit ssb_bus_ssbbus_register(st
1506
1507 err = ssb_bus_register(bus, get_invariants, baseaddr);
1508 if (!err) {
1509 - ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
1510 - "address 0x%08lX\n", baseaddr);
1511 + ssb_info("Sonics Silicon Backplane found at address 0x%08lX\n",
1512 + baseaddr);
1513 }
1514
1515 return err;
1516 @@ -1094,6 +1129,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1517 u32 plltype;
1518 u32 clkctl_n, clkctl_m;
1519
1520 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1521 + return ssb_pmu_get_controlclock(&bus->chipco);
1522 +
1523 if (ssb_extif_available(&bus->extif))
1524 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1525 &clkctl_n, &clkctl_m);
1526 @@ -1131,8 +1169,7 @@ static u32 ssb_tmslow_reject_bitmask(str
1527 case SSB_IDLOW_SSBREV_27: /* same here */
1528 return SSB_TMSLOW_REJECT; /* this is a guess */
1529 default:
1530 - printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1531 - WARN_ON(1);
1532 + WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1533 }
1534 return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1535 }
1536 @@ -1324,7 +1361,7 @@ out:
1537 #endif
1538 return err;
1539 error:
1540 - ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1541 + ssb_err("Bus powerdown failed\n");
1542 goto out;
1543 }
1544 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1545 @@ -1347,7 +1384,7 @@ int ssb_bus_powerup(struct ssb_bus *bus,
1546
1547 return 0;
1548 error:
1549 - ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1550 + ssb_err("Bus powerup failed\n");
1551 return err;
1552 }
1553 EXPORT_SYMBOL(ssb_bus_powerup);
1554 @@ -1455,15 +1492,13 @@ static int __init ssb_modinit(void)
1555
1556 err = b43_pci_ssb_bridge_init();
1557 if (err) {
1558 - ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1559 - "initialization failed\n");
1560 + ssb_err("Broadcom 43xx PCI-SSB-bridge initialization failed\n");
1561 /* don't fail SSB init because of this */
1562 err = 0;
1563 }
1564 err = ssb_gige_init();
1565 if (err) {
1566 - ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1567 - "driver initialization failed\n");
1568 + ssb_err("SSB Broadcom Gigabit Ethernet driver initialization failed\n");
1569 /* don't fail SSB init because of this */
1570 err = 0;
1571 }
1572 --- a/drivers/ssb/pci.c
1573 +++ b/drivers/ssb/pci.c
1574 @@ -56,7 +56,7 @@ int ssb_pci_switch_coreidx(struct ssb_bu
1575 }
1576 return 0;
1577 error:
1578 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
1579 + ssb_err("Failed to switch to core %u\n", coreidx);
1580 return -ENODEV;
1581 }
1582
1583 @@ -67,10 +67,9 @@ int ssb_pci_switch_core(struct ssb_bus *
1584 unsigned long flags;
1585
1586 #if SSB_VERBOSE_PCICORESWITCH_DEBUG
1587 - ssb_printk(KERN_INFO PFX
1588 - "Switching to %s core, index %d\n",
1589 - ssb_core_name(dev->id.coreid),
1590 - dev->core_index);
1591 + ssb_info("Switching to %s core, index %d\n",
1592 + ssb_core_name(dev->id.coreid),
1593 + dev->core_index);
1594 #endif
1595
1596 spin_lock_irqsave(&bus->bar_lock, flags);
1597 @@ -178,6 +177,18 @@ err_pci:
1598 #define SPEX(_outvar, _offset, _mask, _shift) \
1599 SPEX16(_outvar, _offset, _mask, _shift)
1600
1601 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
1602 + do { \
1603 + SPEX(_field[0], _offset + 0, _mask, _shift); \
1604 + SPEX(_field[1], _offset + 2, _mask, _shift); \
1605 + SPEX(_field[2], _offset + 4, _mask, _shift); \
1606 + SPEX(_field[3], _offset + 6, _mask, _shift); \
1607 + SPEX(_field[4], _offset + 8, _mask, _shift); \
1608 + SPEX(_field[5], _offset + 10, _mask, _shift); \
1609 + SPEX(_field[6], _offset + 12, _mask, _shift); \
1610 + SPEX(_field[7], _offset + 14, _mask, _shift); \
1611 + } while (0)
1612 +
1613
1614 static inline u8 ssb_crc8(u8 crc, u8 data)
1615 {
1616 @@ -219,6 +230,15 @@ static inline u8 ssb_crc8(u8 crc, u8 dat
1617 return t[crc ^ data];
1618 }
1619
1620 +static void sprom_get_mac(char *mac, const u16 *in)
1621 +{
1622 + int i;
1623 + for (i = 0; i < 3; i++) {
1624 + *mac++ = in[i] >> 8;
1625 + *mac++ = in[i];
1626 + }
1627 +}
1628 +
1629 static u8 ssb_sprom_crc(const u16 *sprom, u16 size)
1630 {
1631 int word;
1632 @@ -266,7 +286,7 @@ static int sprom_do_write(struct ssb_bus
1633 u32 spromctl;
1634 u16 size = bus->sprom_size;
1635
1636 - ssb_printk(KERN_NOTICE PFX "Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1637 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
1638 err = pci_read_config_dword(pdev, SSB_SPROMCTL, &spromctl);
1639 if (err)
1640 goto err_ctlreg;
1641 @@ -274,17 +294,17 @@ static int sprom_do_write(struct ssb_bus
1642 err = pci_write_config_dword(pdev, SSB_SPROMCTL, spromctl);
1643 if (err)
1644 goto err_ctlreg;
1645 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
1646 + ssb_notice("[ 0%%");
1647 msleep(500);
1648 for (i = 0; i < size; i++) {
1649 if (i == size / 4)
1650 - ssb_printk("25%%");
1651 + ssb_cont("25%%");
1652 else if (i == size / 2)
1653 - ssb_printk("50%%");
1654 + ssb_cont("50%%");
1655 else if (i == (size * 3) / 4)
1656 - ssb_printk("75%%");
1657 + ssb_cont("75%%");
1658 else if (i % 2)
1659 - ssb_printk(".");
1660 + ssb_cont(".");
1661 writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1662 mmiowb();
1663 msleep(20);
1664 @@ -297,12 +317,12 @@ static int sprom_do_write(struct ssb_bus
1665 if (err)
1666 goto err_ctlreg;
1667 msleep(500);
1668 - ssb_printk("100%% ]\n");
1669 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
1670 + ssb_cont("100%% ]\n");
1671 + ssb_notice("SPROM written\n");
1672
1673 return 0;
1674 err_ctlreg:
1675 - ssb_printk(KERN_ERR PFX "Could not access SPROM control register.\n");
1676 + ssb_err("Could not access SPROM control register.\n");
1677 return err;
1678 }
1679
1680 @@ -327,11 +347,23 @@ static s8 r123_extract_antgain(u8 sprom_
1681 return (s8)gain;
1682 }
1683
1684 +static void sprom_extract_r23(struct ssb_sprom *out, const u16 *in)
1685 +{
1686 + SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1687 + SPEX(opo, SSB_SPROM2_OPO, SSB_SPROM2_OPO_VALUE, 0);
1688 + SPEX(pa1lob0, SSB_SPROM2_PA1LOB0, 0xFFFF, 0);
1689 + SPEX(pa1lob1, SSB_SPROM2_PA1LOB1, 0xFFFF, 0);
1690 + SPEX(pa1lob2, SSB_SPROM2_PA1LOB2, 0xFFFF, 0);
1691 + SPEX(pa1hib0, SSB_SPROM2_PA1HIB0, 0xFFFF, 0);
1692 + SPEX(pa1hib1, SSB_SPROM2_PA1HIB1, 0xFFFF, 0);
1693 + SPEX(pa1hib2, SSB_SPROM2_PA1HIB2, 0xFFFF, 0);
1694 + SPEX(maxpwr_ah, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_HI, 0);
1695 + SPEX(maxpwr_al, SSB_SPROM2_MAXP_A, SSB_SPROM2_MAXP_A_LO,
1696 + SSB_SPROM2_MAXP_A_LO_SHIFT);
1697 +}
1698 +
1699 static void sprom_extract_r123(struct ssb_sprom *out, const u16 *in)
1700 {
1701 - int i;
1702 - u16 v;
1703 - s8 gain;
1704 u16 loc[3];
1705
1706 if (out->revision == 3) /* rev 3 moved MAC */
1707 @@ -341,19 +373,10 @@ static void sprom_extract_r123(struct ss
1708 loc[1] = SSB_SPROM1_ET0MAC;
1709 loc[2] = SSB_SPROM1_ET1MAC;
1710 }
1711 - for (i = 0; i < 3; i++) {
1712 - v = in[SPOFF(loc[0]) + i];
1713 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1714 - }
1715 + sprom_get_mac(out->il0mac, &in[SPOFF(loc[0])]);
1716 if (out->revision < 3) { /* only rev 1-2 have et0, et1 */
1717 - for (i = 0; i < 3; i++) {
1718 - v = in[SPOFF(loc[1]) + i];
1719 - *(((__be16 *)out->et0mac) + i) = cpu_to_be16(v);
1720 - }
1721 - for (i = 0; i < 3; i++) {
1722 - v = in[SPOFF(loc[2]) + i];
1723 - *(((__be16 *)out->et1mac) + i) = cpu_to_be16(v);
1724 - }
1725 + sprom_get_mac(out->et0mac, &in[SPOFF(loc[1])]);
1726 + sprom_get_mac(out->et1mac, &in[SPOFF(loc[2])]);
1727 }
1728 SPEX(et0phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0A, 0);
1729 SPEX(et1phyaddr, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1A,
1730 @@ -361,8 +384,10 @@ static void sprom_extract_r123(struct ss
1731 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
1732 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
1733 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
1734 - SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1735 - SSB_SPROM1_BINF_CCODE_SHIFT);
1736 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1737 + if (out->revision == 1)
1738 + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
1739 + SSB_SPROM1_BINF_CCODE_SHIFT);
1740 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
1741 SSB_SPROM1_BINF_ANTA_SHIFT);
1742 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
1743 @@ -386,24 +411,19 @@ static void sprom_extract_r123(struct ss
1744 SSB_SPROM1_ITSSI_A_SHIFT);
1745 SPEX(itssi_bg, SSB_SPROM1_ITSSI, SSB_SPROM1_ITSSI_BG, 0);
1746 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
1747 - if (out->revision >= 2)
1748 - SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1749 +
1750 + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
1751 + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
1752
1753 /* Extract the antenna gain values. */
1754 - gain = r123_extract_antgain(out->revision, in,
1755 - SSB_SPROM1_AGAIN_BG,
1756 - SSB_SPROM1_AGAIN_BG_SHIFT);
1757 - out->antenna_gain.ghz24.a0 = gain;
1758 - out->antenna_gain.ghz24.a1 = gain;
1759 - out->antenna_gain.ghz24.a2 = gain;
1760 - out->antenna_gain.ghz24.a3 = gain;
1761 - gain = r123_extract_antgain(out->revision, in,
1762 - SSB_SPROM1_AGAIN_A,
1763 - SSB_SPROM1_AGAIN_A_SHIFT);
1764 - out->antenna_gain.ghz5.a0 = gain;
1765 - out->antenna_gain.ghz5.a1 = gain;
1766 - out->antenna_gain.ghz5.a2 = gain;
1767 - out->antenna_gain.ghz5.a3 = gain;
1768 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1769 + SSB_SPROM1_AGAIN_BG,
1770 + SSB_SPROM1_AGAIN_BG_SHIFT);
1771 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1772 + SSB_SPROM1_AGAIN_A,
1773 + SSB_SPROM1_AGAIN_A_SHIFT);
1774 + if (out->revision >= 2)
1775 + sprom_extract_r23(out, in);
1776 }
1777
1778 /* Revs 4 5 and 8 have partially shared layout */
1779 @@ -448,30 +468,30 @@ static void sprom_extract_r458(struct ss
1780
1781 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1782 {
1783 - int i;
1784 - u16 v;
1785 u16 il0mac_offset;
1786
1787 if (out->revision == 4)
1788 il0mac_offset = SSB_SPROM4_IL0MAC;
1789 else
1790 il0mac_offset = SSB_SPROM5_IL0MAC;
1791 - /* extract the MAC address */
1792 - for (i = 0; i < 3; i++) {
1793 - v = in[SPOFF(il0mac_offset) + i];
1794 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1795 - }
1796 +
1797 + sprom_get_mac(out->il0mac, &in[SPOFF(il0mac_offset)]);
1798 +
1799 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
1800 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
1801 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
1802 + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
1803 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1804 if (out->revision == 4) {
1805 - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1806 + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
1807 + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
1808 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1809 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1810 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1811 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1812 } else {
1813 - SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1814 + SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
1815 + SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
1816 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1817 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1818 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1819 @@ -504,16 +524,14 @@ static void sprom_extract_r45(struct ssb
1820 }
1821
1822 /* Extract the antenna gain values. */
1823 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1824 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1825 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1826 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1827 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1828 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1829 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1830 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1831 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1832 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1833 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1834 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1835 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1836 - sizeof(out->antenna_gain.ghz5));
1837
1838 sprom_extract_r458(out, in);
1839
1840 @@ -523,14 +541,21 @@ static void sprom_extract_r45(struct ssb
1841 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1842 {
1843 int i;
1844 - u16 v;
1845 + u16 o;
1846 + u16 pwr_info_offset[] = {
1847 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1848 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1849 + };
1850 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1851 + ARRAY_SIZE(out->core_pwr_info));
1852
1853 /* extract the MAC address */
1854 - for (i = 0; i < 3; i++) {
1855 - v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1856 - *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1857 - }
1858 - SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1859 + sprom_get_mac(out->il0mac, &in[SPOFF(SSB_SPROM8_IL0MAC)]);
1860 +
1861 + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
1862 + SPEX(board_type, SSB_SPROM1_SPID, 0xFFFF, 0);
1863 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
1864 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
1865 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1866 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1867 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1868 @@ -596,16 +621,46 @@ static void sprom_extract_r8(struct ssb_
1869 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1870
1871 /* Extract the antenna gain values. */
1872 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1873 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1874 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1875 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
1876 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1877 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1878 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
1879 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1880 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1881 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
1882 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1883 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1884 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1885 - sizeof(out->antenna_gain.ghz5));
1886 +
1887 + /* Extract cores power info info */
1888 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1889 + o = pwr_info_offset[i];
1890 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1891 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1892 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1893 + SSB_SPROM8_2G_MAXP, 0);
1894 +
1895 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1896 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1897 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1898 +
1899 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1900 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1901 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1902 + SSB_SPROM8_5G_MAXP, 0);
1903 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1904 + SSB_SPROM8_5GH_MAXP, 0);
1905 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1906 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1907 +
1908 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1909 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1910 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1911 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1912 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1913 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1914 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1915 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1916 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1917 + }
1918
1919 /* Extract FEM info */
1920 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1921 @@ -630,6 +685,63 @@ static void sprom_extract_r8(struct ssb_
1922 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1923 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1924
1925 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1926 + SSB_SPROM8_LEDDC_ON_SHIFT);
1927 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
1928 + SSB_SPROM8_LEDDC_OFF_SHIFT);
1929 +
1930 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
1931 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
1932 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
1933 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
1934 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
1935 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
1936 +
1937 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
1938 +
1939 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
1940 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
1941 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
1942 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
1943 +
1944 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
1945 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
1946 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
1947 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
1948 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
1949 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
1950 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
1951 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
1952 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
1953 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
1954 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
1955 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
1956 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
1957 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
1958 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
1959 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
1960 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
1961 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
1962 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
1963 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
1964 +
1965 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
1966 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
1967 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
1968 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
1969 +
1970 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
1971 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
1972 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
1973 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
1974 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
1975 + SSB_SPROM8_TEMPDELTA_PHYCAL,
1976 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
1977 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
1978 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
1979 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
1980 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
1981 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
1982 sprom_extract_r458(out, in);
1983
1984 /* TODO - get remaining rev 8 stuff needed */
1985 @@ -641,7 +753,7 @@ static int sprom_extract(struct ssb_bus
1986 memset(out, 0, sizeof(*out));
1987
1988 out->revision = in[size - 1] & 0x00FF;
1989 - ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1990 + ssb_dbg("SPROM revision %d detected\n", out->revision);
1991 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1992 memset(out->et1mac, 0xFF, 6);
1993
1994 @@ -650,7 +762,7 @@ static int sprom_extract(struct ssb_bus
1995 * number stored in the SPROM.
1996 * Always extract r1. */
1997 out->revision = 1;
1998 - ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1999 + ssb_dbg("SPROM treated as revision %d\n", out->revision);
2000 }
2001
2002 switch (out->revision) {
2003 @@ -667,9 +779,8 @@ static int sprom_extract(struct ssb_bus
2004 sprom_extract_r8(out, in);
2005 break;
2006 default:
2007 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
2008 - " revision %d detected. Will extract"
2009 - " v1\n", out->revision);
2010 + ssb_warn("Unsupported SPROM revision %d detected. Will extract v1\n",
2011 + out->revision);
2012 out->revision = 1;
2013 sprom_extract_r123(out, in);
2014 }
2015 @@ -689,7 +800,7 @@ static int ssb_pci_sprom_get(struct ssb_
2016 u16 *buf;
2017
2018 if (!ssb_is_sprom_available(bus)) {
2019 - ssb_printk(KERN_ERR PFX "No SPROM available!\n");
2020 + ssb_err("No SPROM available!\n");
2021 return -ENODEV;
2022 }
2023 if (bus->chipco.dev) { /* can be unavailable! */
2024 @@ -708,7 +819,7 @@ static int ssb_pci_sprom_get(struct ssb_
2025 } else {
2026 bus->sprom_offset = SSB_SPROM_BASE1;
2027 }
2028 - ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
2029 + ssb_dbg("SPROM offset is 0x%x\n", bus->sprom_offset);
2030
2031 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
2032 if (!buf)
2033 @@ -733,18 +844,15 @@ static int ssb_pci_sprom_get(struct ssb_
2034 * available for this device in some other storage */
2035 err = ssb_fill_sprom_with_fallback(bus, sprom);
2036 if (err) {
2037 - ssb_printk(KERN_WARNING PFX "WARNING: Using"
2038 - " fallback SPROM failed (err %d)\n",
2039 - err);
2040 + ssb_warn("WARNING: Using fallback SPROM failed (err %d)\n",
2041 + err);
2042 } else {
2043 - ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
2044 - " revision %d provided by"
2045 - " platform.\n", sprom->revision);
2046 + ssb_dbg("Using SPROM revision %d provided by platform\n",
2047 + sprom->revision);
2048 err = 0;
2049 goto out_free;
2050 }
2051 - ssb_printk(KERN_WARNING PFX "WARNING: Invalid"
2052 - " SPROM CRC (corrupt SPROM)\n");
2053 + ssb_warn("WARNING: Invalid SPROM CRC (corrupt SPROM)\n");
2054 }
2055 }
2056 err = sprom_extract(bus, sprom, buf, bus->sprom_size);
2057 @@ -759,7 +867,6 @@ static void ssb_pci_get_boardinfo(struct
2058 {
2059 bi->vendor = bus->host_pci->subsystem_vendor;
2060 bi->type = bus->host_pci->subsystem_device;
2061 - bi->rev = bus->host_pci->revision;
2062 }
2063
2064 int ssb_pci_get_invariants(struct ssb_bus *bus,
2065 --- a/drivers/ssb/pcihost_wrapper.c
2066 +++ b/drivers/ssb/pcihost_wrapper.c
2067 @@ -38,7 +38,7 @@ static int ssb_pcihost_resume(struct pci
2068 struct ssb_bus *ssb = pci_get_drvdata(dev);
2069 int err;
2070
2071 - pci_set_power_state(dev, 0);
2072 + pci_set_power_state(dev, PCI_D0);
2073 err = pci_enable_device(dev);
2074 if (err)
2075 return err;
2076 --- a/drivers/ssb/pcmcia.c
2077 +++ b/drivers/ssb/pcmcia.c
2078 @@ -143,7 +143,7 @@ int ssb_pcmcia_switch_coreidx(struct ssb
2079
2080 return 0;
2081 error:
2082 - ssb_printk(KERN_ERR PFX "Failed to switch to core %u\n", coreidx);
2083 + ssb_err("Failed to switch to core %u\n", coreidx);
2084 return err;
2085 }
2086
2087 @@ -153,10 +153,9 @@ int ssb_pcmcia_switch_core(struct ssb_bu
2088 int err;
2089
2090 #if SSB_VERBOSE_PCMCIACORESWITCH_DEBUG
2091 - ssb_printk(KERN_INFO PFX
2092 - "Switching to %s core, index %d\n",
2093 - ssb_core_name(dev->id.coreid),
2094 - dev->core_index);
2095 + ssb_info("Switching to %s core, index %d\n",
2096 + ssb_core_name(dev->id.coreid),
2097 + dev->core_index);
2098 #endif
2099
2100 err = ssb_pcmcia_switch_coreidx(bus, dev->core_index);
2101 @@ -192,7 +191,7 @@ int ssb_pcmcia_switch_segment(struct ssb
2102
2103 return 0;
2104 error:
2105 - ssb_printk(KERN_ERR PFX "Failed to switch pcmcia segment\n");
2106 + ssb_err("Failed to switch pcmcia segment\n");
2107 return err;
2108 }
2109
2110 @@ -549,44 +548,39 @@ static int ssb_pcmcia_sprom_write_all(st
2111 bool failed = 0;
2112 size_t size = SSB_PCMCIA_SPROM_SIZE;
2113
2114 - ssb_printk(KERN_NOTICE PFX
2115 - "Writing SPROM. Do NOT turn off the power! "
2116 - "Please stand by...\n");
2117 + ssb_notice("Writing SPROM. Do NOT turn off the power! Please stand by...\n");
2118 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEEN);
2119 if (err) {
2120 - ssb_printk(KERN_NOTICE PFX
2121 - "Could not enable SPROM write access.\n");
2122 + ssb_notice("Could not enable SPROM write access\n");
2123 return -EBUSY;
2124 }
2125 - ssb_printk(KERN_NOTICE PFX "[ 0%%");
2126 + ssb_notice("[ 0%%");
2127 msleep(500);
2128 for (i = 0; i < size; i++) {
2129 if (i == size / 4)
2130 - ssb_printk("25%%");
2131 + ssb_cont("25%%");
2132 else if (i == size / 2)
2133 - ssb_printk("50%%");
2134 + ssb_cont("50%%");
2135 else if (i == (size * 3) / 4)
2136 - ssb_printk("75%%");
2137 + ssb_cont("75%%");
2138 else if (i % 2)
2139 - ssb_printk(".");
2140 + ssb_cont(".");
2141 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
2142 if (err) {
2143 - ssb_printk(KERN_NOTICE PFX
2144 - "Failed to write to SPROM.\n");
2145 + ssb_notice("Failed to write to SPROM\n");
2146 failed = 1;
2147 break;
2148 }
2149 }
2150 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
2151 if (err) {
2152 - ssb_printk(KERN_NOTICE PFX
2153 - "Could not disable SPROM write access.\n");
2154 + ssb_notice("Could not disable SPROM write access\n");
2155 failed = 1;
2156 }
2157 msleep(500);
2158 if (!failed) {
2159 - ssb_printk("100%% ]\n");
2160 - ssb_printk(KERN_NOTICE PFX "SPROM written.\n");
2161 + ssb_cont("100%% ]\n");
2162 + ssb_notice("SPROM written\n");
2163 }
2164
2165 return failed ? -EBUSY : 0;
2166 @@ -676,14 +670,10 @@ static int ssb_pcmcia_do_get_invariants(
2167 case SSB_PCMCIA_CIS_ANTGAIN:
2168 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2169 "antg tpl size");
2170 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
2171 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
2172 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
2173 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
2174 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
2175 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
2176 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
2177 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
2178 + sprom->antenna_gain.a0 = tuple->TupleData[1];
2179 + sprom->antenna_gain.a1 = tuple->TupleData[1];
2180 + sprom->antenna_gain.a2 = tuple->TupleData[1];
2181 + sprom->antenna_gain.a3 = tuple->TupleData[1];
2182 break;
2183 case SSB_PCMCIA_CIS_BFLAGS:
2184 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2185 @@ -704,7 +694,7 @@ static int ssb_pcmcia_do_get_invariants(
2186 return -ENOSPC; /* continue with next entry */
2187
2188 error:
2189 - ssb_printk(KERN_ERR PFX
2190 + ssb_err(
2191 "PCMCIA: Failed to fetch device invariants: %s\n",
2192 error_description);
2193 return -ENODEV;
2194 @@ -726,7 +716,7 @@ int ssb_pcmcia_get_invariants(struct ssb
2195 res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
2196 ssb_pcmcia_get_mac, sprom);
2197 if (res != 0) {
2198 - ssb_printk(KERN_ERR PFX
2199 + ssb_err(
2200 "PCMCIA: Failed to fetch MAC address\n");
2201 return -ENODEV;
2202 }
2203 @@ -737,7 +727,7 @@ int ssb_pcmcia_get_invariants(struct ssb
2204 if ((res == 0) || (res == -ENOSPC))
2205 return 0;
2206
2207 - ssb_printk(KERN_ERR PFX
2208 + ssb_err(
2209 "PCMCIA: Failed to fetch device invariants\n");
2210 return -ENODEV;
2211 }
2212 @@ -847,6 +837,6 @@ int ssb_pcmcia_init(struct ssb_bus *bus)
2213
2214 return 0;
2215 error:
2216 - ssb_printk(KERN_ERR PFX "Failed to initialize PCMCIA host device\n");
2217 + ssb_err("Failed to initialize PCMCIA host device\n");
2218 return err;
2219 }
2220 --- a/drivers/ssb/scan.c
2221 +++ b/drivers/ssb/scan.c
2222 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
2223 return "ARM 1176";
2224 case SSB_DEV_ARM_7TDMI:
2225 return "ARM 7TDMI";
2226 + case SSB_DEV_ARM_CM3:
2227 + return "ARM Cortex M3";
2228 }
2229 return "UNKNOWN";
2230 }
2231 @@ -123,8 +125,7 @@ static u16 pcidev_to_chipid(struct pci_d
2232 chipid_fallback = 0x4401;
2233 break;
2234 default:
2235 - ssb_printk(KERN_ERR PFX
2236 - "PCI-ID not in fallback list\n");
2237 + ssb_err("PCI-ID not in fallback list\n");
2238 }
2239
2240 return chipid_fallback;
2241 @@ -150,8 +151,7 @@ static u8 chipid_to_nrcores(u16 chipid)
2242 case 0x4704:
2243 return 9;
2244 default:
2245 - ssb_printk(KERN_ERR PFX
2246 - "CHIPID not in nrcores fallback list\n");
2247 + ssb_err("CHIPID not in nrcores fallback list\n");
2248 }
2249
2250 return 1;
2251 @@ -318,12 +318,13 @@ int ssb_bus_scan(struct ssb_bus *bus,
2252 bus->chip_package = 0;
2253 }
2254 }
2255 + ssb_info("Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
2256 + bus->chip_id, bus->chip_rev, bus->chip_package);
2257 if (!bus->nr_devices)
2258 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
2259 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
2260 - ssb_printk(KERN_ERR PFX
2261 - "More than %d ssb cores found (%d)\n",
2262 - SSB_MAX_NR_CORES, bus->nr_devices);
2263 + ssb_err("More than %d ssb cores found (%d)\n",
2264 + SSB_MAX_NR_CORES, bus->nr_devices);
2265 goto err_unmap;
2266 }
2267 if (bus->bustype == SSB_BUSTYPE_SSB) {
2268 @@ -365,8 +366,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2269 nr_80211_cores++;
2270 if (nr_80211_cores > 1) {
2271 if (!we_support_multiple_80211_cores(bus)) {
2272 - ssb_dprintk(KERN_INFO PFX "Ignoring additional "
2273 - "802.11 core\n");
2274 + ssb_dbg("Ignoring additional 802.11 core\n");
2275 continue;
2276 }
2277 }
2278 @@ -374,8 +374,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2279 case SSB_DEV_EXTIF:
2280 #ifdef CONFIG_SSB_DRIVER_EXTIF
2281 if (bus->extif.dev) {
2282 - ssb_printk(KERN_WARNING PFX
2283 - "WARNING: Multiple EXTIFs found\n");
2284 + ssb_warn("WARNING: Multiple EXTIFs found\n");
2285 break;
2286 }
2287 bus->extif.dev = dev;
2288 @@ -383,8 +382,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2289 break;
2290 case SSB_DEV_CHIPCOMMON:
2291 if (bus->chipco.dev) {
2292 - ssb_printk(KERN_WARNING PFX
2293 - "WARNING: Multiple ChipCommon found\n");
2294 + ssb_warn("WARNING: Multiple ChipCommon found\n");
2295 break;
2296 }
2297 bus->chipco.dev = dev;
2298 @@ -393,8 +391,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2299 case SSB_DEV_MIPS_3302:
2300 #ifdef CONFIG_SSB_DRIVER_MIPS
2301 if (bus->mipscore.dev) {
2302 - ssb_printk(KERN_WARNING PFX
2303 - "WARNING: Multiple MIPS cores found\n");
2304 + ssb_warn("WARNING: Multiple MIPS cores found\n");
2305 break;
2306 }
2307 bus->mipscore.dev = dev;
2308 @@ -415,8 +412,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2309 }
2310 }
2311 if (bus->pcicore.dev) {
2312 - ssb_printk(KERN_WARNING PFX
2313 - "WARNING: Multiple PCI(E) cores found\n");
2314 + ssb_warn("WARNING: Multiple PCI(E) cores found\n");
2315 break;
2316 }
2317 bus->pcicore.dev = dev;
2318 --- a/drivers/ssb/sdio.c
2319 +++ b/drivers/ssb/sdio.c
2320 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
2321 case SSB_SDIO_CIS_ANTGAIN:
2322 GOTO_ERROR_ON(tuple->size != 2,
2323 "antg tpl size");
2324 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
2325 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
2326 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
2327 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
2328 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
2329 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
2330 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
2331 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
2332 + sprom->antenna_gain.a0 = tuple->data[1];
2333 + sprom->antenna_gain.a1 = tuple->data[1];
2334 + sprom->antenna_gain.a2 = tuple->data[1];
2335 + sprom->antenna_gain.a3 = tuple->data[1];
2336 break;
2337 case SSB_SDIO_CIS_BFLAGS:
2338 GOTO_ERROR_ON((tuple->size != 3) &&
2339 --- a/drivers/ssb/sprom.c
2340 +++ b/drivers/ssb/sprom.c
2341 @@ -54,7 +54,7 @@ static int hex2sprom(u16 *sprom, const c
2342 while (cnt < sprom_size_words) {
2343 memcpy(tmp, dump, 4);
2344 dump += 4;
2345 - err = strict_strtoul(tmp, 16, &parsed);
2346 + err = kstrtoul(tmp, 16, &parsed);
2347 if (err)
2348 return err;
2349 sprom[cnt++] = swab16((u16)parsed);
2350 @@ -127,13 +127,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
2351 goto out_kfree;
2352 err = ssb_devices_freeze(bus, &freeze);
2353 if (err) {
2354 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
2355 + ssb_err("SPROM write: Could not freeze all devices\n");
2356 goto out_unlock;
2357 }
2358 res = sprom_write(bus, sprom);
2359 err = ssb_devices_thaw(&freeze);
2360 if (err)
2361 - ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
2362 + ssb_err("SPROM write: Could not thaw all devices\n");
2363 out_unlock:
2364 mutex_unlock(&bus->sprom_mutex);
2365 out_kfree:
2366 --- a/drivers/ssb/ssb_private.h
2367 +++ b/drivers/ssb/ssb_private.h
2368 @@ -3,21 +3,33 @@
2369
2370 #include <linux/ssb/ssb.h>
2371 #include <linux/types.h>
2372 +#include <linux/bcm47xx_wdt.h>
2373
2374
2375 #define PFX "ssb: "
2376
2377 #ifdef CONFIG_SSB_SILENT
2378 -# define ssb_printk(fmt, x...) do { /* nothing */ } while (0)
2379 +# define ssb_printk(fmt, ...) \
2380 + do { if (0) printk(fmt, ##__VA_ARGS__); } while (0)
2381 #else
2382 -# define ssb_printk printk
2383 +# define ssb_printk(fmt, ...) \
2384 + printk(fmt, ##__VA_ARGS__)
2385 #endif /* CONFIG_SSB_SILENT */
2386
2387 +#define ssb_emerg(fmt, ...) ssb_printk(KERN_EMERG PFX fmt, ##__VA_ARGS__)
2388 +#define ssb_err(fmt, ...) ssb_printk(KERN_ERR PFX fmt, ##__VA_ARGS__)
2389 +#define ssb_warn(fmt, ...) ssb_printk(KERN_WARNING PFX fmt, ##__VA_ARGS__)
2390 +#define ssb_notice(fmt, ...) ssb_printk(KERN_NOTICE PFX fmt, ##__VA_ARGS__)
2391 +#define ssb_info(fmt, ...) ssb_printk(KERN_INFO PFX fmt, ##__VA_ARGS__)
2392 +#define ssb_cont(fmt, ...) ssb_printk(KERN_CONT fmt, ##__VA_ARGS__)
2393 +
2394 /* dprintk: Debugging printk; vanishes for non-debug compilation */
2395 #ifdef CONFIG_SSB_DEBUG
2396 -# define ssb_dprintk(fmt, x...) ssb_printk(fmt , ##x)
2397 +# define ssb_dbg(fmt, ...) \
2398 + ssb_printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__)
2399 #else
2400 -# define ssb_dprintk(fmt, x...) do { /* nothing */ } while (0)
2401 +# define ssb_dbg(fmt, ...) \
2402 + do { if (0) printk(KERN_DEBUG PFX fmt, ##__VA_ARGS__); } while (0)
2403 #endif
2404
2405 #ifdef CONFIG_SSB_DEBUG
2406 @@ -207,4 +219,79 @@ static inline void b43_pci_ssb_bridge_ex
2407 }
2408 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
2409
2410 +/* driver_chipcommon_pmu.c */
2411 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
2412 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
2413 +extern u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc);
2414 +
2415 +extern u32 ssb_chipco_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2416 + u32 ticks);
2417 +extern u32 ssb_chipco_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2418 +
2419 +/* driver_chipcommon_sflash.c */
2420 +#ifdef CONFIG_SSB_SFLASH
2421 +int ssb_sflash_init(struct ssb_chipcommon *cc);
2422 +#else
2423 +static inline int ssb_sflash_init(struct ssb_chipcommon *cc)
2424 +{
2425 + pr_err("Serial flash not supported\n");
2426 + return 0;
2427 +}
2428 +#endif /* CONFIG_SSB_SFLASH */
2429 +
2430 +#ifdef CONFIG_SSB_DRIVER_MIPS
2431 +extern struct platform_device ssb_pflash_dev;
2432 +#endif
2433 +
2434 +#ifdef CONFIG_SSB_SFLASH
2435 +extern struct platform_device ssb_sflash_dev;
2436 +#endif
2437 +
2438 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2439 +extern u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt, u32 ticks);
2440 +extern u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt, u32 ms);
2441 +#else
2442 +static inline u32 ssb_extif_watchdog_timer_set_wdt(struct bcm47xx_wdt *wdt,
2443 + u32 ticks)
2444 +{
2445 + return 0;
2446 +}
2447 +static inline u32 ssb_extif_watchdog_timer_set_ms(struct bcm47xx_wdt *wdt,
2448 + u32 ms)
2449 +{
2450 + return 0;
2451 +}
2452 +#endif
2453 +
2454 +#ifdef CONFIG_SSB_EMBEDDED
2455 +extern int ssb_watchdog_register(struct ssb_bus *bus);
2456 +#else /* CONFIG_SSB_EMBEDDED */
2457 +static inline int ssb_watchdog_register(struct ssb_bus *bus)
2458 +{
2459 + return 0;
2460 +}
2461 +#endif /* CONFIG_SSB_EMBEDDED */
2462 +
2463 +#ifdef CONFIG_SSB_DRIVER_EXTIF
2464 +extern void ssb_extif_init(struct ssb_extif *extif);
2465 +#else
2466 +static inline void ssb_extif_init(struct ssb_extif *extif)
2467 +{
2468 +}
2469 +#endif
2470 +
2471 +#ifdef CONFIG_SSB_DRIVER_GPIO
2472 +extern int ssb_gpio_init(struct ssb_bus *bus);
2473 +extern int ssb_gpio_unregister(struct ssb_bus *bus);
2474 +#else /* CONFIG_SSB_DRIVER_GPIO */
2475 +static inline int ssb_gpio_init(struct ssb_bus *bus)
2476 +{
2477 + return -ENOTSUPP;
2478 +}
2479 +static inline int ssb_gpio_unregister(struct ssb_bus *bus)
2480 +{
2481 + return 0;
2482 +}
2483 +#endif /* CONFIG_SSB_DRIVER_GPIO */
2484 +
2485 #endif /* LINUX_SSB_PRIVATE_H_ */
2486 --- a/include/linux/ssb/ssb.h
2487 +++ b/include/linux/ssb/ssb.h
2488 @@ -6,8 +6,10 @@
2489 #include <linux/types.h>
2490 #include <linux/spinlock.h>
2491 #include <linux/pci.h>
2492 +#include <linux/gpio.h>
2493 #include <linux/mod_devicetable.h>
2494 #include <linux/dma-mapping.h>
2495 +#include <linux/platform_device.h>
2496
2497 #include <linux/ssb/ssb_regs.h>
2498
2499 @@ -16,19 +18,28 @@ struct pcmcia_device;
2500 struct ssb_bus;
2501 struct ssb_driver;
2502
2503 +struct ssb_sprom_core_pwr_info {
2504 + u8 itssi_2g, itssi_5g;
2505 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
2506 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
2507 +};
2508 +
2509 struct ssb_sprom {
2510 u8 revision;
2511 - u8 il0mac[6]; /* MAC address for 802.11b/g */
2512 - u8 et0mac[6]; /* MAC address for Ethernet */
2513 - u8 et1mac[6]; /* MAC address for 802.11a */
2514 + u8 il0mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11b/g */
2515 + u8 et0mac[6] __aligned(sizeof(u16)); /* MAC address for Ethernet */
2516 + u8 et1mac[6] __aligned(sizeof(u16)); /* MAC address for 802.11a */
2517 u8 et0phyaddr; /* MII address for enet0 */
2518 u8 et1phyaddr; /* MII address for enet1 */
2519 u8 et0mdcport; /* MDIO for enet0 */
2520 u8 et1mdcport; /* MDIO for enet1 */
2521 u16 board_rev; /* Board revision number from SPROM. */
2522 + u16 board_num; /* Board number from SPROM. */
2523 + u16 board_type; /* Board type from SPROM. */
2524 u8 country_code; /* Country Code */
2525 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
2526 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
2527 + char alpha2[2]; /* Country Code as two chars like EU or US */
2528 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
2529 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
2530 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
2531 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
2532 u16 pa0b0;
2533 @@ -47,10 +58,10 @@ struct ssb_sprom {
2534 u8 gpio1; /* GPIO pin 1 */
2535 u8 gpio2; /* GPIO pin 2 */
2536 u8 gpio3; /* GPIO pin 3 */
2537 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2538 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2539 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2540 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2541 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
2542 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
2543 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
2544 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
2545 u8 itssi_a; /* Idle TSSI Target for A-PHY */
2546 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
2547 u8 tri2g; /* 2.4GHz TX isolation */
2548 @@ -61,8 +72,8 @@ struct ssb_sprom {
2549 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
2550 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
2551 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
2552 - u8 rxpo2g; /* 2GHz RX power offset */
2553 - u8 rxpo5g; /* 5GHz RX power offset */
2554 + s8 rxpo2g; /* 2GHz RX power offset */
2555 + s8 rxpo5g; /* 5GHz RX power offset */
2556 u8 rssisav2g; /* 2GHz RSSI params */
2557 u8 rssismc2g;
2558 u8 rssismf2g;
2559 @@ -82,16 +93,13 @@ struct ssb_sprom {
2560 u16 boardflags2_hi; /* Board flags (bits 48-63) */
2561 /* TODO store board flags in a single u64 */
2562
2563 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
2564 +
2565 /* Antenna gain values for up to 4 antennas
2566 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
2567 * loss in the connectors is bigger than the gain. */
2568 struct {
2569 - struct {
2570 - s8 a0, a1, a2, a3;
2571 - } ghz24; /* 2.4GHz band */
2572 - struct {
2573 - s8 a0, a1, a2, a3;
2574 - } ghz5; /* 5GHz band */
2575 + s8 a0, a1, a2, a3;
2576 } antenna_gain;
2577
2578 struct {
2579 @@ -103,14 +111,85 @@ struct ssb_sprom {
2580 } ghz5;
2581 } fem;
2582
2583 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
2584 + u16 mcs2gpo[8];
2585 + u16 mcs5gpo[8];
2586 + u16 mcs5glpo[8];
2587 + u16 mcs5ghpo[8];
2588 + u8 opo;
2589 +
2590 + u8 rxgainerr2ga[3];
2591 + u8 rxgainerr5gla[3];
2592 + u8 rxgainerr5gma[3];
2593 + u8 rxgainerr5gha[3];
2594 + u8 rxgainerr5gua[3];
2595 +
2596 + u8 noiselvl2ga[3];
2597 + u8 noiselvl5gla[3];
2598 + u8 noiselvl5gma[3];
2599 + u8 noiselvl5gha[3];
2600 + u8 noiselvl5gua[3];
2601 +
2602 + u8 regrev;
2603 + u8 txchain;
2604 + u8 rxchain;
2605 + u8 antswitch;
2606 + u16 cddpo;
2607 + u16 stbcpo;
2608 + u16 bw40po;
2609 + u16 bwduppo;
2610 +
2611 + u8 tempthresh;
2612 + u8 tempoffset;
2613 + u16 rawtempsense;
2614 + u8 measpower;
2615 + u8 tempsense_slope;
2616 + u8 tempcorrx;
2617 + u8 tempsense_option;
2618 + u8 freqoffset_corr;
2619 + u8 iqcal_swp_dis;
2620 + u8 hw_iqcal_en;
2621 + u8 elna2g;
2622 + u8 elna5g;
2623 + u8 phycal_tempdelta;
2624 + u8 temps_period;
2625 + u8 temps_hysteresis;
2626 + u8 measpower1;
2627 + u8 measpower2;
2628 + u8 pcieingress_war;
2629 +
2630 + /* power per rate from sromrev 9 */
2631 + u16 cckbw202gpo;
2632 + u16 cckbw20ul2gpo;
2633 + u32 legofdmbw202gpo;
2634 + u32 legofdmbw20ul2gpo;
2635 + u32 legofdmbw205glpo;
2636 + u32 legofdmbw20ul5glpo;
2637 + u32 legofdmbw205gmpo;
2638 + u32 legofdmbw20ul5gmpo;
2639 + u32 legofdmbw205ghpo;
2640 + u32 legofdmbw20ul5ghpo;
2641 + u32 mcsbw202gpo;
2642 + u32 mcsbw20ul2gpo;
2643 + u32 mcsbw402gpo;
2644 + u32 mcsbw205glpo;
2645 + u32 mcsbw20ul5glpo;
2646 + u32 mcsbw405glpo;
2647 + u32 mcsbw205gmpo;
2648 + u32 mcsbw20ul5gmpo;
2649 + u32 mcsbw405gmpo;
2650 + u32 mcsbw205ghpo;
2651 + u32 mcsbw20ul5ghpo;
2652 + u32 mcsbw405ghpo;
2653 + u16 mcs32po;
2654 + u16 legofdm40duppo;
2655 + u8 sar2g;
2656 + u8 sar5g;
2657 };
2658
2659 /* Information about the PCB the circuitry is soldered on. */
2660 struct ssb_boardinfo {
2661 u16 vendor;
2662 u16 type;
2663 - u8 rev;
2664 };
2665
2666
2667 @@ -166,6 +245,7 @@ struct ssb_bus_ops {
2668 #define SSB_DEV_MINI_MACPHY 0x823
2669 #define SSB_DEV_ARM_1176 0x824
2670 #define SSB_DEV_ARM_7TDMI 0x825
2671 +#define SSB_DEV_ARM_CM3 0x82A
2672
2673 /* Vendor-ID values */
2674 #define SSB_VENDOR_BROADCOM 0x4243
2675 @@ -260,13 +340,61 @@ enum ssb_bustype {
2676 #define SSB_BOARDVENDOR_DELL 0x1028 /* Dell */
2677 #define SSB_BOARDVENDOR_HP 0x0E11 /* HP */
2678 /* board_type */
2679 +#define SSB_BOARD_BCM94301CB 0x0406
2680 +#define SSB_BOARD_BCM94301MP 0x0407
2681 +#define SSB_BOARD_BU4309 0x040A
2682 +#define SSB_BOARD_BCM94309CB 0x040B
2683 +#define SSB_BOARD_BCM4309MP 0x040C
2684 +#define SSB_BOARD_BU4306 0x0416
2685 #define SSB_BOARD_BCM94306MP 0x0418
2686 #define SSB_BOARD_BCM4309G 0x0421
2687 #define SSB_BOARD_BCM4306CB 0x0417
2688 -#define SSB_BOARD_BCM4309MP 0x040C
2689 +#define SSB_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */
2690 +#define SSB_BOARD_BCM94306CBSG 0x042B /* with SiGe PA */
2691 +#define SSB_BOARD_PCSG94306 0x042D /* with SiGe PA */
2692 +#define SSB_BOARD_BU4704SD 0x042E /* with sdram */
2693 +#define SSB_BOARD_BCM94704AGR 0x042F /* dual 11a/11g Router */
2694 +#define SSB_BOARD_BCM94308MP 0x0430 /* 11a-only minipci */
2695 +#define SSB_BOARD_BU4318 0x0447
2696 +#define SSB_BOARD_CB4318 0x0448
2697 +#define SSB_BOARD_MPG4318 0x0449
2698 #define SSB_BOARD_MP4318 0x044A
2699 -#define SSB_BOARD_BU4306 0x0416
2700 -#define SSB_BOARD_BU4309 0x040A
2701 +#define SSB_BOARD_SD4318 0x044B
2702 +#define SSB_BOARD_BCM94306P 0x044C /* with SiGe */
2703 +#define SSB_BOARD_BCM94303MP 0x044E
2704 +#define SSB_BOARD_BCM94306MPM 0x0450
2705 +#define SSB_BOARD_BCM94306MPL 0x0453
2706 +#define SSB_BOARD_PC4303 0x0454 /* pcmcia */
2707 +#define SSB_BOARD_BCM94306MPLNA 0x0457
2708 +#define SSB_BOARD_BCM94306MPH 0x045B
2709 +#define SSB_BOARD_BCM94306PCIV 0x045C
2710 +#define SSB_BOARD_BCM94318MPGH 0x0463
2711 +#define SSB_BOARD_BU4311 0x0464
2712 +#define SSB_BOARD_BCM94311MC 0x0465
2713 +#define SSB_BOARD_BCM94311MCAG 0x0466
2714 +/* 4321 boards */
2715 +#define SSB_BOARD_BU4321 0x046B
2716 +#define SSB_BOARD_BU4321E 0x047C
2717 +#define SSB_BOARD_MP4321 0x046C
2718 +#define SSB_BOARD_CB2_4321 0x046D
2719 +#define SSB_BOARD_CB2_4321_AG 0x0066
2720 +#define SSB_BOARD_MC4321 0x046E
2721 +/* 4325 boards */
2722 +#define SSB_BOARD_BCM94325DEVBU 0x0490
2723 +#define SSB_BOARD_BCM94325BGABU 0x0491
2724 +#define SSB_BOARD_BCM94325SDGWB 0x0492
2725 +#define SSB_BOARD_BCM94325SDGMDL 0x04AA
2726 +#define SSB_BOARD_BCM94325SDGMDL2 0x04C6
2727 +#define SSB_BOARD_BCM94325SDGMDL3 0x04C9
2728 +#define SSB_BOARD_BCM94325SDABGWBA 0x04E1
2729 +/* 4322 boards */
2730 +#define SSB_BOARD_BCM94322MC 0x04A4
2731 +#define SSB_BOARD_BCM94322USB 0x04A8 /* dualband */
2732 +#define SSB_BOARD_BCM94322HM 0x04B0
2733 +#define SSB_BOARD_BCM94322USB2D 0x04Bf /* single band discrete front end */
2734 +/* 4312 boards */
2735 +#define SSB_BOARD_BU4312 0x048A
2736 +#define SSB_BOARD_BCM4312MCGSG 0x04B5
2737 /* chip_package */
2738 #define SSB_CHIPPACK_BCM4712S 1 /* Small 200pin 4712 */
2739 #define SSB_CHIPPACK_BCM4712M 2 /* Medium 225pin 4712 */
2740 @@ -354,7 +482,11 @@ struct ssb_bus {
2741 #ifdef CONFIG_SSB_EMBEDDED
2742 /* Lock for GPIO register access. */
2743 spinlock_t gpio_lock;
2744 + struct platform_device *watchdog;
2745 #endif /* EMBEDDED */
2746 +#ifdef CONFIG_SSB_DRIVER_GPIO
2747 + struct gpio_chip gpio;
2748 +#endif /* DRIVER_GPIO */
2749
2750 /* Internal-only stuff follows. Do not touch. */
2751 struct list_head list;
2752 --- a/include/linux/ssb/ssb_driver_chipcommon.h
2753 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
2754 @@ -219,6 +219,7 @@
2755 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
2756 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
2757 #define SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT 16
2758 +#define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
2759 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
2760 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
2761 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
2762 @@ -504,7 +505,9 @@
2763 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
2764 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
2765 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
2766 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
2767 +#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
2768 +#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
2769 +#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
2770
2771 /* Status register bits for ST flashes */
2772 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
2773 @@ -588,7 +591,10 @@ struct ssb_chipcommon {
2774 u32 status;
2775 /* Fast Powerup Delay constant */
2776 u16 fast_pwrup_delay;
2777 + spinlock_t gpio_lock;
2778 struct ssb_chipcommon_pmu pmu;
2779 + u32 ticks_per_ms;
2780 + u32 max_timer_ms;
2781 };
2782
2783 static inline bool ssb_chipco_available(struct ssb_chipcommon *cc)
2784 @@ -628,8 +634,7 @@ enum ssb_clkmode {
2785 extern void ssb_chipco_set_clockmode(struct ssb_chipcommon *cc,
2786 enum ssb_clkmode mode);
2787
2788 -extern void ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc,
2789 - u32 ticks);
2790 +extern u32 ssb_chipco_watchdog_timer_set(struct ssb_chipcommon *cc, u32 ticks);
2791
2792 void ssb_chipco_irq_mask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2793
2794 @@ -642,6 +647,8 @@ u32 ssb_chipco_gpio_outen(struct ssb_chi
2795 u32 ssb_chipco_gpio_control(struct ssb_chipcommon *cc, u32 mask, u32 value);
2796 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value);
2797 u32 ssb_chipco_gpio_polarity(struct ssb_chipcommon *cc, u32 mask, u32 value);
2798 +u32 ssb_chipco_gpio_pullup(struct ssb_chipcommon *cc, u32 mask, u32 value);
2799 +u32 ssb_chipco_gpio_pulldown(struct ssb_chipcommon *cc, u32 mask, u32 value);
2800
2801 #ifdef CONFIG_SSB_SERIAL
2802 extern int ssb_chipco_serial_init(struct ssb_chipcommon *cc,
2803 @@ -661,5 +668,6 @@ enum ssb_pmu_ldo_volt_id {
2804 void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
2805 enum ssb_pmu_ldo_volt_id id, u32 voltage);
2806 void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
2807 +void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid);
2808
2809 #endif /* LINUX_SSB_CHIPCO_H_ */
2810 --- a/include/linux/ssb/ssb_driver_extif.h
2811 +++ b/include/linux/ssb/ssb_driver_extif.h
2812 @@ -152,12 +152,16 @@
2813 /* watchdog */
2814 #define SSB_EXTIF_WATCHDOG_CLK 48000000 /* Hz */
2815
2816 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER ((1 << 28) - 1)
2817 +#define SSB_EXTIF_WATCHDOG_MAX_TIMER_MS (SSB_EXTIF_WATCHDOG_MAX_TIMER \
2818 + / (SSB_EXTIF_WATCHDOG_CLK / 1000))
2819
2820
2821 #ifdef CONFIG_SSB_DRIVER_EXTIF
2822
2823 struct ssb_extif {
2824 struct ssb_device *dev;
2825 + spinlock_t gpio_lock;
2826 };
2827
2828 static inline bool ssb_extif_available(struct ssb_extif *extif)
2829 @@ -171,8 +175,7 @@ extern void ssb_extif_get_clockcontrol(s
2830 extern void ssb_extif_timing_init(struct ssb_extif *extif,
2831 unsigned long ns);
2832
2833 -extern void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2834 - u32 ticks);
2835 +extern u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks);
2836
2837 /* Extif GPIO pin access */
2838 u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask);
2839 @@ -205,10 +208,52 @@ void ssb_extif_get_clockcontrol(struct s
2840 }
2841
2842 static inline
2843 -void ssb_extif_watchdog_timer_set(struct ssb_extif *extif,
2844 - u32 ticks)
2845 +void ssb_extif_timing_init(struct ssb_extif *extif, unsigned long ns)
2846 {
2847 }
2848
2849 +static inline
2850 +u32 ssb_extif_watchdog_timer_set(struct ssb_extif *extif, u32 ticks)
2851 +{
2852 + return 0;
2853 +}
2854 +
2855 +static inline u32 ssb_extif_gpio_in(struct ssb_extif *extif, u32 mask)
2856 +{
2857 + return 0;
2858 +}
2859 +
2860 +static inline u32 ssb_extif_gpio_out(struct ssb_extif *extif, u32 mask,
2861 + u32 value)
2862 +{
2863 + return 0;
2864 +}
2865 +
2866 +static inline u32 ssb_extif_gpio_outen(struct ssb_extif *extif, u32 mask,
2867 + u32 value)
2868 +{
2869 + return 0;
2870 +}
2871 +
2872 +static inline u32 ssb_extif_gpio_polarity(struct ssb_extif *extif, u32 mask,
2873 + u32 value)
2874 +{
2875 + return 0;
2876 +}
2877 +
2878 +static inline u32 ssb_extif_gpio_intmask(struct ssb_extif *extif, u32 mask,
2879 + u32 value)
2880 +{
2881 + return 0;
2882 +}
2883 +
2884 +#ifdef CONFIG_SSB_SERIAL
2885 +static inline int ssb_extif_serial_init(struct ssb_extif *extif,
2886 + struct ssb_serial_port *ports)
2887 +{
2888 + return 0;
2889 +}
2890 +#endif /* CONFIG_SSB_SERIAL */
2891 +
2892 #endif /* CONFIG_SSB_DRIVER_EXTIF */
2893 #endif /* LINUX_SSB_EXTIFCORE_H_ */
2894 --- a/include/linux/ssb/ssb_driver_gige.h
2895 +++ b/include/linux/ssb/ssb_driver_gige.h
2896 @@ -2,6 +2,7 @@
2897 #define LINUX_SSB_DRIVER_GIGE_H_
2898
2899 #include <linux/ssb/ssb.h>
2900 +#include <linux/bug.h>
2901 #include <linux/pci.h>
2902 #include <linux/spinlock.h>
2903
2904 @@ -96,21 +97,16 @@ static inline bool ssb_gige_must_flush_p
2905 return 0;
2906 }
2907
2908 -#ifdef CONFIG_BCM47XX
2909 -#include <asm/mach-bcm47xx/nvram.h>
2910 /* Get the device MAC address */
2911 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2912 -{
2913 - char buf[20];
2914 - if (nvram_getenv("et0macaddr", buf, sizeof(buf)) < 0)
2915 - return;
2916 - nvram_parse_macaddr(buf, macaddr);
2917 -}
2918 -#else
2919 -static inline void ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2920 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2921 {
2922 + struct ssb_gige *dev = pdev_to_ssb_gige(pdev);
2923 + if (!dev)
2924 + return -ENODEV;
2925 +
2926 + memcpy(macaddr, dev->dev->bus->sprom.et0mac, 6);
2927 + return 0;
2928 }
2929 -#endif
2930
2931 extern int ssb_gige_pcibios_plat_dev_init(struct ssb_device *sdev,
2932 struct pci_dev *pdev);
2933 @@ -174,6 +170,10 @@ static inline bool ssb_gige_must_flush_p
2934 {
2935 return 0;
2936 }
2937 +static inline int ssb_gige_get_macaddr(struct pci_dev *pdev, u8 *macaddr)
2938 +{
2939 + return -ENODEV;
2940 +}
2941
2942 #endif /* CONFIG_SSB_DRIVER_GIGE */
2943 #endif /* LINUX_SSB_DRIVER_GIGE_H_ */
2944 --- a/include/linux/ssb/ssb_driver_mips.h
2945 +++ b/include/linux/ssb/ssb_driver_mips.h
2946 @@ -13,6 +13,24 @@ struct ssb_serial_port {
2947 unsigned int reg_shift;
2948 };
2949
2950 +struct ssb_pflash {
2951 + bool present;
2952 + u8 buswidth;
2953 + u32 window;
2954 + u32 window_size;
2955 +};
2956 +
2957 +#ifdef CONFIG_SSB_SFLASH
2958 +struct ssb_sflash {
2959 + bool present;
2960 + u32 window;
2961 + u32 blocksize;
2962 + u16 numblocks;
2963 + u32 size;
2964 +
2965 + void *priv;
2966 +};
2967 +#endif
2968
2969 struct ssb_mipscore {
2970 struct ssb_device *dev;
2971 @@ -20,9 +38,10 @@ struct ssb_mipscore {
2972 int nr_serial_ports;
2973 struct ssb_serial_port serial_ports[4];
2974
2975 - u8 flash_buswidth;
2976 - u32 flash_window;
2977 - u32 flash_window_size;
2978 + struct ssb_pflash pflash;
2979 +#ifdef CONFIG_SSB_SFLASH
2980 + struct ssb_sflash sflash;
2981 +#endif
2982 };
2983
2984 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
2985 @@ -41,6 +60,11 @@ void ssb_mipscore_init(struct ssb_mipsco
2986 {
2987 }
2988
2989 +static inline unsigned int ssb_mips_irq(struct ssb_device *dev)
2990 +{
2991 + return 0;
2992 +}
2993 +
2994 #endif /* CONFIG_SSB_DRIVER_MIPS */
2995
2996 #endif /* LINUX_SSB_MIPSCORE_H_ */
2997 --- a/include/linux/ssb/ssb_regs.h
2998 +++ b/include/linux/ssb/ssb_regs.h
2999 @@ -172,6 +172,7 @@
3000 #define SSB_SPROMSIZE_WORDS_R4 220
3001 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
3002 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
3003 +#define SSB_SPROMSIZE_WORDS_R10 230
3004 #define SSB_SPROM_BASE1 0x1000
3005 #define SSB_SPROM_BASE31 0x0800
3006 #define SSB_SPROM_REVISION 0x007E
3007 @@ -228,6 +229,7 @@
3008 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
3009 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
3010 #define SSB_SPROM1_AGAIN_A_SHIFT 8
3011 +#define SSB_SPROM1_CCODE 0x0076
3012
3013 /* SPROM Revision 2 (inherits from rev 1) */
3014 #define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
3015 @@ -267,6 +269,7 @@
3016 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
3017
3018 /* SPROM Revision 4 */
3019 +#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
3020 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
3021 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
3022 #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
3023 @@ -287,11 +290,11 @@
3024 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
3025 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3026 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3027 -#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
3028 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3029 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
3030 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
3031 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
3032 +#define SSB_SPROM4_ANTAVAIL 0x005C /* Antenna available bitfields */
3033 +#define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
3034 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 0
3035 +#define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
3036 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 8
3037 #define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
3038 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
3039 #define SSB_SPROM4_AGAIN0_SHIFT 0
3040 @@ -389,6 +392,11 @@
3041 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
3042 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
3043 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
3044 +#define SSB_SPROM8_LEDDC 0x009A
3045 +#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
3046 +#define SSB_SPROM8_LEDDC_ON_SHIFT 8
3047 +#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
3048 +#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
3049 #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
3050 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
3051 #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
3052 @@ -404,6 +412,13 @@
3053 #define SSB_SPROM8_AGAIN2_SHIFT 0
3054 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
3055 #define SSB_SPROM8_AGAIN3_SHIFT 8
3056 +#define SSB_SPROM8_TXRXC 0x00A2
3057 +#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
3058 +#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
3059 +#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
3060 +#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
3061 +#define SSB_SPROM8_TXRXC_SWITCH 0xff00
3062 +#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
3063 #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
3064 #define SSB_SPROM8_RSSISMF2G 0x000F
3065 #define SSB_SPROM8_RSSISMC2G 0x00F0
3066 @@ -430,6 +445,7 @@
3067 #define SSB_SPROM8_TRI5GH_SHIFT 8
3068 #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
3069 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
3070 +#define SSB_SPROM8_RXPO2G_SHIFT 0
3071 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
3072 #define SSB_SPROM8_RXPO5G_SHIFT 8
3073 #define SSB_SPROM8_FEM2G 0x00AE
3074 @@ -445,10 +461,71 @@
3075 #define SSB_SROM8_FEM_ANTSWLUT 0xF800
3076 #define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
3077 #define SSB_SPROM8_THERMAL 0x00B2
3078 -#define SSB_SPROM8_MPWR_RAWTS 0x00B4
3079 -#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
3080 -#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
3081 -#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
3082 +#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
3083 +#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
3084 +#define SSB_SPROM8_THERMAL_TRESH 0xff00
3085 +#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
3086 +/* Temp sense related entries */
3087 +#define SSB_SPROM8_RAWTS 0x00B4
3088 +#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
3089 +#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
3090 +#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
3091 +#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
3092 +#define SSB_SPROM8_OPT_CORRX 0x00B6
3093 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
3094 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
3095 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
3096 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
3097 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
3098 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
3099 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
3100 +#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
3101 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
3102 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
3103 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
3104 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
3105 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
3106 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
3107 +#define SSB_SPROM8_TEMPDELTA 0x00BC
3108 +#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
3109 +#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
3110 +#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
3111 +#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
3112 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
3113 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
3114 +
3115 +/* There are 4 blocks with power info sharing the same layout */
3116 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
3117 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
3118 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
3119 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
3120 +
3121 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
3122 +#define SSB_SPROM8_2G_MAXP 0x00FF
3123 +#define SSB_SPROM8_2G_ITSSI 0xFF00
3124 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
3125 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
3126 +#define SSB_SROM8_2G_PA_1 0x04
3127 +#define SSB_SROM8_2G_PA_2 0x06
3128 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
3129 +#define SSB_SPROM8_5G_MAXP 0x00FF
3130 +#define SSB_SPROM8_5G_ITSSI 0xFF00
3131 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
3132 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
3133 +#define SSB_SPROM8_5GH_MAXP 0x00FF
3134 +#define SSB_SPROM8_5GL_MAXP 0xFF00
3135 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
3136 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
3137 +#define SSB_SROM8_5G_PA_1 0x0E
3138 +#define SSB_SROM8_5G_PA_2 0x10
3139 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
3140 +#define SSB_SROM8_5GL_PA_1 0x14
3141 +#define SSB_SROM8_5GL_PA_2 0x16
3142 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
3143 +#define SSB_SROM8_5GH_PA_1 0x1A
3144 +#define SSB_SROM8_5GH_PA_2 0x1C
3145 +
3146 +/* TODO: Make it deprecated */
3147 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
3148 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
3149 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
3150 @@ -473,12 +550,23 @@
3151 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
3152 #define SSB_SPROM8_PA1HIB1 0x00DA
3153 #define SSB_SPROM8_PA1HIB2 0x00DC
3154 +
3155 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
3156 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
3157 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
3158 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
3159 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
3160
3161 +#define SSB_SPROM8_2G_MCSPO 0x0152
3162 +#define SSB_SPROM8_5G_MCSPO 0x0162
3163 +#define SSB_SPROM8_5GL_MCSPO 0x0172
3164 +#define SSB_SPROM8_5GH_MCSPO 0x0182
3165 +
3166 +#define SSB_SPROM8_CDDPO 0x0192
3167 +#define SSB_SPROM8_STBCPO 0x0194
3168 +#define SSB_SPROM8_BW40PO 0x0196
3169 +#define SSB_SPROM8_BWDUPPO 0x0198
3170 +
3171 /* Values for boardflags_lo read from SPROM */
3172 #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
3173 #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
3174 --- /dev/null
3175 +++ b/include/linux/bcm47xx_wdt.h
3176 @@ -0,0 +1,19 @@
3177 +#ifndef LINUX_BCM47XX_WDT_H_
3178 +#define LINUX_BCM47XX_WDT_H_
3179 +
3180 +#include <linux/types.h>
3181 +
3182 +
3183 +struct bcm47xx_wdt {
3184 + u32 (*timer_set)(struct bcm47xx_wdt *, u32);
3185 + u32 (*timer_set_ms)(struct bcm47xx_wdt *, u32);
3186 + u32 max_timer_ms;
3187 +
3188 + void *driver_data;
3189 +};
3190 +
3191 +static inline void *bcm47xx_wdt_get_drvdata(struct bcm47xx_wdt *wdt)
3192 +{
3193 + return wdt->driver_data;
3194 +}
3195 +#endif /* LINUX_BCM47XX_WDT_H_ */
3196 --- a/drivers/net/wireless/b43/phy_n.c
3197 +++ b/drivers/net/wireless/b43/phy_n.c
3198 @@ -4259,7 +4259,8 @@ static void b43_nphy_pmu_spur_avoid(stru
3199 #endif
3200 #ifdef CONFIG_B43_SSB
3201 case B43_BUS_SSB:
3202 - /* FIXME */
3203 + ssb_pmu_spuravoid_pllupdate(&dev->dev->sdev->bus->chipco,
3204 + avoid);
3205 break;
3206 #endif
3207 }
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