target/linux/ifxmips/files-2.6.33/arch/mips/ifxmips/common/setup.c

   1 #include <linux/init.h>
   2 #include <linux/cpu.h>
   3
   4 #include <asm/time.h>
   5 #include <asm/traps.h>
   6 #include <asm/irq.h>
   7 #include <asm/bootinfo.h>
   8
   9 #include <ifxmips.h>
  10 #include <ifxmips_irq.h>
  11 #include <ifxmips_pmu.h>
  12 #include <ifxmips_cgu.h>
  13 #include <ifxmips_prom.h>
  14
  15 #include <machine.h>
  16
  17 DEFINE_SPINLOCK(ebu_lock);
  18 EXPORT_SYMBOL_GPL(ebu_lock);
  19
  20 static unsigned int r4k_offset;
  21 static unsigned int r4k_cur;
  22
  23 static unsigned int ifxmips_ram_clocks[] = {CLOCK_167M, CLOCK_133M, CLOCK_111M, CLOCK_83M };
  24 #define DDR_HZ ifxmips_ram_clocks[ifxmips_r32(IFXMIPS_CGU_SYS) & 0x3]
  25
  26 extern void __init ifxmips_soc_setup(void);
  27
  28 static inline u32
  29 ifxmips_get_counter_resolution(void)
  30 {
  31         u32 res;
  32         __asm__ __volatile__(
  33                 ".set   push\n"
  34                 ".set   mips32r2\n"
  35                 ".set   noreorder\n"
  36                 "rdhwr  %0, $3\n"
  37                 "ehb\n"
  38                 ".set pop\n"
  39                 : "=&r" (res)
  40                 : /* no input */
  41                 : "memory");
  42         instruction_hazard();
  43         return res;
  44 }
  45
  46 void __init
  47 plat_time_init(void)
  48 {
  49         mips_hpt_frequency = ifxmips_get_cpu_hz() / ifxmips_get_counter_resolution();
  50         r4k_cur = (read_c0_count() + r4k_offset);
  51         write_c0_compare(r4k_cur);
  52
  53         ifxmips_pmu_enable(IFXMIPS_PMU_PWDCR_GPT | IFXMIPS_PMU_PWDCR_FPI);
  54         ifxmips_w32(0x100, IFXMIPS_GPTU_GPT_CLC); /* set clock divider to 1 */
  55 }
  56
  57 void __init
  58 plat_mem_setup(void)
  59 {
  60         u32 status;
  61
  62         /* make sure to have no "reverse endian" for user mode! */
  63         status = read_c0_status();
  64         status &= (~(1<<25));
  65         write_c0_status(status);
  66
  67         /* call the chip specific init code */
  68         ifxmips_soc_setup();
  69 }
  70
  71
  72 unsigned int
  73 ifxmips_get_cpu_hz(void)
  74 {
  75         switch (ifxmips_r32(IFXMIPS_CGU_SYS) & 0xc)
  76         {
  77         case 0:
  78                 return CLOCK_333M;
  79         case 4:
  80                 return DDR_HZ;
  81         case 8:
  82                 return DDR_HZ << 1;
  83         default:
  84                 return DDR_HZ >> 1;
  85         }
  86 }
  87 EXPORT_SYMBOL(ifxmips_get_cpu_hz);
  88
  89 static int __init
  90 ifxmips_machine_setup(void)
  91 {
  92         mips_machine_setup();
  93         return 0;
  94 }
  95
  96 arch_initcall(ifxmips_machine_setup);
  97
  98 static void __init
  99 ifxmips_generic_init(void)
 100 {
 101 }
 102
 103 MIPS_MACHINE(IFXMIPS_MACH_GENERIC, "Generic", "Generic Infineon board",
 104         ifxmips_generic_init);
 105
 106 __setup("board=", mips_machtype_setup);
 107