target/linux/lantiq/files-3.3/arch/mips/include/asm/mach-lantiq/svip/lantiq_soc.h

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
   7  */
   8
   9 #ifndef _LTQ_SVIP_H__
  10 #define _LTQ_SVIP_H__
  11
  12 #ifdef CONFIG_SOC_SVIP
  13
  14 #include <lantiq.h>
  15
  16 /* Chip IDs */
  17 #define SOC_ID_SVIP             0x169
  18
  19 /* SoC Types */
  20 #define SOC_TYPE_SVIP           0x01
  21
  22 /* ASC0/1 - serial port */
  23 #define LTQ_ASC0_BASE_ADDR      0x14100100
  24 #define LTQ_ASC1_BASE_ADDR      0x14100200
  25 #define LTQ_ASC_SIZE            0x100
  26 #define LTQ_EARLY_ASC           KSEG1ADDR(LTQ_ASC0_BASE_ADDR)
  27
  28 #define LTQ_ASC_TIR(x)          (INT_NUM_IM0_IRL0 + (x * 8))
  29 #define LTQ_ASC_RIR(x)          (INT_NUM_IM0_IRL0 + (x * 8) + 2)
  30 #define LTQ_ASC_EIR(x)          (INT_NUM_IM0_IRL0 + (x * 8) + 3)
  31
  32 /* ICU - interrupt control unit */
  33 #define LTQ_ICU_BASE_ADDR       0x14106000
  34 #define LTQ_ICU_BASE_ADDR1      0x14106028
  35 #define LTQ_ICU_BASE_ADDR2      0x1E016000
  36 #define LTQ_ICU_BASE_ADDR3      0x1E016028
  37 #define LTQ_ICU_BASE_ADDR4      0x14106050
  38 #define LTQ_ICU_BASE_ADDR5      0x14106078
  39 #define LTQ_ICU_SIZE            0x100
  40
  41 /* WDT */
  42 #define LTQ_WDT_BASE_ADDR       0x1F8803F0
  43 #define LTQ_WDT_SIZE            0x10
  44
  45 /* Status */
  46 #define LTQ_STATUS_BASE_ADDR    (KSEG1 + 0x1E000500)
  47 #define LTQ_STATUS_CHIPID       ((u32 *)(LTQ_STATUS_BASE_ADDR + 0x000C))
  48
  49 #define LTQ_EIU_BASE_ADDR       0
  50
  51 #define ltq_ebu_w32(x, y)       ltq_w32((x), ltq_ebu_membase + (y))
  52 #define ltq_ebu_r32(x)          ltq_r32(ltq_ebu_membase + (x))
  53
  54 extern __iomem void *ltq_ebu_membase;
  55
  56 extern void ltq_gpio_configure(int port, int pin, bool dirin, bool puen,
  57                                bool altsel0, bool altsel1);
  58 extern int ltq_port_get_dir(unsigned int port, unsigned int pin);
  59 extern int ltq_port_get_puden(unsigned int port, unsigned int pin);
  60 extern int ltq_port_get_altsel0(unsigned int port, unsigned int pin);
  61 extern int ltq_port_get_altsel1(unsigned int port, unsigned int pin);
  62
  63 #define ltq_is_ar9()    0
  64 #define ltq_is_vr9()    0
  65 #define ltq_is_falcon() 0
  66
  67 #define BS_FLASH                0
  68 #define LTQ_RST_CAUSE_WDTRST    0x2
  69
  70 #endif /* CONFIG_SOC_SVIP */
  71 #endif /* _LTQ_SVIP_H__ */