target/linux/lantiq/files-3.3/arch/mips/lantiq/svip/clk-svip.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License as published by
   4  * the Free Software Foundation; either version 2 of the License, or
   5  * (at your option) any later version.
   6  *
   7  * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
   8  */
   9
  10 #include <linux/io.h>
  11 #include <linux/module.h>
  12 #include <linux/init.h>
  13 #include <linux/time.h>
  14
  15 #include <asm/irq.h>
  16 #include <asm/div64.h>
  17
  18 #include <lantiq_soc.h>
  19 #include <base_reg.h>
  20 #include <sys0_reg.h>
  21 #include <sys1_reg.h>
  22 #include <status_reg.h>
  23
  24 static struct svip_reg_status *const status =
  25 (struct svip_reg_status *)LTQ_STATUS_BASE;
  26 static struct svip_reg_sys0 *const sys0 = (struct svip_reg_sys0 *)LTQ_SYS0_BASE;
  27 static struct svip_reg_sys1 *const sys1 = (struct svip_reg_sys1 *)LTQ_SYS1_BASE;
  28
  29 unsigned int ltq_svip_io_region_clock(void)
  30 {
  31         return 200000000; /* 200 MHz */
  32 }
  33 EXPORT_SYMBOL(ltq_svip_io_region_clock);
  34
  35 unsigned int ltq_svip_cpu_hz(void)
  36 {
  37         /* Magic BootROM speed location... */
  38         if ((*(u32 *)0x9fc07ff0) == 1)
  39                 return *(u32 *)0x9fc07ff4;
  40
  41         if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) {
  42                 /* xT16 */
  43                 return 393216000;
  44         } else {
  45                 switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) {
  46                 case 3:
  47                         return 475000000;
  48                 case 2:
  49                         return 450000000;
  50                 case 1:
  51                         return 425000000;
  52                 default:
  53                         return 400000000;
  54                 }
  55         }
  56 }
  57 EXPORT_SYMBOL(ltq_svip_cpu_hz);
  58
  59 unsigned int ltq_svip_fpi_hz(void)
  60 {
  61         u32 fbs0_div[2] = {4, 8};
  62         u32 div;
  63
  64         div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr));
  65         return ltq_svip_cpu_hz()/fbs0_div[div];
  66 }
  67 EXPORT_SYMBOL(ltq_svip_fpi_hz);
  68
  69 unsigned int ltq_get_ppl_hz(void)
  70 {
  71         /* Magic BootROM speed location... */
  72         if ((*(u32 *)0x9fc07ff0) == 1)
  73                 return *(u32 *)0x9fc07ff4;
  74
  75         if (STATUS_CONFIG_CLK_MODE_GET(status_r32(config)) == 1) {
  76                 /* xT16 */
  77                 return 393216000;
  78         } else {
  79                 switch (SYS0_PLL1CR_PLLDIV_GET(sys0_r32(pll1cr))) {
  80                 case 3:
  81                         return 475000000;
  82                 case 2:
  83                         return 450000000;
  84                 case 1:
  85                         return 425000000;
  86                 default:
  87                         return 400000000;
  88                 }
  89         }
  90 }
  91
  92 unsigned int ltq_get_fbs0_hz(void)
  93 {
  94         u32 fbs0_div[2] = {4, 8};
  95         u32 div;
  96
  97         div = SYS1_FPICR_FPIDIV_GET(sys1_r32(fpicr));
  98         return ltq_get_ppl_hz()/fbs0_div[div];
  99 }
 100 EXPORT_SYMBOL(ltq_get_fbs0_hz);