2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
9 #include <linux/mtd/physmap.h>
10 #include <linux/mtd/nand.h>
11 #include <linux/platform_device.h>
14 #include <lantiq_soc.h>
15 #include <lantiq_irq.h>
16 #include <lantiq_platform.h>
21 #define LTQ_EBU_NAND_WAIT 0xB4
22 #define LTQ_EBU_NAND_ECC0 0xB8
23 #define LTQ_EBU_NAND_ECC_AC 0xBC
24 #define LTQ_EBU_NAND_CON 0xB0
25 #define LTQ_EBU_ADDSEL1 0x24
27 /* gpio definitions */
31 #define PIN_RDY 48 /* NFLASH_READY */
32 #define PIN_RD 49 /* NFLASH_READ_N */
34 #define NAND_CMD_ALE (1 << 2)
35 #define NAND_CMD_CLE (1 << 3)
36 #define NAND_CMD_CS (1 << 4)
37 #define NAND_WRITE_CMD_RESET 0xff
38 #define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
39 #define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
40 #define NAND_WRITE_DATA (NAND_CMD_CS)
41 #define NAND_READ_DATA (NAND_CMD_CS)
42 #define NAND_WAIT_WR_C (1 << 3)
43 #define NAND_WAIT_RD (0x1)
45 #define ADDSEL1_MASK(x) (x << 4)
46 #define ADDSEL1_REGEN 1
47 #define BUSCON1_SETUP (1 << 22)
48 #define BUSCON1_BCGEN_RES (0x3 << 12)
49 #define BUSCON1_WAITWRC2 (2 << 8)
50 #define BUSCON1_WAITRDC2 (2 << 6)
51 #define BUSCON1_HOLDC1 (1 << 4)
52 #define BUSCON1_RECOVC1 (1 << 2)
53 #define BUSCON1_CMULT4 1
54 #define NAND_CON_NANDM 1
55 #define NAND_CON_CSMUX (1 << 1)
56 #define NAND_CON_CS_P (1 << 4)
57 #define NAND_CON_SE_P (1 << 5)
58 #define NAND_CON_WP_P (1 << 6)
59 #define NAND_CON_PRE_P (1 << 7)
60 #define NAND_CON_IN_CS0 0
61 #define NAND_CON_OUT_CS0 0
62 #define NAND_CON_IN_CS1 (1 << 8)
63 #define NAND_CON_OUT_CS1 (1 << 10)
64 #define NAND_CON_CE (1 << 20)
66 #define NAND_BASE_ADDRESS (KSEG1 | 0x14000000)
68 static const char *part_probes
[] = { "cmdlinepart", NULL
};
70 static void xway_select_chip(struct mtd_info
*mtd
, int chip
)
74 ltq_ebu_w32_mask(NAND_CON_CE
, 0, LTQ_EBU_NAND_CON
);
75 ltq_ebu_w32_mask(NAND_CON_NANDM
, 0, LTQ_EBU_NAND_CON
);
78 ltq_ebu_w32_mask(0, NAND_CON_NANDM
, LTQ_EBU_NAND_CON
);
79 ltq_ebu_w32_mask(0, NAND_CON_CE
, LTQ_EBU_NAND_CON
);
80 /* reset the nand chip */
81 while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT
) & NAND_WAIT_WR_C
) == 0)
83 ltq_w32(NAND_WRITE_CMD_RESET
,
84 ((u32
*) (NAND_BASE_ADDRESS
| NAND_WRITE_CMD
)));
91 static void xway_cmd_ctrl(struct mtd_info
*mtd
, int data
, unsigned int ctrl
)
93 struct nand_chip
*this = mtd
->priv
;
95 if (ctrl
& NAND_CTRL_CHANGE
) {
97 this->IO_ADDR_W
= (void __iomem
*)
98 (NAND_BASE_ADDRESS
| NAND_WRITE_CMD
);
99 else if (ctrl
& NAND_ALE
)
100 this->IO_ADDR_W
= (void __iomem
*)
101 (NAND_BASE_ADDRESS
| NAND_WRITE_ADDR
);
104 if (data
!= NAND_CMD_NONE
) {
105 *(volatile u8
*) ((u32
) this->IO_ADDR_W
) = data
;
106 while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT
) & NAND_WAIT_WR_C
) == 0)
111 static int xway_dev_ready(struct mtd_info
*mtd
)
113 return ltq_ebu_r32(LTQ_EBU_NAND_WAIT
) & NAND_WAIT_RD
;
116 void nand_write(unsigned int addr
, unsigned int val
)
118 ltq_w32(val
, ((u32
*) (NAND_BASE_ADDRESS
| addr
)));
119 while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT
) & NAND_WAIT_WR_C
) == 0)
123 unsigned char xway_read_byte(struct mtd_info
*mtd
)
125 return ltq_r8((void __iomem
*)(NAND_BASE_ADDRESS
| (NAND_READ_DATA
)));
128 static void xway_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
132 for (i
= 0; i
< len
; i
++)
134 unsigned char res8
= ltq_r8((void __iomem
*)(NAND_BASE_ADDRESS
| (NAND_READ_DATA
)));
139 static void xway_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
143 for (i
= 0; i
< len
; i
++)
145 ltq_w8(buf
[i
], ((u32
*)(NAND_BASE_ADDRESS
| (NAND_WRITE_DATA
))));
146 while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT
) & NAND_WAIT_WR_C
) == 0);
150 int xway_probe(struct platform_device
*pdev
)
152 /* might need this later ?
153 ltq_gpio_request(PIN_CS1, 2, 1, "NAND_CS1");
155 ltq_gpio_request(&pdev
->dev
, PIN_CLE
, 2, 1, "NAND_CLE");
156 ltq_gpio_request(&pdev
->dev
, PIN_ALE
, 2, 1, "NAND_ALE");
157 if (ltq_is_ar9() || ltq_is_vr9()) {
158 ltq_gpio_request(&pdev
->dev
, PIN_RDY
, 2, 0, "NAND_BSY");
159 ltq_gpio_request(&pdev
->dev
, PIN_RD
, 2, 1, "NAND_RD");
162 ltq_ebu_w32((NAND_BASE_ADDRESS
& 0x1fffff00)
163 | ADDSEL1_MASK(3) | ADDSEL1_REGEN
, LTQ_EBU_ADDSEL1
);
165 ltq_ebu_w32(BUSCON1_SETUP
| BUSCON1_BCGEN_RES
| BUSCON1_WAITWRC2
166 | BUSCON1_WAITRDC2
| BUSCON1_HOLDC1
| BUSCON1_RECOVC1
167 | BUSCON1_CMULT4
, LTQ_EBU_BUSCON1
);
169 ltq_ebu_w32(NAND_CON_NANDM
| NAND_CON_CSMUX
| NAND_CON_CS_P
170 | NAND_CON_SE_P
| NAND_CON_WP_P
| NAND_CON_PRE_P
171 | NAND_CON_IN_CS0
| NAND_CON_OUT_CS0
, LTQ_EBU_NAND_CON
);
173 ltq_w32(NAND_WRITE_CMD_RESET
,
174 ((u32
*) (NAND_BASE_ADDRESS
| NAND_WRITE_CMD
)));
175 while ((ltq_ebu_r32(LTQ_EBU_NAND_WAIT
) & NAND_WAIT_WR_C
) == 0)
181 static struct platform_nand_data falcon_flash_nand_data
= {
185 .part_probe_types
= part_probes
,
189 .cmd_ctrl
= xway_cmd_ctrl
,
190 .dev_ready
= xway_dev_ready
,
191 .select_chip
= xway_select_chip
,
192 .read_byte
= xway_read_byte
,
193 .read_buf
= xway_read_buf
,
194 .write_buf
= xway_write_buf
,
198 static struct resource ltq_nand_res
=
199 MEM_RES("nand", 0x14000000, 0x7ffffff);
201 static struct platform_device ltq_flash_nand
= {
205 .resource
= <q_nand_res
,
207 .platform_data
= &falcon_flash_nand_data
,
211 void __init
xway_register_nand(struct mtd_partition
*parts
, int count
)
213 falcon_flash_nand_data
.chip
.partitions
= parts
;
214 falcon_flash_nand_data
.chip
.nr_partitions
= count
;
215 platform_device_register(<q_flash_nand
);