2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
6 * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
9 #include <linux/module.h>
10 #include <linux/device.h>
11 #include <linux/platform_device.h>
12 #include <linux/spi/spi.h>
13 #include <linux/delay.h>
14 #include <linux/workqueue.h>
16 #include <lantiq_soc.h>
18 #define DRV_NAME "falcon_spi"
20 #define FALCON_SPI_XFER_BEGIN (1 << 0)
21 #define FALCON_SPI_XFER_END (1 << 1)
23 /* Bus Read Configuration Register0 */
24 #define LTQ_BUSRCON0 0x00000010
25 /* Bus Write Configuration Register0 */
26 #define LTQ_BUSWCON0 0x00000018
27 /* Serial Flash Configuration Register */
28 #define LTQ_SFCON 0x00000080
29 /* Serial Flash Time Register */
30 #define LTQ_SFTIME 0x00000084
31 /* Serial Flash Status Register */
32 #define LTQ_SFSTAT 0x00000088
33 /* Serial Flash Command Register */
34 #define LTQ_SFCMD 0x0000008C
35 /* Serial Flash Address Register */
36 #define LTQ_SFADDR 0x00000090
37 /* Serial Flash Data Register */
38 #define LTQ_SFDATA 0x00000094
39 /* Serial Flash I/O Control Register */
40 #define LTQ_SFIO 0x00000098
41 /* EBU Clock Control Register */
42 #define LTQ_EBUCC 0x000000C4
44 /* Dummy Phase Length */
45 #define SFCMD_DUMLEN_OFFSET 16
46 #define SFCMD_DUMLEN_MASK 0x000F0000
48 #define SFCMD_CS_OFFSET 24
49 #define SFCMD_CS_MASK 0x07000000
51 #define SFCMD_ALEN_OFFSET 20
52 #define SFCMD_ALEN_MASK 0x00700000
53 /* SCK Rise-edge Position */
54 #define SFTIME_SCKR_POS_OFFSET 8
55 #define SFTIME_SCKR_POS_MASK 0x00000F00
57 #define SFTIME_SCK_PER_OFFSET 0
58 #define SFTIME_SCK_PER_MASK 0x0000000F
59 /* SCK Fall-edge Position */
60 #define SFTIME_SCKF_POS_OFFSET 12
61 #define SFTIME_SCKF_POS_MASK 0x0000F000
63 #define SFCON_DEV_SIZE_A23_0 0x03000000
64 #define SFCON_DEV_SIZE_MASK 0x0F000000
65 /* Read Data Position */
66 #define SFTIME_RD_POS_MASK 0x000F0000
68 #define SFIO_UNUSED_WD_MASK 0x0000000F
69 /* Command Opcode mask */
70 #define SFCMD_OPC_MASK 0x000000FF
71 /* dlen bytes of data to write */
72 #define SFCMD_DIR_WRITE 0x00000100
73 /* Data Length offset */
74 #define SFCMD_DLEN_OFFSET 9
76 #define SFSTAT_CMD_ERR 0x20000000
77 /* Access Command Pending */
78 #define SFSTAT_CMD_PEND 0x00400000
79 /* Frequency set to 100MHz. */
80 #define EBUCC_EBUDIV_SELF100 0x00000001
82 #define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
83 /* 8-bit multiplexed */
84 #define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
86 #define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
87 /* Chip Select after opcode */
88 #define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
91 u32 sfcmd
; /* for caching of opcode, direction, ... */
92 struct spi_master
*master
;
96 falcon_spi_xfer(struct spi_device
*spi
,
97 struct spi_transfer
*t
,
100 struct device
*dev
= &spi
->dev
;
101 struct falcon_spi
*priv
= spi_master_get_devdata(spi
->master
);
102 const u8
*txp
= t
->tx_buf
;
104 unsigned int bytelen
= ((8 * t
->len
+ 7) / 8);
105 unsigned int len
, alen
, dumlen
;
109 state_command_prepare
,
114 } state
= state_init
;
118 case state_init
: /* detect phase of upper layer sequence */
120 /* initial write ? */
121 if (flags
& FALCON_SPI_XFER_BEGIN
) {
124 "BEGIN without tx data!\n");
128 * Prepare the parts of the sfcmd register,
130 * change during a sequence!
131 * Only exception are the length fields,
132 * especially alen and dumlen.
135 priv
->sfcmd
= ((spi
->chip_select
138 priv
->sfcmd
|= SFCMD_KEEP_CS_KEEP_SELECTED
;
145 * maybe address and/or dummy
147 state
= state_command_prepare
;
150 dev_dbg(dev
, "write cmd %02X\n",
151 priv
->sfcmd
& SFCMD_OPC_MASK
);
154 /* continued write ? */
155 if (txp
&& bytelen
) {
160 if (rxp
&& bytelen
) {
164 /* end of sequence? */
165 if (flags
& FALCON_SPI_XFER_END
)
166 state
= state_disable_cs
;
171 /* collect tx data for address and dummy phase */
172 case state_command_prepare
:
174 /* txp is valid, already checked */
178 while (bytelen
> 0) {
180 val
= (val
<<8)|(*txp
++);
182 } else if ((dumlen
< 15) && (*txp
== 0)) {
184 * assume dummy bytes are set to 0
193 priv
->sfcmd
&= ~(SFCMD_ALEN_MASK
| SFCMD_DUMLEN_MASK
);
194 priv
->sfcmd
|= (alen
<< SFCMD_ALEN_OFFSET
) |
195 (dumlen
<< SFCMD_DUMLEN_OFFSET
);
197 ltq_ebu_w32(val
, LTQ_SFADDR
);
199 dev_dbg(dev
, "write cmd %02X, alen=%d "
200 "(addr=%06X) dumlen=%d\n",
201 priv
->sfcmd
& SFCMD_OPC_MASK
,
205 /* continue with write */
207 } else if (flags
& FALCON_SPI_XFER_END
) {
208 /* end of sequence? */
209 state
= state_disable_cs
;
212 * go to end and expect another
213 * call (read or write)
221 /* txp still valid */
222 priv
->sfcmd
|= SFCMD_DIR_WRITE
;
227 val
|= (*txp
++) << (8 * len
++);
228 if ((flags
& FALCON_SPI_XFER_END
)
231 ~SFCMD_KEEP_CS_KEEP_SELECTED
;
233 if ((len
== 4) || (bytelen
== 0)) {
234 ltq_ebu_w32(val
, LTQ_SFDATA
);
235 ltq_ebu_w32(priv
->sfcmd
236 | (len
<<SFCMD_DLEN_OFFSET
),
240 priv
->sfcmd
&= ~(SFCMD_ALEN_MASK
241 | SFCMD_DUMLEN_MASK
);
250 priv
->sfcmd
&= ~SFCMD_DIR_WRITE
;
252 if ((flags
& FALCON_SPI_XFER_END
)
255 ~SFCMD_KEEP_CS_KEEP_SELECTED
;
257 len
= (bytelen
> 4) ? 4 : bytelen
;
259 ltq_ebu_w32(priv
->sfcmd
260 |(len
<<SFCMD_DLEN_OFFSET
), LTQ_SFCMD
);
261 priv
->sfcmd
&= ~(SFCMD_ALEN_MASK
262 | SFCMD_DUMLEN_MASK
);
264 val
= ltq_ebu_r32(LTQ_SFSTAT
);
265 if (val
& SFSTAT_CMD_ERR
) {
266 /* reset error status */
267 dev_err(dev
, "SFSTAT: CMD_ERR "
269 ltq_ebu_w32(SFSTAT_CMD_ERR
,
273 } while (val
& SFSTAT_CMD_PEND
);
274 val
= ltq_ebu_r32(LTQ_SFDATA
);
285 case state_disable_cs
:
287 priv
->sfcmd
&= ~SFCMD_KEEP_CS_KEEP_SELECTED
;
288 ltq_ebu_w32(priv
->sfcmd
| (0 << SFCMD_DLEN_OFFSET
),
290 val
= ltq_ebu_r32(LTQ_SFSTAT
);
291 if (val
& SFSTAT_CMD_ERR
) {
292 /* reset error status */
293 dev_err(dev
, "SFSTAT: CMD_ERR (%x)\n", val
);
294 ltq_ebu_w32(SFSTAT_CMD_ERR
, LTQ_SFSTAT
);
303 } while (state
!= state_end
);
309 falcon_spi_setup(struct spi_device
*spi
)
311 struct device
*dev
= &spi
->dev
;
312 const u32 ebuclk
= 100000000;
316 dev_dbg(dev
, "setup\n");
318 if (spi
->master
->bus_num
> 0 || spi
->chip_select
> 0)
321 spin_lock_irqsave(&ebu_lock
, flags
);
323 if (ebuclk
< spi
->max_speed_hz
) {
324 /* set EBU clock to 100 MHz */
325 ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100
, LTQ_EBUCC
);
328 /* set EBU clock to 50 MHz */
329 ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100
, 0, LTQ_EBUCC
);
331 /* search for suitable divider */
332 for (i
= 1; i
< 7; i
++) {
333 if (ebuclk
/ i
<= spi
->max_speed_hz
)
338 /* setup period of serial clock */
339 ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
340 | SFTIME_SCKR_POS_MASK
341 | SFTIME_SCK_PER_MASK
,
342 (i
<< SFTIME_SCKR_POS_OFFSET
)
343 | (i
<< (SFTIME_SCK_PER_OFFSET
+ 1)),
347 * set some bits of unused_wd, to not trigger HOLD/WP
348 * signals on non QUAD flashes
350 ltq_ebu_w32((SFIO_UNUSED_WD_MASK
& (0x8 | 0x4)), LTQ_SFIO
);
352 ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH
| BUSRCON0_PORTW_8_BIT_MUX
,
354 ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH
, LTQ_BUSWCON0
);
355 /* set address wrap around to maximum for 24-bit addresses */
356 ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK
, SFCON_DEV_SIZE_A23_0
, LTQ_SFCON
);
358 spin_unlock_irqrestore(&ebu_lock
, flags
);
364 falcon_spi_transfer(struct spi_device
*spi
, struct spi_message
*m
)
366 struct falcon_spi
*priv
= spi_master_get_devdata(spi
->master
);
367 struct spi_transfer
*t
;
368 unsigned long spi_flags
;
373 m
->actual_length
= 0;
375 spi_flags
= FALCON_SPI_XFER_BEGIN
;
376 list_for_each_entry(t
, &m
->transfers
, transfer_list
) {
377 if (list_is_last(&t
->transfer_list
, &m
->transfers
))
378 spi_flags
|= FALCON_SPI_XFER_END
;
380 spin_lock_irqsave(&ebu_lock
, flags
);
381 ret
= falcon_spi_xfer(spi
, t
, spi_flags
);
382 spin_unlock_irqrestore(&ebu_lock
, flags
);
387 m
->actual_length
+= t
->len
;
389 if (t
->delay_usecs
|| t
->cs_change
)
396 m
->complete(m
->context
);
402 falcon_spi_cleanup(struct spi_device
*spi
)
404 struct device
*dev
= &spi
->dev
;
406 dev_dbg(dev
, "cleanup\n");
410 falcon_spi_probe(struct platform_device
*pdev
)
412 struct device
*dev
= &pdev
->dev
;
413 struct falcon_spi
*priv
;
414 struct spi_master
*master
;
417 dev_dbg(dev
, "probing\n");
419 master
= spi_alloc_master(&pdev
->dev
, sizeof(*priv
));
421 dev_err(dev
, "no memory for spi_master\n");
425 priv
= spi_master_get_devdata(master
);
426 priv
->master
= master
;
428 master
->mode_bits
= SPI_MODE_3
;
429 master
->num_chipselect
= 1;
432 master
->setup
= falcon_spi_setup
;
433 master
->transfer
= falcon_spi_transfer
;
434 master
->cleanup
= falcon_spi_cleanup
;
436 platform_set_drvdata(pdev
, priv
);
438 ret
= spi_register_master(master
);
440 spi_master_put(master
);
446 falcon_spi_remove(struct platform_device
*pdev
)
448 struct device
*dev
= &pdev
->dev
;
449 struct falcon_spi
*priv
= platform_get_drvdata(pdev
);
451 dev_dbg(dev
, "removed\n");
453 spi_unregister_master(priv
->master
);
458 static struct platform_driver falcon_spi_driver
= {
459 .probe
= falcon_spi_probe
,
460 .remove
= __devexit_p(falcon_spi_remove
),
468 falcon_spi_init(void)
470 return platform_driver_register(&falcon_spi_driver
);
474 falcon_spi_exit(void)
476 platform_driver_unregister(&falcon_spi_driver
);
479 module_init(falcon_spi_init
);
480 module_exit(falcon_spi_exit
);
482 MODULE_LICENSE("GPL");
483 MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver");