1 From c2c9c788b91218bccbb9ac31539ffa577fe502bf Mon Sep 17 00:00:00 2001
2 From: John Crispin <blogic@openwrt.org>
3 Date: Thu, 16 Aug 2012 08:09:20 +0000
4 Subject: [PATCH 3/9] MIPS: lantiq: timer irq can be different to 7
6 The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
7 code to be able to handle this.
9 Signed-off-by: John Crispin <blogic@openwrt.org>
10 Patchwork: http://patchwork.linux-mips.org/patch/4229/
12 arch/mips/lantiq/irq.c | 19 ++++++++++++++++---
13 1 file changed, 16 insertions(+), 3 deletions(-)
15 diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
16 index a2699a70..0cec43d 100644
17 --- a/arch/mips/lantiq/irq.c
18 +++ b/arch/mips/lantiq/irq.c
19 @@ -84,6 +84,7 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = {
20 static int exin_avail;
21 static void __iomem *ltq_icu_membase[MAX_IM];
22 static void __iomem *ltq_eiu_membase;
23 +static struct irq_domain *ltq_domain;
25 void ltq_disable_irq(struct irq_data *d)
27 @@ -219,10 +220,14 @@ DEFINE_HWx_IRQDISPATCH(2)
28 DEFINE_HWx_IRQDISPATCH(3)
29 DEFINE_HWx_IRQDISPATCH(4)
31 +#if MIPS_CPU_TIMER_IRQ == 7
32 static void ltq_hw5_irqdispatch(void)
34 do_IRQ(MIPS_CPU_TIMER_IRQ);
37 +DEFINE_HWx_IRQDISPATCH(5)
40 #ifdef CONFIG_MIPS_MT_SMP
41 void __init arch_init_ipiirq(int irq, struct irqaction *action)
42 @@ -270,7 +275,7 @@ asmlinkage void plat_irq_dispatch(void)
43 unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
46 - if (pending & CAUSEF_IP7) {
47 + if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
48 do_IRQ(MIPS_CPU_TIMER_IRQ);
51 @@ -376,7 +381,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
52 set_vi_handler(7, ltq_hw5_irqdispatch);
55 - irq_domain_add_linear(node,
56 + ltq_domain = irq_domain_add_linear(node,
57 (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
60 @@ -401,12 +406,20 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
62 /* tell oprofile which irq to use */
63 cp0_perfcount_irq = LTQ_PERF_IRQ;
66 + * if the timer irq is not one of the mips irqs we need to
69 + if (MIPS_CPU_TIMER_IRQ != 7)
70 + irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
75 unsigned int __cpuinit get_c0_compare_int(void)
77 - return CP0_LEGACY_COMPARE_IRQ;
78 + return MIPS_CPU_TIMER_IRQ;
81 static struct of_device_id __initdata of_irq_ids[] = {