target/linux/ramips/files/arch/mips/ralink/common/gpio.c

   1 /*
   2  * Ralink SoC specific GPIO support
   3  *
   4  * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/io.h>
  13
  14 #include <asm/mach-ralink/ramips_gpio.h>
  15 #include <ralink_soc.h>
  16
  17 static inline struct ramips_gpio_chip *to_ramips_gpio(struct gpio_chip *chip)
  18 {
  19         struct ramips_gpio_chip *rg;
  20
  21         rg = container_of(chip, struct ramips_gpio_chip, chip);
  22         return rg;
  23 }
  24
  25 static inline void ramips_gpio_wr(struct ramips_gpio_chip *rg, u8 reg, u32 val)
  26 {
  27         __raw_writel(val, rg->regs_base + rg->regs[reg]);
  28 }
  29
  30 static inline u32 ramips_gpio_rr(struct ramips_gpio_chip *rg, u8 reg)
  31 {
  32         return __raw_readl(rg->regs_base + rg->regs[reg]);
  33 }
  34
  35 static int ramips_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
  36 {
  37         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
  38         unsigned long flags;
  39         u32 t;
  40
  41         spin_lock_irqsave(&rg->lock, flags);
  42         t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
  43         t &= ~(1 << offset);
  44         ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
  45         spin_unlock_irqrestore(&rg->lock, flags);
  46
  47         return 0;
  48 }
  49
  50 static int ramips_gpio_direction_output(struct gpio_chip *chip,
  51                                         unsigned offset, int value)
  52 {
  53         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
  54         unsigned long flags;
  55         u32 reg;
  56         u32 t;
  57
  58         reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
  59
  60         spin_lock_irqsave(&rg->lock, flags);
  61         ramips_gpio_wr(rg, reg, 1 << offset);
  62
  63         t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DIR);
  64         t |= 1 << offset;
  65         ramips_gpio_wr(rg, RAMIPS_GPIO_REG_DIR, t);
  66         spin_unlock_irqrestore(&rg->lock, flags);
  67
  68         return 0;
  69 }
  70
  71 static void ramips_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  72 {
  73         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
  74         u32 reg;
  75
  76         reg = (value) ? RAMIPS_GPIO_REG_SET : RAMIPS_GPIO_REG_RESET;
  77         ramips_gpio_wr(rg, reg, 1 << offset);
  78 }
  79
  80 static int ramips_gpio_get(struct gpio_chip *chip, unsigned offset)
  81 {
  82         struct ramips_gpio_chip *rg = to_ramips_gpio(chip);
  83         u32 t;
  84
  85         t = ramips_gpio_rr(rg, RAMIPS_GPIO_REG_DATA);
  86         return !!(t & (1 << offset));
  87 }
  88
  89 static struct ramips_gpio_chip ramips_gpio_chip0 = {
  90         .chip = {
  91                 .label                  = "ramips-gpio0",
  92                 .base                   = 0,
  93                 .ngpio                  = RALINK_SOC_GPIO0_COUNT,
  94         },
  95         .regs = {
  96                 [RAMIPS_GPIO_REG_INT]   = GPIO0_REG_INT,
  97                 [RAMIPS_GPIO_REG_EDGE]  = GPIO0_REG_EDGE,
  98                 [RAMIPS_GPIO_REG_RENA]  = GPIO0_REG_RENA,
  99                 [RAMIPS_GPIO_REG_FENA]  = GPIO0_REG_FENA,
 100                 [RAMIPS_GPIO_REG_DATA]  = GPIO0_REG_DATA,
 101                 [RAMIPS_GPIO_REG_DIR]   = GPIO0_REG_DIR,
 102                 [RAMIPS_GPIO_REG_POL]   = GPIO0_REG_POL,
 103                 [RAMIPS_GPIO_REG_SET]   = GPIO0_REG_SET,
 104                 [RAMIPS_GPIO_REG_RESET] = GPIO0_REG_RESET,
 105                 [RAMIPS_GPIO_REG_TOGGLE] = GPIO0_REG_TOGGLE,
 106         },
 107         .map_base       = RALINK_SOC_GPIO_BASE,
 108         .map_size       = PAGE_SIZE,
 109 };
 110
 111 static struct ramips_gpio_chip ramips_gpio_chip1 = {
 112         .chip = {
 113                 .label                  = "ramips-gpio1",
 114                 .base                   = 32,
 115                 .ngpio                  = RALINK_SOC_GPIO1_COUNT,
 116         },
 117         .regs = {
 118                 [RAMIPS_GPIO_REG_INT]   = GPIO1_REG_INT,
 119                 [RAMIPS_GPIO_REG_EDGE]  = GPIO1_REG_EDGE,
 120                 [RAMIPS_GPIO_REG_RENA]  = GPIO1_REG_RENA,
 121                 [RAMIPS_GPIO_REG_FENA]  = GPIO1_REG_FENA,
 122                 [RAMIPS_GPIO_REG_DATA]  = GPIO1_REG_DATA,
 123                 [RAMIPS_GPIO_REG_DIR]   = GPIO1_REG_DIR,
 124                 [RAMIPS_GPIO_REG_POL]   = GPIO1_REG_POL,
 125                 [RAMIPS_GPIO_REG_SET]   = GPIO1_REG_SET,
 126                 [RAMIPS_GPIO_REG_RESET] = GPIO1_REG_RESET,
 127                 [RAMIPS_GPIO_REG_TOGGLE] = GPIO1_REG_TOGGLE,
 128         },
 129         .map_base       = RALINK_SOC_GPIO_BASE,
 130         .map_size       = PAGE_SIZE,
 131 };
 132
 133 static struct ramips_gpio_chip ramips_gpio_chip2 = {
 134         .chip = {
 135                 .label                  = "ramips-gpio2",
 136                 .base                   = 64,
 137                 .ngpio                  = RALINK_SOC_GPIO2_COUNT,
 138         },
 139         .regs = {
 140                 [RAMIPS_GPIO_REG_INT]   = GPIO2_REG_INT,
 141                 [RAMIPS_GPIO_REG_EDGE]  = GPIO2_REG_EDGE,
 142                 [RAMIPS_GPIO_REG_RENA]  = GPIO2_REG_RENA,
 143                 [RAMIPS_GPIO_REG_FENA]  = GPIO2_REG_FENA,
 144                 [RAMIPS_GPIO_REG_DATA]  = GPIO2_REG_DATA,
 145                 [RAMIPS_GPIO_REG_DIR]   = GPIO2_REG_DIR,
 146                 [RAMIPS_GPIO_REG_POL]   = GPIO2_REG_POL,
 147                 [RAMIPS_GPIO_REG_SET]   = GPIO2_REG_SET,
 148                 [RAMIPS_GPIO_REG_RESET] = GPIO2_REG_RESET,
 149                 [RAMIPS_GPIO_REG_TOGGLE] = GPIO2_REG_TOGGLE,
 150         },
 151         .map_base       = RALINK_SOC_GPIO_BASE,
 152         .map_size       = PAGE_SIZE,
 153 };
 154
 155 static __init void ramips_gpio_chip_add(struct ramips_gpio_chip *rg)
 156 {
 157         spin_lock_init(&rg->lock);
 158
 159         rg->regs_base = ioremap(rg->map_base, rg->map_size);
 160
 161         rg->chip.direction_input = ramips_gpio_direction_input;
 162         rg->chip.direction_output = ramips_gpio_direction_output;
 163         rg->chip.get = ramips_gpio_get;
 164         rg->chip.set = ramips_gpio_set;
 165
 166         /* set polarity to low for all lines */
 167         ramips_gpio_wr(rg, RAMIPS_GPIO_REG_POL, 0);
 168
 169         gpiochip_add(&rg->chip);
 170 }
 171
 172 __init int ramips_gpio_init(void)
 173 {
 174         ramips_gpio_chip_add(&ramips_gpio_chip0);
 175         ramips_gpio_chip_add(&ramips_gpio_chip1);
 176         ramips_gpio_chip_add(&ramips_gpio_chip2);
 177
 178         return 0;
 179 }