target/linux/ramips/patches-3.8/0112-MIPS-add-MT7620-dts-files.patch

   1 From 9c83b58b49f88a48565fad6acea921a0ae222856 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <blogic@openwrt.org>
   3 Date: Thu, 21 Mar 2013 17:50:05 +0100
   4 Subject: [PATCH 112/121] MIPS: add MT7620 dts files
   5
   6 Adds the dtsi file for MT7620 SoC. This is the latest and greatest SoC shipped
   7 by Mediatek.
   8
   9 Signed-off-by: John Crispin <blogic@openwrt.org>
  10 ---
  11  arch/mips/ralink/Kconfig             |    4 +
  12  arch/mips/ralink/dts/Makefile        |    1 +
  13  arch/mips/ralink/dts/mt7620.dtsi     |  138 ++++++++++++++++++++++++++++++++++
  14  arch/mips/ralink/dts/mt7620_eval.dts |   22 ++++++
  15  4 files changed, 165 insertions(+)
  16  create mode 100644 arch/mips/ralink/dts/mt7620.dtsi
  17  create mode 100644 arch/mips/ralink/dts/mt7620_eval.dts
  18
  19 --- a/arch/mips/ralink/Kconfig
  20 +++ b/arch/mips/ralink/Kconfig
  21 @@ -46,6 +46,10 @@ choice
  22                 bool "RT3883 eval kit"
  23                 depends on SOC_RT3883
  24
  25 +       config DTB_MT7620_EVAL
  26 +               bool "MT7620 eval kit"
  27 +               depends on SOC_MT7620
  28 +
  29  endchoice
  30
  31  endif
  32 --- a/arch/mips/ralink/dts/Makefile
  33 +++ b/arch/mips/ralink/dts/Makefile
  34 @@ -1,3 +1,4 @@
  35  obj-$(CONFIG_DTB_RT2880_EVAL) := rt2880_eval.dtb.o
  36  obj-$(CONFIG_DTB_RT305X_EVAL) := rt3052_eval.dtb.o
  37  obj-$(CONFIG_DTB_RT3883_EVAL) := rt3883_eval.dtb.o
  38 +obj-$(CONFIG_DTB_MT7620_EVAL) := mt7620_eval.dtb.o
  39 --- /dev/null
  40 +++ b/arch/mips/ralink/dts/mt7620.dtsi
  41 @@ -0,0 +1,138 @@
  42 +/ {
  43 +       #address-cells = <1>;
  44 +       #size-cells = <1>;
  45 +       compatible = "ralink,mtk7620n-soc", "ralink,mt7620-soc";
  46 +
  47 +       cpus {
  48 +               cpu@0 {
  49 +                       compatible = "mips,mips24KEc";
  50 +               };
  51 +       };
  52 +
  53 +       chosen {
  54 +               bootargs = "console=ttyS0,57600 init=/init";
  55 +       };
  56 +
  57 +       cpuintc: cpuintc@0 {
  58 +               #address-cells = <0>;
  59 +               #interrupt-cells = <1>;
  60 +               interrupt-controller;
  61 +               compatible = "mti,cpu-interrupt-controller";
  62 +       };
  63 +
  64 +       palmbus@10000000 {
  65 +               compatible = "palmbus";
  66 +               reg = <0x10000000 0x200000>;
  67 +                ranges = <0x0 0x10000000 0x1FFFFF>;
  68 +
  69 +               #address-cells = <1>;
  70 +               #size-cells = <1>;
  71 +
  72 +               sysc@0 {
  73 +                       compatible = "ralink,mt7620-sysc", "ralink,mt7620n-sysc";
  74 +                       reg = <0x0 0x100>;
  75 +               };
  76 +
  77 +               timer@100 {
  78 +                       compatible = "ralink,mt7620-timer", "ralink,rt2880-timer";
  79 +                       reg = <0x100 0x20>;
  80 +
  81 +                       interrupt-parent = <&intc>;
  82 +                       interrupts = <1>;
  83 +
  84 +                       status = "disabled";
  85 +               };
  86 +
  87 +               watchdog@120 {
  88 +                       compatible = "ralink,mt7620-wdt", "ralink,rt2880-wdt";
  89 +                       reg = <0x120 0x10>;
  90 +               };
  91 +
  92 +               intc: intc@200 {
  93 +                       compatible = "ralink,mt7620-intc", "ralink,rt2880-intc";
  94 +                       reg = <0x200 0x100>;
  95 +
  96 +                       interrupt-controller;
  97 +                       #interrupt-cells = <1>;
  98 +
  99 +                       interrupt-parent = <&cpuintc>;
 100 +                       interrupts = <2>;
 101 +               };
 102 +
 103 +               memc@300 {
 104 +                       compatible = "ralink,mt7620-memc", "ralink,rt3050-memc";
 105 +                       reg = <0x300 0x100>;
 106 +               };
 107 +
 108 +               gpio0: gpio@600 {
 109 +                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
 110 +                       reg = <0x600 0x34>;
 111 +
 112 +                       gpio-controller;
 113 +                       #gpio-cells = <2>;
 114 +
 115 +                       ralink,num-gpios = <24>;
 116 +                       ralink,register-map = [ 00 04 08 0c
 117 +                                               20 24 28 2c
 118 +                                               30 34 ];
 119 +               };
 120 +
 121 +               gpio1: gpio@638 {
 122 +                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
 123 +                       reg = <0x638 0x24>;
 124 +
 125 +                       gpio-controller;
 126 +                       #gpio-cells = <2>;
 127 +
 128 +                       ralink,num-gpios = <16>;
 129 +                       ralink,register-map = [ 00 04 08 0c
 130 +                                               10 14 18 1c
 131 +                                               20 24 ];
 132 +               };
 133 +
 134 +               gpio2: gpio@660 {
 135 +                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
 136 +                       reg = <0x660 0x24>;
 137 +
 138 +                       gpio-controller;
 139 +                       #gpio-cells = <2>;
 140 +
 141 +                       ralink,num-gpios = <32>;
 142 +                       ralink,register-map = [ 00 04 08 0c
 143 +                                               10 14 18 1c
 144 +                                               20 24 ];
 145 +               };
 146 +
 147 +               gpio3: gpio@688 {
 148 +                       compatible = "ralink,mt7620-gpio", "ralink,rt2880-gpio";
 149 +                       reg = <0x688 0x24>;
 150 +
 151 +                       gpio-controller;
 152 +                       #gpio-cells = <2>;
 153 +
 154 +                       ralink,num-gpios = <1>;
 155 +                       ralink,register-map = [ 00 04 08 0c
 156 +                                               10 14 18 1c
 157 +                                               20 24 ];
 158 +               };
 159 +
 160 +               spi@b00 {
 161 +                       compatible = "ralink,rt3883-spi", "ralink,rt2880-spi";
 162 +                       reg = <0xb00 0x100>;
 163 +                       #address-cells = <1>;
 164 +                       #size-cells = <0>;
 165 +
 166 +                       status = "disabled";
 167 +               };
 168 +
 169 +               uartlite@c00 {
 170 +                       compatible = "ralink,mt7620-uart", "ralink,rt2880-uart", "ns16550a";
 171 +                       reg = <0xc00 0x100>;
 172 +
 173 +                       interrupt-parent = <&intc>;
 174 +                       interrupts = <12>;
 175 +
 176 +                       reg-shift = <2>;
 177 +               };
 178 +       };
 179 +};
 180 --- /dev/null
 181 +++ b/arch/mips/ralink/dts/mt7620_eval.dts
 182 @@ -0,0 +1,22 @@
 183 +/dts-v1/;
 184 +
 185 +/include/ "mt7620.dtsi"
 186 +
 187 +/ {
 188 +       #address-cells = <1>;
 189 +       #size-cells = <1>;
 190 +       compatible = "ralink,mt7620a-eval-board", "ralink,mt7620a-soc";
 191 +       model = "Ralink MT7620 evaluation board";
 192 +
 193 +       memory@0 {
 194 +               reg = <0x0 0x4000000>;
 195 +       };
 196 +
 197 +       palmbus@10000000 {
 198 +               sysc@0 {
 199 +                       ralink,pinmux = "uartlite", "spi";
 200 +                       ralink,uartmux = "gpio";
 201 +                       ralink,wdtmux = <0>;
 202 +               };
 203 +       };
 204 +};