config OCF_CRYPTOSOFT
tristate "cryptosoft (software crypto engine)"
- select CRYPTO_MANAGER
depends on OCF_OCF
help
A software driver for the OCF framework that uses
patch=ocf-linux-base.patch; \
patch24=ocf-linux-24.patch; \
patch26=ocf-linux-26.patch; \
+ patch3=ocf-linux-3.patch; \
( \
find . -name Makefile; \
find . -name Config.in; \
done > $$patch; \
cat $$patchbase/patches/linux-2.4.35-ocf.patch $$patch > $$patch24; \
cat $$patchbase/patches/linux-2.6.38-ocf.patch $$patch > $$patch26; \
+ cat $$patchbase/patches/linux-3.2.1-ocf.patch $$patch > $$patch3; \
+
#
# this target probably does nothing for anyone but me - davidm
+++ /dev/null
-###########################
-README - ocf-linux-20100530
-###########################
-
-This README provides instructions for getting ocf-linux compiled and
-operating in a generic linux environment. Other information on the project
-can be found at the home page:
-
- http://ocf-linux.sourceforge.net/
-
-Embedded systems and applications requiring userspace acceleration will need
-to patch the kernel source to get full OCF support. See "Adding OCF to
-linux source" below. Otherwise the "OCF Quickstart" that follows is the
-easiest way to get started.
-
-If your goal is to accelerate Openswan on Ubuntu or CentOS, you may find
-that the required binaries are already available on openswan.org:
-
- ftp://ftp.openswan.org/ocf/
- ftp://ftp.openswan.org/openswan/binaries/ubuntu/
-
-#####################################################
-OCF Quickstart for Ubuntu/Others (including Openswan)
-#####################################################
-
-This section provides instructions on how to quickly add kernel only support
-for OCF to a GNU/Linux system. It is only suitable for in-kernel use such as
-Openswan MAST/KLIPS.
-
-If the target is an embedded system, or, userspace acceleration of
-applications such as OpenVPN and OpenSSL, the section below titled
-"Adding OCF to linux source" is more appropriate.
-
-Before building kernel only support for OCF ensure that the appropriate
-linux-headers package is installed:
-
- cd ocf
- make ocf_modules
- sudo make ocf_install
- OCF_DIR=`pwd` # remember where OCF sources were built
-
-At this point the ocf, cryptosoft, ocfnull, hifn7751 and ocf-bench modules
-should have been built and installed. The OCF installation can be tested
-with the following commands:
-
- modprobe ocf
- modprobe cryptosoft
- modprobe ocf-bench
- dmesg | tail -5
-
-The final modprobe of ocf-bench will fail, this is intentional as ocf-bench
-is a short lived module that tests in-kernel performance of OCF. If
-everything worked correctly the "dmesg | tail -5" should include a line
-like:
-
- [ 583.128741] OCF: 45133 requests of 1488 bytes in 251 jiffies (535.122 Mbps)
-
-This shows the in-kernel performance of OCF using the cryptosoft driver.
-For addition driver load options, see "How to load the OCF modules" below.
-
-If the intention is to run an OCF accelerated Openswan (KLIPS/MAST) then use
-these steps to compile openswan downloaded from openswan.org (2.6.34 or later).
-
- tar xf openswan-2.6.34.tar.gz
- cd openswan-2.6.34
- make programs
- make KERNELSRC=/lib/modules/`uname -r`/build \
- KBUILD_EXTRA_SYMBOLS=$OCF_DIR/Module.symvers \
- MODULE_DEF_INCLUDE=`pwd`/packaging/ocf/config-all.hmodules \
- MODULE_DEFCONFIG=`pwd`/packaging/ocf/defconfig \
- module
- sudo make KERNELSRC=/lib/modules/`uname -r`/build \
- KBUILD_EXTRA_SYMBOLS=$OCF_DIR/Module.symvers \
- MODULE_DEF_INCLUDE=`pwd`/packaging/ocf/config-all.hmodules \
- MODULE_DEFCONFIG=`pwd`/packaging/ocf/defconfig \
- install minstall
-
-The rest of this document is only required for more complex build
-requirements.
-
-##########################
-Adding OCF to linux source
-##########################
-
-It is recommended that OCF be built as modules as it increases the
-flexibility and ease of debugging the system.
-
-Ensure that the system has /dev/crypto for userspace access to OCF:
-
- mknod /dev/crypto c 10 70
-
-Generate the kernel patches and apply the appropriate one.
-
- cd ocf
- make patch
-
-This will provide three files:
-
- linux-2.4.*-ocf.patch
- linux-2.6.*-ocf.patch
- ocf-linux-base.patch
-
-If either of the first two patches applies to the targets kernel, then one
-of the following as required:
-
- cd linux-2.X.Y; patch -p1 < linux-2.4.*-ocf.patch
- cd linux-2.6.Y; patch -p1 < linux-2.6.*-ocf.patch
-
-Otherwise, locate the appropriate kernel patch in the patches directory and
-apply that as well as the ocf-linux-base.patch using '-p1'.
-
-When using a linux-2.4 system on a non-x86 platform, the following may be
-required to build cryptosoft:
-
- cp linux-2.X.x/include/asm-i386/kmap_types.h linux-2.X.x/include/asm-YYY
-
-When using cryptosoft, for simplicity, enable all the crypto support in the
-kernel except for the test driver. Likewise for the OCF options. Do not
-enable OCF crypto drivers for HW that is not present (for example the ixp4xx
-driver will not compile on non-Xscale systems).
-
-Make sure that cryptodev.h from the ocf directory is installed as
-crypto/cryptodev.h in an include directory that is used for building
-applications for the target platform. For example on a host system that
-might be:
-
- /usr/include/crypto/cryptodev.h
-
-Patch the openssl-0.9.8r code the openssl-0.9.8r.patch from the patches
-directory. There are many older patch versions in the patches directory
-if required.
-
-The openssl patches provide the following functionality:
-
- * enables --with-cryptodev for non BSD systems
- * adds -cpu option to openssl speed for calculating CPU load under linux
- * fixes null pointer in openssl speed multi thread output.
- * fixes test keys to work with linux crypto's more stringent key checking.
- * adds MD5/SHA acceleration (Ronen Shitrit), only enabled with the
- --with-cryptodev-digests option
- * fixes bug in engine code caching.
-
-Build the crypto-tools directory for the target to obtain a userspace
-testing tool call cryptotest.
-
-###########################
-How to load the OCF modules
-###########################
-
-First insert the base modules (cryptodev is optional, it is only used
-for userspace acceleration):
-
- modprobe ocf
- modprobe cryptodev
-
-Load the software OCF driver with:
-
- modprobe cryptosoft
-
-and zero or more of the OCF HW drivers with:
-
- modprobe safe
- modprobe hifn7751
- modprobe ixp4xx
- ...
-
-All the drivers take a debug option to enable verbose debug so that
-OCF operation may be observed via "dmesg" or the console. For debug
-load the modules as:
-
- modprobe ocf crypto_debug=1
- modprobe cryptodev cryptodev_debug=1
- modprobe cryptosoft swcr_debug=1
-
-More than one OCF crypto driver may be loaded but then there is no
-guarantee as to which will be used (other than a preference for HW
-drivers over SW drivers by most applications).
-
-It is also possible to enable debug at run time on linux-2.6 systems
-with the following:
-
- echo 1 > /sys/module/ocf/parameters/crypto_debug
- echo 1 > /sys/module/cryptodev/parameters/cryptodev_debug
- echo 1 > /sys/module/cryptosoft/parameters/swcr_debug
- echo 1 > /sys/module/hifn7751/parameters/hifn_debug
- echo 1 > /sys/module/safe/parameters/safe_debug
- echo 1 > /sys/module/ixp4xx/parameters/ixp_debug
- ...
-
-The ocf-bench driver accepts the following parameters:
-
- request_q_len - Maximum number of outstanding requests to OCF
- request_num - run for at least this many requests
- request_size - size of each request (multiple of 16 bytes recommended)
- request_batch - enable OCF request batching
- request_cbimm - enable OCF immediate callback on completion
-
-For example:
-
- modprobe ocf-bench request_size=1024 request_cbimm=0
-
-#######################
-Testing the OCF support
-#######################
-
-run "cryptotest", it should do a short test for a couple of
-des packets. If it does everything is working.
-
-If this works, then ssh will use the driver when invoked as:
-
- ssh -c 3des username@host
-
-to see for sure that it is operating, enable debug as defined above.
-
-To get a better idea of performance run:
-
- cryptotest 100 4096
-
-There are more options to cryptotest, see the help.
-
-It is also possible to use openssl to test the speed of the crypto
-drivers.
-
- openssl speed -evp des -engine cryptodev -elapsed
- openssl speed -evp des3 -engine cryptodev -elapsed
- openssl speed -evp aes128 -engine cryptodev -elapsed
-
-and multiple threads (10) with:
-
- openssl speed -evp des -engine cryptodev -elapsed -multi 10
- openssl speed -evp des3 -engine cryptodev -elapsed -multi 10
- openssl speed -evp aes128 -engine cryptodev -elapsed -multi 10
-
-for public key testing you can try:
-
- cryptokeytest
- openssl speed -engine cryptodev rsa -elapsed
- openssl speed -engine cryptodev dsa -elapsed
-
-
-#############################
-#
-# David McCullough
-# david_mccullough@mcafee.com
-#
-#############################
i < skb_shinfo(skb)->nr_frags &&
sg_num < SCATTERLIST_MAX; i++) {
if (skip < skb_shinfo(skb)->frags[i].size) {
- //sg[sg_num].page = skb_frag_page(&kb_shinfo(skb)->frags[i]);
+ //sg[sg_num].page = skb_frag_page(&skb_shinfo(skb)->frags[i]);
//sg[sg_num].offset = skb_shinfo(skb)->frags[i].page_offset + skip;
len = skb_shinfo(skb)->frags[i].size - skip;
if (len + sg_len > crd->crd_len)
sg_set_page(&sg[0], virt_to_page(crp->crp_buf + skip), sg_len, offset_in_page(crp->crp_buf + skip));
sg_num = 1;
}
+ if (sg_num > 0)
+ sg_mark_end(&sg[sg_num-1]);
switch (sw->xfm_type) {
EXPORT_SYMBOL(cuio_copydata);
EXPORT_SYMBOL(cuio_getptr);
-
static void
skb_copy_bits_back(struct sk_buff *skb, int offset, caddr_t cp, int len)
{
--- /dev/null
+
+You will need the CRYPTO package installed to build this driver, and
+potentially the ADK.
+
+cavium_crypto sourced from:
+
+ adk/components/source/cavium_ipsec_kame/cavium_ipsec.c
+
+and significantly modified to suit use with OCF. All original
+copyright/ownership headers retained.
+
offset_in_page(crp->crp_buf));
sg_num = 1;
}
-
+ if (sg_num > 0)
+ sg_mark_end(&sg[sg_num-1]);
/*
* setup a new explicit key
sg_len, offset_in_page(crp->crp_buf + skip));
sg_num = 1;
}
+ if (sg_num > 0)
+ sg_mark_end(&req->sg[sg_num-1]);
switch (sw->sw_type & SW_TYPE_ALG_AMASK) {
--- /dev/null
+ ###########################################################################
+ #
+# This file is provided under a dual BSD/GPLv2 license. When using or
+# redistributing this file, you may do so under either license.
+#
+# GPL LICENSE SUMMARY
+#
+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of version 2 of the GNU General Public License as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+# The full GNU General Public License is included in this distribution
+# in the file called LICENSE.GPL.
+#
+# Contact Information:
+# Intel Corporation
+#
+# BSD LICENSE
+#
+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of Intel Corporation nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#
+# version: Security.L.1.0.130
+ #
+ ###########################################################################
+
+
+ICP_LAC_API=$(ICP_ROOT)/Acceleration/include/lac
+ICP_BTR_API=$(ICP_ROOT)/Acceleration/include/btr
+ICP_API_DIR=$(ICP_ROOT)/Acceleration/include
+ICP_OCF_SHIM_DIR?=$(KERNEL_SOURCE_ROOT)/crypto/ocf/
+ifeq ($(wildcard $(ICP_OCF_SHIM_DIR)),)
+ICP_OCF_SHIM_DIR?=$(ROOTDIR)/modules/ocf/
+endif
+
+ICP_OS_LEVEL?=kernel_space
+
+ICP_OS?=linux_2.6
+
+ICP_CORE?=ia
+
--- /dev/null
+###################
+# @par
+# This file is provided under a dual BSD/GPLv2 license. When using or
+# redistributing this file, you may do so under either license.
+#
+# GPL LICENSE SUMMARY
+#
+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of version 2 of the GNU General Public License as
+# published by the Free Software Foundation.
+#
+# This program is distributed in the hope that it will be useful, but
+# WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+# General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+# The full GNU General Public License is included in this distribution
+# in the file called LICENSE.GPL.
+#
+# Contact Information:
+# Intel Corporation
+#
+# BSD LICENSE
+#
+# Copyright(c) 2007,2008 Intel Corporation. All rights reserved.
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# * Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# * Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# * Neither the name of Intel Corporation nor the names of its
+# contributors may be used to endorse or promote products derived
+# from this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#
+# version: Security.L.1.0.130
+###################
+
+#specific include directories in kernel space
+INCLUDES+=#e.g. -I$(OSAL_DIR)/include \
+
+#Extra Flags Specific in kernel space e.g. include path or debug flags etc. e.g to add an include path EXTRA_CFLAGS += -I$(src)/../include
+EXTRA_CFLAGS += $(INCLUDES) -O2 -Wall
+EXTRA_LDFLAGS +=-whole-archive
+
if (pci_enable_device(dev) < 0)
return(-ENODEV);
-#ifdef HAVE_PCI_SET_MWI
if (pci_set_mwi(dev))
return(-ENODEV);
-#endif
if (!dev->irq) {
printk("hifn: found device with no IRQ assigned. check BIOS settings!");
if (pci_enable_device(dev) < 0)
return(-ENODEV);
-#ifdef HAVE_PCI_SET_MWI
if (pci_set_mwi(dev))
return(-ENODEV);
-#endif
if (!dev->irq) {
printk("hifn: found device with no IRQ assigned. check BIOS settings!");
PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
{ PCI_VENDOR_HIFN, PCI_PRODUCT_HIFN_8155,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, },
- { 0 }
};
MODULE_DEVICE_TABLE(pci, hipp_pci_tbl);
#endif /* MV_CESA_VERSION >= 2 */
#define MV_CESA_MAX_PKT_SIZE (64 * 1024)
-#define MV_CESA_MAX_MBUF_FRAGS 20
+#define MV_CESA_MAX_MBUF_FRAGS 20\r
#define MV_CESA_MAX_REQ_FRAGS ( (MV_CESA_MAX_PKT_SIZE / MV_CESA_MAX_BUF_SIZE) + 1)
extern MV_CESA_SRAM_MAP* cesaSramVirtPtr;
extern MV_U32 cesaSramPhysAddr;
-
+\r
static INLINE MV_ULONG mvCesaVirtToPhys(MV_BUF_INFO* pBufInfo, void* pVirt)
{
return (pBufInfo->bufPhysAddr + ((MV_U8*)pVirt - pBufInfo->bufVirtPtr));
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#ifndef __mvCesaRegs_h__
-#define __mvCesaRegs_h__
-
-#include "mvTypes.h"
-
-typedef struct
-{
- /* word 0 */
- MV_U32 config;
- /* word 1 */
- MV_U16 cryptoSrcOffset;
- MV_U16 cryptoDstOffset;
- /* word 2 */
- MV_U16 cryptoDataLen;
- MV_U16 reserved1;
- /* word 3 */
- MV_U16 cryptoKeyOffset;
- MV_U16 reserved2;
- /* word 4 */
- MV_U16 cryptoIvOffset;
- MV_U16 cryptoIvBufOffset;
- /* word 5 */
- MV_U16 macSrcOffset;
- MV_U16 macTotalLen;
- /* word 6 */
- MV_U16 macDigestOffset;
- MV_U16 macDataLen;
- /* word 7 */
- MV_U16 macInnerIvOffset;
- MV_U16 macOuterIvOffset;
-
-} MV_CESA_DESC;
-
-/* operation */
-typedef enum
-{
- MV_CESA_MAC_ONLY = 0,
- MV_CESA_CRYPTO_ONLY = 1,
- MV_CESA_MAC_THEN_CRYPTO = 2,
- MV_CESA_CRYPTO_THEN_MAC = 3,
-
- MV_CESA_MAX_OPERATION
-
-} MV_CESA_OPERATION;
-
-#define MV_CESA_OPERATION_OFFSET 0
-#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET)
-
-/* mac algorithm */
-typedef enum
-{
- MV_CESA_MAC_NULL = 0,
- MV_CESA_MAC_MD5 = 4,
- MV_CESA_MAC_SHA1 = 5,
- MV_CESA_MAC_HMAC_MD5 = 6,
- MV_CESA_MAC_HMAC_SHA1 = 7,
-
-} MV_CESA_MAC_MODE;
-
-#define MV_CESA_MAC_MODE_OFFSET 4
-#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET)
-
-typedef enum
-{
- MV_CESA_MAC_DIGEST_FULL = 0,
- MV_CESA_MAC_DIGEST_96B = 1,
-
-} MV_CESA_MAC_DIGEST_SIZE;
-
-#define MV_CESA_MAC_DIGEST_SIZE_BIT 7
-#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT)
-
-
-typedef enum
-{
- MV_CESA_CRYPTO_NULL = 0,
- MV_CESA_CRYPTO_DES = 1,
- MV_CESA_CRYPTO_3DES = 2,
- MV_CESA_CRYPTO_AES = 3,
-
-} MV_CESA_CRYPTO_ALG;
-
-#define MV_CESA_CRYPTO_ALG_OFFSET 8
-#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET)
-
-
-/* direction */
-typedef enum
-{
- MV_CESA_DIR_ENCODE = 0,
- MV_CESA_DIR_DECODE = 1,
-
-} MV_CESA_DIRECTION;
-
-#define MV_CESA_DIRECTION_BIT 12
-#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT)
-
-/* crypto IV mode */
-typedef enum
-{
- MV_CESA_CRYPTO_ECB = 0,
- MV_CESA_CRYPTO_CBC = 1,
-
- /* NO HW Support */
- MV_CESA_CRYPTO_CTR = 10,
-
-} MV_CESA_CRYPTO_MODE;
-
-#define MV_CESA_CRYPTO_MODE_BIT 16
-#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT)
-
-/* 3DES mode */
-typedef enum
-{
- MV_CESA_CRYPTO_3DES_EEE = 0,
- MV_CESA_CRYPTO_3DES_EDE = 1,
-
-} MV_CESA_CRYPTO_3DES_MODE;
-
-#define MV_CESA_CRYPTO_3DES_MODE_BIT 20
-#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT)
-
-
-/* AES Key Length */
-typedef enum
-{
- MV_CESA_CRYPTO_AES_KEY_128 = 0,
- MV_CESA_CRYPTO_AES_KEY_192 = 1,
- MV_CESA_CRYPTO_AES_KEY_256 = 2,
-
-} MV_CESA_CRYPTO_AES_KEY_LEN;
-
-#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24
-#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET)
-
-/* Fragmentation mode */
-typedef enum
-{
- MV_CESA_FRAG_NONE = 0,
- MV_CESA_FRAG_FIRST = 1,
- MV_CESA_FRAG_LAST = 2,
- MV_CESA_FRAG_MIDDLE = 3,
-
-} MV_CESA_FRAG_MODE;
-
-#define MV_CESA_FRAG_MODE_OFFSET 30
-#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET)
-/*---------------------------------------------------------------------------*/
-
-/********** Security Accelerator Command Register **************/
-#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00)
-
-#define MV_CESA_CMD_CHAN_ENABLE_BIT 0
-#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT)
-
-#define MV_CESA_CMD_CHAN_DISABLE_BIT 2
-#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT)
-
-/********** Security Accelerator Descriptor Pointers Register **********/
-#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04)
-
-/********** Security Accelerator Configuration Register **********/
-#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08)
-
-#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0
-#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT)
-
-#define MV_CESA_CFG_WAIT_DMA_BIT 7
-#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT)
-
-#define MV_CESA_CFG_ACT_DMA_BIT 9
-#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT)
-
-#define MV_CESA_CFG_CHAIN_MODE_BIT 11
-#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT)
-
-/********** Security Accelerator Status Register ***********/
-#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C)
-
-#define MV_CESA_STATUS_ACTIVE_BIT 0
-#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT)
-
-#define MV_CESA_STATUS_DIGEST_ERR_BIT 8
-#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT)
-
-
-/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */
-#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20)
-
-/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */
-#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24)
-
-#define MV_CESA_CAUSE_AUTH_MASK (1 << 0)
-#define MV_CESA_CAUSE_DES_MASK (1 << 1)
-#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2)
-#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3)
-#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4)
-
-#define MV_CESA_CAUSE_ACC_BIT 5
-#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT)
-
-#define MV_CESA_CAUSE_ACC_DMA_BIT 7
-#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT)
-#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT)
-
-#define MV_CESA_CAUSE_DMA_COMPL_BIT 9
-#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT)
-
-#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10
-#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT)
-
-#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11
-#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT)
-
-
-#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38)
-#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20)
-#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24)
-
-#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2))
-
-#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00)
-#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04)
-#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08)
-#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c)
-#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10)
-#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18)
-
-#define MV_CESA_AUTH_ALGORITHM_BIT 0
-#define MV_CESA_AUTH_ALGORITHM_MD5 (0<<AUTH_ALGORITHM_BIT)
-#define MV_CESA_AUTH_ALGORITHM_SHA1 (1<<AUTH_ALGORITHM_BIT)
-
-#define MV_CESA_AUTH_IV_MODE_BIT 1
-#define MV_CESA_AUTH_IV_MODE_INIT (0<<AUTH_IV_MODE_BIT)
-#define MV_CESA_AUTH_IV_MODE_CONTINUE (1<<AUTH_IV_MODE_BIT)
-
-#define MV_CESA_AUTH_DATA_BYTE_SWAP_BIT 2
-#define MV_CESA_AUTH_DATA_BYTE_SWAP_MASK (1<<AUTH_DATA_BYTE_SWAP_BIT)
-
-
-#define MV_CESA_AUTH_IV_BYTE_SWAP_BIT 4
-#define MV_CESA_AUTH_IV_BYTE_SWAP_MASK (1<<AUTH_IV_BYTE_SWAP_BIT)
-
-#define MV_CESA_AUTH_TERMINATION_BIT 31
-#define MV_CESA_AUTH_TERMINATION_MASK (1<<AUTH_TERMINATION_BIT)
-
-
-/*************** TDMA Control Register ************************************************/
-#define MV_CESA_TDMA_CTRL_REG (MV_CESA_TDMA_REG_BASE + 0x840)
-
-#define MV_CESA_TDMA_BURST_32B 3
-#define MV_CESA_TDMA_BURST_128B 4
-
-#define MV_CESA_TDMA_DST_BURST_OFFSET 0
-#define MV_CESA_TDMA_DST_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_DST_BURST_OFFSET)
-#define MV_CESA_TDMA_DST_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_DST_BURST_OFFSET)
-
-#define MV_CESA_TDMA_OUTSTAND_READ_EN_BIT 4
-#define MV_CESA_TDMA_OUTSTAND_READ_EN_MASK (1<<MV_CESA_TDMA_OUTSTAND_READ_EN_BIT)
-
-#define MV_CESA_TDMA_SRC_BURST_OFFSET 6
-#define MV_CESA_TDMA_SRC_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_SRC_BURST_OFFSET)
-#define MV_CESA_TDMA_SRC_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_SRC_BURST_OFFSET)
-
-#define MV_CESA_TDMA_CHAIN_MODE_BIT 9
-#define MV_CESA_TDMA_NON_CHAIN_MODE_MASK (1<<MV_CESA_TDMA_CHAIN_MODE_BIT)
-
-#define MV_CESA_TDMA_BYTE_SWAP_BIT 11
-#define MV_CESA_TDMA_BYTE_SWAP_MASK (0 << MV_CESA_TDMA_BYTE_SWAP_BIT)
-#define MV_CESA_TDMA_NO_BYTE_SWAP_MASK (1 << MV_CESA_TDMA_BYTE_SWAP_BIT)
-
-#define MV_CESA_TDMA_ENABLE_BIT 12
-#define MV_CESA_TDMA_ENABLE_MASK (1<<MV_CESA_TDMA_ENABLE_BIT)
-
-#define MV_CESA_TDMA_FETCH_NEXT_DESC_BIT 13
-#define MV_CESA_TDMA_FETCH_NEXT_DESC_MASK (1<<MV_CESA_TDMA_FETCH_NEXT_DESC_BIT)
-
-#define MV_CESA_TDMA_CHAN_ACTIVE_BIT 14
-#define MV_CESA_TDMA_CHAN_ACTIVE_MASK (1<<MV_CESA_TDMA_CHAN_ACTIVE_BIT)
-/*------------------------------------------------------------------------------------*/
-
-#define MV_CESA_TDMA_BYTE_COUNT_REG (MV_CESA_TDMA_REG_BASE + 0x800)
-#define MV_CESA_TDMA_SRC_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x810)
-#define MV_CESA_TDMA_DST_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x820)
-#define MV_CESA_TDMA_NEXT_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x830)
-#define MV_CESA_TDMA_CURR_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x870)
-
-#define MV_CESA_TDMA_ERROR_CAUSE_REG (MV_CESA_TDMA_REG_BASE + 0x8C0)
-#define MV_CESA_TDMA_ERROR_MASK_REG (MV_CESA_TDMA_REG_BASE + 0x8C4)
-
-
-#endif /* __mvCesaRegs_h__ */
-
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell \r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File in accordance with the terms and conditions of the General \r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is \r
+available along with the File in the license.txt file or by writing to the Free \r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or \r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. \r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY \r
+DISCLAIMED. The GPL License provides additional details about this warranty \r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File under the following licensing terms. \r
+Redistribution and use in source and binary forms, with or without modification, \r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer. \r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution. \r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be \r
+ used to endorse or promote products derived from this software without \r
+ specific prior written permission. \r
+ \r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND \r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR \r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON \r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+\r
+#ifndef __mvCesaRegs_h__\r
+#define __mvCesaRegs_h__\r
+\r
+#include "mvTypes.h"\r
+\r
+typedef struct\r
+{\r
+ /* word 0 */\r
+ MV_U32 config;\r
+ /* word 1 */ \r
+ MV_U16 cryptoSrcOffset;\r
+ MV_U16 cryptoDstOffset;\r
+ /* word 2 */ \r
+ MV_U16 cryptoDataLen;\r
+ MV_U16 reserved1;\r
+ /* word 3 */\r
+ MV_U16 cryptoKeyOffset;\r
+ MV_U16 reserved2;\r
+ /* word 4 */\r
+ MV_U16 cryptoIvOffset;\r
+ MV_U16 cryptoIvBufOffset;\r
+ /* word 5 */\r
+ MV_U16 macSrcOffset;\r
+ MV_U16 macTotalLen;\r
+ /* word 6 */\r
+ MV_U16 macDigestOffset;\r
+ MV_U16 macDataLen;\r
+ /* word 7 */\r
+ MV_U16 macInnerIvOffset;\r
+ MV_U16 macOuterIvOffset;\r
+\r
+} MV_CESA_DESC;\r
+\r
+/* operation */\r
+typedef enum \r
+{\r
+ MV_CESA_MAC_ONLY = 0,\r
+ MV_CESA_CRYPTO_ONLY = 1,\r
+ MV_CESA_MAC_THEN_CRYPTO = 2,\r
+ MV_CESA_CRYPTO_THEN_MAC = 3,\r
+ \r
+ MV_CESA_MAX_OPERATION\r
+\r
+} MV_CESA_OPERATION;\r
+\r
+#define MV_CESA_OPERATION_OFFSET 0\r
+#define MV_CESA_OPERATION_MASK (0x3 << MV_CESA_OPERATION_OFFSET)\r
+\r
+/* mac algorithm */\r
+typedef enum \r
+{ \r
+ MV_CESA_MAC_NULL = 0,\r
+ MV_CESA_MAC_MD5 = 4,\r
+ MV_CESA_MAC_SHA1 = 5,\r
+ MV_CESA_MAC_HMAC_MD5 = 6,\r
+ MV_CESA_MAC_HMAC_SHA1 = 7,\r
+\r
+} MV_CESA_MAC_MODE;\r
+\r
+#define MV_CESA_MAC_MODE_OFFSET 4\r
+#define MV_CESA_MAC_MODE_MASK (0x7 << MV_CESA_MAC_MODE_OFFSET)\r
+\r
+typedef enum\r
+{\r
+ MV_CESA_MAC_DIGEST_FULL = 0,\r
+ MV_CESA_MAC_DIGEST_96B = 1,\r
+\r
+} MV_CESA_MAC_DIGEST_SIZE;\r
+\r
+#define MV_CESA_MAC_DIGEST_SIZE_BIT 7\r
+#define MV_CESA_MAC_DIGEST_SIZE_MASK (1 << MV_CESA_MAC_DIGEST_SIZE_BIT)\r
+\r
+\r
+typedef enum \r
+{\r
+ MV_CESA_CRYPTO_NULL = 0,\r
+ MV_CESA_CRYPTO_DES = 1,\r
+ MV_CESA_CRYPTO_3DES = 2,\r
+ MV_CESA_CRYPTO_AES = 3,\r
+\r
+} MV_CESA_CRYPTO_ALG;\r
+\r
+#define MV_CESA_CRYPTO_ALG_OFFSET 8\r
+#define MV_CESA_CRYPTO_ALG_MASK (0x3 << MV_CESA_CRYPTO_ALG_OFFSET)\r
+\r
+\r
+/* direction */\r
+typedef enum \r
+{\r
+ MV_CESA_DIR_ENCODE = 0,\r
+ MV_CESA_DIR_DECODE = 1,\r
+\r
+} MV_CESA_DIRECTION;\r
+\r
+#define MV_CESA_DIRECTION_BIT 12\r
+#define MV_CESA_DIRECTION_MASK (1 << MV_CESA_DIRECTION_BIT)\r
+\r
+/* crypto IV mode */\r
+typedef enum \r
+{\r
+ MV_CESA_CRYPTO_ECB = 0,\r
+ MV_CESA_CRYPTO_CBC = 1,\r
+\r
+ /* NO HW Support */\r
+ MV_CESA_CRYPTO_CTR = 10,\r
+\r
+} MV_CESA_CRYPTO_MODE;\r
+\r
+#define MV_CESA_CRYPTO_MODE_BIT 16\r
+#define MV_CESA_CRYPTO_MODE_MASK (1 << MV_CESA_CRYPTO_MODE_BIT) \r
+\r
+/* 3DES mode */\r
+typedef enum \r
+{\r
+ MV_CESA_CRYPTO_3DES_EEE = 0,\r
+ MV_CESA_CRYPTO_3DES_EDE = 1,\r
+\r
+} MV_CESA_CRYPTO_3DES_MODE;\r
+\r
+#define MV_CESA_CRYPTO_3DES_MODE_BIT 20\r
+#define MV_CESA_CRYPTO_3DES_MODE_MASK (1 << MV_CESA_CRYPTO_3DES_MODE_BIT)\r
+\r
+\r
+/* AES Key Length */\r
+typedef enum \r
+{\r
+ MV_CESA_CRYPTO_AES_KEY_128 = 0,\r
+ MV_CESA_CRYPTO_AES_KEY_192 = 1,\r
+ MV_CESA_CRYPTO_AES_KEY_256 = 2,\r
+\r
+} MV_CESA_CRYPTO_AES_KEY_LEN;\r
+\r
+#define MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET 24\r
+#define MV_CESA_CRYPTO_AES_KEY_LEN_MASK (0x3 << MV_CESA_CRYPTO_AES_KEY_LEN_OFFSET)\r
+\r
+/* Fragmentation mode */\r
+typedef enum \r
+{\r
+ MV_CESA_FRAG_NONE = 0,\r
+ MV_CESA_FRAG_FIRST = 1,\r
+ MV_CESA_FRAG_LAST = 2,\r
+ MV_CESA_FRAG_MIDDLE = 3,\r
+\r
+} MV_CESA_FRAG_MODE;\r
+\r
+#define MV_CESA_FRAG_MODE_OFFSET 30\r
+#define MV_CESA_FRAG_MODE_MASK (0x3 << MV_CESA_FRAG_MODE_OFFSET)\r
+/*---------------------------------------------------------------------------*/\r
+\r
+/********** Security Accelerator Command Register **************/\r
+#define MV_CESA_CMD_REG (MV_CESA_REG_BASE + 0xE00)\r
+\r
+#define MV_CESA_CMD_CHAN_ENABLE_BIT 0 \r
+#define MV_CESA_CMD_CHAN_ENABLE_MASK (1 << MV_CESA_CMD_CHAN_ENABLE_BIT)\r
+\r
+#define MV_CESA_CMD_CHAN_DISABLE_BIT 2 \r
+#define MV_CESA_CMD_CHAN_DISABLE_MASK (1 << MV_CESA_CMD_CHAN_DISABLE_BIT) \r
+\r
+/********** Security Accelerator Descriptor Pointers Register **********/\r
+#define MV_CESA_CHAN_DESC_OFFSET_REG (MV_CESA_REG_BASE + 0xE04)\r
+\r
+/********** Security Accelerator Configuration Register **********/\r
+#define MV_CESA_CFG_REG (MV_CESA_REG_BASE + 0xE08)\r
+\r
+#define MV_CESA_CFG_STOP_DIGEST_ERR_BIT 0\r
+#define MV_CESA_CFG_STOP_DIGEST_ERR_MASK (1 << MV_CESA_CFG_STOP_DIGEST_ERR_BIT)\r
+\r
+#define MV_CESA_CFG_WAIT_DMA_BIT 7\r
+#define MV_CESA_CFG_WAIT_DMA_MASK (1 << MV_CESA_CFG_WAIT_DMA_BIT)\r
+ \r
+#define MV_CESA_CFG_ACT_DMA_BIT 9\r
+#define MV_CESA_CFG_ACT_DMA_MASK (1 << MV_CESA_CFG_ACT_DMA_BIT)\r
+\r
+#define MV_CESA_CFG_CHAIN_MODE_BIT 11\r
+#define MV_CESA_CFG_CHAIN_MODE_MASK (1 << MV_CESA_CFG_CHAIN_MODE_BIT)\r
+\r
+/********** Security Accelerator Status Register ***********/\r
+#define MV_CESA_STATUS_REG (MV_CESA_REG_BASE + 0xE0C)\r
+\r
+#define MV_CESA_STATUS_ACTIVE_BIT 0\r
+#define MV_CESA_STATUS_ACTIVE_MASK (1 << MV_CESA_STATUS_ACTIVE_BIT)\r
+\r
+#define MV_CESA_STATUS_DIGEST_ERR_BIT 8\r
+#define MV_CESA_STATUS_DIGEST_ERR_MASK (1 << MV_CESA_STATUS_DIGEST_ERR_BIT)\r
+\r
+\r
+/* Cryptographic Engines and Security Accelerator Interrupt Cause Register */\r
+#define MV_CESA_ISR_CAUSE_REG (MV_CESA_REG_BASE + 0xE20)\r
+\r
+/* Cryptographic Engines and Security Accelerator Interrupt Mask Register */\r
+#define MV_CESA_ISR_MASK_REG (MV_CESA_REG_BASE + 0xE24)\r
+\r
+#define MV_CESA_CAUSE_AUTH_MASK (1 << 0)\r
+#define MV_CESA_CAUSE_DES_MASK (1 << 1)\r
+#define MV_CESA_CAUSE_AES_ENCR_MASK (1 << 2)\r
+#define MV_CESA_CAUSE_AES_DECR_MASK (1 << 3)\r
+#define MV_CESA_CAUSE_DES_ALL_MASK (1 << 4)\r
+\r
+#define MV_CESA_CAUSE_ACC_BIT 5\r
+#define MV_CESA_CAUSE_ACC_MASK (1 << MV_CESA_CAUSE_ACC_BIT)\r
+\r
+#define MV_CESA_CAUSE_ACC_DMA_BIT 7\r
+#define MV_CESA_CAUSE_ACC_DMA_MASK (1 << MV_CESA_CAUSE_ACC_DMA_BIT)\r
+#define MV_CESA_CAUSE_ACC_DMA_ALL_MASK (3 << MV_CESA_CAUSE_ACC_DMA_BIT)\r
+\r
+#define MV_CESA_CAUSE_DMA_COMPL_BIT 9\r
+#define MV_CESA_CAUSE_DMA_COMPL_MASK (1 << MV_CESA_CAUSE_DMA_COMPL_BIT)\r
+\r
+#define MV_CESA_CAUSE_DMA_OWN_ERR_BIT 10\r
+#define MV_CESA_CAUSE_DMA_OWN_ERR_MASK (1 < MV_CESA_CAUSE_DMA_OWN_ERR_BIT)\r
+\r
+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT 11\r
+#define MV_CESA_CAUSE_DMA_CHAIN_PKT_MASK (1 < MV_CESA_CAUSE_DMA_CHAIN_PKT_BIT)\r
+\r
+\r
+#define MV_CESA_AUTH_DATA_IN_REG (MV_CESA_REG_BASE + 0xd38)\r
+#define MV_CESA_AUTH_BIT_COUNT_LOW_REG (MV_CESA_REG_BASE + 0xd20)\r
+#define MV_CESA_AUTH_BIT_COUNT_HIGH_REG (MV_CESA_REG_BASE + 0xd24)\r
+\r
+#define MV_CESA_AUTH_INIT_VAL_DIGEST_REG(i) (MV_CESA_REG_BASE + 0xd00 + (i<<2))\r
+\r
+#define MV_CESA_AUTH_INIT_VAL_DIGEST_A_REG (MV_CESA_REG_BASE + 0xd00)\r
+#define MV_CESA_AUTH_INIT_VAL_DIGEST_B_REG (MV_CESA_REG_BASE + 0xd04)\r
+#define MV_CESA_AUTH_INIT_VAL_DIGEST_C_REG (MV_CESA_REG_BASE + 0xd08)\r
+#define MV_CESA_AUTH_INIT_VAL_DIGEST_D_REG (MV_CESA_REG_BASE + 0xd0c)\r
+#define MV_CESA_AUTH_INIT_VAL_DIGEST_E_REG (MV_CESA_REG_BASE + 0xd10)\r
+#define MV_CESA_AUTH_COMMAND_REG (MV_CESA_REG_BASE + 0xd18)\r
+\r
+#define MV_CESA_AUTH_ALGORITHM_BIT 0\r
+#define MV_CESA_AUTH_ALGORITHM_MD5 (0<<AUTH_ALGORITHM_BIT)\r
+#define MV_CESA_AUTH_ALGORITHM_SHA1 (1<<AUTH_ALGORITHM_BIT)\r
+\r
+#define MV_CESA_AUTH_IV_MODE_BIT 1\r
+#define MV_CESA_AUTH_IV_MODE_INIT (0<<AUTH_IV_MODE_BIT)\r
+#define MV_CESA_AUTH_IV_MODE_CONTINUE (1<<AUTH_IV_MODE_BIT)\r
+\r
+#define MV_CESA_AUTH_DATA_BYTE_SWAP_BIT 2\r
+#define MV_CESA_AUTH_DATA_BYTE_SWAP_MASK (1<<AUTH_DATA_BYTE_SWAP_BIT)\r
+\r
+\r
+#define MV_CESA_AUTH_IV_BYTE_SWAP_BIT 4\r
+#define MV_CESA_AUTH_IV_BYTE_SWAP_MASK (1<<AUTH_IV_BYTE_SWAP_BIT)\r
+\r
+#define MV_CESA_AUTH_TERMINATION_BIT 31\r
+#define MV_CESA_AUTH_TERMINATION_MASK (1<<AUTH_TERMINATION_BIT)\r
+\r
+\r
+/*************** TDMA Control Register ************************************************/\r
+#define MV_CESA_TDMA_CTRL_REG (MV_CESA_TDMA_REG_BASE + 0x840)\r
+\r
+#define MV_CESA_TDMA_BURST_32B 3 \r
+#define MV_CESA_TDMA_BURST_128B 4 \r
+\r
+#define MV_CESA_TDMA_DST_BURST_OFFSET 0\r
+#define MV_CESA_TDMA_DST_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_DST_BURST_OFFSET)\r
+#define MV_CESA_TDMA_DST_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_DST_BURST_OFFSET)\r
+\r
+#define MV_CESA_TDMA_OUTSTAND_READ_EN_BIT 4\r
+#define MV_CESA_TDMA_OUTSTAND_READ_EN_MASK (1<<MV_CESA_TDMA_OUTSTAND_READ_EN_BIT)\r
+\r
+#define MV_CESA_TDMA_SRC_BURST_OFFSET 6\r
+#define MV_CESA_TDMA_SRC_BURST_ALL_MASK (0x7<<MV_CESA_TDMA_SRC_BURST_OFFSET)\r
+#define MV_CESA_TDMA_SRC_BURST_MASK(burst) ((burst)<<MV_CESA_TDMA_SRC_BURST_OFFSET)\r
+\r
+#define MV_CESA_TDMA_CHAIN_MODE_BIT 9\r
+#define MV_CESA_TDMA_NON_CHAIN_MODE_MASK (1<<MV_CESA_TDMA_CHAIN_MODE_BIT)\r
+\r
+#define MV_CESA_TDMA_BYTE_SWAP_BIT 11\r
+#define MV_CESA_TDMA_BYTE_SWAP_MASK (0 << MV_CESA_TDMA_BYTE_SWAP_BIT)\r
+#define MV_CESA_TDMA_NO_BYTE_SWAP_MASK (1 << MV_CESA_TDMA_BYTE_SWAP_BIT) \r
+\r
+#define MV_CESA_TDMA_ENABLE_BIT 12\r
+#define MV_CESA_TDMA_ENABLE_MASK (1<<MV_CESA_TDMA_ENABLE_BIT)\r
+ \r
+#define MV_CESA_TDMA_FETCH_NEXT_DESC_BIT 13 \r
+#define MV_CESA_TDMA_FETCH_NEXT_DESC_MASK (1<<MV_CESA_TDMA_FETCH_NEXT_DESC_BIT) \r
+\r
+#define MV_CESA_TDMA_CHAN_ACTIVE_BIT 14 \r
+#define MV_CESA_TDMA_CHAN_ACTIVE_MASK (1<<MV_CESA_TDMA_CHAN_ACTIVE_BIT)\r
+/*------------------------------------------------------------------------------------*/\r
+\r
+#define MV_CESA_TDMA_BYTE_COUNT_REG (MV_CESA_TDMA_REG_BASE + 0x800)\r
+#define MV_CESA_TDMA_SRC_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x810)\r
+#define MV_CESA_TDMA_DST_ADDR_REG (MV_CESA_TDMA_REG_BASE + 0x820)\r
+#define MV_CESA_TDMA_NEXT_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x830)\r
+#define MV_CESA_TDMA_CURR_DESC_PTR_REG (MV_CESA_TDMA_REG_BASE + 0x870)\r
+\r
+#define MV_CESA_TDMA_ERROR_CAUSE_REG (MV_CESA_TDMA_REG_BASE + 0x8C0)\r
+#define MV_CESA_TDMA_ERROR_MASK_REG (MV_CESA_TDMA_REG_BASE + 0x8C4)\r
+\r
+\r
+#endif /* __mvCesaRegs_h__ */ \r
+\r
#if defined(CONFIG_MV646xx)
#include "marvell_pic.h"
-#endif
+#endif\r
#define MV_CESA_USE_TIMER_ID 0
#define CESA_DEF_BUF_SIZE 1500
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.4\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
#define CESA_OCF_MAX_SES 128
#define CESA_Q_SIZE 64
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(3,2,0)
+#define FRAG_PAGE(f) (f).p
+#else
+#define FRAG_PAGE(f) (f)
+#endif
/* data structures */
struct cesa_ocf_data {
for ( i = 0; i < skb_shinfo(skb)->nr_frags; i++ ) {
skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
p_buf_info->bufSize = frag->size;
- p_buf_info->bufVirtPtr = page_address(frag->page) + frag->page_offset;
+ p_buf_info->bufVirtPtr = page_address(FRAG_PAGE(frag->page)) + frag->page_offset;
p_buf_info++;
}
p_mbuf_info->numFrags = skb_shinfo(skb)->nr_frags + 1;
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.4\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-
-#ifndef __INCmvHalVerh
-#define __INCmvHalVerh
-
-/* Defines */
-#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7"
-#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4"
-
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell\r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or\r
+modify this File in accordance with the terms and conditions of the General\r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is\r
+available along with the File in the license.txt file or by writing to the Free\r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or\r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.\r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED\r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY\r
+DISCLAIMED. The GPL License provides additional details about this warranty\r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or\r
+modify this File under the following licensing terms.\r
+Redistribution and use in source and binary forms, with or without modification,\r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer.\r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution.\r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be\r
+ used to endorse or promote products derived from this software without\r
+ specific prior written permission.\r
+\r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND\r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED\r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE\r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR\r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES\r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;\r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON\r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT\r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+\r
+\r
+#ifndef __INCmvHalVerh\r
+#define __INCmvHalVerh\r
+\r
+/* Defines */\r
+#define MV_HAL_VERSION "FEROCEON_HAL_3_1_7"\r
+#define MV_RELEASE_BASELINE "SoCandControllers_FEROCEON_RELEASE_7_9_2009_KW_4_3_4_DD_2_1_4_6183_1_1_4"\r
+\r
#endif /* __INCmvHalVerh */
\ No newline at end of file
return target;
}
-
-MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
- MV_DEC_WIN_PARAMS *pWinParam)
-{
- MV_U32 baseToReg=0, sizeToReg=0;
-
- /* BaseLow[31:16] => base register [31:16] */
- baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK;
-
- /* Write to address decode Base Address Register */
- pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK;
- pWinParam->baseAddr |= baseToReg;
-
- /* Get size register value according to window size */
- sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT);
-
- /* Size parameter validity check. */
- if (-1 == sizeToReg)
- {
- mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n");
- return MV_BAD_PARAM;
- }
- pWinParam->size = sizeToReg;
-
- pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib;
- pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId;
-
- return MV_OK;
-}
-
-MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
- MV_DEC_WIN *pAddrDecWin)
-{
- MV_TARGET_ATTRIB targetAttrib;
-
- pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr;
-
- /* Upper 32bit address base is supported under PCI High Address remap */
- pAddrDecWin->addrWin.baseHigh = 0;
-
- /* Prepare sizeReg to ctrlRegToSize function */
- pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT);
-
- if (-1 == pAddrDecWin->addrWin.size)
- {
- DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n"));
- return MV_BAD_PARAM;
- }
- targetAttrib.targetId = pWinParam->targetId;
- targetAttrib.attrib = pWinParam->attrib;
-
- pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
-
- return MV_OK;
-}
-
-
-
+\r
+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, \r
+ MV_DEC_WIN_PARAMS *pWinParam)\r
+{\r
+ MV_U32 baseToReg=0, sizeToReg=0;\r
+ \r
+ /* BaseLow[31:16] => base register [31:16] */\r
+ baseToReg = pAddrDecWin->addrWin.baseLow & CTRL_DEC_BASE_MASK;\r
+\r
+ /* Write to address decode Base Address Register */\r
+ pWinParam->baseAddr &= ~CTRL_DEC_BASE_MASK;\r
+ pWinParam->baseAddr |= baseToReg;\r
+\r
+ /* Get size register value according to window size */\r
+ sizeToReg = ctrlSizeToReg(pAddrDecWin->addrWin.size, CTRL_DEC_SIZE_ALIGNMENT);\r
+ \r
+ /* Size parameter validity check. */\r
+ if (-1 == sizeToReg)\r
+ {\r
+ mvOsPrintf("mvCtrlAddrDecToParams: ERR. ctrlSizeToReg failed.\n");\r
+ return MV_BAD_PARAM;\r
+ }\r
+ pWinParam->size = sizeToReg;\r
+\r
+ pWinParam->attrib = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].attrib;\r
+ pWinParam->targetId = mvTargetDefaultsArray[MV_CHANGE_BOOT_CS(pAddrDecWin->target)].targetId;\r
+\r
+ return MV_OK;\r
+}\r
+\r
+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, \r
+ MV_DEC_WIN *pAddrDecWin)\r
+{\r
+ MV_TARGET_ATTRIB targetAttrib;\r
+\r
+ pAddrDecWin->addrWin.baseLow = pWinParam->baseAddr;\r
+ \r
+ /* Upper 32bit address base is supported under PCI High Address remap */\r
+ pAddrDecWin->addrWin.baseHigh = 0; \r
+\r
+ /* Prepare sizeReg to ctrlRegToSize function */\r
+ pAddrDecWin->addrWin.size = ctrlRegToSize(pWinParam->size, CTRL_DEC_SIZE_ALIGNMENT);\r
+\r
+ if (-1 == pAddrDecWin->addrWin.size)\r
+ {\r
+ DB(mvOsPrintf("mvCtrlParamsToAddrDec: ERR. ctrlRegToSize failed.\n"));\r
+ return MV_BAD_PARAM;\r
+ }\r
+ targetAttrib.targetId = pWinParam->targetId;\r
+ targetAttrib.attrib = pWinParam->attrib;\r
+\r
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);\r
+\r
+ return MV_OK;\r
+}\r
+\r
+
+\r
MV_TARGET_ID targetId; /* Target Id of this MV_TARGET */
}MV_TARGET_ATTRIB;
-
-
-/* This structure describes address decode window */
-typedef struct _mvDecWin
-{
- MV_TARGET target; /* Target for addr decode window */
- MV_ADDR_WIN addrWin; /* Address window of target */
- MV_BOOL enable; /* Window enable/disable */
-}MV_DEC_WIN;
-
-typedef struct _mvDecWinParams
-{
- MV_TARGET_ID targetId; /* Target ID field */
- MV_U8 attrib; /* Attribute field */
- MV_U32 baseAddr; /* Base address in register format */
- MV_U32 size; /* Size in register format */
-}MV_DEC_WIN_PARAMS;
+\r
+\r
+/* This structure describes address decode window */\r
+typedef struct _mvDecWin \r
+{\r
+ MV_TARGET target; /* Target for addr decode window */\r
+ MV_ADDR_WIN addrWin; /* Address window of target */\r
+ MV_BOOL enable; /* Window enable/disable */\r
+}MV_DEC_WIN;\r
+\r
+typedef struct _mvDecWinParams\r
+{\r
+ MV_TARGET_ID targetId; /* Target ID field */\r
+ MV_U8 attrib; /* Attribute field */\r
+ MV_U32 baseAddr; /* Base address in register format */\r
+ MV_U32 size; /* Size in register format */\r
+}MV_DEC_WIN_PARAMS;\r
/* mvCtrlEnvAddrDec API list */
MV_TARGET mvCtrlTargetGet(MV_TARGET_ATTRIB *targetAttrib);
-MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin,
- MV_DEC_WIN_PARAMS *pWinParam);
+MV_STATUS mvCtrlAddrDecToParams(MV_DEC_WIN *pAddrDecWin, \r
+ MV_DEC_WIN_PARAMS *pWinParam);\r
-MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam,
- MV_DEC_WIN *pAddrDecWin);
+MV_STATUS mvCtrlParamsToAddrDec(MV_DEC_WIN_PARAMS *pWinParam, \r
+ MV_DEC_WIN *pAddrDecWin);\r
--- /dev/null
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define MV_ASMLANGUAGE
+#include "mvOsAsm.h"
+#include "mvDeviceId.h"
+#include "mvCtrlEnvRegs.h"
+#include "mvCpuIfRegs.h"
+#include "mvCtrlEnvAsm.h"
+
+
+/*******************************************************************************
+* mvCpuIfPreInit - Make early initialization of CPU interface.
+*
+* DESCRIPTION:
+* The function will initialize the CPU interface parameters that must
+* be initialize before any BUS activity towards the DDR interface,
+* which means it must be executed from ROM. Because of that, the function
+* is implemented in assembly code.
+* The function configure the following CPU config register parameters:
+* 1) CPU2MbusLTickDrv
+* 2) CPU2MbusLTickSample.
+* NOTE: This function must be called AFTER the internal register
+* base is modified to INTER_REGS_BASE.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+* r11 holds return function address.
+*******************************************************************************/
+#define MV88F6281_PCKG_OPT 2
+#define MV88F6192_PCKG_OPT 1
+#define MV88F6180_PCKG_OPT 0
+
+ .globl _mvCpuIfPreInit
+_mvCpuIfPreInit:
+
+ mov r11, LR /* Save link register */
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r4, r5);
+
+ /* goto calcConfigReg if device is 6281 */
+ ldr r5, =MV88F6281_PCKG_OPT
+ cmp r4, r5
+ beq calcConfigReg
+
+ /* goto calcConfigReg if device is 6192/6190 */
+ ldr r5, =MV88F6192_PCKG_OPT
+ cmp r4, r5
+ beq calcConfigReg
+
+ /* Else 6180 */
+ /* Get the "sample on reset" register */
+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
+ ldr r5, =MSAR_CPUCLCK_MASK_6180
+ and r5, r4, r5
+ mov r5, r5, lsr #MSAR_CPUCLCK_OFFS_6180
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
+ cmp r5, #CPU_2_DDR_CLK_1x3_1
+ beq setConfigReg
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
+ cmp r5, #CPU_2_DDR_CLK_1x4_1
+ beq setConfigReg
+ b setConfigReg
+
+calcConfigReg:
+ /* Get the "sample on reset" register */
+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
+ ldr r5, =MSAR_DDRCLCK_RTIO_MASK
+ and r5, r4, r5
+ mov r5, r5, lsr #MSAR_DDRCLCK_RTIO_OFFS
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x3
+ cmp r5, #CPU_2_DDR_CLK_1x3
+ beq setConfigReg
+
+ ldr r4, =CPU_2_MBUSL_DDR_CLK_1x4
+ cmp r5, #CPU_2_DDR_CLK_1x4
+ beq setConfigReg
+
+ /* Else */
+ ldr r4, =0
+
+setConfigReg:
+ /* Read CPU Config register */
+ MV_REG_READ_ASM (r7, r5, CPU_CONFIG_REG)
+ ldr r5, =~(CCR_CPU_2_MBUSL_TICK_DRV_MASK | CCR_CPU_2_MBUSL_TICK_SMPL_MASK)
+ and r7, r7, r5 /* Clear register fields */
+ orr r7, r7, r4 /* Set the values according to the findings */
+ MV_REG_WRITE_ASM (r7, r5, CPU_CONFIG_REG)
+
+done:
+ mov PC, r11 /* r11 is saved link register */
-
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef __INCMVSysSataAddrDech
-#define __INCMVSysSataAddrDech
-
-#include "mvCommon.h"
-#include "ctrlEnv/mvCtrlEnvLib.h"
-#include "ctrlEnv/sys/mvCpuIf.h"
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct _mvSataDecWin
-{
- MV_TARGET target;
- MV_ADDR_WIN addrWin; /* An address window*/
- MV_BOOL enable; /* Address decode window is enabled/disabled */
-
-} MV_SATA_DEC_WIN;
-
-
-#define MV_SATA_MAX_ADDR_DECODE_WIN 4
-
-#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4))
-#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4))
-
-/* BITs in Bridge Interrupt Cause and Mask registers */
-#define MV_SATA_ADDR_DECODE_ERROR_BIT 0
-#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<<MV_SATA_ADDR_DECODE_ERROR_BIT)
-
-/* BITs in Windows 0-3 Control and Base Registers */
-#define MV_SATA_WIN_ENABLE_BIT 0
-#define MV_SATA_WIN_ENABLE_MASK (1<<MV_SATA_WIN_ENABLE_BIT)
-
-#define MV_SATA_WIN_TARGET_OFFSET 4
-#define MV_SATA_WIN_TARGET_MASK (0xF<<MV_SATA_WIN_TARGET_OFFSET)
-
-#define MV_SATA_WIN_ATTR_OFFSET 8
-#define MV_SATA_WIN_ATTR_MASK (0xFF<<MV_SATA_WIN_ATTR_OFFSET)
-
-#define MV_SATA_WIN_SIZE_OFFSET 16
-#define MV_SATA_WIN_SIZE_MASK (0xFFFF<<MV_SATA_WIN_SIZE_OFFSET)
-
-#define MV_SATA_WIN_BASE_OFFSET 16
-#define MV_SATA_WIN_BASE_MASK (0xFFFF<<MV_SATA_WIN_BASE_OFFSET)
-
-MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);
-MV_STATUS mvSataWinSet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);
-MV_STATUS mvSataWinByTargetGet(MV_TARGET target, MV_SATA_DEC_WIN *pAddrDecWin);
-MV_STATUS mvSataWinInit(MV_VOID);
-MV_VOID mvSataAddrDecShow(MV_VOID);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
-
-
-
-
-
+\r
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell \r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File in accordance with the terms and conditions of the General \r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is \r
+available along with the File in the license.txt file or by writing to the Free \r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or \r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. \r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY \r
+DISCLAIMED. The GPL License provides additional details about this warranty \r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File under the following licensing terms. \r
+Redistribution and use in source and binary forms, with or without modification, \r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer. \r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution. \r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be \r
+ used to endorse or promote products derived from this software without \r
+ specific prior written permission. \r
+ \r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND \r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR \r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON \r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+#ifndef __INCMVSysSataAddrDech\r
+#define __INCMVSysSataAddrDech\r
+\r
+#include "mvCommon.h"\r
+#include "ctrlEnv/mvCtrlEnvLib.h"\r
+#include "ctrlEnv/sys/mvCpuIf.h"\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+typedef struct _mvSataDecWin\r
+{\r
+ MV_TARGET target;\r
+ MV_ADDR_WIN addrWin; /* An address window*/\r
+ MV_BOOL enable; /* Address decode window is enabled/disabled */\r
+ \r
+} MV_SATA_DEC_WIN;\r
+\r
+\r
+#define MV_SATA_MAX_ADDR_DECODE_WIN 4\r
+\r
+#define MV_SATA_WIN_CTRL_REG(dev, win) (SATA_REG_BASE + 0x30 + ((win)<<4))\r
+#define MV_SATA_WIN_BASE_REG(dev, win) (SATA_REG_BASE + 0x34 + ((win)<<4))\r
+\r
+/* BITs in Bridge Interrupt Cause and Mask registers */\r
+#define MV_SATA_ADDR_DECODE_ERROR_BIT 0\r
+#define MV_SATA_ADDR_DECODE_ERROR_MASK (1<<MV_SATA_ADDR_DECODE_ERROR_BIT)\r
+\r
+/* BITs in Windows 0-3 Control and Base Registers */\r
+#define MV_SATA_WIN_ENABLE_BIT 0\r
+#define MV_SATA_WIN_ENABLE_MASK (1<<MV_SATA_WIN_ENABLE_BIT)\r
+\r
+#define MV_SATA_WIN_TARGET_OFFSET 4\r
+#define MV_SATA_WIN_TARGET_MASK (0xF<<MV_SATA_WIN_TARGET_OFFSET)\r
+\r
+#define MV_SATA_WIN_ATTR_OFFSET 8\r
+#define MV_SATA_WIN_ATTR_MASK (0xFF<<MV_SATA_WIN_ATTR_OFFSET)\r
+\r
+#define MV_SATA_WIN_SIZE_OFFSET 16\r
+#define MV_SATA_WIN_SIZE_MASK (0xFFFF<<MV_SATA_WIN_SIZE_OFFSET)\r
+\r
+#define MV_SATA_WIN_BASE_OFFSET 16\r
+#define MV_SATA_WIN_BASE_MASK (0xFFFF<<MV_SATA_WIN_BASE_OFFSET)\r
+\r
+MV_STATUS mvSataWinGet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);\r
+MV_STATUS mvSataWinSet(int dev, MV_U32 winNum, MV_SATA_DEC_WIN *pAddrDecWin);\r
+MV_STATUS mvSataWinByTargetGet(MV_TARGET target, MV_SATA_DEC_WIN *pAddrDecWin);\r
+MV_STATUS mvSataWinInit(MV_VOID);\r
+MV_VOID mvSataAddrDecShow(MV_VOID);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
-
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-#ifndef __INCMVSysSdmmcAddrDech
-#define __INCMVSysSdmmcAddrDech
-
-#include "mvCommon.h"
-#include "ctrlEnv/mvCtrlEnvLib.h"
-#include "ctrlEnv/sys/mvCpuIf.h"
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct _mvSdmmcDecWin
-{
- MV_TARGET target;
- MV_ADDR_WIN addrWin; /* An address window*/
- MV_BOOL enable; /* Address decode window is enabled/disabled */
-
-} MV_SDMMC_DEC_WIN;
-
-
-#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4
-
-#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3))
-#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3))
-
-
-/* BITs in Windows 0-3 Control and Base Registers */
-#define MV_SDMMC_WIN_ENABLE_BIT 0
-#define MV_SDMMC_WIN_ENABLE_MASK (1<<MV_SDMMC_WIN_ENABLE_BIT)
-
-#define MV_SDMMC_WIN_TARGET_OFFSET 4
-#define MV_SDMMC_WIN_TARGET_MASK (0xF<<MV_SDMMC_WIN_TARGET_OFFSET)
-
-#define MV_SDMMC_WIN_ATTR_OFFSET 8
-#define MV_SDMMC_WIN_ATTR_MASK (0xFF<<MV_SDMMC_WIN_ATTR_OFFSET)
-
-#define MV_SDMMC_WIN_SIZE_OFFSET 16
-#define MV_SDMMC_WIN_SIZE_MASK (0xFFFF<<MV_SDMMC_WIN_SIZE_OFFSET)
-
-#define MV_SDMMC_WIN_BASE_OFFSET 16
-#define MV_SDMMC_WIN_BASE_MASK (0xFFFF<<MV_SDMMC_WIN_BASE_OFFSET)
-
-MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);
-MV_STATUS mvSdmmcWinSet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);
-MV_STATUS mvSdmmcWinByTargetGet(MV_TARGET target, MV_SDMMC_DEC_WIN *pAddrDecWin);
-MV_STATUS mvSdmmcWinInit(MV_VOID);
-MV_VOID mvSdmmcAddrDecShow(MV_VOID);
-
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif
-
-
-
-
-
+\r
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell \r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File in accordance with the terms and conditions of the General \r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is \r
+available along with the File in the license.txt file or by writing to the Free \r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or \r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. \r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY \r
+DISCLAIMED. The GPL License provides additional details about this warranty \r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File under the following licensing terms. \r
+Redistribution and use in source and binary forms, with or without modification, \r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer. \r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution. \r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be \r
+ used to endorse or promote products derived from this software without \r
+ specific prior written permission. \r
+ \r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND \r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR \r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON \r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+#ifndef __INCMVSysSdmmcAddrDech\r
+#define __INCMVSysSdmmcAddrDech\r
+\r
+#include "mvCommon.h"\r
+#include "ctrlEnv/mvCtrlEnvLib.h"\r
+#include "ctrlEnv/sys/mvCpuIf.h"\r
+\r
+\r
+#ifdef __cplusplus\r
+extern "C" {\r
+#endif\r
+\r
+typedef struct _mvSdmmcDecWin\r
+{\r
+ MV_TARGET target;\r
+ MV_ADDR_WIN addrWin; /* An address window*/\r
+ MV_BOOL enable; /* Address decode window is enabled/disabled */\r
+ \r
+} MV_SDMMC_DEC_WIN;\r
+\r
+\r
+#define MV_SDMMC_MAX_ADDR_DECODE_WIN 4\r
+\r
+#define MV_SDMMC_WIN_CTRL_REG(dev, win) (MV_SDIO_REG_BASE + 0x108 + ((win)<<3))\r
+#define MV_SDMMC_WIN_BASE_REG(dev, win) (MV_SDIO_REG_BASE + 0x10c + ((win)<<3))\r
+\r
+\r
+/* BITs in Windows 0-3 Control and Base Registers */\r
+#define MV_SDMMC_WIN_ENABLE_BIT 0\r
+#define MV_SDMMC_WIN_ENABLE_MASK (1<<MV_SDMMC_WIN_ENABLE_BIT)\r
+\r
+#define MV_SDMMC_WIN_TARGET_OFFSET 4\r
+#define MV_SDMMC_WIN_TARGET_MASK (0xF<<MV_SDMMC_WIN_TARGET_OFFSET)\r
+\r
+#define MV_SDMMC_WIN_ATTR_OFFSET 8\r
+#define MV_SDMMC_WIN_ATTR_MASK (0xFF<<MV_SDMMC_WIN_ATTR_OFFSET)\r
+\r
+#define MV_SDMMC_WIN_SIZE_OFFSET 16\r
+#define MV_SDMMC_WIN_SIZE_MASK (0xFFFF<<MV_SDMMC_WIN_SIZE_OFFSET)\r
+\r
+#define MV_SDMMC_WIN_BASE_OFFSET 16\r
+#define MV_SDMMC_WIN_BASE_MASK (0xFFFF<<MV_SDMMC_WIN_BASE_OFFSET)\r
+\r
+MV_STATUS mvSdmmcWinGet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);\r
+MV_STATUS mvSdmmcWinSet(int dev, MV_U32 winNum, MV_SDMMC_DEC_WIN *pAddrDecWin);\r
+MV_STATUS mvSdmmcWinByTargetGet(MV_TARGET target, MV_SDMMC_DEC_WIN *pAddrDecWin);\r
+MV_STATUS mvSdmmcWinInit(MV_VOID);\r
+MV_VOID mvSdmmcAddrDecShow(MV_VOID);\r
+\r
+\r
+#ifdef __cplusplus\r
+}\r
+#endif\r
+\r
+\r
+#endif\r
+\r
+\r
+\r
+\r
+\r
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "mvSysTdm.h"
-
-
-/* defines */
-#ifdef MV_DEBUG
- #define DB(x) x
-#else
- #define DB(x)
-#endif
-
-static MV_TARGET tdmAddrDecPrioTap[] =
-{
- PEX0_MEM,
- SDRAM_CS0,
- SDRAM_CS1,
- SDRAM_CS2,
- SDRAM_CS3,
- DEVICE_CS0,
- DEVICE_CS1,
- DEVICE_CS2,
- DEV_BOOCS,
- PEX0_IO,
- TBL_TERM
-};\r
-
-static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin);
-
-/*******************************************************************************
-* mvTdmWinInit - Initialize TDM address decode windows
-*
-* DESCRIPTION:
-* This function initialize TDM window decode unit. It set the
-* default address decode
-* windows of the unit.
-*
-* INPUT:
-* None.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* MV_ERROR if setting fail.
-*******************************************************************************/
-
-MV_STATUS mvTdmWinInit(void)
-{
- MV_U32 winNum;
- MV_U32 winPrioIndex = 0;
- MV_CPU_DEC_WIN cpuAddrDecWin;
- MV_TDM_DEC_WIN tdmWin;
- MV_STATUS status;
-
- /*Disable all windows*/
- for (winNum = 0; winNum < TDM_MBUS_MAX_WIN; winNum++)
- {
- mvTdmWinEnable(winNum, MV_FALSE);
- }
-
- for (winNum = 0; ((tdmAddrDecPrioTap[winPrioIndex] != TBL_TERM) &&
- (winNum < TDM_MBUS_MAX_WIN)); )
- {
- status = mvCpuIfTargetWinGet(tdmAddrDecPrioTap[winPrioIndex],
- &cpuAddrDecWin);
- if (MV_NO_SUCH == status)
- {
- winPrioIndex++;
- continue;
- }
- if (MV_OK != status)
- {
- mvOsPrintf("mvTdmInit: ERR. mvCpuIfTargetWinGet failed\n");
- return MV_ERROR;
- }
-
- if (cpuAddrDecWin.enable == MV_TRUE)
- {
- tdmWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;
- tdmWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;
- tdmWin.addrWin.size = cpuAddrDecWin.addrWin.size;
- tdmWin.enable = MV_TRUE;
- tdmWin.target = tdmAddrDecPrioTap[winPrioIndex];
- if (MV_OK != mvTdmWinSet(winNum, &tdmWin))
- {
- return MV_ERROR;
- }
- winNum++;
- }
- winPrioIndex++;
- }
- return MV_OK;
-}
-
-/*******************************************************************************
-* mvTdmWinSet - Set TDM target address window
-*
-* DESCRIPTION:
-* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)
-* address window, also known as address decode window.
-* After setting this target window, the TDM will be able to access the
-* target within the address window.
-*
-* INPUT:
-* winNum - TDM to target address decode window number.
-* pAddrDecWin - TDM target window data structure.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* MV_ERROR if address window overlapps with other address decode windows.
-* MV_BAD_PARAM if base address is invalid parameter or target is
-* unknown.
-*
-*******************************************************************************/
-
-MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)
-{
- MV_TARGET_ATTRIB targetAttribs;
- MV_DEC_REGS decRegs;
- MV_U32 ctrlReg = 0;
-
- /* Parameter checking */
- if (winNum >= TDM_MBUS_MAX_WIN)
- {
- mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum);
- return MV_BAD_PARAM;
- }
-
- /* Check if the requested window overlapps with current windows */
- if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin))
- {
- mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum);
- return MV_ERROR;
- }
-
- /* check if address is aligned to the size */
- if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))
- {
- mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\
- "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",
- winNum,
- mvCtrlTargetNameGet(pAddrDecWin->target),
- pAddrDecWin->addrWin.baseLow,
- pAddrDecWin->addrWin.size);
- return MV_ERROR;
- }
-
- decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));
- decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;
-
- if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))
- {
- mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n");
- return MV_ERROR;
- }
-
- mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);
-
- /* for the safe side we disable the window before writing the new
- values */
- mvTdmWinEnable(winNum, MV_FALSE);
-
- ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS);
- ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS);
- ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK);
-
- /* Write to address base and control registers */
- MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg);
- MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg);
- /* Enable address decode target window */
- if (pAddrDecWin->enable == MV_TRUE)
- {
- mvTdmWinEnable(winNum, MV_TRUE);
- }
- return MV_OK;
-}
-
-/*******************************************************************************
-* mvTdmWinGet - Get peripheral target address window.
-*
-* DESCRIPTION:
-* Get TDM peripheral target address window.
-*
-* INPUT:
-* winNum - TDM to target address decode window number.
-*
-* OUTPUT:
-* pAddrDecWin - TDM target window data structure.
-*
-* RETURN:
-* MV_ERROR if register parameters are invalid.
-*
-*******************************************************************************/
-
-MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)
-{
-
- MV_DEC_REGS decRegs;
- MV_TARGET_ATTRIB targetAttrib;
-
- /* Parameter checking */
- if (winNum >= TDM_MBUS_MAX_WIN)
- {
- mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum);
- return MV_NOT_SUPPORTED;
- }
-
- decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));
- decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;
-
- if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))
- {
- mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n");
- return MV_ERROR;
- }
-
- /* attrib and targetId */
- targetAttrib.attrib =
- (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS;
- targetAttrib.targetId =
- (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS;
-
- pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);
-
- /* Check if window is enabled */
- if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)
- {
- pAddrDecWin->enable = MV_TRUE;
- }
- else
- {
- pAddrDecWin->enable = MV_FALSE;
- }
-
- return MV_OK;
-}
-
-/*******************************************************************************
-* mvTdmWinEnable - Enable/disable a TDM to target address window
-*
-* DESCRIPTION:
-* This function enable/disable a TDM to target address window.
-* According to parameter 'enable' the routine will enable the
-* window, thus enabling TDM accesses (before enabling the window it is
-* tested for overlapping). Otherwise, the window will be disabled.
-*
-* INPUT:
-* winNum - TDM to target address decode window number.
-* enable - Enable/disable parameter.
-*
-* OUTPUT:
-* N/A
-*
-* RETURN:
-* MV_ERROR if decode window number was wrong or enabled window overlapps.
-*
-*******************************************************************************/
-MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable)
-{
- MV_TDM_DEC_WIN addrDecWin;
-
- if (MV_TRUE == enable)
- {
- if (winNum >= TDM_MBUS_MAX_WIN)
- {
- mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum);
- return MV_ERROR;
- }
-
- /* First check for overlap with other enabled windows */
- /* Get current window */
- if (MV_OK != mvTdmWinGet(winNum, &addrDecWin))
- {
- mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n");
- return MV_ERROR;
- }
- /* Check for overlapping */
- if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin)))
- {
- /* No Overlap. Enable address decode target window */
- MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);
- }
- else
- { /* Overlap detected */
- mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n");
- return MV_ERROR;
- }
- }
- else
- {
- MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);
- }
- return MV_OK;
-}
-
-
-/*******************************************************************************
-* tdmWinOverlapDetect - Detect TDM address windows overlapping
-*
-* DESCRIPTION:
-* An unpredicted behaviour is expected in case TDM address decode
-* windows overlapps.
-* This function detects TDM address decode windows overlapping of a
-* specified window. The function does not check the window itself for
-* overlapping. The function also skipps disabled address decode windows.
-*
-* INPUT:
-* winNum - address decode window number.
-* pAddrDecWin - An address decode window struct.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* MV_TRUE if the given address window overlap current address
-* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data
-* from registers.
-*
-*******************************************************************************/
-static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)
-{
- MV_U32 winNumIndex;
- MV_TDM_DEC_WIN addrDecWin;
-
- for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++)
- {
- /* Do not check window itself */
- if (winNumIndex == winNum)
- {
- continue;
- }
- /* Do not check disabled windows */
- if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)
- {
- /* Get window parameters */
- if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin))
- {
- DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n"));
- return MV_ERROR;
- }
-
- if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))
- {
- return MV_TRUE;
- }
- }
- }
- return MV_FALSE;
-}
-
-/*******************************************************************************
-* mvTdmAddrDecShow - Print the TDM address decode map.
-*
-* DESCRIPTION:
-* This function print the TDM address decode map.
-*
-* INPUT:
-* None.
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* None.
-*
-*******************************************************************************/
-MV_VOID mvTdmAddrDecShow(MV_VOID)
-{
- MV_TDM_DEC_WIN win;
- int i;
-
- mvOsOutput( "\n" );
- mvOsOutput( "TDM:\n" );
- mvOsOutput( "----\n" );
-
- for( i = 0; i < TDM_MBUS_MAX_WIN; i++ )
- {
- memset( &win, 0, sizeof(MV_TDM_DEC_WIN) );
-
- mvOsOutput( "win%d - ", i );
-
- if (mvTdmWinGet(i, &win ) == MV_OK )
- {
- if( win.enable )
- {
- mvOsOutput( "%s base %08x, ",
- mvCtrlTargetNameGet(win.target), win.addrWin.baseLow);
- mvOsOutput( "...." );
- mvSizePrint( win.addrWin.size );
- mvOsOutput( "\n" );
- }
- else
- mvOsOutput( "disable\n" );
- }
- }
-}
-
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell \r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File in accordance with the terms and conditions of the General \r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is \r
+available along with the File in the license.txt file or by writing to the Free \r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or \r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. \r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY \r
+DISCLAIMED. The GPL License provides additional details about this warranty \r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File under the following licensing terms. \r
+Redistribution and use in source and binary forms, with or without modification, \r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer. \r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution. \r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be \r
+ used to endorse or promote products derived from this software without \r
+ specific prior written permission. \r
+ \r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND \r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR \r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON \r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+\r
+#include "mvSysTdm.h"\r
+\r
+\r
+/* defines */\r
+#ifdef MV_DEBUG\r
+ #define DB(x) x\r
+#else\r
+ #define DB(x)\r
+#endif \r
+\r
+static MV_TARGET tdmAddrDecPrioTap[] =\r
+{\r
+ PEX0_MEM,\r
+ SDRAM_CS0,\r
+ SDRAM_CS1,\r
+ SDRAM_CS2,\r
+ SDRAM_CS3,\r
+ DEVICE_CS0,\r
+ DEVICE_CS1,\r
+ DEVICE_CS2,\r
+ DEV_BOOCS,\r
+ PEX0_IO,\r
+ TBL_TERM\r
+};\r\r
+\r
+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin);\r
+\r
+/*******************************************************************************\r
+* mvTdmWinInit - Initialize TDM address decode windows \r
+*\r
+* DESCRIPTION:\r
+* This function initialize TDM window decode unit. It set the \r
+* default address decode\r
+* windows of the unit.\r
+*\r
+* INPUT:\r
+* None.\r
+*\r
+* OUTPUT:\r
+* None.\r
+*\r
+* RETURN:\r
+* MV_ERROR if setting fail.\r
+*******************************************************************************/\r
+\r
+MV_STATUS mvTdmWinInit(void)\r
+{\r
+ MV_U32 winNum;\r
+ MV_U32 winPrioIndex = 0;\r
+ MV_CPU_DEC_WIN cpuAddrDecWin;\r
+ MV_TDM_DEC_WIN tdmWin;\r
+ MV_STATUS status;\r
+\r
+ /*Disable all windows*/ \r
+ for (winNum = 0; winNum < TDM_MBUS_MAX_WIN; winNum++)\r
+ {\r
+ mvTdmWinEnable(winNum, MV_FALSE);\r
+ }\r
+\r
+ for (winNum = 0; ((tdmAddrDecPrioTap[winPrioIndex] != TBL_TERM) && \r
+ (winNum < TDM_MBUS_MAX_WIN)); )\r
+ { \r
+ status = mvCpuIfTargetWinGet(tdmAddrDecPrioTap[winPrioIndex], \r
+ &cpuAddrDecWin);\r
+ if (MV_NO_SUCH == status)\r
+ {\r
+ winPrioIndex++;\r
+ continue;\r
+ }\r
+ if (MV_OK != status)\r
+ {\r
+ mvOsPrintf("mvTdmInit: ERR. mvCpuIfTargetWinGet failed\n");\r
+ return MV_ERROR;\r
+ }\r
+\r
+ if (cpuAddrDecWin.enable == MV_TRUE)\r
+ {\r
+ tdmWin.addrWin.baseHigh = cpuAddrDecWin.addrWin.baseHigh;\r
+ tdmWin.addrWin.baseLow = cpuAddrDecWin.addrWin.baseLow;\r
+ tdmWin.addrWin.size = cpuAddrDecWin.addrWin.size;\r
+ tdmWin.enable = MV_TRUE;\r
+ tdmWin.target = tdmAddrDecPrioTap[winPrioIndex];\r
+ if (MV_OK != mvTdmWinSet(winNum, &tdmWin))\r
+ {\r
+ return MV_ERROR;\r
+ }\r
+ winNum++;\r
+ }\r
+ winPrioIndex++; \r
+ }\r
+ return MV_OK;\r
+}\r
+\r
+/*******************************************************************************\r
+* mvTdmWinSet - Set TDM target address window\r
+*\r
+* DESCRIPTION:\r
+* This function sets a peripheral target (e.g. SDRAM bank0, PCI_MEM0)\r
+* address window, also known as address decode window.\r
+* After setting this target window, the TDM will be able to access the\r
+* target within the address window.\r
+*\r
+* INPUT:\r
+* winNum - TDM to target address decode window number.\r
+* pAddrDecWin - TDM target window data structure.\r
+*\r
+* OUTPUT:\r
+* None.\r
+*\r
+* RETURN:\r
+* MV_ERROR if address window overlapps with other address decode windows.\r
+* MV_BAD_PARAM if base address is invalid parameter or target is\r
+* unknown.\r
+*\r
+*******************************************************************************/\r
+\r
+MV_STATUS mvTdmWinSet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)\r
+{\r
+ MV_TARGET_ATTRIB targetAttribs;\r
+ MV_DEC_REGS decRegs;\r
+ MV_U32 ctrlReg = 0;\r
+\r
+ /* Parameter checking */\r
+ if (winNum >= TDM_MBUS_MAX_WIN)\r
+ {\r
+ mvOsPrintf("mvTdmWinSet: ERR. Invalid win num %d\n",winNum);\r
+ return MV_BAD_PARAM;\r
+ }\r
+ \r
+ /* Check if the requested window overlapps with current windows */\r
+ if (MV_TRUE == tdmWinOverlapDetect(winNum, &pAddrDecWin->addrWin))\r
+ {\r
+ mvOsPrintf("mvTdmWinSet: ERR. Window %d overlap\n", winNum);\r
+ return MV_ERROR;\r
+ }\r
+\r
+ /* check if address is aligned to the size */\r
+ if (MV_IS_NOT_ALIGN(pAddrDecWin->addrWin.baseLow, pAddrDecWin->addrWin.size))\r
+ {\r
+ mvOsPrintf("mvTdmWinSet: Error setting TDM window %d to "\\r
+ "target %s.\nAddress 0x%08x is unaligned to size 0x%x.\n",\r
+ winNum,\r
+ mvCtrlTargetNameGet(pAddrDecWin->target), \r
+ pAddrDecWin->addrWin.baseLow,\r
+ pAddrDecWin->addrWin.size);\r
+ return MV_ERROR;\r
+ }\r
+\r
+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum));\r
+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;\r
+\r
+ if (MV_OK != mvCtrlAddrDecToReg(&(pAddrDecWin->addrWin),&decRegs))\r
+ {\r
+ mvOsPrintf("mvTdmWinSet: mvCtrlAddrDecToReg Failed\n");\r
+ return MV_ERROR;\r
+ }\r
+ \r
+ mvCtrlAttribGet(pAddrDecWin->target, &targetAttribs);\r
+ \r
+ /* for the safe side we disable the window before writing the new\r
+ values */\r
+ mvTdmWinEnable(winNum, MV_FALSE);\r
+\r
+ ctrlReg |= (targetAttribs.attrib << TDM_WIN_ATTRIB_OFFS);\r
+ ctrlReg |= (targetAttribs.targetId << TDM_WIN_TARGET_OFFS);\r
+ ctrlReg |= (decRegs.sizeReg & TDM_WIN_SIZE_MASK);\r
+\r
+ /* Write to address base and control registers */\r
+ MV_REG_WRITE(TDM_WIN_BASE_REG(winNum), decRegs.baseReg);\r
+ MV_REG_WRITE(TDM_WIN_CTRL_REG(winNum), ctrlReg); \r
+ /* Enable address decode target window */\r
+ if (pAddrDecWin->enable == MV_TRUE)\r
+ {\r
+ mvTdmWinEnable(winNum, MV_TRUE);\r
+ } \r
+ return MV_OK;\r
+}\r
+\r
+/*******************************************************************************\r
+* mvTdmWinGet - Get peripheral target address window.\r
+*\r
+* DESCRIPTION:\r
+* Get TDM peripheral target address window.\r
+*\r
+* INPUT:\r
+* winNum - TDM to target address decode window number.\r
+*\r
+* OUTPUT:\r
+* pAddrDecWin - TDM target window data structure.\r
+*\r
+* RETURN:\r
+* MV_ERROR if register parameters are invalid.\r
+*\r
+*******************************************************************************/\r
+\r
+MV_STATUS mvTdmWinGet(MV_U32 winNum, MV_TDM_DEC_WIN *pAddrDecWin)\r
+{\r
+\r
+ MV_DEC_REGS decRegs;\r
+ MV_TARGET_ATTRIB targetAttrib;\r
+\r
+ /* Parameter checking */\r
+ if (winNum >= TDM_MBUS_MAX_WIN)\r
+ {\r
+ mvOsPrintf("mvTdmWinGet: ERR. Invalid winNum %d\n", winNum);\r
+ return MV_NOT_SUPPORTED;\r
+ }\r
+ \r
+ decRegs.baseReg = MV_REG_READ(TDM_WIN_BASE_REG(winNum)); \r
+ decRegs.sizeReg = (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_SIZE_MASK) >> TDM_WIN_SIZE_OFFS;\r
+ \r
+ if (MV_OK != mvCtrlRegToAddrDec(&decRegs,&(pAddrDecWin->addrWin)))\r
+ {\r
+ mvOsPrintf("mvTdmWinGet: mvCtrlRegToAddrDec Failed \n");\r
+ return MV_ERROR;\r
+ }\r
+ \r
+ /* attrib and targetId */\r
+ targetAttrib.attrib = \r
+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ATTRIB_MASK) >> TDM_WIN_ATTRIB_OFFS;\r
+ targetAttrib.targetId = \r
+ (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_TARGET_MASK) >> TDM_WIN_TARGET_OFFS;\r
+ \r
+ pAddrDecWin->target = mvCtrlTargetGet(&targetAttrib);\r
+\r
+ /* Check if window is enabled */\r
+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)\r
+ {\r
+ pAddrDecWin->enable = MV_TRUE;\r
+ }\r
+ else\r
+ {\r
+ pAddrDecWin->enable = MV_FALSE;\r
+ }\r
+ \r
+ return MV_OK;\r
+}\r
+\r
+/*******************************************************************************\r
+* mvTdmWinEnable - Enable/disable a TDM to target address window\r
+*\r
+* DESCRIPTION:\r
+* This function enable/disable a TDM to target address window.\r
+* According to parameter 'enable' the routine will enable the\r
+* window, thus enabling TDM accesses (before enabling the window it is\r
+* tested for overlapping). Otherwise, the window will be disabled.\r
+*\r
+* INPUT:\r
+* winNum - TDM to target address decode window number.\r
+* enable - Enable/disable parameter.\r
+*\r
+* OUTPUT:\r
+* N/A\r
+*\r
+* RETURN:\r
+* MV_ERROR if decode window number was wrong or enabled window overlapps.\r
+*\r
+*******************************************************************************/\r
+MV_STATUS mvTdmWinEnable(int winNum, MV_BOOL enable)\r
+{\r
+ MV_TDM_DEC_WIN addrDecWin;\r
+\r
+ if (MV_TRUE == enable)\r
+ {\r
+ if (winNum >= TDM_MBUS_MAX_WIN)\r
+ {\r
+ mvOsPrintf("mvTdmWinEnable:ERR. Invalid winNum%d\n",winNum);\r
+ return MV_ERROR;\r
+ } \r
+ \r
+ /* First check for overlap with other enabled windows */\r
+ /* Get current window */\r
+ if (MV_OK != mvTdmWinGet(winNum, &addrDecWin))\r
+ {\r
+ mvOsPrintf("mvTdmWinEnable:ERR. targetWinGet fail\n");\r
+ return MV_ERROR;\r
+ }\r
+ /* Check for overlapping */\r
+ if (MV_FALSE == tdmWinOverlapDetect(winNum, &(addrDecWin.addrWin)))\r
+ {\r
+ /* No Overlap. Enable address decode target window */\r
+ MV_REG_BIT_SET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK);\r
+ }\r
+ else\r
+ { /* Overlap detected */\r
+ mvOsPrintf("mvTdmWinEnable:ERR. Overlap detected\n");\r
+ return MV_ERROR;\r
+ }\r
+ }\r
+ else\r
+ {\r
+ MV_REG_BIT_RESET(TDM_WIN_CTRL_REG(winNum), TDM_WIN_ENABLE_MASK); \r
+ }\r
+ return MV_OK;\r
+}\r
+\r
+\r
+/*******************************************************************************\r
+* tdmWinOverlapDetect - Detect TDM address windows overlapping\r
+*\r
+* DESCRIPTION:\r
+* An unpredicted behaviour is expected in case TDM address decode \r
+* windows overlapps.\r
+* This function detects TDM address decode windows overlapping of a \r
+* specified window. The function does not check the window itself for \r
+* overlapping. The function also skipps disabled address decode windows.\r
+*\r
+* INPUT:\r
+* winNum - address decode window number.\r
+* pAddrDecWin - An address decode window struct.\r
+*\r
+* OUTPUT:\r
+* None.\r
+*\r
+* RETURN:\r
+* MV_TRUE if the given address window overlap current address\r
+* decode map, MV_FALSE otherwise, MV_ERROR if reading invalid data \r
+* from registers.\r
+*\r
+*******************************************************************************/\r
+static MV_STATUS tdmWinOverlapDetect(MV_U32 winNum, MV_ADDR_WIN *pAddrWin)\r
+{\r
+ MV_U32 winNumIndex;\r
+ MV_TDM_DEC_WIN addrDecWin;\r
+\r
+ for (winNumIndex = 0; winNumIndex < TDM_MBUS_MAX_WIN; winNumIndex++)\r
+ {\r
+ /* Do not check window itself */\r
+ if (winNumIndex == winNum)\r
+ {\r
+ continue;\r
+ }\r
+ /* Do not check disabled windows */\r
+ if (MV_REG_READ(TDM_WIN_CTRL_REG(winNum)) & TDM_WIN_ENABLE_MASK)\r
+ {\r
+ /* Get window parameters */\r
+ if (MV_OK != mvTdmWinGet(winNumIndex, &addrDecWin))\r
+ {\r
+ DB(mvOsPrintf("dmaWinOverlapDetect: ERR. TargetWinGet failed\n"));\r
+ return MV_ERROR;\r
+ }\r
+\r
+ if (MV_TRUE == ctrlWinOverlapTest(pAddrWin, &(addrDecWin.addrWin)))\r
+ {\r
+ return MV_TRUE;\r
+ } \r
+ }\r
+ }\r
+ return MV_FALSE;\r
+}\r
+\r
+/*******************************************************************************\r
+* mvTdmAddrDecShow - Print the TDM address decode map.\r
+*\r
+* DESCRIPTION:\r
+* This function print the TDM address decode map.\r
+*\r
+* INPUT:\r
+* None.\r
+*\r
+* OUTPUT:\r
+* None.\r
+*\r
+* RETURN:\r
+* None.\r
+*\r
+*******************************************************************************/\r
+MV_VOID mvTdmAddrDecShow(MV_VOID)\r
+{\r
+ MV_TDM_DEC_WIN win;\r
+ int i;\r
+\r
+ mvOsOutput( "\n" );\r
+ mvOsOutput( "TDM:\n" );\r
+ mvOsOutput( "----\n" );\r
+\r
+ for( i = 0; i < TDM_MBUS_MAX_WIN; i++ )\r
+ {\r
+ memset( &win, 0, sizeof(MV_TDM_DEC_WIN) );\r
+\r
+ mvOsOutput( "win%d - ", i );\r
+\r
+ if (mvTdmWinGet(i, &win ) == MV_OK )\r
+ {\r
+ if( win.enable )\r
+ {\r
+ mvOsOutput( "%s base %08x, ",\r
+ mvCtrlTargetNameGet(win.target), win.addrWin.baseLow);\r
+ mvOsOutput( "...." );\r
+ mvSizePrint( win.addrWin.size );\r
+ mvOsOutput( "\n" );\r
+ }\r
+ else\r
+ mvOsOutput( "disable\n" );\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.5\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.3\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.3\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define MV_ASMLANGUAGE
+#include "mvSysHwConfig.h"
+#include "mvOsAsm.h"
+#include "mvBoardEnvSpec.h"
+#include "mvCpuIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "mvDramIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "pci/mvPciRegs.h"
+#include "mvCtrlEnvSpec.h"
+#include "mvCtrlEnvAsm.h"
+#include "cpu/mvCpuArm.h"
+#include "mvCommon.h"
+
+/* defines */
+
+#if !defined(MV_INC_BOARD_DDIM)
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/******************************************************************************
+*
+*
+*
+*
+*******************************************************************************/
+#if defined(DB_PRPMC) || defined(DB_PEX_PCI) || defined(DB_MNG)
+
+/* PEX_PCI and PRPMC boards 256 MB*/
+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
+#define STATIC_SDRAM_CONFIG 0x03248400
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000030F
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#elif defined(DB_FPGA)
+
+/* FPGA DC boards 256 MB*/
+#define STATIC_SDRAM0_BANK0_SIZE 0x0fff0001
+#define STATIC_SDRAM_CONFIG 0x03208400 /* 32bit */
+#define STATIC_SDRAM_MODE 0x22
+#define STATIC_DUNIT_CTRL_LOW 0x03041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11112220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000000D
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x1
+
+#elif defined(RD_88F6183GP) || defined(DB_CUSTOMER)
+
+/* Customer 1 DDR2 2 devices 512Mbit by 16 bit */
+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
+#define STATIC_SDRAM_CONFIG 0x03158400
+#define STATIC_SDRAM_MODE 0x452
+#define STATIC_DUNIT_CTRL_LOW 0x06041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+
+
+#elif defined(RD_88F6183AP)
+
+/* DDR2 1 devices 512Mbit by 16 bit */
+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
+#define STATIC_SDRAM_CONFIG 0x1f154400
+#define STATIC_SDRAM_MODE 0x432
+#define STATIC_DUNIT_CTRL_LOW 0x04041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11912220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000502
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000601
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+
+/* 6082L MARVELL DIMM */
+#elif defined(DB_88F6082LBP)
+#define STATIC_SDRAM0_BANK0_SIZE 0x07ff0001
+#define STATIC_SDRAM_CONFIG 0x7f158400
+#define STATIC_SDRAM_MODE 0x432
+#define STATIC_DUNIT_CTRL_LOW 0x04041040
+#define STATIC_SDRAM_ADDR_CTRL 0x00000020
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11612220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000501
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x00010000
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000002
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x00000a01
+#define STATIC_SDRAM_EXT_MODE 0x00000440
+
+#elif defined(RD_88W8660_AP82S)
+
+/* Shark RD */
+
+#if defined(MV_DRAM_32M)
+#define STATIC_SDRAM0_BANK0_SIZE 0x01ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x00000010
+#elif defined(MV_DRAM_16M)
+
+#define STATIC_SDRAM0_BANK0_SIZE 0x00ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x00000000
+
+#else
+#error "NO DDR size selected"
+#endif
+
+#define STATIC_SDRAM_CONFIG 0x03144400
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#elif defined(RD_88W8660)
+
+/* Shark RD */
+#define STATIC_SDRAM0_BANK0_SIZE 0x03ff0001
+#define STATIC_SDRAM_CONFIG 0x03144400
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+#define STATIC_SDRAM_ADDR_CTRL 0x00000010
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x0000040b
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#else /* NAS */
+
+
+#if defined(RD_88F5182)
+
+#if defined(MV_88F5082)
+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#else
+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#endif
+
+#elif defined(RD_88F5182_3)
+
+#if defined(MV_88F5082)
+#define STATIC_SDRAM0_BANK0_SIZE 0x3ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#else
+#define STATIC_SDRAM0_BANK0_SIZE 0x7ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x20
+#endif
+
+#else
+
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ff0001
+#define STATIC_SDRAM_ADDR_CTRL 0x0
+
+#endif
+
+#if defined(MV_88F5082)
+#define STATIC_SDRAM_CONFIG 0x3144400
+#else
+#define STATIC_SDRAM_CONFIG 0x3148400
+#endif
+#define STATIC_SDRAM_MODE 0x62
+#define STATIC_DUNIT_CTRL_LOW 0x4041000
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x11602220
+#define STATIC_SDRAM_TIME_CTRL_HI 0x40c
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x0
+#define STATIC_SDRAM_ODT_CTRL_HI 0x0
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0
+#define STATIC_SDRAM_EXT_MODE 0x0
+
+#endif
+
+ .globl _mvDramIfStaticInit
+_mvDramIfStaticInit:
+
+ mov r11, LR /* Save link register */
+ mov r10, r2
+
+ /* If we boot from NAND jump to DRAM sddress */
+
+ mov r5, #1
+ ldr r6, =dramBoot1
+ str r5, [r6] /* We started executing from DRAM */
+
+ ldr r6, dramBoot1
+ cmp r6, #0
+ bne 1f
+
+
+ /* set all dram windows to 0 */
+ mov r6, #0
+ MV_REG_WRITE_ASM(r6, r5, 0x1504)
+ MV_REG_WRITE_ASM(r6, r5, 0x150c)
+ MV_REG_WRITE_ASM(r6, r5, 0x1514)
+ MV_REG_WRITE_ASM(r6, r5, 0x151c)
+
+ /* set all dram configuration in temp registers */
+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
+ ldr r6, = STATIC_SDRAM_CONFIG
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
+ ldr r6, = STATIC_SDRAM_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
+ ldr r6, = STATIC_DUNIT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
+ ldr r6, = STATIC_SDRAM_ADDR_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
+ ldr r6, = STATIC_SDRAM_EXT_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
+
+ mov sp, #0
+ bl _mvDramIfConfig
+1:
+ mov r2, r10
+ mov PC, r11 /* r11 is saved link register */
+
+#else /* #if !defined(MV_INC_BOARD_DDIM) */
+
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/*******************************************************************************
+* mvDramIfBasicInit - Basic initialization of DRAM interface
+*
+* DESCRIPTION:
+* The function will initialize the DRAM for basic usage. The function
+* will use the TWSI assembly API to extract DIMM parameters according
+* to which DRAM interface will be initialized.
+* The function referes to the following DRAM parameters:
+* 1) DIMM is registered or not.
+* 2) DIMM width detection.
+* 3) DIMM density.
+*
+* INPUT:
+* r3 - required size for initial DRAM.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+* Note:
+* r4 holds I2C EEPROM address
+* r5 holds SDRAM register base address
+* r7 holds returned values
+* r8 holds SDRAM various configuration registers value.
+* r11 holds return function address.
+*******************************************************************************/
+/* Setting the offsets of the I2C registers */
+#define NUM_OF_ROWS_OFFSET 3
+#define NUM_OF_COLS_OFFSET 4
+#define NUM_OF_RANKS 5
+#define SDRAM_WIDTH_OFFSET 13
+#define NUM_OF_BANKS_OFFSET 17
+#define SUPPORTED_CL_OFFSET 18
+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
+#define SDRAM_MODULES_ATTR_OFFSET 21
+
+#define DRAM_DEV_DENSITY_128M 0x080
+#define DRAM_DEV_DENSITY_256M 0x100
+#define DRAM_DEV_DENSITY_512M 0x200
+ .globl _mvDramIfBasicInit
+ .extern _i2cInit
+
+_mvDramIfBasicInit:
+
+ mov r11, LR /* Save link register */
+
+ mov r5, #1
+ ldr r8, =dramBoot1
+ str r5, [r8] /* We started executing from DRAM */
+
+ /* If we boot from NAND jump to DRAM sddress */
+ ldr r8, dramBoot1
+ cmp r8, #0
+ movne pc, r11
+
+
+
+ bl _i2cInit /* Initialize TWSI master */
+
+ /* Get default SDRAM Config values */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+ bic r8, r8, #SDRAM_DCFG_MASK
+
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r4, r5);
+
+ /* Return if OrionN */
+ ldr r5, =MV_5180_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* Return if Orion1 */
+ ldr r5, =MV_5181_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* Return if Nas */
+ ldr r5, =MV_5182_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* Return if Shark */
+ ldr r5, =MV_8660_DEV_ID
+ cmp r4, r5
+ beq cat_through_end
+
+ /* goto calcConfigReg if bigger than Orion2*/
+ ldr r5, =MV_5281_DEV_ID
+ cmp r4, r5
+ bne cat_through
+
+cat_through:
+ /* set cat through - for better performance - in orion2 b0 and higher*/
+ orr r8, r8, #SDRAM_CATTHR_EN
+
+cat_through_end:
+
+
+ /* Get registered/non registered info from DIMM */
+ bl _is_Registered
+ beq nonRegistered
+
+setRegistered:
+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
+
+nonRegistered:
+ /* Get SDRAM width */
+ bl _get_width
+
+ orr r6, r8, #SDRAM_DCFG_X16_DEV /* x16 devices */
+ cmp r7, #16
+ beq setConfigReg
+
+ orr r6, r8, #SDRAM_DCFG_X8_DEV /* x8 devices */
+ cmp r7, #8
+ beq setConfigReg
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+setConfigReg:
+ mov r8, r6
+ ldr r6, =SDRAM_CONFIG_DV
+ orr r8, r8, r6 /* Add default settings */
+ mov r6, r8 /* Do not swap r8 content */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_CONFIG_REG)
+
+ /* Set maximum CL supported by DIMM */
+ bl _get_CAL
+
+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
+ clz r6, r7
+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
+
+ /* Check the DDR version */
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne casDdr2
+
+casDdr1:
+ ldr r7, =3 /* stBurstDel field value */
+ ldr r8, =0x52 /* Assuming MAX CL = 1.5 */
+ cmp r6, #1 /* If CL = 1.5 break */
+ beq setModeReg
+
+ ldr r7, =3 /* stBurstDel field value */
+ ldr r8, =0x22 /* Assuming MAX CL = 2 */
+ cmp r6, #2 /* If CL = 2 break */
+ beq setModeReg
+
+ ldr r7, =4 /* stBurstDel field value */
+ ldr r8, =0x62 /* Assuming MAX CL = 2.5 */
+ cmp r6, #3 /* If CL = 2.5 break */
+ beq setModeReg
+
+ ldr r7, =4 /* stBurstDel field value */
+ ldr r8, =0x32 /* Assuming MAX CL = 3 */
+ cmp r6, #4 /* If CL = 3 break */
+ beq setModeReg
+
+ ldr r7, =5 /* stBurstDel field value */
+ ldr r8, =0x42 /* Assuming MAX CL = 4 */
+ cmp r6, #6 /* If CL = 4 break */
+ b setModeReg
+
+ b exit_ddrAutoConfig /* This is an error !! */
+
+casDdr2:
+ ldr r7, =4 /* stBurstDel field value */
+ ldr r8, =0x32 /* Assuming MAX CL = 3 */
+ cmp r6, #3 /* If CL = 3 break */
+ beq casDdr2Cont
+
+ ldr r7, =5 /* stBurstDel field value */
+ ldr r8, =0x42 /* Assuming MAX CL = 4 */
+ cmp r6, #4 /* If CL = 4 break */
+ beq casDdr2Cont
+
+ /* CL 5 currently unsupported. We use CL 4 instead */
+ ldr r7, =5 /* stBurstDel field value */
+ ldr r8, =0x42 /* Assuming MAX CL = 5 */
+ cmp r6, #5 /* If CL = 5 break */
+ beq casDdr2Cont
+
+ b exit_ddrAutoConfig /* This is an error !! */
+casDdr2Cont:
+ /* Write recovery for auto-precharge relevant only in DDR2 */
+ orr r8, r8, #0x400 /* Default value */
+
+setModeReg:
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to it's new value. */
+
+ /* write 'nop' to SDRAM operation */
+ mov r6, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll1:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll1
+
+ /* Now its safe to write new value to SDRAM Mode register */
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_MODE_REG)
+
+ /* Make the Dunit write the DRAM its new mode */
+ mov r6, #0x3 /* Mode Register Set command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll2:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll2
+
+ /* Set Dunit control register according to max CL detected */
+ /* If we use registered DIMM, add 1 to stBurstDel */
+ MV_REG_READ_ASM (r6, r5, SDRAM_CONFIG_REG)
+ tst r6, #SDRAM_REGISTERED
+ beq setDunitReg
+ add r7, r7, #1
+
+setDunitReg:
+ ldr r6, =SDRAM_DUNIT_CTRL_LOW_DV
+ orr r6, r6, r7, LSL #SDRAM_ST_BURST_DEL_OFFS
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+
+
+ /* DIMM density configuration*/
+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
+Density:
+ bl _getDensity
+ mov r8, r7
+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */
+ /* For example 0x10000000 --> 0x1000 */
+
+ mov r6, #0x00
+ cmp r8, #DRAM_DEV_DENSITY_128M
+ beq densCont
+
+ mov r6, #0x10
+ cmp r8, #DRAM_DEV_DENSITY_256M
+ beq densCont
+
+ mov r6, #0x20
+ cmp r8, #DRAM_DEV_DENSITY_512M
+ beq densCont
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+densCont:
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_REG)
+
+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+ tst r8, #SDRAM_DTYPE_DDR2
+ beq _extModeODTEnd
+
+
+ /* Set DDR Extended Mode register for working with CS[0] */
+ /* write 'nop' to SDRAM operation */
+ mov r6, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll3:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll3
+
+ /* Now its safe to write new value to SDRAM Extended Mode register */
+ ldr r6, =DDR_SDRAM_EXT_MODE_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_EXTENDED_MODE_REG)
+
+ /* Make the Dunit write the DRAM its new extended mode */
+ mov r6, #0x4 /* Extended Mode Register Set command */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll4:
+ ldr r6, [r5]
+ cmp r6, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll4
+
+ /* ODT configuration is done for single bank CS[0] only */
+ /* Config DDR2 On Die Termination (ODT) registers */
+ ldr r6, =DDR2_ODT_CTRL_LOW_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_LOW_REG)
+
+ ldr r6, =DDR2_ODT_CTRL_HIGH_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+
+ ldr r6, =DDR2_DUNIT_ODT_CTRL_CS0_DV
+ MV_REG_WRITE_ASM (r6, r5, DDR2_DUNIT_ODT_CONTROL_REG)
+
+
+ /* we will check what device we are running and perform
+ Initialization according to device value */
+
+_extModeODTEnd:
+
+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
+ /* Does Not Work for Address/Control and Data Pads. */
+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r6, r5);
+ /* Read device revision */
+ MV_CTRL_REV_GET_ASM(r8, r5);
+
+ /* Continue if OrionN */
+ ldr r5, =MV_5180_DEV_ID
+ cmp r6, r5
+ bne 1f
+ b glMem2End
+1:
+
+ /* Continue if Orion1 and device revision B1 */
+ ldr r5, =MV_5181_DEV_ID
+ cmp r6, r5
+ bne 1f
+
+ cmp r8, #MV_5181_B1_REV
+ bge glMem2End
+ b glMem2Start
+1:
+
+ /* Orion NAS */
+ ldr r5, =MV_5182_DEV_ID
+ cmp r6, r5
+ beq glMem2Start
+
+ /* Orion Shark */
+ ldr r5, =MV_8660_DEV_ID
+ cmp r6, r5
+ beq glMem2Start
+
+ b glMem2End
+
+glMem2Start:
+
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r8, r6, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r5, r6
+ mov r5, r5, LSL #9
+ mov r5, r5, LSR #26 /* r5[5:0]<DrvN> = r6[22:17]<LockN> */
+ orr r5, r5, r5, LSL #6 /* r5[11:6]<DrvP> = r5[5:0]<DrvN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r5
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r8, r6, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_DATA_PADS_CAL_REG)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r6, r6, #SDRAM_DRVN_MASK /* Clear r5[5:0]<DrvN> */
+ bic r6, r6, #SDRAM_DRVP_MASK /* Clear r5[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r5, r6
+ mov r5, r5, LSL #9
+ mov r5, r5, LSR #26
+ orr r5, r5, r5, LSL #6 /* r5[5:0] = r6[22:17]<LockN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r6, r6, r5
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+glMem2End:
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r8, #SDRAM_DTYPE_DDR2
+ beq ddr1StrengthVal
+
+ddr2StrengthVal:
+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r8, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
+ b setDrvStrength
+ddr1StrengthVal:
+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r8, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
+
+setDrvStrength:
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+ HTOLL(r6,r5)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r6, r4, r6 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+ orr r6, r6, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+ HTOLL(r6,r5)
+
+ bic r6, r6, #SDRAM_WR_EN /* Make register read-only */
+ bic r6, r6, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r6, r8, r6 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DATA_PADS_CAL_REG)
+
+
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
+ /* Get the "sample on reset" register for the DDR frequancy */
+
+#if defined(MV_RUN_FROM_FLASH)
+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
+ ldr r7, = _cpuARMDDRCLK
+ ldr r4, =_start
+ ldr r4, [r4]
+ sub r7, r7, r4
+ ldr r4, = Lrom_start_of_data
+ ldr r4, [r4]
+ add r7, r4, r7
+#else
+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
+ ldr r7, = _cpuARMDDRCLK
+ ldr r4, =_start
+ sub r7, r7, r4
+ add r7, r7, #CFG_MONITOR_BASE
+#endif
+ /* Get the "sample on reset" register for the DDR frequancy */
+ MV_REG_READ_ASM (r4, r5, MPP_SAMPLE_AT_RESET)
+ ldr r5, =MSAR_ARMDDRCLCK_MASK
+ and r5, r4, r5
+#if 0 /* YOTAM TO BE FIX */
+ mov r5, r5, LSR #MSAR_ARMDDRCLCK_OFFS
+#endif
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r6, r8);
+
+ /* Continue if TC90 */
+ ldr r8, =MV_1281_DEV_ID
+ cmp r6, r6
+ beq armClkMsb
+
+ /* Continue if Orion2 */
+ ldr r8, =MV_5281_DEV_ID
+ cmp r6, r8
+#if 0 /* YOTAM TO BE FIX */
+ bne 1f
+#endif
+
+armClkMsb:
+#if 0 /* YOTAM TO BE FIX */
+ tst r4, #MSAR_ARMDDRCLCK_H_MASK
+ beq 1f
+ orr r5, r5, #BIT4
+1:
+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
+ mul r5, r4, r5
+ add r7, r7, r5
+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
+ ldr r5, [r7]
+#endif
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r8, r4, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r8, #SDRAM_DTYPE_DDR2
+ beq ddr1FtdllVal
+
+ddr2FtdllVal:
+ ldr r4, =FTDLL_DDR2_250MHZ
+ ldr r7, =_250MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ
+ ldr r7, =_200MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ
+ ldr r7, =_166MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_133MHZ
+ b setFtdllReg
+
+ddr1FtdllVal:
+ ldr r4, =FTDLL_DDR1_200MHZ
+ ldr r7, =_200MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR1_166MHZ
+ ldr r7, =_166MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR1_133MHZ
+ ldr r7, =_133MHz
+ cmp r5, r7
+ beq setFtdllReg
+ ldr r4, =0
+
+setFtdllReg:
+
+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
+ MV_REG_READ_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
+ orr r8, r8, r4
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
+ bic r8, r8, #1
+ MV_REG_WRITE_ASM (r8, r5, SDRAM_FTDLL_CONFIG_REG)
+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)*/
+
+
+setTimingReg:
+ /* Set default Timing parameters */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne ddr2TimeParam
+
+ddr1TimeParam:
+ ldr r6, =DDR1_TIMING_LOW_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
+ ldr r6, =DDR1_TIMING_HIGH_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
+ b timeParamDone
+
+ddr2TimeParam:
+ ldr r6, =DDR2_TIMING_LOW_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_LOW_REG)
+ ldr r6, =DDR2_TIMING_HIGH_DV
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG)
+
+timeParamDone:
+ /* Open CS[0] window to requested size and enable it. Disable other */
+ /* windows */
+ ldr r6, =SCBAR_BASE_MASK
+ sub r3, r3, #1
+ and r3, r3, r6
+ orr r3, r3, #1 /* Enable bank */
+ MV_REG_WRITE_ASM (r3, r5, SDRAM_SIZE_REG(0))
+ ldr r6, =0
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(1))
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(2))
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(3))
+
+exit_ddrAutoConfig:
+ mov PC, r11 /* r11 is saved link register */
+
+
+/***************************************************************************************/
+/* r4 holds I2C EEPROM address
+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
+ * r8 holds SDRAM various configuration registers value.
+ * r13 holds Link register
+ */
+/**************************/
+_getDensity:
+ mov r13, LR /* Save link register */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
+ bl _i2cRead
+ mov r8, r7 /* r8 save number of rows */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
+ bl _i2cRead
+ add r8, r8, r7 /* r8 = number of rows + number of col */
+
+ mov r7, #0x1
+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
+ bl _i2cRead
+ mul r8, r7, r8
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
+ bl _i2cRead
+ mul r7, r8, r7
+
+ mov PC, r13
+
+/**************************/
+_get_width:
+ mov r13, LR /* Save link register */
+
+ /* Get SDRAM width (SPD offset 13) */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_WIDTH_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ mov PC, r13
+
+/**************************/
+_get_CAL:
+ mov r13, LR /* Save link register */
+
+ /* Set maximum CL supported by DIMM */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
+ bl _i2cRead
+
+ mov PC, r13
+
+/**************************/
+/* R8 - sdram configuration register.
+ * Return value in flag if no-registered then Z-flag is set
+ */
+_is_Registered:
+ mov r13, LR /* Save link register */
+
+ /* Get registered/non registered info from DIMM */
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne regDdr2
+
+regDdr1:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_MODULES_ATTR_OFFSET
+ bl _i2cRead /* result in r7 */
+ tst r7, #0x2
+ b exit
+regDdr2:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_TYPE_INFO_OFFSET
+ bl _i2cRead /* result in r7 */
+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
+ /* or Mini-RDIMM (0x10) */
+exit:
+ mov PC, r13
+
+
+#endif
--- /dev/null
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvDramIfBasicAsm.s
+*
+* DESCRIPTION:
+* Memory full detection and best timing configuration is done in
+* C code. C runtime environment requires a stack. This module API
+* initialize DRAM interface chip select 0 for basic functionality for
+* the use of stack.
+* The module API assumes DRAM information is stored in I2C EEPROM reside
+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
+* internal data structure is assumed to be orgenzied in common DRAM
+* vendor SPD structure.
+* NOTE: DFCDL values are assumed to be already initialized prior to
+* this module API activity.
+*
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+/* includes */
+#define MV_ASMLANGUAGE
+#include "mvOsAsm.h"
+#include "mvSysHwConfig.h"
+#include "mvDramIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "mvCpuIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "pci/mvPciRegs.h"
+#include "mvCtrlEnvSpec.h"
+#include "mvCtrlEnvAsm.h"
+#include "cpu/mvCpuArm.h"
+#include "mvCommon.h"
+
+/* defines */
+
+/* locals */
+.data
+.globl _mvDramIfConfig
+
+.text
+
+/*******************************************************************************
+* _mvDramIfConfig - Basic DRAM interface initialization.
+*
+* DESCRIPTION:
+* The function will initialize the following DRAM parameters using the
+* values prepared by mvDramIfDetect routine. Values are located
+* in predefined registers.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+
+_mvDramIfConfig:
+
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_s
+save_on_stack:
+ stmdb sp!, {r1, r2, r3, r4, r7, r11}
+no_stack_s:
+
+ /* 1) Write to SDRAM coniguration register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
+ str r4, [r1]
+
+ /* 2) Write Dunit control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
+ str r4, [r1]
+
+ /* 3) Write SDRAM address control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
+ str r4, [r1]
+
+ /* 4) Write SDRAM bank 0 size register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0))
+ str r4, [r1]
+
+ /* 5) Write SDRAM open pages control register */
+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
+ str r4, [r1]
+
+ /* 6) Write SDRAM timing Low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* 7) Write SDRAM timing High register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to it\92s new value. */
+
+ /* 8.1 write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll1:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll1
+
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
+ str r4, [r1]
+
+ /* 8.4 Make the Dunit write the DRAM its new mode */
+ mov r4, #0x3 /* Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll2:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll2
+
+#ifndef DB_FPGA
+ /* Config DDR2 registers (Extended mode, ODTs and pad calibration) */
+ MV_REG_READ_ASM (r4, r1, SDRAM_CONFIG_REG)
+ tst r4, #SDRAM_DTYPE_DDR2
+ beq _extModeODTEnd
+#endif /* DB_FPGA */
+
+ /* 9) Write SDRAM Extended mode register This operation should be */
+ /* done for each memory bank */
+ /* write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll3:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll3
+
+ /* Now its safe to write new value to SDRAM Extended Mode register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
+ str r4, [r1]
+
+ /* Go over each of the Banks */
+ ldr r3, =0 /* r3 = DRAM bank Num */
+
+extModeLoop:
+ /* Set the SDRAM Operation Control to each of the DRAM banks */
+ mov r2, r3 /* Do not swap the bank counter value */
+ MV_REG_WRITE_ASM (r2, r1, SDRAM_OPERATION_CTRL_REG)
+
+ /* Make the Dunit write the DRAM its new mode */
+ mov r4, #0x4 /* Extended Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll4:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll4
+#ifndef DB_FPGA
+ add r3, r3, #1
+ cmp r3, #4 /* 4 = Number of banks */
+ bne extModeLoop
+
+extModeEnd:
+ /* Config DDR2 On Die Termination (ODT) registers */
+ /* Write SDRAM DDR2 ODT control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 ODT control high register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 Dunit ODT control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
+ str r4, [r1]
+
+#endif /* DB_FPGA */
+_extModeODTEnd:
+#ifndef DB_FPGA
+ /* Implement Guideline (GL# MEM-2) P_CAL Automatic Calibration */
+ /* Does Not Work for Address/Control and Data Pads. */
+ /* Relevant for: 88F5181-A1/B0 and 88F5281-A0 */
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r3, r1);
+ /* Read device revision */
+ MV_CTRL_REV_GET_ASM(r2, r1);
+
+ /* Continue if OrionN */
+ ldr r1, =MV_5180_DEV_ID
+ cmp r3, r1
+ bne 1f
+ b glMem2End
+1:
+ /* Continue if Orion1 and device revision B1 */
+ ldr r1, =MV_5181_DEV_ID
+ cmp r3, r1
+ bne 1f
+
+ cmp r2, #MV_5181_B1_REV
+ bge glMem2End
+ b glMem2Start
+1:
+
+ /* Orion NAS */
+ ldr r1, =MV_5182_DEV_ID
+ cmp r3, r1
+ beq glMem2Start
+
+ /* Orion NAS */
+ ldr r1, =MV_5082_DEV_ID
+ cmp r3, r1
+ beq glMem2Start
+
+ /* Orion Shark */
+ ldr r1, =MV_8660_DEV_ID
+ cmp r3, r1
+ beq glMem2Start
+
+ b glMem2End
+
+glMem2Start:
+
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r2, r3, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r2, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r3
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
+ orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r3, r3, r1
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+ /* Set Bit [31] to make the register writable */
+ orr r2, r3, #SDRAM_WR_EN
+
+ MV_REG_WRITE_ASM (r2, r1, SDRAM_DATA_PADS_CAL_REG)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_TUNE_EN /* Disable auto calibration */
+ bic r3, r3, #SDRAM_DRVN_MASK /* Clear r1[5:0]<DrvN> */
+ bic r3, r3, #SDRAM_DRVP_MASK /* Clear r1[11:6]<DrvP> */
+
+ /* Get the final N locked value of driving strength [22:17] */
+ mov r1, r3
+ mov r1, r1, LSL #9
+ mov r1, r1, LSR #26
+ orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
+
+ /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
+ orr r3, r3, r1
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+glMem2End:
+
+
+ /* Implement Guideline (GL# MEM-3) Drive Strength Value */
+ /* Relevant for: 88F5181-A1/B0/B1, 88F5281-A0/B0/C/D, 88F5182, */
+ /* 88F5082, 88F5181L, 88F6082/L, 88F6183, 88F6183L */
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r2, r1, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r2, #SDRAM_DTYPE_DDR2
+ beq ddr1StrengthVal
+
+ddr2StrengthVal:
+ ldr r4, =DDR2_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r2, =DDR2_DATA_PAD_STRENGTH_TYPICAL_DV
+ b setDrvStrength
+ddr1StrengthVal:
+ ldr r4, =DDR1_ADDR_CTRL_PAD_STRENGTH_TYPICAL_DV
+ ldr r2, =DDR1_DATA_PAD_STRENGTH_TYPICAL_DV
+
+setDrvStrength:
+ /* DDR SDRAM Address/Control Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+ HTOLL(r3,r1)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r3, r4, r3 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_ADDR_CTRL_PADS_CAL_REG)
+
+
+ /* DDR SDRAM Data Pads Calibration */
+ MV_REG_READ_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+ orr r3, r3, #SDRAM_WR_EN /* Make register writeable */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+ HTOLL(r3,r1)
+
+ bic r3, r3, #SDRAM_WR_EN /* Make register read-only */
+ bic r3, r3, #SDRAM_PRE_DRIVER_STRENGTH_MASK
+ orr r3, r2, r3 /* Set default value for DDR */
+
+ MV_REG_WRITE_ASM (r3, r1, SDRAM_DATA_PADS_CAL_REG)
+
+#if !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L)
+ /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
+ /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0/C/D, 88F5182 */
+ /* 88F5082, 88F5181L, 88F6082/L */
+
+ /* Calc the absolute address of the _cpuARMDDRCLK[] in the boot flash */
+ ldr r7, = _cpuARMDDRCLK
+ ldr r4, =_start
+ sub r7, r7, r4
+ add r7, r7, #CFG_MONITOR_BASE
+
+ /* Get the "sample on reset" register for the DDR frequancy */
+ MV_REG_READ_ASM (r4, r1, MPP_SAMPLE_AT_RESET)
+ ldr r1, =MSAR_ARMDDRCLCK_MASK
+ and r1, r4, r1
+#if 0 /* YOTAM TO BE FIX */
+ mov r1, r1, LSR #MSAR_ARMDDRCLCK_OFFS
+#endif
+
+ /* Read device ID */
+ MV_CTRL_MODEL_GET_ASM(r3, r2);
+
+ /* Continue if TC90 */
+ ldr r2, =MV_1281_DEV_ID
+ cmp r3, r2
+ beq armClkMsb
+
+ /* Continue if Orion2 */
+ ldr r2, =MV_5281_DEV_ID
+ cmp r3, r2
+#if 0 /* YOTAM TO BE FIX */
+ bne 1f
+#endif
+
+armClkMsb:
+#if 0 /* YOTAM TO BE FIX */
+ tst r4, #MSAR_ARMDDRCLCK_H_MASK
+ beq 1f
+ orr r1, r1, #BIT4
+1:
+ ldr r4, =MV_CPU_ARM_CLK_ELM_SIZE
+ mul r1, r4, r1
+ add r7, r7, r1
+ add r7, r7, #MV_CPU_ARM_CLK_DDR_OFF
+ ldr r1, [r7]
+#endif
+
+ /* Get SDRAM Config value */
+ MV_REG_READ_ASM (r2, r4, SDRAM_CONFIG_REG)
+
+ /* Get DIMM type */
+ tst r2, #SDRAM_DTYPE_DDR2
+ beq ddr1FtdllVal
+
+ddr2FtdllVal:
+ ldr r2, =MV_5281_DEV_ID
+ cmp r3, r2
+ bne 2f
+ MV_CTRL_REV_GET_ASM(r3, r2)
+ cmp r3, #MV_5281_D0_REV
+ beq orin2_d0_ddr2_ftdll_val
+ cmp r3, #MV_5281_D1_REV
+ beq orin2_d1_ddr2_ftdll_val
+ cmp r3, #MV_5281_D2_REV
+ beq orin2_d1_ddr2_ftdll_val
+ b ddr2_default_val
+
+/* Set Orion 2 D1 ftdll values for DDR2 */
+orin2_d1_ddr2_ftdll_val:
+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D1
+ ldr r7, =_250MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D1
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ b ddr2_default_val
+
+/* Set Orion 2 D0 ftdll values for DDR2 */
+orin2_d0_ddr2_ftdll_val:
+ ldr r4, =FTDLL_DDR2_250MHZ_5281_D0
+ ldr r7, =_250MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ_5281_D0
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ_5281_D0
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ b ddr2_default_val
+2:
+ ldr r2, =MV_5182_DEV_ID
+ cmp r3, r2
+ bne 3f
+
+/* Set Orion nas ftdll values for DDR2 */
+orin_nas_ftdll_val:
+ ldr r4, =FTDLL_DDR2_166MHZ_5182
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+/* default values for all other devices */
+3:
+ddr2_default_val:
+ ldr r4, =FTDLL_DDR2_250MHZ
+ ldr r7, =_250MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_200MHZ
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_166MHZ
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR2_133MHZ
+ ldr r7, =_133MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =0
+ b setFtdllReg
+
+ddr1FtdllVal:
+ ldr r2, =MV_5281_DEV_ID
+ cmp r3, r2
+ bne 2f
+ MV_CTRL_REV_GET_ASM(r3, r2)
+ cmp r3, #MV_5281_D0_REV
+ bge orin2_ddr1_ftdll_val
+ b ddr1_default_val
+
+/* Set Orion 2 D0 and above ftdll values for DDR1 */
+orin2_ddr1_ftdll_val:
+ ldr r4, =FTDLL_DDR1_200MHZ_5281_D0
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+ ldr r4, =FTDLL_DDR1_166MHZ_5281_D0
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+ b ddr1_default_val
+2:
+ ldr r2, =MV_5181_DEV_ID
+ cmp r3, r2
+ bne 3f
+ MV_CTRL_REV_GET_ASM(r3, r2)
+ cmp r3, #MV_5181_B1_REV
+ bge orin1_ddr1_ftdll_val
+ b ddr1_default_val
+
+/* Set Orion 1 ftdll values for DDR1 */
+orin1_ddr1_ftdll_val:
+ ldr r4, =FTDLL_DDR1_166MHZ_5181_B1
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+3:
+ddr1_default_val:
+ ldr r4, =FTDLL_DDR1_133MHZ
+ ldr r7, =_133MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+ ldr r4, =FTDLL_DDR1_166MHZ
+ ldr r7, =_166MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+ ldr r4, =FTDLL_DDR1_200MHZ
+ ldr r7, =_200MHz
+ cmp r1, r7
+ beq setFtdllReg
+
+ ldr r4, =0
+
+setFtdllReg:
+
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
+ HTOLL(r4,r1)
+ bic r4, r4, #1
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_FTDLL_CONFIG_REG)
+
+#endif /* !defined(MV_88W8660) && !defined(MV_88F6183) && !defined(MV_88F6183L) */
+#endif /* DB_FPGA */
+
+restoreTmpRegs:
+ /* Restore the registers we used to save the DDR detect values */
+
+ ldr r4, =DRAM_BUF_REG0_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG0)
+
+ ldr r4, =DRAM_BUF_REG1_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG1)
+
+ ldr r4, =DRAM_BUF_REG2_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG2)
+
+ ldr r4, =DRAM_BUF_REG3_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG3)
+
+ ldr r4, =DRAM_BUF_REG4_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG4)
+
+ ldr r4, =DRAM_BUF_REG5_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG5)
+
+ ldr r4, =DRAM_BUF_REG6_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG6)
+
+ ldr r4, =DRAM_BUF_REG7_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG7)
+
+ ldr r4, =DRAM_BUF_REG8_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG8)
+
+ ldr r4, =DRAM_BUF_REG9_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG9)
+
+ ldr r4, =DRAM_BUF_REG10_DV
+ MV_REG_WRITE_ASM (r4, r1, DRAM_BUF_REG10)
+
+
+ /* Restore registers */
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_l
+load_from_stack:
+ ldmia sp!, {r1, r2, r3, r4, r7, r11}
+no_stack_l:
+
+ mov pc, lr
+
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.4\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+#define _ASMLANGUAGE
+#define MV_ASMLANGUAGE
+#include "mvSysHwConfig.h"
+#include "mvOsAsm.h"
+#include "boardEnv/mvBoardEnvSpec.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "mvDramIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "ctrlEnv/mvCtrlEnvAsm.h"
+#include "mvCommon.h"
+
+/* defines */
+
+#if defined(MV_STATIC_DRAM_ON_BOARD)
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/******************************************************************************
+*
+*
+*
+*
+*******************************************************************************/
+#if defined(DB_MV78XX0) || defined(DB_MV88F632X)
+/* DDR2 boards 512MB 333MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43048C30 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000FFFF /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125441 /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A29 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000E80F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#elif defined(RD_MV78XX0_AMC)
+/* On board DDR2 512MB 400MHz CL5 */
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43008C30 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x23135441 /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A32 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#elif defined(RD_MV78XX0_H3C)
+/* DDR2 boards 512MB 333MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x1ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43048a25 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x00000088 /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A22 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#elif defined(RD_MV78XX0_PCAC)
+/* DDR2 boards 256MB 200MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x0ffffff1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43000a25 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000652 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x38543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F07F /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x000000DD /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x2202444e /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000822 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x84210000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000EB0F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000040 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+
+#else
+/* DDR2 MV88F6281 boards 256MB 400MHz */
+#define STATIC_SDRAM0_BANK0_SIZE 0x0FFFFFF1 /* 0x1504 */
+#define STATIC_SDRAM_CONFIG 0x43000c30 /* 0x1400 */
+#define STATIC_SDRAM_MODE 0x00000C52 /* 0x141c */
+#define STATIC_DUNIT_CTRL_LOW 0x39543000 /* 0x1404 */
+#define STATIC_DUNIT_CTRL_HI 0x0000F1FF /* 0x1424 */
+#define STATIC_SDRAM_ADDR_CTRL 0x000000cc /* 0x1410 */
+#define STATIC_SDRAM_TIME_CTRL_LOW 0x22125451 /* 0x1408 */
+#define STATIC_SDRAM_TIME_CTRL_HI 0x00000A33 /* 0x140c */
+#define STATIC_SDRAM_ODT_CTRL_LOW 0x003C0000 /* 0x1494 */
+#define STATIC_SDRAM_ODT_CTRL_HI 0x00000000 /* 0x1498 */
+#define STATIC_SDRAM_DUNIT_ODT_CTRL 0x0000F80F /* 0x149c */
+#define STATIC_SDRAM_EXT_MODE 0x00000042 /* 0x1420 */
+#define STATIC_SDRAM_DDR2_TIMING_LO 0x00085520 /* 0x1428 */
+#define STATIC_SDRAM_DDR2_TIMING_HI 0x00008552 /* 0x147C */
+#endif /* MV78XX0 */
+
+ .globl _mvDramIfStaticInit
+_mvDramIfStaticInit:
+
+ mov r11, LR /* Save link register */
+ mov r10, r2
+
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+ orr r6, r6, #BIT4 /* Enable 2T mode */
+ bic r6, r6, #BIT6 /* clear ctrlPos */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+#endif
+
+ /*DDR SDRAM Initialization Control */
+ ldr r6, =DSICR_INIT_EN
+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+ and r6, r6, #DSICR_INIT_EN
+ cmp r6, #0
+ bne 2b
+
+ /* If we boot from NAND jump to DRAM address */
+ mov r5, #1
+ ldr r6, =dramBoot1
+ str r5, [r6] /* We started executing from DRAM */
+
+ ldr r6, dramBoot1
+ cmp r6, #0
+ bne 1f
+
+ /* set all dram windows to 0 */
+ mov r6, #0
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,1))
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,2))
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,3))
+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE
+ MV_REG_WRITE_ASM(r6, r5, SDRAM_SIZE_REG(0,0))
+
+
+ /* set all dram configuration in temp registers */
+ ldr r6, = STATIC_SDRAM0_BANK0_SIZE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG0)
+ ldr r6, = STATIC_SDRAM_CONFIG
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG1)
+ ldr r6, = STATIC_SDRAM_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG2)
+ ldr r6, = STATIC_DUNIT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG3)
+ ldr r6, = STATIC_SDRAM_ADDR_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG4)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG5)
+ ldr r6, = STATIC_SDRAM_TIME_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_LOW
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG7)
+ ldr r6, = STATIC_SDRAM_ODT_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG8)
+ ldr r6, = STATIC_SDRAM_DUNIT_ODT_CTRL
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG9)
+ ldr r6, = STATIC_SDRAM_EXT_MODE
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG10)
+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_LO
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG11)
+ ldr r6, = STATIC_SDRAM_DDR2_TIMING_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG12)
+#ifndef MV_NAND_BOOT
+ ldr r6, = STATIC_DUNIT_CTRL_HI
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG13)
+#endif
+
+ ldr sp,=0
+ bl _mvDramIfConfig
+ ldr r0, =0
+#ifdef MV78XX0
+ bl _mvDramIfEccMemInit
+#endif
+1:
+ mov r2, r10
+ mov PC, r11 /* r11 is saved link register */
+
+#else /* #if defined(MV_STATIC_DRAM_ON_BOARD) */
+
+.globl dramBoot1
+dramBoot1:
+ .word 0
+
+/*******************************************************************************
+* mvDramIfBasicInit - Basic initialization of DRAM interface
+*
+* DESCRIPTION:
+* The function will initialize the DRAM for basic usage. The function
+* will use the TWSI assembly API to extract DIMM parameters according
+* to which DRAM interface will be initialized.
+* The function referes to the following DRAM parameters:
+* 1) DIMM is registered or not.
+* 2) DIMM width detection.
+* 3) DIMM density.
+*
+* INPUT:
+* r3 - required size for initial DRAM.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+* Note:
+* r4 holds I2C EEPROM address
+* r5 holds SDRAM register base address
+* r7 holds returned values
+* r8 holds SDRAM various configuration registers value.
+* r11 holds return function address.
+*******************************************************************************/
+/* Setting the offsets of the I2C registers */
+#define DIMM_TYPE_OFFSET 2
+#define NUM_OF_ROWS_OFFSET 3
+#define NUM_OF_COLS_OFFSET 4
+#define NUM_OF_RANKS 5
+#define DIMM_CONFIG_TYPE 11
+#define SDRAM_WIDTH_OFFSET 13
+#define NUM_OF_BANKS_OFFSET 17
+#define SUPPORTED_CL_OFFSET 18
+#define DIMM_TYPE_INFO_OFFSET 20 /* DDR2 only */
+#define SDRAM_MODULES_ATTR_OFFSET 21
+#define RANK_SIZE_OFFSET 31
+
+#define DRAM_DEV_DENSITY_128M 128
+#define DRAM_DEV_DENSITY_256M 256
+#define DRAM_DEV_DENSITY_512M 512
+#define DRAM_DEV_DENSITY_1G 1024
+#define DRAM_DEV_DENSITY_2G 2048
+
+#define DRAM_RANK_DENSITY_128M 0x20
+#define DRAM_RANK_DENSITY_256M 0x40
+#define DRAM_RANK_DENSITY_512M 0x80
+#define DRAM_RANK_DENSITY_1G 0x1
+#define DRAM_RANK_DENSITY_2G 0x2
+
+ .globl _mvDramIfBasicInit
+ .extern _i2cInit
+_mvDramIfBasicInit:
+
+ mov r11, LR /* Save link register */
+
+ /* Set Dunit high control register */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
+#ifdef MV78XX0
+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
+#endif
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
+
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+ orr r6, r6, #BIT4 /* Enable 2T mode */
+ bic r6, r6, #BIT6 /* clear ctrlPos */
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+#endif
+
+ /*DDR SDRAM Initialization Control */
+ ldr r6, =DSICR_INIT_EN
+ MV_REG_WRITE_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+2: MV_REG_READ_ASM (r6, r1, DDR_SDRAM_INIT_CTRL_REG)
+ and r6, r6, #DSICR_INIT_EN
+ cmp r6, #0
+ bne 2b
+
+ mov r5, #1
+ ldr r8, =dramBoot1
+ str r5, [r8] /* We started executing from DRAM */
+
+ /* If we boot from NAND jump to DRAM address */
+ ldr r8, dramBoot1
+ cmp r8, #0
+ movne pc, r11
+
+ bl _i2cInit /* Initialize TWSI master */
+
+ /* Check if we have more then 1 dimm */
+ ldr r6, =0
+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
+#ifdef MV78XX0
+ bl _is_Second_Dimm_Exist
+ beq single_dimm
+ ldr r6, =1
+ MV_REG_WRITE_ASM (r6, r1, DRAM_BUF_REG14)
+single_dimm:
+ bl _i2cInit /* Initialize TWSI master */
+#endif
+
+ /* Get default SDRAM Config values */
+ MV_REG_READ_ASM (r8, r5, SDRAM_CONFIG_REG)
+
+ /* Get registered/non registered info from DIMM */
+ bl _is_Registered
+ beq nonRegistered
+
+setRegistered:
+ orr r8, r8, #SDRAM_REGISTERED /* Set registered bit(17) */
+nonRegistered:
+#ifdef MV78XX0
+ /* Get ECC/non ECC info from DIMM */
+ bl _is_Ecc
+ beq setConfigReg
+
+setEcc:
+ orr r8, r8, #SDRAM_ECC_EN /* Set ecc bit(18) */
+#endif
+setConfigReg:
+ MV_REG_WRITE_ASM (r8, r5, DRAM_BUF_REG1)
+
+ /* Set maximum CL supported by DIMM */
+ bl _get_CAL
+
+ /* r7 is DIMM supported CAS (e.g: 3 --> 0x1C) */
+ clz r6, r7
+ rsb r6, r6, #31 /* r6 = the bit number of MAX CAS supported */
+
+casDdr2:
+ ldr r7, =0x41 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x53 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x32 /* Assuming MAX CL = 3 */
+ cmp r6, #3 /* If CL = 3 break */
+ beq casDdr2Cont
+
+ ldr r7, =0x53 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x65 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x42 /* Assuming MAX CL = 4 */
+ cmp r6, #4 /* If CL = 4 break */
+ beq casDdr2Cont
+
+ ldr r7, =0x65 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x77 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x52 /* Assuming MAX CL = 5 */
+ cmp r6, #5 /* If CL = 5 break */
+ beq casDdr2Cont
+
+ ldr r7, =0x77 /* stBurstInDel|stBurstOutDel field value */
+ ldr r3, =0x89 /* stBurstInDel|stBurstOutDel registered value*/
+ ldr r8, =0x62 /* Assuming MAX CL = 6 */
+ cmp r6, #6 /* If CL = 5 break */
+ beq casDdr2Cont
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig /* This is an error !! */
+casDdr2Cont:
+
+ /* Get default SDRAM Mode values */
+ MV_REG_READ_ASM (r6, r5, SDRAM_MODE_REG)
+ bic r6, r6, #(BIT6 | BIT5 | BIT4) /* Clear CL filed */
+ orr r6, r6, r8
+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG2)
+
+ /* Set Dunit control register according to max CL detected */
+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG1)
+ tst r6, #SDRAM_REGISTERED
+ beq setDunitReg
+ mov r7, r3
+
+setDunitReg:
+#ifdef MV78XX0
+ /* Set SDRAM Extended Mode register for double DIMM */
+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
+
+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
+ ldr r5, =MSAR_SYSCLCK_MASK
+ and r4, r4, r5
+ ldr r5, =MSAR_SYSCLCK_333
+ cmp r4, r5
+ ble Clock333
+ add r7, r7, #0x10
+Clock333:
+#endif
+
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_REG)
+ bic r6, r6, #(0xff << 20) /* Clear SBout and SBin */
+ orr r6, r6, #BIT4 /* Enable 2T mode */
+ bic r6, r6, #BIT6 /* clear ctrlPos */
+ orr r6, r6, r7, LSL #20
+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG3)
+
+ /* Set Dunit high control register */
+ MV_REG_READ_ASM (r6, r5, SDRAM_DUNIT_CTRL_HI_REG)
+ orr r6, r6, #BIT7 /* SDRAM__D2P_EN */
+ orr r6, r6, #BIT8 /* SDRAM__P2D_EN */
+#ifdef MV78XX0
+ orr r6, r6, #BIT9 /* SDRAM__ADD_HALF_FCC_EN */
+ orr r6, r6, #BIT10 /* SDRAM__PUP_ZERO_SKEW_EN */
+ orr r6, r6, #BIT11 /* SDRAM__WR_MASH_DELAY_EN */
+#endif
+ MV_REG_WRITE_ASM (r6, r5, DRAM_BUF_REG13)
+
+ /* DIMM density configuration*/
+ /* Density = (1 << (rowNum + colNum)) * dramWidth * dramBankNum */
+Density:
+ /* Get bank 0 and 1 density */
+ ldr r6, =0
+ bl _getDensity
+
+ mov r8, r7
+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */
+ /* For example 0x10000000 --> 0x1000 */
+
+ mov r3, #(SDRAM_DSIZE_256Mb(0) | SDRAM_DSIZE_256Mb(1))
+ cmp r8, #DRAM_DEV_DENSITY_256M
+ beq get_bank_2_density
+
+ mov r3, #(SDRAM_DSIZE_512Mb(0) | SDRAM_DSIZE_512Mb(1))
+ cmp r8, #DRAM_DEV_DENSITY_512M
+ beq get_bank_2_density
+
+ mov r3, #(SDRAM_DSIZE_1Gb(0) | SDRAM_DSIZE_1Gb(1))
+ cmp r8, #DRAM_DEV_DENSITY_1G
+ beq get_bank_2_density
+
+ mov r3, #(SDRAM_DSIZE_2Gb(0) | SDRAM_DSIZE_2Gb(1))
+ cmp r8, #DRAM_DEV_DENSITY_2G
+ beq get_bank_2_density
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+get_bank_2_density:
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne get_width
+
+ /* Get bank 2 and 3 density */
+ ldr r6, =2
+ bl _getDensity
+
+ mov r8, r7
+ mov r8, r8, LSR #20 /* Move density 20 bits to the right */
+ /* For example 0x10000000 --> 0x1000 */
+
+ orr r3, r3, #(SDRAM_DSIZE_256Mb(2) | SDRAM_DSIZE_256Mb(3))
+ cmp r8, #DRAM_DEV_DENSITY_256M
+ beq get_width
+
+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
+ orr r3, r3, #(SDRAM_DSIZE_512Mb(2) | SDRAM_DSIZE_512Mb(3))
+ cmp r8, #DRAM_DEV_DENSITY_512M
+ beq get_width
+
+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
+ orr r3, r3, #(SDRAM_DSIZE_1Gb(2) | SDRAM_DSIZE_1Gb(3))
+ cmp r8, #DRAM_DEV_DENSITY_1G
+ beq get_width
+
+ and r3, r3, #~(SDRAM_DSIZE_MASK(2) | SDRAM_DSIZE_MASK(3))
+ orr r3, r3, #(SDRAM_DSIZE_2Gb(2) | SDRAM_DSIZE_2Gb(3))
+ cmp r8, #DRAM_DEV_DENSITY_2G
+ beq get_width
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+ /* Get SDRAM width */
+get_width:
+ /* Get bank 0 and 1 width */
+ ldr r6, =0
+ bl _get_width
+
+ cmp r7, #8 /* x8 devices */
+ beq get_bank_2_width
+
+ orr r3, r3, #(SDRAM_ADDRSEL_X16(0) | SDRAM_ADDRSEL_X16(1)) /* x16 devices */
+ cmp r7, #16
+ beq get_bank_2_width
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+get_bank_2_width:
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne densCont
+
+ /* Get bank 2 and 3 width */
+ ldr r6, =2
+ bl _get_width
+
+ cmp r7, #8 /* x8 devices */
+ beq densCont
+
+ orr r3, r3, #(SDRAM_ADDRSEL_X16(2) | SDRAM_ADDRSEL_X16(3)) /* x16 devices */
+ cmp r7, #16
+ beq densCont
+
+ /* This is an error. return */
+ b exit_ddrAutoConfig
+
+densCont:
+ MV_REG_WRITE_ASM (r3, r5, DRAM_BUF_REG4)
+
+ /* Set SDRAM timing control low register */
+ ldr r4, =SDRAM_TIMING_CTRL_LOW_REG_DEFAULT
+ /* MV_REG_READ_ASM (r4, r5, SDRAM_TIMING_CTRL_LOW_REG) */
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG5)
+
+ /* Set SDRAM timing control high register */
+ ldr r6, =SDRAM_TIMING_CTRL_HIGH_REG_DEFAULT
+
+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
+ ldr r5, =MSAR_SYSCLCK_MASK
+ and r4, r4, r5
+ ldr r5, =MSAR_SYSCLCK_333
+ cmp r4, r5
+ blt timingHighClock333
+ orr r6, r6, #BIT9
+
+timingHighClock333:
+ /* MV_REG_READ_ASM (r6, r5, SDRAM_TIMING_CTRL_HIGH_REG) */
+ MV_REG_WRITE_ASM(r6, r5, DRAM_BUF_REG6)
+
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne single_dimm_odt
+
+ /* Set SDRAM ODT control low register for double DIMM*/
+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
+
+ /* Set DUNIT ODT control register for double DIMM */
+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
+
+#ifdef MV78XX0
+ /* Set SDRAM Extended Mode register for double DIMM */
+ /* Check DRAM frequency for more then 267MHz set ODT Rtt to 50ohm */
+
+ MV_REG_READ_ASM (r4, r5, CPU_RESET_SAMPLE_L_REG)
+ ldr r5, =MSAR_SYSCLCK_MASK
+ and r4, r4, r5
+ ldr r5, =MSAR_SYSCLCK_267
+ cmp r4, r5
+ beq slow_dram_clock_rtt
+ ldr r5, =MSAR_SYSCLCK_300
+ cmp r4, r5
+ beq slow_dram_clock_rtt
+ ldr r5, =MSAR_SYSCLCK_333
+ cmp r4, r5
+ beq fast_dram_clock_rtt
+ ldr r5, =MSAR_SYSCLCK_400
+ cmp r4, r5
+ beq fast_dram_clock_rtt
+
+ b slow_dram_clock_rtt
+
+fast_dram_clock_rtt:
+ ldr r4, =DDR_SDRAM_EXT_MODE_FAST_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
+ b odt_config_end
+#endif
+slow_dram_clock_rtt:
+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_CS2_CS3_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
+ b odt_config_end
+
+single_dimm_odt:
+ /* Set SDRAM ODT control low register */
+ ldr r4, =DDR2_ODT_CTRL_LOW_CS0_CS1_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG7)
+
+ /* Set DUNIT ODT control register */
+ ldr r4, =DDR2_DUNIT_ODT_CTRL_CS0_CS1_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG9)
+
+ /* Set SDRAM Extended Mode register */
+ ldr r4, =DDR_SDRAM_EXT_MODE_CS0_CS1_DV
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG10)
+
+odt_config_end:
+ /* SDRAM ODT control high register is left as default */
+ MV_REG_READ_ASM (r4, r5, DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG8)
+
+ /*Read CL and set the DDR2 registers accordingly */
+ MV_REG_READ_ASM (r6, r5, DRAM_BUF_REG2)
+ and r6, r6, #SDRAM_CL_MASK
+ mov r4, r6
+ orr r4, r4, r6, LSL #4
+ orr r4, r4, r6, LSL #8
+ orr r4, r4, r6, LSL #12
+ mov r5, #0x30000
+ add r4, r4, r5
+ sub r4, r4, #0x30
+ /* Set SDRAM Ddr2 Timing Low register */
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG11)
+
+ /* Set SDRAM Ddr2 Timing High register */
+ mov r4, r4, LSR #4
+ MV_REG_WRITE_ASM(r4, r5, DRAM_BUF_REG12)
+
+timeParamDone:
+ /* Close all windows */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+ and r6, r6,#~SCSR_SIZE_MASK
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+
+ /* Set sdram bank 0 size and enable it */
+ ldr r6, =0
+ bl _mvDramIfGetDimmSizeFromSpd
+#ifdef MV78XX0
+ /* Check DRAM width */
+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
+ ldr r5, =SDRAM_DWIDTH_MASK
+ and r4, r4, r5
+ ldr r5, =SDRAM_DWIDTH_64BIT
+ cmp r4, r5
+ beq dram_64bit_width
+ /* Utilize only 32bit width */
+ mov r8, r8, LSR #1
+#else
+ /* Utilize only 16bit width */
+ mov r8, r8, LSR #2
+#endif
+dram_64bit_width:
+ /* Update first dimm size return value R8 */
+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,0))
+ ldr r6, =~SCSR_SIZE_MASK
+ and r5, r5, r6
+ orr r5, r5, r8
+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,0))
+
+ /* Clear bank 2 size */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ and r6, r6,#~SCSR_SIZE_MASK
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+
+ /* Check for second dimm */
+ MV_REG_READ_ASM (r6, r1, DRAM_BUF_REG14)
+ cmp r6, #1
+ bne defualt_order
+
+ /* Set sdram bank 2 size */
+ ldr r6, =2
+ bl _mvDramIfGetDimmSizeFromSpd
+#ifdef MV78XX0
+ /* Check DRAM width */
+ MV_REG_READ_ASM (r4, r5, SDRAM_CONFIG_REG)
+ ldr r5, =SDRAM_DWIDTH_MASK
+ and r4, r4, r5
+ ldr r5, =SDRAM_DWIDTH_64BIT
+ cmp r4, r5
+ beq dram_64bit_width2
+ /* Utilize only 32bit width */
+ mov r8, r8, LSR #1
+#else
+ /* Utilize only 16bit width */
+ mov r8, r8, LSR #2
+#endif
+dram_64bit_width2:
+ /* Update first dimm size return value R8 */
+ MV_REG_READ_ASM (r5, r6, SDRAM_SIZE_REG(0,2))
+ ldr r6, =~SCSR_SIZE_MASK
+ and r5, r5, r6
+ orr r5, r5, r8
+ MV_REG_WRITE_ASM(r5, r8, SDRAM_SIZE_REG(0,2))
+
+ /* Close windows 1 and 3 */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,1))
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+ and r6, r6,#~1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,3))
+
+ /* Check dimm size for setting dram bank order */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ MV_REG_READ_ASM (r4, r5, SDRAM_SIZE_REG(0,2))
+ and r6, r6,#SCSR_SIZE_MASK
+ and r4, r4,#SCSR_SIZE_MASK
+ cmp r6, r4
+ bge defualt_order
+
+ /* Bank 2 is biger then bank 0 */
+ ldr r6,=0
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_BASE_ADDR_REG(0,2))
+
+ /* Open win 2 */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+ orr r6, r6,#1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,2))
+
+ ldr sp,=0
+ bl _mvDramIfConfig
+#ifdef MV78XX0
+ /* Init ECC on CS 2 */
+ ldr r0, =2
+ bl _mvDramIfEccMemInit
+#endif
+ mov PC, r11 /* r11 is saved link register */
+
+defualt_order:
+
+ /* Open win 0 */
+ MV_REG_READ_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+ orr r6, r6,#1
+ MV_REG_WRITE_ASM (r6, r5, SDRAM_SIZE_REG(0,0))
+
+ ldr sp,=0
+ bl _mvDramIfConfig
+#ifdef MV78XX0
+ /* Init ECC on CS 0 */
+ ldr r0, =0
+ bl _mvDramIfEccMemInit
+#endif
+exit_ddrAutoConfig:
+ mov PC, r11 /* r11 is saved link register */
+
+
+/***************************************************************************************/
+/* r4 holds I2C EEPROM address
+ * r7 holds I2C EEPROM offset parameter for i2cRead and its --> returned value
+ * r8 holds SDRAM various configuration registers value.
+ * r13 holds Link register
+ */
+/**************************/
+_getDensity:
+ mov r13, LR /* Save link register */
+
+ /* Read SPD rank size from DIMM0 */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+
+ cmp r6, #0
+ beq 1f
+
+ /* Read SPD rank size from DIMM1 */
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
+
+1:
+ mov r7, #NUM_OF_ROWS_OFFSET /* offset 3 */
+ bl _i2cRead
+ mov r8, r7 /* r8 save number of rows */
+
+ mov r7, #NUM_OF_COLS_OFFSET /* offset 4 */
+ bl _i2cRead
+ add r8, r8, r7 /* r8 = number of rows + number of col */
+
+ mov r7, #0x1
+ mov r8, r7, LSL r8 /* r8 = (1 << r8) */
+
+ mov r7, #SDRAM_WIDTH_OFFSET /* offset 13 */
+ bl _i2cRead
+ mul r8, r7, r8
+
+ mov r7, #NUM_OF_BANKS_OFFSET /* offset 17 */
+ bl _i2cRead
+ mul r7, r8, r7
+
+ mov PC, r13
+
+/**************************/
+_get_width:
+ mov r13, LR /* Save link register */
+
+ /* Read SPD rank size from DIMM0 */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+
+ cmp r6, #0
+ beq 1f
+
+ /* Read SPD rank size from DIMM1 */
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
+
+1:
+ /* Get SDRAM width (SPD offset 13) */
+ mov r7, #SDRAM_WIDTH_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ mov PC, r13
+
+/**************************/
+_get_CAL:
+ mov r13, LR /* Save link register */
+
+ /* Set maximum CL supported by DIMM */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SUPPORTED_CL_OFFSET /* offset 18 */
+ bl _i2cRead
+
+ mov PC, r13
+
+/**************************/
+/* R8 - sdram configuration register.
+ * Return value in flag if no-registered then Z-flag is set
+ */
+_is_Registered:
+ mov r13, LR /* Save link register */
+#if defined(MV645xx)
+ /* Get registered/non registered info from DIMM */
+ tst r8, #SDRAM_DTYPE_DDR2
+ bne regDdr2
+
+regDdr1:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #SDRAM_MODULES_ATTR_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x2
+ b exit
+#endif
+regDdr2:
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_TYPE_INFO_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x11 /* DIMM type = regular RDIMM (0x01) */
+ /* or Mini-RDIMM (0x10) */
+exit:
+ mov PC, r13
+
+
+/**************************/
+/* Return value in flag if no-Ecc then Z-flag is set */
+_is_Ecc:
+ mov r13, LR /* Save link register */
+
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_CONFIG_TYPE
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x2 /* bit 1 -> Data ECC */
+ mov PC, r13
+
+/**************************/
+/* Return value in flag if no second DIMM then Z-flag is set */
+_is_Second_Dimm_Exist:
+ mov r13, LR /* Save link register */
+
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM0 */
+ mov r7, #DIMM_TYPE_OFFSET
+ bl _i2cRead /* result in r7 */
+
+ tst r7, #0x8 /* bit3 is '1' -> DDR 2 */
+ mov PC, r13
+
+/*******************************************************************************
+* _mvDramIfGetDimmSizeFromSpd - read bank 0 dram's size
+*
+* DESCRIPTION:
+* The function will read the bank 0 dram size(SPD version 1.0 and above )
+*
+* INPUT:
+* r6 - dram bank number.
+*
+* OUTPUT:
+* none
+*/
+_mvDramIfGetDimmSizeFromSpd:
+
+ mov r13, LR /* Save link register */
+
+ /* Read SPD rank size from DIMM0 */
+ mov r4, #MV_BOARD_DIMM0_I2C_ADDR /* reading from DIMM0 */
+
+ cmp r6, #0
+ beq 1f
+
+ /* Read SPD rank size from DIMM1 */
+ mov r4, #MV_BOARD_DIMM1_I2C_ADDR /* reading from DIMM1 */
+
+1:
+ mov r7, #RANK_SIZE_OFFSET /* offset 31 */
+ bl _i2cRead
+
+pass_read:
+ ldr r8, =(0x7 << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_128M
+ beq endDimmSize
+
+ ldr r8, =(0xf << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_256M
+ beq endDimmSize
+
+ ldr r8, =(0x1f << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_512M
+ beq endDimmSize
+
+ ldr r8, =(0x3f << SCSR_SIZE_OFFS)
+ cmp r7, #DRAM_RANK_DENSITY_1G
+ beq endDimmSize
+
+ ldr r8, =(0x7f << SCSR_SIZE_OFFS) /* DRAM_RANK_DENSITY_2G */
+endDimmSize:
+ mov PC, r13
+#endif
--- /dev/null
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+/*******************************************************************************
+* mvDramIfBasicAsm.s
+*
+* DESCRIPTION:
+* Memory full detection and best timing configuration is done in
+* C code. C runtime environment requires a stack. This module API
+* initialize DRAM interface chip select 0 for basic functionality for
+* the use of stack.
+* The module API assumes DRAM information is stored in I2C EEPROM reside
+* in a given I2C address MV_BOARD_DIMM0_I2C_ADDR. The I2C EEPROM
+* internal data structure is assumed to be orgenzied in common DRAM
+* vendor SPD structure.
+* NOTE: DFCDL values are assumed to be already initialized prior to
+* this module API activity.
+*
+*
+* DEPENDENCIES:
+* None.
+*
+*******************************************************************************/
+
+/* includes */
+#define _ASMLANGUAGE
+#define MV_ASMLANGUAGE
+#include "mvOsAsm.h"
+#include "mvSysHwConfig.h"
+#include "mvDramIfRegs.h"
+#include "mvDramIfConfig.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "pex/mvPexRegs.h"
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "mvCommon.h"
+
+/* defines */
+
+/* locals */
+.data
+.globl _mvDramIfConfig
+.text
+.globl _mvDramIfMemInit
+
+/*******************************************************************************
+* _mvDramIfConfig - Basic DRAM interface initialization.
+*
+* DESCRIPTION:
+* The function will initialize the following DRAM parameters using the
+* values prepared by mvDramIfDetect routine. Values are located
+* in predefined registers.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+
+_mvDramIfConfig:
+
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_s
+save_on_stack:
+ stmdb sp!, {r1, r2, r3, r4}
+no_stack_s:
+
+ /* Dunit FTDLL Configuration Register */
+ /* 0) Write to SDRAM FTDLL coniguration register */
+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_LEFT;
+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_LEFT_REG)
+ str r4, [r1]
+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_RIGHT;
+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_RIGHT_REG)
+ str r4, [r1]
+ ldr r4, = SDRAM_FTDLL_REG_DEFAULT_UP;
+ ldr r1, =(INTER_REGS_BASE + SDRAM_FTDLL_CONFIG_UP_REG)
+ str r4, [r1]
+
+ /* 1) Write to SDRAM coniguration register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG1)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_CONFIG_REG)
+ str r4, [r1]
+
+ /* 2) Write Dunit control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG3)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_REG)
+ str r4, [r1]
+
+ /* 2) Write Dunit control high register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG13)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DUNIT_CTRL_HI_REG)
+ str r4, [r1]
+
+ /* 3) Write SDRAM address control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG4)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_ADDR_CTRL_REG)
+ str r4, [r1]
+#if defined(MV_STATIC_DRAM_ON_BOARD)
+ /* 4) Write SDRAM bank 0 size register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG0)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_SIZE_REG(0,0))
+ str r4, [r1]
+#endif
+
+ /* 5) Write SDRAM open pages control register */
+ ldr r1, =(INTER_REGS_BASE + SDRAM_OPEN_PAGE_CTRL_REG)
+ ldr r4, =SDRAM_OPEN_PAGES_CTRL_REG_DV
+ str r4, [r1]
+
+ /* 6) Write SDRAM timing Low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG5)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* 7) Write SDRAM timing High register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG6)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_TIMING_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* Config DDR2 On Die Termination (ODT) registers */
+ /* Write SDRAM DDR2 ODT control low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG7)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_LOW_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 ODT control high register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG8)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_SDRAM_ODT_CTRL_HIGH_REG)
+ str r4, [r1]
+
+ /* Write SDRAM DDR2 Dunit ODT control register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG9)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + DDR2_DUNIT_ODT_CONTROL_REG)
+ str r4, [r1]
+
+ /* Write DDR2 SDRAM timing Low register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG11)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_LO_REG)
+ str r4, [r1]
+
+ /* Write DDR2 SDRAM timing High register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG12)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_DDR2_TIMING_HI_REG)
+ str r4, [r1]
+
+ /* 8) Write SDRAM mode register */
+ /* The CPU must not attempt to change the SDRAM Mode register setting */
+ /* prior to DRAM controller completion of the DRAM initialization */
+ /* sequence. To guarantee this restriction, it is recommended that */
+ /* the CPU sets the SDRAM Operation register to NOP command, performs */
+ /* read polling until the register is back in Normal operation value, */
+ /* and then sets SDRAM Mode register to its new value. */
+
+ /* 8.1 write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM(r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.2 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll1:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll1
+
+ /* 8.3 Now its safe to write new value to SDRAM Mode register */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG2)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_MODE_REG)
+ str r4, [r1]
+
+ /* 8.4 Make the Dunit write the DRAM its new mode */
+ mov r4, #0x3 /* Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* 8.5 poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll2:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll2
+
+ /* Now its safe to write new value to SDRAM Extended Mode regist */
+ ldr r1, =(INTER_REGS_BASE + DRAM_BUF_REG10)
+ ldr r4, [r1]
+ ldr r1, =(INTER_REGS_BASE + SDRAM_EXTENDED_MODE_REG)
+ str r4, [r1]
+
+ /* 9) Write SDRAM Extended mode register This operation should be */
+ /* done for each memory bank */
+ /* write 'nop' to SDRAM operation */
+ mov r4, #0x5 /* 'NOP' command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll3:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll3
+ /* Go over each of the Banks */
+ ldr r3, =0 /* r3 = DRAM bank Num */
+
+extModeLoop:
+ /* Set the SDRAM Operation Control to each of the DRAM banks */
+ mov r4, r3 /* Do not swap the bank counter value */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_CTRL_REG)
+
+ /* Make the Dunit write the DRAM its new mode */
+ mov r4, #0x4 /* Extended Mode Register Set command */
+ MV_REG_WRITE_ASM (r4, r1, SDRAM_OPERATION_REG)
+
+ /* poll SDRAM operation. Make sure its back to normal operation */
+_sdramOpPoll4:
+ ldr r4, [r1]
+ cmp r4, #0 /* '0' = Normal SDRAM Mode */
+ bne _sdramOpPoll4
+
+ add r3, r3, #1
+ cmp r3, #4 /* 4 = Number of banks */
+ bne extModeLoop
+
+extModeEnd:
+cmp sp, #0
+ beq no_stack_l
+ mov r1, LR /* Save link register */
+#if defined(MV78XX0)
+ bl _mvDramIfMemInit
+#endif
+ mov LR,r1 /* restore link register */
+load_from_stack:
+ /* Restore registers */
+ ldmia sp!, {r1, r2, r3, r4}
+no_stack_l:
+
+ mov pc, lr
+
+
+/*******************************************************************************
+* _mvDramIfEccMemInit - Basic DRAM ECC initialization.
+*
+* DESCRIPTION:
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+#define XOR_CHAN0 0 /* XOR channel 0 used for memory initialization */
+#define XOR_UNIT0 0 /* XOR unit 0 used for memory initialization */
+#define XOR_ADDR_DEC_WIN0 0 /* Enable DRAM access using XOR decode window 0 */
+/* XOR engine register offsets macros */
+#define XOR_CONFIG_REG(chan) (XOR_UNIT_BASE(0) + 0x10 + ((chan) * 4))
+#define XOR_ACTIVATION_REG(chan) (XOR_UNIT_BASE(0) + 0x20 + ((chan) * 4))
+#define XOR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x30)
+#define XOR_ERROR_CAUSE_REG (XOR_UNIT_BASE(0) + 0x50)
+#define XOR_ERROR_ADDR_REG (XOR_UNIT_BASE(0) + 0x60)
+#define XOR_INIT_VAL_LOW_REG (XOR_UNIT_BASE(0) + 0x2E0)
+#define XOR_INIT_VAL_HIGH_REG (XOR_UNIT_BASE(0) + 0x2E4)
+#define XOR_DST_PTR_REG(chan) (XOR_UNIT_BASE(0) + 0x2B0 + ((chan) * 4))
+#define XOR_BLOCK_SIZE_REG(chan) (XOR_UNIT_BASE(0) + 0x2C0 + ((chan) * 4))
+
+/* XOR Engine Address Decoding Register Map */
+#define XOR_WINDOW_CTRL_REG(unit,chan) (XOR_UNIT_BASE(unit)+(0x240 + ((chan) * 4)))
+#define XOR_BASE_ADDR_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x250 + ((winNum) * 4)))
+#define XOR_SIZE_MASK_REG(unit,winNum) (XOR_UNIT_BASE(unit)+(0x270 + ((winNum) * 4)))
+
+.globl _mvDramIfEccMemInit
+/*******************************************************************************
+* _mvDramIfEccMemInit - mem init for dram cs
+*
+* DESCRIPTION:
+* This function will clean the cs by ussing the XOR mem init.
+*
+* INPUT:
+* r0 - dram bank number.
+*
+* OUTPUT:
+* none
+*/
+_mvDramIfEccMemInit:
+
+ /* Save register on stack */
+ cmp sp, #0
+ beq no_stack_s1
+save_on_stack1:
+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
+no_stack_s1:
+
+ ldr r1, = 0
+
+ /* Disable all XOR address decode windows to avoid possible overlap */
+ MV_REG_WRITE_ASM (r1, r5, (XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0)))
+
+ /* Init r5 to first XOR_SIZE_MASK_REG */
+ mov r5, r0, LSL #3
+ add r5, r5,#0x1500
+ add r5, r5,#0x04
+ add r5, r5,#(INTER_REGS_BASE)
+ ldr r6, [r5]
+ HTOLL(r6,r5)
+ MV_REG_WRITE_ASM (r6, r5, XOR_SIZE_MASK_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
+
+ mov r5, r0, LSL #3
+ add r5, r5,#0x1500
+ add r5, r5,#(INTER_REGS_BASE)
+ ldr r6, [r5]
+ /* Update destination & size */
+ MV_REG_WRITE_ASM(r6, r5, XOR_DST_PTR_REG(XOR_CHAN0))
+ HTOLL(r6,r5)
+ /* Init r6 to first XOR_BASE_ADDR_REG */
+ ldr r4, = 0xf
+ ldr r5, = 0x1
+ mov r5, r5, LSL r0
+ bic r4, r4, r5
+ mov r4, r4, LSL #8
+
+ orr r6, r6, r4
+ MV_REG_WRITE_ASM (r6, r5, XOR_BASE_ADDR_REG(XOR_UNIT0,XOR_ADDR_DEC_WIN0))
+
+ ldr r6, = 0xff0001
+ MV_REG_WRITE_ASM (r6, r5, XOR_WINDOW_CTRL_REG(XOR_UNIT0,XOR_CHAN0))
+
+ /* Configure XOR engine for memory init function. */
+ MV_REG_READ_ASM (r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
+ and r6, r6, #~0x7 /* Clear operation mode field */
+ orr r6, r6, #0x4 /* Set operation to memory init */
+ MV_REG_WRITE_ASM(r6, r5, XOR_CONFIG_REG(XOR_CHAN0))
+
+ /* Set initVal in the XOR Engine Initial Value Registers */
+ ldr r6, = 0xfeedfeed
+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_LOW_REG)
+ ldr r6, = 0xfeedfeed
+ MV_REG_WRITE_ASM(r6, r5, XOR_INIT_VAL_HIGH_REG)
+
+ /* Set block size using DRAM bank size */
+
+ mov r5, r0, LSL #3
+ add r5, r5,#0x1500
+ add r5, r5,#0x04
+ add r5, r5,#(INTER_REGS_BASE)
+
+ ldr r6, [r5]
+ HTOLL(r6,r5)
+ and r6, r6, #SCSR_SIZE_MASK
+ mov r5, r6, LSR #SCSR_SIZE_OFFS
+ add r5, r5, #1
+ mov r6, r5, LSL #SCSR_SIZE_OFFS
+ MV_REG_WRITE_ASM(r6, r5, XOR_BLOCK_SIZE_REG(XOR_CHAN0))
+
+ /* Clean interrupt cause*/
+ MV_REG_WRITE_ASM(r1, r5, XOR_CAUSE_REG)
+
+ /* Clean error interrupt cause*/
+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_CAUSE_REG)
+ MV_REG_READ_ASM(r6, r5, XOR_ERROR_ADDR_REG)
+
+ /* Start transfer */
+ MV_REG_READ_ASM (r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
+ orr r6, r6, #0x1 /* Preform start command */
+ MV_REG_WRITE_ASM(r6, r5, XOR_ACTIVATION_REG(XOR_CHAN0))
+
+ /* Wait for engine to finish */
+waitForComplete:
+ MV_REG_READ_ASM(r6, r5, XOR_CAUSE_REG)
+ and r6, r6, #2
+ cmp r6, #0
+ beq waitForComplete
+
+ /* Clear all error report registers */
+ MV_REG_WRITE_ASM(r1, r5, SDRAM_SINGLE_BIT_ERR_CNTR_REG)
+ MV_REG_WRITE_ASM(r1, r5, SDRAM_DOUBLE_BIT_ERR_CNTR_REG)
+
+ MV_REG_WRITE_ASM(r1, r5, SDRAM_ERROR_CAUSE_REG)
+
+ cmp sp, #0
+ beq no_stack_l1
+load_from_stack1:
+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
+no_stack_l1:
+ mov pc, lr
+
+
+/*******************************************************************************
+* mvDramIfMemInit - Use XOR to clear all memory.
+*
+* DESCRIPTION:
+* Use assembler function _mvDramIfEccMemInit to fill all memory with FEADFEAD pattern.
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+#if defined(MV78XX0)
+
+_mvDramIfMemInit:
+ stmdb sp!, {r0,r1, r2, r3, r4, r5, r6}
+ mov r6, LR /* Save link register */
+ /* Check if dram bank 0 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,0))
+ and r3, r0, #SCSR_WIN_EN
+ cmp r3, #0
+ beq no_bank_0
+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,0))
+ cmp r0, #0
+ beq no_bank_0
+ mov r0,#0
+ bl _mvDramIfEccMemInit
+
+no_bank_0:
+ /* Check if dram bank 1 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,1))
+ and r0, r0, #SCSR_WIN_EN
+ cmp r0, #0
+ beq no_bank_1
+ mov r0,#1
+ bl _mvDramIfEccMemInit
+no_bank_1:
+ /* Check if dram bank 2 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,2))
+ and r0, r0, #SCSR_WIN_EN
+ cmp r0, #0
+ beq no_bank_2
+ MV_REG_READ_ASM(r0, r5, SDRAM_BASE_ADDR_REG(0,2))
+ cmp r0, #0
+ beq no_bank_2
+ mov r0,#2
+ bl _mvDramIfEccMemInit
+
+no_bank_2:
+ /* Check if dram bank 3 has to be init for ECC */
+ MV_REG_READ_ASM (r0, r5, SDRAM_SIZE_REG(0,3))
+ and r0, r0, #SCSR_WIN_EN
+ cmp r0, #0
+ beq no_bank_3
+ mov r0,#3
+ bl _mvDramIfEccMemInit
+no_bank_3:
+ mov LR ,r6 /* restore link register */
+ ldmia sp!, {r0, r1, r2, r3, r4, r5, r6}
+ mov pc, lr
+#endif
+
mvEthEjpModeSet(pHndl, mode);
}
}
-#endif /* (MV_ETH_VERSION >= 4) */
+#endif /* (MV_ETH_VERSION >= 4) */\r
void ethBpduRxQ(int port, int bpduQueue)
{
mvOsPrintf("\n\t TX policy Port #%d configuration registers\n", port);
- mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n",
- ETH_TX_QUEUE_COMMAND_REG(port),
- MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) );
-
+ mvOsPrintf("ETH_TX_QUEUE_COMMAND_REG : 0x%X = 0x%08x\n", \r
+ ETH_TX_QUEUE_COMMAND_REG(port), \r
+ MV_REG_READ( ETH_TX_QUEUE_COMMAND_REG(port) ) ); \r
+ \r
mvOsPrintf("ETH_TX_FIXED_PRIO_CFG_REG : 0x%X = 0x%08x\n",
ETH_TX_FIXED_PRIO_CFG_REG(port),
MV_REG_READ( ETH_TX_FIXED_PRIO_CFG_REG(port) ) );
mvOsPrintf("ETH_TX_TOKEN_BUCKET_COUNT_REG : 0x%X = 0x%08x\n",
ETH_TX_TOKEN_BUCKET_COUNT_REG(port),
- MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) );
-
+ MV_REG_READ( ETH_TX_TOKEN_BUCKET_COUNT_REG(port) ) );\r
+\r
for(queue=0; queue<MV_ETH_MAX_TXQ; queue++)
{
mvOsPrintf("\n\t TX policy Port #%d, Queue #%d configuration registers\n", port, queue);
mvOsPrintf("ETH_TXQ_ARBITER_CFG_REG : 0x%X = 0x%08x\n",
ETH_TXQ_ARBITER_CFG_REG(port, queue),
MV_REG_READ( ETH_TXQ_ARBITER_CFG_REG(port, queue) ) );
- }
+ }\r
mvOsPrintf("\n");
}
mvOsPrintf("RxCoal = %d usec, TxCoal = %d usec\n",
rxCoal, txCoal);
- mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n",
- pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ,
- pPortCtrl->portConfig.rxBpduQ,
- pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ);
-
+ mvOsPrintf("rxDefQ=%d, arpQ=%d, bpduQ=%d, tcpQ=%d, udpQ=%d\n\n",\r
+ pPortCtrl->portConfig.rxDefQ, pPortCtrl->portConfig.rxArpQ, \r
+ pPortCtrl->portConfig.rxBpduQ, \r
+ pPortCtrl->portConfig.rxTcpQ, pPortCtrl->portConfig.rxUdpQ); \r
+\r
/* Print all RX and TX queues */
for(queue=0; queue<MV_ETH_RX_Q_NUM; queue++)
{
mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%4d, buf=%08x, pkt=%lx, os=%lx\n",
i, (MV_U32)pRxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pRxDescr),
pRxDescr->cmdSts, pRxDescr->byteCnt, (MV_U32)pRxDescr->bufSize,
- (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo,
+ (unsigned int)pRxDescr->bufPtr, (MV_ULONG)pRxDescr->returnInfo,\r
((MV_PKT_INFO*)pRxDescr->returnInfo)->osInfo);
ETH_DESCR_INV(pPortCtrl, pRxDescr);
mvOsPrintf("%3d. desc=%08x (%08x), cmd=%08x, data=%4d, buf=%08x, pkt=%lx, os=%lx\n",
i, (MV_U32)pTxDescr, (MV_U32)ethDescVirtToPhy(pQueueCtrl, (MV_U8*)pTxDescr),
pTxDescr->cmdSts, pTxDescr->byteCnt,
- (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo,
+ (MV_U32)pTxDescr->bufPtr, (MV_ULONG)pTxDescr->returnInfo,\r
pTxDescr->returnInfo ? (((MV_PKT_INFO*)pTxDescr->returnInfo)->osInfo) : 0x0);
ETH_DESCR_INV(pPortCtrl, pTxDescr);
void ethTxCoal(int port, int usec);
#if (MV_ETH_VERSION >= 4)
void ethEjpModeSet(int port, int mode);
-#endif /* (MV_ETH_VERSION >= 4) */
+#endif /* (MV_ETH_VERSION >= 4) */\r
void ethBpduRxQ(int port, int bpduQueue);
void ethArpRxQ(int port, int arpQueue);
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.4\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.4\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.3\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.2\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.4\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#include "mvPex.h"
-
-//#define MV_DEBUG
-/* defines */
-#ifdef MV_DEBUG
- #define DB(x) x
-#else
- #define DB(x)
-#endif
-
-/* locals */
-typedef struct
-{
- MV_U32 data;
- MV_U32 mask;
-}PEX_HEADER_DATA;
-
-/* local function forwad decleration */
-MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
- MV_U32 regOff);
-MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func, MV_U32 regOff, MV_U32 data);
-void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev);
-
-
-PEX_HEADER_DATA configHdr[16] =
-{
-{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */
-{0x00100007, 0x0000ffff}, /*[status register, command register] */
-{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */
-{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */
-{0x00000000, 0x00000000}, /*[base address 0] */
-{0x00000000, 0x00000000}, /*[base address 1] */
-{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */
-{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */
-{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */
-{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */
-{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */
-{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */
-{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */
-{0x00000000, 0x00000000}, /*[reserved, capability pointer] */
-{0x00000000, 0x00000000}, /*[expansion ROM base address] */
-{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */
-};
-
-
-#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \
- (data & configHdr[offset/4].mask))
-#define HEADER_READ(offset) configHdr[offset/4].data
-
-/*******************************************************************************
-* mvVrtBrgPexInit - Initialize PEX interfaces
-*
-* DESCRIPTION:
-*
-* This function is responsible of intialization of the Pex Interface , It
-* configure the Pex Bars and Windows in the following manner:
-*
-* Assumptions :
-* Bar0 is always internal registers bar
-* Bar1 is always the DRAM bar
-* Bar2 is always the Device bar
-*
-* 1) Sets the Internal registers bar base by obtaining the base from
-* the CPU Interface
-* 2) Sets the DRAM bar base and size by getting the base and size from
-* the CPU Interface when the size is the sum of all enabled DRAM
-* chip selects and the base is the base of CS0 .
-* 3) Sets the Device bar base and size by getting these values from the
-* CPU Interface when the base is the base of the lowest base of the
-* Device chip selects, and the
-*
-*
-* INPUT:
-*
-* pexIf - PEX interface number.
-*
-*
-* OUTPUT:
-* None.
-*
-* RETURN:
-* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM
-*
-*******************************************************************************/
-MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf)
-{
- /* reset PEX tree to recover previous U-boot/Boot configurations */
- MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
-
-
- resetPexConfig(pexIf, localBus, 1);
- return MV_OK;
-}
-
-
-MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func,
- MV_U32 regOff)
-{
-
- MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
- MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
- MV_U32 val;
- if(bus == localBus)
- {
- if(dev > 1)
- {
-/* on the local device allow only device #0 & #1 */
- return 0xffffffff;
- }
- else
- if (dev == localDev)
- {
- /* read the memory controller registers */
- return mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
- }
- else
- {
- /* access the virtual brg header */
- return HEADER_READ(regOff);
- }
- }
- else
- if(bus == (localBus + 1))
- {
- /* access the device behind the virtual bridge */
- if((dev == localDev) || (dev > 1))
- {
- return 0xffffffff;
- }
- else
- {
- /* access the device behind the virtual bridge, in this case
- * change the bus number to the local bus number in order to
- * generate type 0 config cycle
- */
- mvPexLocalBusNumSet(pexIf, bus);
- mvPexLocalDevNumSet(pexIf, 1);
- val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff);
- mvPexLocalBusNumSet(pexIf, localBus);
- mvPexLocalDevNumSet(pexIf, localDev);
- return val;
- }
- }
- /* for all other devices use the HW function to get the
- * requested registers
- */
- mvPexLocalDevNumSet(pexIf, 1);
- val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff);
- mvPexLocalDevNumSet(pexIf, localDev);
- return val;
-}
-
-
-MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func, MV_U32 regOff, MV_U32 data)
-{
- MV_U32 localBus = mvPexLocalBusNumGet(pexIf);
- MV_U32 localDev = mvPexLocalDevNumGet(pexIf);
- MV_STATUS status;
-
- if(bus == localBus)
- {
- if(dev > 1)
- {
- /* on the local device allow only device #0 & #1 */
- return MV_ERROR;
- }
- else
- if (dev == localDev)
- {
- /* read the memory controller registers */
- return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
- }
- else
- {
- /* access the virtual brg header */
- HEADER_WRITE(data, regOff);
- return MV_OK;
- }
- }
- else
- if(bus == (localBus + 1))
- {
- /* access the device behind the virtual bridge */
- if((dev == localDev) || (dev > 1))
- {
- return MV_ERROR;
- }
- else
- {
- /* access the device behind the virtual bridge, in this case
- * change the bus number to the local bus number in order to
- * generate type 0 config cycle
- */
- //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data);
- mvPexLocalBusNumSet(pexIf, bus);
- mvPexLocalDevNumSet(pexIf, 1);
- status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data);
- mvPexLocalBusNumSet(pexIf, localBus);
- mvPexLocalDevNumSet(pexIf, localDev);
- return status;
-
- }
- }
- /* for all other devices use the HW function to get the
- * requested registers
- */
- mvPexLocalDevNumSet(pexIf, 1);
- status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);
- mvPexLocalDevNumSet(pexIf, localDev);
- return status;
-}
-
-
-
-
-void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev)
-{
- MV_U32 tData;
- MV_U32 i;
-
- /* restore the PEX configuration to initialization state */
- /* in case PEX P2P call recursive and reset config */
- tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0);
- if(tData != 0xffffffff)
- {
- /* agent had been found - check whether P2P */
- tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8);
- if((tData & 0xffff0000) == 0x06040000)
- {/* P2P */
- /* get the sec bus and the subordinate */
- MV_U32 secBus;
- tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18);
- secBus = ((tData >> 8) & 0xff);
- /* now scan on sec bus */
- for(i = 0;i < 0xff;i++)
- {
- resetPexConfig(pexIf, secBus, i);
- }
- /* now reset this device */
- DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
- mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0);
- DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));
- }
- }
-}
-
-
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell \r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File in accordance with the terms and conditions of the General \r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is \r
+available along with the File in the license.txt file or by writing to the Free \r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or \r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. \r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY \r
+DISCLAIMED. The GPL License provides additional details about this warranty \r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File under the following licensing terms. \r
+Redistribution and use in source and binary forms, with or without modification, \r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer. \r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution. \r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be \r
+ used to endorse or promote products derived from this software without \r
+ specific prior written permission. \r
+ \r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND \r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR \r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON \r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+\r
+#include "mvPex.h"\r
+\r
+//#define MV_DEBUG\r
+/* defines */ \r
+#ifdef MV_DEBUG \r
+ #define DB(x) x\r
+#else \r
+ #define DB(x) \r
+#endif \r
+\r
+/* locals */ \r
+typedef struct\r
+{\r
+ MV_U32 data;\r
+ MV_U32 mask;\r
+}PEX_HEADER_DATA;\r
+\r
+/* local function forwad decleration */\r
+MV_U32 mvPexHwConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, \r
+ MV_U32 regOff);\r
+MV_STATUS mvPexHwConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, \r
+ MV_U32 func, MV_U32 regOff, MV_U32 data);\r
+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev);\r
+\r
+\r
+PEX_HEADER_DATA configHdr[16] = \r
+{\r
+{0x888811ab, 0x00000000}, /*[device ID, vendor ID] */\r
+{0x00100007, 0x0000ffff}, /*[status register, command register] */ \r
+{0x0604000e, 0x00000000}, /*[programming interface, sub class code, class code, revision ID] */\r
+{0x00010008, 0x00000000}, /*[BIST, header type, latency time, cache line] */\r
+{0x00000000, 0x00000000}, /*[base address 0] */ \r
+{0x00000000, 0x00000000}, /*[base address 1] */ \r
+{0x00000000, 0x00ffffff}, /*[secondary latency timersubordinate bus number, secondary bus number, primary bus number] */ \r
+{0x0000f101, 0x00000000}, /*[secondary status ,IO limit, IO base] */\r
+{0x9ff0a000, 0x00000000}, /*[memory limit, memory base] */ \r
+{0x0001fff1, 0x00000000}, /*[prefetch memory limit, prefetch memory base] */ \r
+{0xffffffff, 0x00000000}, /*[prefetch memory base upper] */ \r
+{0x00000000, 0x00000000}, /*[prefetch memory limit upper] */\r
+{0xeffff000, 0x00000000}, /*[IO limit upper 16 bits, IO base upper 16 bits] */ \r
+{0x00000000, 0x00000000}, /*[reserved, capability pointer] */ \r
+{0x00000000, 0x00000000}, /*[expansion ROM base address] */ \r
+{0x00000000, 0x000000FF}, /*[bridge control, interrupt pin, interrupt line] */ \r
+};\r
+\r
+\r
+#define HEADER_WRITE(data, offset) configHdr[offset/4].data = ((configHdr[offset/4].data & ~configHdr[offset/4].mask) | \\r
+ (data & configHdr[offset/4].mask))\r
+#define HEADER_READ(offset) configHdr[offset/4].data\r
+\r
+/*******************************************************************************\r
+* mvVrtBrgPexInit - Initialize PEX interfaces\r
+*\r
+* DESCRIPTION:\r
+*\r
+* This function is responsible of intialization of the Pex Interface , It \r
+* configure the Pex Bars and Windows in the following manner:\r
+*\r
+* Assumptions : \r
+* Bar0 is always internal registers bar\r
+* Bar1 is always the DRAM bar\r
+* Bar2 is always the Device bar\r
+*\r
+* 1) Sets the Internal registers bar base by obtaining the base from\r
+* the CPU Interface\r
+* 2) Sets the DRAM bar base and size by getting the base and size from\r
+* the CPU Interface when the size is the sum of all enabled DRAM \r
+* chip selects and the base is the base of CS0 .\r
+* 3) Sets the Device bar base and size by getting these values from the \r
+* CPU Interface when the base is the base of the lowest base of the\r
+* Device chip selects, and the \r
+*\r
+*\r
+* INPUT:\r
+*\r
+* pexIf - PEX interface number.\r
+*\r
+*\r
+* OUTPUT:\r
+* None.\r
+*\r
+* RETURN:\r
+* MV_OK if function success otherwise MV_ERROR or MV_BAD_PARAM\r
+*\r
+*******************************************************************************/\r
+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf)\r
+{\r
+ /* reset PEX tree to recover previous U-boot/Boot configurations */\r
+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf);\r
+\r
+\r
+ resetPexConfig(pexIf, localBus, 1);\r
+ return MV_OK;\r
+}\r
+\r
+\r
+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev, MV_U32 func, \r
+ MV_U32 regOff)\r
+{\r
+ \r
+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf);\r
+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf);\r
+ MV_U32 val; \r
+ if(bus == localBus)\r
+ {\r
+ if(dev > 1)\r
+ {\r
+/* on the local device allow only device #0 & #1 */\r
+ return 0xffffffff;\r
+ }\r
+ else\r
+ if (dev == localDev)\r
+ {\r
+ /* read the memory controller registers */\r
+ return mvPexHwConfigRead (pexIf, bus, dev, func, regOff);\r
+ }\r
+ else\r
+ {\r
+ /* access the virtual brg header */\r
+ return HEADER_READ(regOff);\r
+ }\r
+ }\r
+ else\r
+ if(bus == (localBus + 1))\r
+ {\r
+ /* access the device behind the virtual bridge */\r
+ if((dev == localDev) || (dev > 1))\r
+ {\r
+ return 0xffffffff;\r
+ }\r
+ else\r
+ {\r
+ /* access the device behind the virtual bridge, in this case \r
+ * change the bus number to the local bus number in order to \r
+ * generate type 0 config cycle\r
+ */ \r
+ mvPexLocalBusNumSet(pexIf, bus);\r
+ mvPexLocalDevNumSet(pexIf, 1);\r
+ val = mvPexHwConfigRead (pexIf, bus, 0, func, regOff);\r
+ mvPexLocalBusNumSet(pexIf, localBus);\r
+ mvPexLocalDevNumSet(pexIf, localDev);\r
+ return val;\r
+ }\r
+ }\r
+ /* for all other devices use the HW function to get the \r
+ * requested registers\r
+ */\r
+ mvPexLocalDevNumSet(pexIf, 1);\r
+ val = mvPexHwConfigRead (pexIf, bus, dev, func, regOff);\r
+ mvPexLocalDevNumSet(pexIf, localDev); \r
+ return val;\r
+}\r
+\r
+\r
+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev, \r
+ MV_U32 func, MV_U32 regOff, MV_U32 data)\r
+{\r
+ MV_U32 localBus = mvPexLocalBusNumGet(pexIf);\r
+ MV_U32 localDev = mvPexLocalDevNumGet(pexIf);\r
+ MV_STATUS status;\r
+\r
+ if(bus == localBus)\r
+ {\r
+ if(dev > 1)\r
+ {\r
+ /* on the local device allow only device #0 & #1 */\r
+ return MV_ERROR;\r
+ }\r
+ else\r
+ if (dev == localDev)\r
+ {\r
+ /* read the memory controller registers */\r
+ return mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data); \r
+ }\r
+ else\r
+ {\r
+ /* access the virtual brg header */\r
+ HEADER_WRITE(data, regOff);\r
+ return MV_OK;\r
+ }\r
+ }\r
+ else\r
+ if(bus == (localBus + 1))\r
+ {\r
+ /* access the device behind the virtual bridge */\r
+ if((dev == localDev) || (dev > 1))\r
+ {\r
+ return MV_ERROR;\r
+ }\r
+ else\r
+ {\r
+ /* access the device behind the virtual bridge, in this case \r
+ * change the bus number to the local bus number in order to \r
+ * generate type 0 config cycle\r
+ */\r
+ //return mvPexHwConfigWrite (pexIf, localBus, dev, func, regOff, data);\r
+ mvPexLocalBusNumSet(pexIf, bus);\r
+ mvPexLocalDevNumSet(pexIf, 1);\r
+ status = mvPexHwConfigWrite (pexIf, bus, 0, func, regOff, data);\r
+ mvPexLocalBusNumSet(pexIf, localBus);\r
+ mvPexLocalDevNumSet(pexIf, localDev);\r
+ return status;\r
+\r
+ }\r
+ }\r
+ /* for all other devices use the HW function to get the \r
+ * requested registers\r
+ */\r
+ mvPexLocalDevNumSet(pexIf, 1);\r
+ status = mvPexHwConfigWrite (pexIf, bus, dev, func, regOff, data);\r
+ mvPexLocalDevNumSet(pexIf, localDev);\r
+ return status;\r
+}\r
+\r
+\r
+\r
+\r
+void resetPexConfig(MV_U32 pexIf, MV_U32 bus, MV_U32 dev)\r
+{\r
+ MV_U32 tData;\r
+ MV_U32 i;\r
+\r
+ /* restore the PEX configuration to initialization state */\r
+ /* in case PEX P2P call recursive and reset config */\r
+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x0);\r
+ if(tData != 0xffffffff)\r
+ {\r
+ /* agent had been found - check whether P2P */\r
+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x8);\r
+ if((tData & 0xffff0000) == 0x06040000)\r
+ {/* P2P */\r
+ /* get the sec bus and the subordinate */\r
+ MV_U32 secBus; \r
+ tData = mvPexHwConfigRead (pexIf, bus, dev, 0x0, 0x18);\r
+ secBus = ((tData >> 8) & 0xff);\r
+ /* now scan on sec bus */\r
+ for(i = 0;i < 0xff;i++)\r
+ {\r
+ resetPexConfig(pexIf, secBus, i);\r
+ }\r
+ /* now reset this device */\r
+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));\r
+ mvPexHwConfigWrite(pexIf, bus, dev, 0x0, 0x18, 0x0); \r
+ DB(mvOsPrintf("Reset bus %d dev %d\n", bus, dev));\r
+ }\r
+ }\r
+}\r
+\r
+\r
-/*******************************************************************************
-Copyright (C) Marvell International Ltd. and its affiliates
-
-This software file (the "File") is owned and distributed by Marvell
-International Ltd. and/or its affiliates ("Marvell") under the following
-alternative licensing terms. Once you have made an election to distribute the
-File under one of the following license alternatives, please (i) delete this
-introductory statement regarding license alternatives, (ii) delete the two
-license alternatives that you have not elected to use and (iii) preserve the
-Marvell copyright notice above.
-
-********************************************************************************
-Marvell Commercial License Option
-
-If you received this File from Marvell and you have entered into a commercial
-license agreement (a "Commercial License") with Marvell, the File is licensed
-to you under the terms of the applicable Commercial License.
-
-********************************************************************************
-Marvell GPL License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File in accordance with the terms and conditions of the General
-Public License Version 2, June 1991 (the "GPL License"), a copy of which is
-available along with the File in the license.txt file or by writing to the Free
-Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
-on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
-
-THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
-WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
-DISCLAIMED. The GPL License provides additional details about this warranty
-disclaimer.
-********************************************************************************
-Marvell BSD License Option
-
-If you received this File from Marvell, you may opt to use, redistribute and/or
-modify this File under the following licensing terms.
-Redistribution and use in source and binary forms, with or without modification,
-are permitted provided that the following conditions are met:
-
- * Redistributions of source code must retain the above copyright notice,
- this list of conditions and the following disclaimer.
-
- * Redistributions in binary form must reproduce the above copyright
- notice, this list of conditions and the following disclaimer in the
- documentation and/or other materials provided with the distribution.
-
- * Neither the name of Marvell nor the names of its contributors may be
- used to endorse or promote products derived from this software without
- specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*******************************************************************************/
-
-#ifndef __INCVRTBRGPEXH
-#define __INCVRTBRGPEXH
-
-
-/* Global Functions prototypes */
-/* mvPexInit - Initialize PEX interfaces*/
-MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf);
-
-/* mvPexConfigRead - Read from configuration space */
-MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func,MV_U32 regOff);
-
-/* mvPexConfigWrite - Write to configuration space */
-MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,
- MV_U32 func, MV_U32 regOff, MV_U32 data);
-
-
-#endif /* #ifndef __INCPEXH */
+/*******************************************************************************\r
+Copyright (C) Marvell International Ltd. and its affiliates\r
+\r
+This software file (the "File") is owned and distributed by Marvell \r
+International Ltd. and/or its affiliates ("Marvell") under the following\r
+alternative licensing terms. Once you have made an election to distribute the\r
+File under one of the following license alternatives, please (i) delete this\r
+introductory statement regarding license alternatives, (ii) delete the two\r
+license alternatives that you have not elected to use and (iii) preserve the\r
+Marvell copyright notice above.\r
+\r
+********************************************************************************\r
+Marvell Commercial License Option\r
+\r
+If you received this File from Marvell and you have entered into a commercial\r
+license agreement (a "Commercial License") with Marvell, the File is licensed\r
+to you under the terms of the applicable Commercial License.\r
+\r
+********************************************************************************\r
+Marvell GPL License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File in accordance with the terms and conditions of the General \r
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is \r
+available along with the File in the license.txt file or by writing to the Free \r
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or \r
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt. \r
+\r
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY \r
+DISCLAIMED. The GPL License provides additional details about this warranty \r
+disclaimer.\r
+********************************************************************************\r
+Marvell BSD License Option\r
+\r
+If you received this File from Marvell, you may opt to use, redistribute and/or \r
+modify this File under the following licensing terms. \r
+Redistribution and use in source and binary forms, with or without modification, \r
+are permitted provided that the following conditions are met:\r
+\r
+ * Redistributions of source code must retain the above copyright notice,\r
+ this list of conditions and the following disclaimer. \r
+\r
+ * Redistributions in binary form must reproduce the above copyright\r
+ notice, this list of conditions and the following disclaimer in the\r
+ documentation and/or other materials provided with the distribution. \r
+\r
+ * Neither the name of Marvell nor the names of its contributors may be \r
+ used to endorse or promote products derived from this software without \r
+ specific prior written permission. \r
+ \r
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND \r
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED \r
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE \r
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR \r
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES \r
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; \r
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON \r
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT \r
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS \r
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+\r
+*******************************************************************************/\r
+\r
+#ifndef __INCVRTBRGPEXH\r
+#define __INCVRTBRGPEXH\r
+\r
+\r
+/* Global Functions prototypes */\r
+/* mvPexInit - Initialize PEX interfaces*/\r
+MV_STATUS mvPexVrtBrgInit(MV_U32 pexIf);\r
+\r
+/* mvPexConfigRead - Read from configuration space */\r
+MV_U32 mvPexVrtBrgConfigRead (MV_U32 pexIf, MV_U32 bus, MV_U32 dev,\r
+ MV_U32 func,MV_U32 regOff);\r
+\r
+/* mvPexConfigWrite - Write to configuration space */\r
+MV_STATUS mvPexVrtBrgConfigWrite(MV_U32 pexIf, MV_U32 bus, MV_U32 dev,\r
+ MV_U32 func, MV_U32 regOff, MV_U32 data);\r
+\r
+\r
+#endif /* #ifndef __INCPEXH */\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.3\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.3\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+Global HAL Version: FEROCEON_HAL_3_1_7\r
+Unit HAL Version: 3.1.5\r
+Description: This component includes an implementation of the unit HAL drivers\r
+\r
--- /dev/null
+/*******************************************************************************
+Copyright (C) Marvell International Ltd. and its affiliates
+
+This software file (the "File") is owned and distributed by Marvell
+International Ltd. and/or its affiliates ("Marvell") under the following
+alternative licensing terms. Once you have made an election to distribute the
+File under one of the following license alternatives, please (i) delete this
+introductory statement regarding license alternatives, (ii) delete the two
+license alternatives that you have not elected to use and (iii) preserve the
+Marvell copyright notice above.
+
+********************************************************************************
+Marvell Commercial License Option
+
+If you received this File from Marvell and you have entered into a commercial
+license agreement (a "Commercial License") with Marvell, the File is licensed
+to you under the terms of the applicable Commercial License.
+
+********************************************************************************
+Marvell GPL License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File in accordance with the terms and conditions of the General
+Public License Version 2, June 1991 (the "GPL License"), a copy of which is
+available along with the File in the license.txt file or by writing to the Free
+Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 or
+on the worldwide web at http://www.gnu.org/licenses/gpl.txt.
+
+THE FILE IS DISTRIBUTED AS-IS, WITHOUT WARRANTY OF ANY KIND, AND THE IMPLIED
+WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY
+DISCLAIMED. The GPL License provides additional details about this warranty
+disclaimer.
+********************************************************************************
+Marvell BSD License Option
+
+If you received this File from Marvell, you may opt to use, redistribute and/or
+modify this File under the following licensing terms.
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+ * Redistributions of source code must retain the above copyright notice,
+ this list of conditions and the following disclaimer.
+
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in the
+ documentation and/or other materials provided with the distribution.
+
+ * Neither the name of Marvell nor the names of its contributors may be
+ used to endorse or promote products derived from this software without
+ specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*******************************************************************************/
+
+
+/* includes */
+#define MV_ASMLANGUAGE
+#include "ctrlEnv/mvCtrlEnvSpec.h"
+#include "boardEnv/mvBoardEnvSpec.h"
+#include "mvOsAsm.h"
+#include "mvTwsiSpec.h"
+#include "mvSysHwConfig.h"
+#include "ctrlEnv/sys/mvCpuIfRegs.h"
+#include "mvCommon.h"
+
+#define I2C_CH MV_BOARD_DIMM_I2C_CHANNEL
+
+/* defines */
+/* defines */
+
+
+ .data
+ .global _i2cInit
+ .global _i2cRead
+
+ .text
+
+/*******************************************************************************
+* _i2cInit - Initialize TWSI interface
+*
+* DESCRIPTION:
+* The function performs TWSI interface initialization. It resets the
+* TWSI state machine and initialize its clock to 100KHz assuming Tclock
+* of 133MHz.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+_i2cInit:
+ mov r9, LR /* Save link register */
+ mov r0, #0 /* Make sure r0 is zero */
+
+ /* Reset the i2c Mechanism first */
+ MV_REG_WRITE_ASM (r0, r1, TWSI_SOFT_RESET_REG(I2C_CH))
+
+ bl _twsiDelay
+ bl _twsiDelay
+
+ /* Initializing the I2C mechanism. Assuming Tclock frequency */
+ /* of 166MHz. The I2C frequency in that case will be 100KHz. */
+ /* For this settings, M = 9 and N = 3. Set the baud-rate with the */
+ /* value of 0x2b (freq of ==> 100KHz */
+ /* see spec for more details about the calculation of this value) */
+ mov r6, #(9 << 3 | 3)
+ MV_REG_WRITE_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+
+ /* Enable the I2C master */
+ /* Enable TWSI interrupt in main mask reg */
+ mov r6, #0xC4
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+ /* Let the slow TWSI machine get used to the idea that it is enabled */
+ bl _twsiDelay
+
+
+ mov PC, r9 /* r9 is saved link register */
+
+/*******************************************************************************
+* _twsiDelay - Perform delay.
+*
+* DESCRIPTION:
+* The function performs a delay to enable TWSI logic to stable.
+*
+* INPUT:
+* None.
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* None.
+*
+*******************************************************************************/
+_twsiDelay:
+ mov r10, #0x100000 /*was 0x400*/
+
+_twsiDelayLoop:
+ subs r10, r10, #1
+ bne _twsiDelayLoop
+
+ mov PC, LR
+
+/*******************************************************************************
+* _i2cRead - Read byte from I2C EEPROM device.
+*
+* DESCRIPTION:
+* The function returns a byte from I2C EEPROM device.
+* The EEPROM device is 7-bit address type.
+*
+* INPUT:
+* r4 has the DIMM0 base address with shift 1 bit to the left
+* r7 has the EEPROM offset
+*
+* OUTPUT:
+* None.
+*
+* RETURN:
+* r4 returns '0' if address can not be read.
+* r7 has byte value in case read is successful.
+*
+*******************************************************************************/
+_i2cRead:
+ mov r9, LR /* Save link register */
+
+ /* Transmit the device address and desired offset within the EEPROM. */
+
+ /* Generate Start Bit */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ orr r6, r6, #TWSI_CONTROL_START_BIT
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+ /* Wait for the interrupt flag (bit3) to be set */
+ mov r10, #0x50000
+loop_1:
+ subs r10, r10, #1
+ beq loop_1_timeout
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_1
+
+loop_1_timeout:
+
+ /* Wait for the start bit to be reset by HW */
+ mov r10, #0x50000
+loop_2:
+ subs r10, r10, #1
+ beq loop_2_timeout
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ tst r6, #TWSI_CONTROL_START_BIT
+ bne loop_2
+
+loop_2_timeout:
+
+ /* Wait for the status TWSI_START_CONDITION_TRA = 0x8 */
+ mov r10, #0x50000
+loop_3:
+ subs r10, r10, #1
+ beq loop_3_timeout
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x08
+ bne loop_3
+
+loop_3_timeout:
+
+ /* writing the address of (DIMM0/1 << 1) with write indication */
+ mov r6, r4, LSL #1 /* Write operation address bit 0 must be 0 */
+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
+
+ bl _twsiDelay
+ /* Clear the interrupt flag */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Waiting for the interrupt flag to be set which means that the
+ address has been transmitted */
+loop_4:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_4 /* if tst = 0, then the bit is not set yet */
+
+ /* Wait for status TWSI_ADDR_PLUS_WRITE_BIT_TRA_ACK_REC = 0x18 */
+ mov r10, #0x50000 /* Set r10 to 0x50000 =~ 328,000 */
+
+loop_5:
+ subs r10, r10, #1 /* timeout count down */
+ bne testStatus
+ mov r4, #0 /* r4 = 0 -> operation failed */
+ b exit_i2cRead /* Exit if timeout (No DIMM) */
+
+testStatus:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x18
+ bne loop_5
+
+
+ /* check if the offset is bigger than 256 byte*/
+ tst r7, #0x80000000
+ bne great_than_256
+
+ /* Write the offset to be read from the DIMM EEPROM */
+ MV_REG_WRITE_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
+
+ b after_offset
+
+great_than_256:
+ mov r10, r7, LSR #8
+ and r10, r10, #0xff
+ /* Write the offset0 to be read from the EEPROM */
+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
+
+ /* Clear the interrupt flag ==> signaling that the address can now
+ be transmited */
+
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt to be set again ==> address has transmited */
+loop_6_1:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_6_1
+
+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
+loop_7_1:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x28
+ bne loop_7_1
+
+
+ mov r10, r7
+ and r10, r10, #0xff
+ /* Write the offset1 to be read from the EEPROM */
+ MV_REG_WRITE_ASM (r10, r1, TWSI_DATA_REG(I2C_CH))
+
+
+
+after_offset:
+
+ /* Clear the interrupt flag ==> signaling that the address can now
+ be transmited */
+
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt to be set again ==> address has transmited */
+loop_6:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_6
+
+ /* Wait for status TWSI_MAS_TRAN_DATA_BYTE_ACK_REC = 0x28 */
+loop_7:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x28
+ bne loop_7
+
+ /* Retransmit the device address with read indication to get the data */
+
+ /* generate a repeated start bit */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ orr r6, r6, #TWSI_CONTROL_START_BIT
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+
+ /* Clear the interrupt flag ==> the start bit will be transmitted. */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt flag (bit3) to be set */
+loop_9:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_9
+
+ /* Wait for the start bit to be reset by HW */
+loop_8:
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ tst r6, #TWSI_CONTROL_START_BIT
+ bne loop_8
+
+ /* Wait for status TWSI_REPEATED_START_CONDITION_TRA = 0x10 */
+loop_10:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x10
+ bne loop_10
+
+ /* Writing the address of (DIMM0<<1) with read indication (bit0 is 1) */
+ mov r6, r4, LSL #1
+ orr r6, r6, #1 /* Read operation address bit 0 must be 1 */
+ MV_REG_WRITE_ASM (r6, r1, TWSI_DATA_REG(I2C_CH))
+
+ /* Clear the interrupt flag ==> the address will be transmitted */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt flag (bit3) to be set as a result of
+ transmitting the address. */
+loop_11:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_11
+
+ /* Wait for status TWSI_ADDR_PLUS_READ_BIT_TRA_ACK_REC = 0x40 */
+loop_12:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x40
+ bne loop_12
+
+ /* Clear the interrupt flag and the Acknoledge bit */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #(TWSI_CONTROL_INT_FLAG_SET | TWSI_CONTROL_ACK)
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the interrupt flag (bit3) to be set */
+loop_14:
+#ifdef MV78XX0
+ MV_REG_READ_ASM (r6, r1, CPU_INT_LOW_REG(I2C_CH))
+ tst r6, #BIT2
+#else
+ MV_REG_READ_ASM (r6, r1, CPU_MAIN_INT_CAUSE_REG)
+ tst r6, #BIT5
+#endif
+ beq loop_14
+
+ /* Wait for status TWSI_MAS_REC_READ_DATA_ACK_NOT_TRA = 0x58 */
+loop_15:
+ MV_REG_READ_ASM (r6, r1, TWSI_STATUS_BAUDE_RATE_REG(I2C_CH))
+ cmp r6, #0x58
+ bne loop_15
+
+ /* Store the data in r7. */
+ MV_REG_READ_ASM (r7, r1, TWSI_DATA_REG(I2C_CH))
+
+ /* Generate stop bit */
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ orr r6, r6, #TWSI_CONTROL_STOP_BIT
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+
+
+ /* Clear the interrupt flag */
+ bl _twsiDelay
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bic r6, r6, #TWSI_CONTROL_INT_FLAG_SET
+ MV_REG_WRITE_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ bl _twsiDelay
+
+ /* Wait for the stop bit to be reset by HW */
+loop_16:
+ MV_REG_READ_ASM (r6, r1, TWSI_CONTROL_REG(I2C_CH))
+ tst r6, #TWSI_CONTROL_INT_FLAG_SET
+ bne loop_16
+
+exit_i2cRead:
+ mov PC, r9 /* r9 is saved link register */
#define sg_init_table(sg, n)
+#define sg_mark_end(sg)
+
#endif
#ifndef late_initcall
#include <linux/kthread.h>
#endif
-#include <linux/skbuff.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,2,0)
-static inline struct page *skb_frag_page(const skb_frag_t *frag)
-{
- return frag->page;
-}
+#define skb_frag_page(x) ((x)->page)
#endif
#endif /* __KERNEL__ */
return(-ENODEV);
}
-#ifdef HAVE_PCI_SET_MWI
if (pci_set_mwi(dev)) {
printk("safe: pci_set_mwi failed!");
return(-ENODEV);
}
-#endif
sc = (struct safe_softc *) kmalloc(sizeof(*sc), GFP_KERNEL);
if (!sc)
+++ /dev/null
---- a/kernel/pid.c
-+++ b/kernel/pid.c
-@@ -430,6 +430,7 @@ struct task_struct *find_task_by_vpid(pi
- {
- return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns);
- }
-+EXPORT_SYMBOL(find_task_by_vpid);
-
- struct pid *get_task_pid(struct task_struct *task, enum pid_type type)
- {
---- a/drivers/char/random.c
-+++ b/drivers/char/random.c
-@@ -130,6 +130,9 @@
- * void add_interrupt_randomness(int irq);
- * void add_disk_randomness(struct gendisk *disk);
- *
-+ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
-+ * int random_input_wait(void);
-+ *
- * add_input_randomness() uses the input layer interrupt timing, as well as
- * the event type information from the hardware.
- *
-@@ -147,6 +150,13 @@
- * seek times do not make for good sources of entropy, as their seek
- * times are usually fairly consistent.
- *
-+ * random_input_words() just provides a raw block of entropy to the input
-+ * pool, such as from a hardware entropy generator.
-+ *
-+ * random_input_wait() suspends the caller until such time as the
-+ * entropy pool falls below the write threshold, and returns a count of how
-+ * much entropy (in bits) is needed to sustain the pool.
-+ *
- * All of these routines try to estimate how many bits of randomness a
- * particular randomness source. They do this by keeping track of the
- * first and second order deltas of the event timings.
-@@ -726,6 +736,63 @@ void add_disk_randomness(struct gendisk
- }
- #endif
-
-+/*
-+ * random_input_words - add bulk entropy to pool
-+ *
-+ * @buf: buffer to add
-+ * @wordcount: number of __u32 words to add
-+ * @ent_count: total amount of entropy (in bits) to credit
-+ *
-+ * this provides bulk input of entropy to the input pool
-+ *
-+ */
-+void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
-+{
-+ mix_pool_bytes(&input_pool, buf, wordcount*4);
-+
-+ credit_entropy_bits(&input_pool, ent_count);
-+
-+ DEBUG_ENT("crediting %d bits => %d\n",
-+ ent_count, input_pool.entropy_count);
-+ /*
-+ * Wake up waiting processes if we have enough
-+ * entropy.
-+ */
-+ if (input_pool.entropy_count >= random_read_wakeup_thresh)
-+ wake_up_interruptible(&random_read_wait);
-+}
-+EXPORT_SYMBOL(random_input_words);
-+
-+/*
-+ * random_input_wait - wait until random needs entropy
-+ *
-+ * this function sleeps until the /dev/random subsystem actually
-+ * needs more entropy, and then return the amount of entropy
-+ * that it would be nice to have added to the system.
-+ */
-+int random_input_wait(void)
-+{
-+ int count;
-+
-+ wait_event_interruptible(random_write_wait,
-+ input_pool.entropy_count < random_write_wakeup_thresh);
-+
-+ count = random_write_wakeup_thresh - input_pool.entropy_count;
-+
-+ /* likely we got woken up due to a signal */
-+ if (count <= 0) count = random_read_wakeup_thresh;
-+
-+ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n",
-+ count,
-+ input_pool.entropy_count, random_write_wakeup_thresh);
-+
-+ return count;
-+}
-+EXPORT_SYMBOL(random_input_wait);
-+
-+
-+#define EXTRACT_SIZE 10
-+
- /*********************************************************************
- *
- * Entropy extraction routines
---- a/fs/fcntl.c
-+++ b/fs/fcntl.c
-@@ -142,6 +142,7 @@ SYSCALL_DEFINE1(dup, unsigned int, filde
- }
- return ret;
- }
-+EXPORT_SYMBOL(sys_dup);
-
- #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME)
-
---- a/include/linux/miscdevice.h
-+++ b/include/linux/miscdevice.h
-@@ -19,6 +19,7 @@
- #define APOLLO_MOUSE_MINOR 7
- #define PC110PAD_MINOR 9
- /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */
-+#define CRYPTODEV_MINOR 70 /* /dev/crypto */
- #define WATCHDOG_MINOR 130 /* Watchdog timer */
- #define TEMP_MINOR 131 /* Temperature Sensor */
- #define RTC_MINOR 135
---- a/include/linux/random.h
-+++ b/include/linux/random.h
-@@ -54,6 +54,10 @@ extern void add_input_randomness(unsigne
- unsigned int value);
- extern void add_interrupt_randomness(int irq);
-
-+extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count);
-+extern int random_input_wait(void);
-+#define HAS_RANDOM_INPUT_WAIT 1
-+
- extern void get_random_bytes(void *buf, int nbytes);
- void generate_random_uuid(unsigned char uuid_out[16]);
-
--- /dev/null
+--- a/drivers/char/random.c
++++ b/drivers/char/random.c
+@@ -130,6 +130,9 @@
+ * void add_interrupt_randomness(int irq);
+ * void add_disk_randomness(struct gendisk *disk);
+ *
++ * void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
++ * int random_input_wait(void);
++ *
+ * add_input_randomness() uses the input layer interrupt timing, as well as
+ * the event type information from the hardware.
+ *
+@@ -147,6 +150,13 @@
+ * seek times do not make for good sources of entropy, as their seek
+ * times are usually fairly consistent.
+ *
++ * random_input_words() just provides a raw block of entropy to the input
++ * pool, such as from a hardware entropy generator.
++ *
++ * random_input_wait() suspends the caller until such time as the
++ * entropy pool falls below the write threshold, and returns a count of how
++ * much entropy (in bits) is needed to sustain the pool.
++ *
+ * All of these routines try to estimate how many bits of randomness a
+ * particular randomness source. They do this by keeping track of the
+ * first and second order deltas of the event timings.
+@@ -726,6 +736,63 @@ void add_disk_randomness(struct gendisk
+ }
+ #endif
+
++/*
++ * random_input_words - add bulk entropy to pool
++ *
++ * @buf: buffer to add
++ * @wordcount: number of __u32 words to add
++ * @ent_count: total amount of entropy (in bits) to credit
++ *
++ * this provides bulk input of entropy to the input pool
++ *
++ */
++void random_input_words(__u32 *buf, size_t wordcount, int ent_count)
++{
++ mix_pool_bytes(&input_pool, buf, wordcount*4);
++
++ credit_entropy_bits(&input_pool, ent_count);
++
++ DEBUG_ENT("crediting %d bits => %d\n",
++ ent_count, input_pool.entropy_count);
++ /*
++ * Wake up waiting processes if we have enough
++ * entropy.
++ */
++ if (input_pool.entropy_count >= random_read_wakeup_thresh)
++ wake_up_interruptible(&random_read_wait);
++}
++EXPORT_SYMBOL(random_input_words);
++
++/*
++ * random_input_wait - wait until random needs entropy
++ *
++ * this function sleeps until the /dev/random subsystem actually
++ * needs more entropy, and then return the amount of entropy
++ * that it would be nice to have added to the system.
++ */
++int random_input_wait(void)
++{
++ int count;
++
++ wait_event_interruptible(random_write_wait,
++ input_pool.entropy_count < random_write_wakeup_thresh);
++
++ count = random_write_wakeup_thresh - input_pool.entropy_count;
++
++ /* likely we got woken up due to a signal */
++ if (count <= 0) count = random_read_wakeup_thresh;
++
++ DEBUG_ENT("requesting %d bits from input_wait()er %d<%d\n",
++ count,
++ input_pool.entropy_count, random_write_wakeup_thresh);
++
++ return count;
++}
++EXPORT_SYMBOL(random_input_wait);
++
++
++#define EXTRACT_SIZE 10
++
+ /*********************************************************************
+ *
+ * Entropy extraction routines
+--- a/fs/fcntl.c
++++ b/fs/fcntl.c
+@@ -142,6 +142,7 @@ SYSCALL_DEFINE1(dup, unsigned int, filde
+ }
+ return ret;
+ }
++EXPORT_SYMBOL(sys_dup);
+
+ #define SETFL_MASK (O_APPEND | O_NONBLOCK | O_NDELAY | O_DIRECT | O_NOATIME)
+
+--- a/include/linux/miscdevice.h
++++ b/include/linux/miscdevice.h
+@@ -19,6 +19,7 @@
+ #define APOLLO_MOUSE_MINOR 7
+ #define PC110PAD_MINOR 9
+ /*#define ADB_MOUSE_MINOR 10 FIXME OBSOLETE */
++#define CRYPTODEV_MINOR 70 /* /dev/crypto */
+ #define WATCHDOG_MINOR 130 /* Watchdog timer */
+ #define TEMP_MINOR 131 /* Temperature Sensor */
+ #define RTC_MINOR 135
+--- a/include/linux/random.h
++++ b/include/linux/random.h
+@@ -34,6 +34,30 @@
+ /* Clear the entropy pool and associated counters. (Superuser only.) */
+ #define RNDCLEARPOOL _IO( 'R', 0x06 )
+
++#ifdef CONFIG_FIPS_RNG
++
++/* Size of seed value - equal to AES blocksize */
++#define AES_BLOCK_SIZE_BYTES 16
++#define SEED_SIZE_BYTES AES_BLOCK_SIZE_BYTES
++/* Size of AES key */
++#define KEY_SIZE_BYTES 16
++
++/* ioctl() structure used by FIPS 140-2 Tests */
++struct rand_fips_test {
++ unsigned char key[KEY_SIZE_BYTES]; /* Input */
++ unsigned char datetime[SEED_SIZE_BYTES]; /* Input */
++ unsigned char seed[SEED_SIZE_BYTES]; /* Input */
++ unsigned char result[SEED_SIZE_BYTES]; /* Output */
++};
++
++/* FIPS 140-2 RNG Variable Seed Test. (Superuser only.) */
++#define RNDFIPSVST _IOWR('R', 0x10, struct rand_fips_test)
++
++/* FIPS 140-2 RNG Monte Carlo Test. (Superuser only.) */
++#define RNDFIPSMCT _IOWR('R', 0x11, struct rand_fips_test)
++
++#endif /* #ifdef CONFIG_FIPS_RNG */
++
+ struct rand_pool_info {
+ int entropy_count;
+ int buf_size;
+@@ -54,6 +78,10 @@ extern void add_input_randomness(unsigne
+ unsigned int value);
+ extern void add_interrupt_randomness(int irq);
+
++extern void random_input_words(__u32 *buf, size_t wordcount, int ent_count);
++extern int random_input_wait(void);
++#define HAS_RANDOM_INPUT_WAIT 1
++
+ extern void get_random_bytes(void *buf, int nbytes);
+ void generate_random_uuid(unsigned char uuid_out[16]);
+
+--- a/kernel/pid.c
++++ b/kernel/pid.c
+@@ -430,6 +430,7 @@ struct task_struct *find_task_by_vpid(pi
+ {
+ return find_task_by_pid_ns(vnr, current->nsproxy->pid_ns);
+ }
++EXPORT_SYMBOL(find_task_by_vpid);
+
+ struct pid *get_task_pid(struct task_struct *task, enum pid_type type)
+ {
projects / openwrt / svn-archive / archive.git / commitdiff