brcm63xx: update bmips patches with upstream submission
authorJonas Gorski <jogo@openwrt.org>
Mon, 13 Jan 2014 12:13:05 +0000 (12:13 +0000)
committerJonas Gorski <jogo@openwrt.org>
Mon, 13 Jan 2014 12:13:05 +0000 (12:13 +0000)
Update bmips cleanup patches with upstream submission and backport a few
bmips fixes.

Signed-off-by: Jonas Gorski <jogo@openwrt.org>
SVN-Revision: 39267

28 files changed:
target/linux/brcm63xx/config-3.10
target/linux/brcm63xx/patches-3.10/056-MIPS-BMIPS-Fix-thinko-to-release-slave-TP-from-reset.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/057-MIPS-BMIPS-do-not-change-interrupt-routing-depending.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/058-MIPS-BMIPS-fix-slave-CPU-booting-when-physical-CPU-i.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/060-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/061-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/062-MIPS-BMIPS-change-compile-time-checks-to-runtime-che.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/063-MIPS-BMIPS-merge-CPU-options-into-one-option.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/064-MIPS-BMIPS-select-CPU_SUPPORTS_HIGHMEM.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/065-MIPS-BMIPS-select-CPU_HAS_PREFETCH.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/066-MIPS-BMIPS-extend-BMIPS3300-to-include-BMIPS32.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/067-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/068-MIPS-BCM63XX-always-register-bmips-smp-ops.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/069-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/071-MIPS-BCM63XX-drop-SYS_HAS_CPU_MIPS32R1.patch [new file with mode: 0644]
target/linux/brcm63xx/patches-3.10/100-MIPS-bmips-fix-compilation-for-BMIPS5000.patch
target/linux/brcm63xx/patches-3.10/101-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch [deleted file]
target/linux/brcm63xx/patches-3.10/102-MIPS-bmips-add-macros-for-testing-the-current-bmips-.patch [deleted file]
target/linux/brcm63xx/patches-3.10/103-MIPS-bmips-change-compile-time-checks-to-runtime-che.patch [deleted file]
target/linux/brcm63xx/patches-3.10/104-MIPS-bmips-merge-CPU-options-into-one-option.patch [deleted file]
target/linux/brcm63xx/patches-3.10/105-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch [deleted file]
target/linux/brcm63xx/patches-3.10/106-MIPS-bmips-add-a-helper-function-for-registering-smp.patch [deleted file]
target/linux/brcm63xx/patches-3.10/107-MIPS-BCM63XX-always-register-bmips-smp-ops.patch [deleted file]
target/linux/brcm63xx/patches-3.10/108-MIPS-BCM63XX-change-the-guard-to-a-BMIPS4350-check.patch [deleted file]
target/linux/brcm63xx/patches-3.10/109-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch [deleted file]
target/linux/brcm63xx/patches-3.10/114-MIPS-BCM63XX-introduce-BCM63XX_OHCI-configuration-sy.patch
target/linux/brcm63xx/smp/config-default

index e47a22ad55ff25200ddebff0522be990467a90e4..7234bc465a814aaf63dd0e2349670f5c536891c8 100644 (file)
@@ -37,13 +37,13 @@ CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=squashfs,jffs2 noinitrd console=t
 CONFIG_CMDLINE_BOOL=y
 # CONFIG_CMDLINE_OVERRIDE is not set
 CONFIG_CPU_BIG_ENDIAN=y
-# CONFIG_CPU_BMIPS is not set
+CONFIG_CPU_BMIPS=y
+CONFIG_CPU_BMIPS32_3300=y
+CONFIG_CPU_BMIPS4350=y
 CONFIG_CPU_GENERIC_DUMP_TLB=y
 CONFIG_CPU_HAS_PREFETCH=y
 CONFIG_CPU_HAS_SYNC=y
 CONFIG_CPU_MIPS32=y
-CONFIG_CPU_MIPS32_R1=y
-CONFIG_CPU_MIPSR1=y
 CONFIG_CPU_R4K_CACHE_TLB=y
 CONFIG_CPU_R4K_FPU=y
 CONFIG_CPU_SUPPORTS_32BIT_KERNEL=y
@@ -65,7 +65,6 @@ CONFIG_GPIO_74X164=y
 CONFIG_GPIO_DEVRES=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HAMRADIO is not set
-CONFIG_HARDWARE_WATCHPOINTS=y
 CONFIG_HAS_DMA=y
 CONFIG_HAS_IOMEM=y
 CONFIG_HAS_IOPORT=y
@@ -172,17 +171,19 @@ CONFIG_SSB_SPROM=y
 CONFIG_SWAP_IO_SPACE=y
 CONFIG_SWCONFIG=y
 CONFIG_SYS_HAS_CPU_BMIPS=y
-CONFIG_SYS_HAS_CPU_BMIPS3300=y
+CONFIG_SYS_HAS_CPU_BMIPS32_3300=y
 CONFIG_SYS_HAS_CPU_BMIPS4350=y
-CONFIG_SYS_HAS_CPU_MIPS32_R1=y
 CONFIG_SYS_HAS_EARLY_PRINTK=y
 CONFIG_SYS_SUPPORTS_32BIT_KERNEL=y
 CONFIG_SYS_SUPPORTS_ARBIT_HZ=y
 CONFIG_SYS_SUPPORTS_BIG_ENDIAN=y
+CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
+CONFIG_SYS_SUPPORTS_SMP=y
 CONFIG_TICK_CPU_ACCOUNTING=y
 CONFIG_UIDGID_CONVERTED=y
 CONFIG_USB_ARCH_HAS_XHCI=y
 CONFIG_USB_SUPPORT=y
 CONFIG_VM_EVENT_COUNTERS=y
 CONFIG_WATCHDOG_NOWAYOUT=y
+CONFIG_WEAK_ORDERING=y
 CONFIG_ZONE_DMA_FLAG=0
diff --git a/target/linux/brcm63xx/patches-3.10/056-MIPS-BMIPS-Fix-thinko-to-release-slave-TP-from-reset.patch b/target/linux/brcm63xx/patches-3.10/056-MIPS-BMIPS-Fix-thinko-to-release-slave-TP-from-reset.patch
new file mode 100644 (file)
index 0000000..5865829
--- /dev/null
@@ -0,0 +1,37 @@
+From 976f39b139cdd06a88a5aadd8202b0c30cac9cda Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 17 Jul 2013 17:56:31 +0000
+Subject: [PATCH] MIPS: BMIPS: Fix thinko to release slave TP from reset
+
+Commit 4df715aa ["MIPS: BMIPS: support booting from physical CPU other
+than 0"] introduced a thinko which will prevents slave CPUs from being
+released from reset on systems where we boot from TP0. The problem is
+that we are checking whether the slave CPU logical CPU map is 0, which
+is never true for systems booting from TP0, so we do not release the
+slave TP from reset and we are just stuck. Fix this by properly checking
+that the CPU we intend to boot really is the physical slave CPU (logical
+and physical value being 1).
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: blogic@openwrt.org
+Cc: jogo@openwrt.org
+Cc: cernekee@gmail.com
+Cc: Florian Fainelli <florian@openwrt.org>
+Patchwork: https://patchwork.linux-mips.org/patch/5598/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/kernel/smp-bmips.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -173,7 +173,7 @@ static void bmips_boot_secondary(int cpu
+       else {
+ #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+               /* Reset slave TP1 if booting from TP0 */
+-              if (cpu_logical_map(cpu) == 0)
++              if (cpu_logical_map(cpu) == 1)
+                       set_c0_brcm_cmt_ctrl(0x01);
+ #elif defined(CONFIG_CPU_BMIPS5000)
+               if (cpu & 0x01)
diff --git a/target/linux/brcm63xx/patches-3.10/057-MIPS-BMIPS-do-not-change-interrupt-routing-depending.patch b/target/linux/brcm63xx/patches-3.10/057-MIPS-BMIPS-do-not-change-interrupt-routing-depending.patch
new file mode 100644 (file)
index 0000000..69c7aa0
--- /dev/null
@@ -0,0 +1,41 @@
+From c4091d3fbbed922a3641e5e749655e49cc0d4dee Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 24 Jul 2013 17:12:10 +0100
+Subject: [PATCH] MIPS: BMIPS: do not change interrupt routing depending on
+ boot CPU
+
+Commit 4df715aa ("MIPS: BMIPS: support booting from physical CPU other
+than 0") changed the interupt routing when we are booting from physical
+CPU 0, but the settings are actually correct if we are booting from
+physical CPU 0 or CPU 1. Revert that specific change.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Cc: blogic@openwrt.org
+Patchwork: https://patchwork.linux-mips.org/patch/5622/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/kernel/smp-bmips.c | 8 +-------
+ 1 file changed, 1 insertion(+), 7 deletions(-)
+
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -79,15 +79,9 @@ static void __init bmips_smp_setup(void)
+        * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
+        * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+        * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
+-       *
+-       * If booting from TP1, leave the existing CMT interrupt routing
+-       * such that TP0 responds to SW1 and TP1 responds to SW0.
+        */
+-      if (boot_cpu == 0)
+-              change_c0_brcm_cmt_intr(0xf8018000,
++      change_c0_brcm_cmt_intr(0xf8018000,
+                                       (0x02 << 27) | (0x03 << 15));
+-      else
+-              change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
+       /* single core, 2 threads (2 pipelines) */
+       max_cpus = 2;
diff --git a/target/linux/brcm63xx/patches-3.10/058-MIPS-BMIPS-fix-slave-CPU-booting-when-physical-CPU-i.patch b/target/linux/brcm63xx/patches-3.10/058-MIPS-BMIPS-fix-slave-CPU-booting-when-physical-CPU-i.patch
new file mode 100644 (file)
index 0000000..3df6e87
--- /dev/null
@@ -0,0 +1,58 @@
+From ff5fadaff39180dc0b652753b5614a564711be29 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Wed, 24 Jul 2013 17:12:11 +0100
+Subject: [PATCH] MIPS: BMIPS: fix slave CPU booting when physical CPU is not 0
+
+The current BMIPS SMP code assumes that the slave CPU is physical and
+logical CPU 1, but on some systems such as BCM3368, the slave CPU is
+physical CPU0. Fix the code to read the physical CPU (thread ID) we are
+running this code on, and adjust the relocation vector address based on
+it. This allows bringing up the second CPU on BCM3368 for instance.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: cernekee@gmail.com
+Cc: jogo@openwrt.org
+Cc: blogic@openwrt.org
+Patchwork: https://patchwork.linux-mips.org/patch/5621/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/kernel/bmips_vec.S |  6 +++++-
+ arch/mips/kernel/smp-bmips.c | 10 ++++++++--
+ 2 files changed, 13 insertions(+), 3 deletions(-)
+
+--- a/arch/mips/kernel/bmips_vec.S
++++ b/arch/mips/kernel/bmips_vec.S
+@@ -56,7 +56,11 @@ LEAF(bmips_smp_movevec)
+       /* set up CPU1 CBR; move BASE to 0xa000_0000 */
+       li      k0, 0xff400000
+       mtc0    k0, $22, 6
+-      li      k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_1
++      /* set up relocation vector address based on thread ID */
++      mfc0    k1, $22, 3
++      srl     k1, 16
++      andi    k1, 0x8000
++      or      k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
+       or      k0, k1
+       li      k1, 0xa0080000
+       sw      k1, 0(k0)
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -196,9 +196,15 @@ static void bmips_init_secondary(void)
+ #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+       void __iomem *cbr = BMIPS_GET_CBR();
+       unsigned long old_vec;
++      unsigned long relo_vector;
++      int boot_cpu;
+-      old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+-      __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
++      boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
++      relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
++                        BMIPS_RELO_VECTOR_CONTROL_1;
++
++      old_vec = __raw_readl(cbr + relo_vector);
++      __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
+       clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
+ #elif defined(CONFIG_CPU_BMIPS5000)
diff --git a/target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch b/target/linux/brcm63xx/patches-3.10/059-MIPS-BMIPS-fix-hardware-interrupt-routing-for-boot-C.patch
new file mode 100644 (file)
index 0000000..a838f1a
--- /dev/null
@@ -0,0 +1,48 @@
+From fcfa66de8a2f0631a65a2cec0f6149dafd36ec81 Mon Sep 17 00:00:00 2001
+From: Florian Fainelli <florian@openwrt.org>
+Date: Mon, 5 Aug 2013 11:50:25 +0100
+Subject: [PATCH] MIPS: BMIPS: fix hardware interrupt routing for boot CPU != 0
+
+The hardware interrupt routing for boot CPU != 0 is wrong because it
+will route all the hardware interrupts to TP0 which is not the one we
+booted from. Fix this by properly checking which boot CPU we are booting
+from and updating the right interrupt mask for the boot CPU. This fixes
+booting on BCM3368 with bmips_smp_emabled = 0.
+
+Signed-off-by: Florian Fainelli <florian@openwrt.org>
+Cc: linux-mips@linux-mips.org
+Cc: blogic@openwrt.org
+Cc: jogo@openwrt.org
+Cc: cernekee@gmail.com
+Patchwork: https://patchwork.linux-mips.org/patch/5650/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/kernel/smp-bmips.c | 10 ++++++++--
+ 1 file changed, 8 insertions(+), 2 deletions(-)
+
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -66,6 +66,8 @@ static void __init bmips_smp_setup(void)
+       int i, cpu = 1, boot_cpu = 0;
+ #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
++      int cpu_hw_intr;
++
+       /* arbitration priority */
+       clear_c0_brcm_cmt_ctrl(0x30);
+@@ -80,8 +82,12 @@ static void __init bmips_smp_setup(void)
+        * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+        * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
+        */
+-      change_c0_brcm_cmt_intr(0xf8018000,
+-                                      (0x02 << 27) | (0x03 << 15));
++      if (boot_cpu == 0)
++              cpu_hw_intr = 0x02;
++      else
++              cpu_hw_intr = 0x1d;
++
++      change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
+       /* single core, 2 threads (2 pipelines) */
+       max_cpus = 2;
diff --git a/target/linux/brcm63xx/patches-3.10/060-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch b/target/linux/brcm63xx/patches-3.10/060-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch
new file mode 100644 (file)
index 0000000..b50f0b8
--- /dev/null
@@ -0,0 +1,36 @@
+From 8bd8f46cbc709974b26396aa440133db4484015e Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Fri, 28 Jun 2013 00:25:13 +0200
+Subject: [PATCH V2 01/13] MIPS: BCM63XX: disable SMP also on BCM3368
+
+BCM3368 has the same shared TLB as BCM6358.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/prom.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -64,9 +64,9 @@ void __init prom_init(void)
+               register_smp_ops(&bmips_smp_ops);
+               /*
+-               * BCM6328 might not have its second CPU enabled, while BCM6358
+-               * needs special handling for its shared TLB, so disable SMP
+-               * for now.
++               * BCM6328 might not have its second CPU enabled, while BCM3368
++               * and BCM6358 need special handling for their shared TLB, so
++               * disable SMP for now.
+                */
+               if (BCMCPU_IS_6328()) {
+                       reg = bcm_readl(BCM_6328_OTP_BASE +
+@@ -74,7 +74,7 @@ void __init prom_init(void)
+                       if (reg & OTP_6328_REG3_TP1_DISABLED)
+                               bmips_smp_enabled = 0;
+-              } else if (BCMCPU_IS_6358()) {
++              } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
+                       bmips_smp_enabled = 0;
+               }
diff --git a/target/linux/brcm63xx/patches-3.10/061-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch b/target/linux/brcm63xx/patches-3.10/061-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch
new file mode 100644 (file)
index 0000000..839cb4f
--- /dev/null
@@ -0,0 +1,31 @@
+From 72a1c3ad0392d7b42bf50e6ecade63a775166c73 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 27 Jun 2013 21:32:41 +0200
+Subject: [PATCH V2 02/13] MIPS: allow asm/cpu.h to be included from assembly
+
+Add guards around the enum to allow including cpu.h from assembly.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/include/asm/cpu.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/mips/include/asm/cpu.h
++++ b/arch/mips/include/asm/cpu.h
+@@ -225,6 +225,8 @@
+ #define FPIR_IMP_NONE         0x0000
++#if !defined(__ASSEMBLY__)
++
+ enum cpu_type_enum {
+       CPU_UNKNOWN,
+@@ -277,6 +279,7 @@ enum cpu_type_enum {
+       CPU_LAST
+ };
++#endif /* !__ASSEMBLY */
+ /*
+  * ISA Level encodings
diff --git a/target/linux/brcm63xx/patches-3.10/062-MIPS-BMIPS-change-compile-time-checks-to-runtime-che.patch b/target/linux/brcm63xx/patches-3.10/062-MIPS-BMIPS-change-compile-time-checks-to-runtime-che.patch
new file mode 100644 (file)
index 0000000..a13dffb
--- /dev/null
@@ -0,0 +1,602 @@
+From 7d790bd6cab314462a29ba194e243b8b1d529524 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 27 Jun 2013 21:33:56 +0200
+Subject: [PATCH V2 03/13] MIPS: BMIPS: change compile time checks to runtime
+ checks
+
+Allow building for all bmips cpus at the same time by changing ifdefs
+to checks for the cpu type, or adding appropriate checks to the
+assembly.
+
+Since BMIPS43XX and BMIPS5000 require different IPI implementations,
+split the SMP ops into one for each, so the runtime overhead is only
+at registration time for them.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+V1 -> V2:
+  * use switch (cpu_type()) instead of if () else if () ...
+  * split the smp ops into bmips43xx and bmips5000
+
+ arch/mips/bcm63xx/prom.c      |   2 +-
+ arch/mips/include/asm/bmips.h |   3 +-
+ arch/mips/kernel/bmips_vec.S  |  55 ++++++--
+ arch/mips/kernel/smp-bmips.c  | 312 +++++++++++++++++++++++++-----------------
+ 4 files changed, 235 insertions(+), 137 deletions(-)
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -61,7 +61,7 @@ void __init prom_init(void)
+       if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
+               /* set up SMP */
+-              register_smp_ops(&bmips_smp_ops);
++              register_smp_ops(&bmips43xx_smp_ops);
+               /*
+                * BCM6328 might not have its second CPU enabled, while BCM3368
+--- a/arch/mips/include/asm/bmips.h
++++ b/arch/mips/include/asm/bmips.h
+@@ -47,7 +47,8 @@
+ #include <linux/cpumask.h>
+ #include <asm/r4kcache.h>
+-extern struct plat_smp_ops bmips_smp_ops;
++extern struct plat_smp_ops bmips43xx_smp_ops;
++extern struct plat_smp_ops bmips5000_smp_ops;
+ extern char bmips_reset_nmi_vec;
+ extern char bmips_reset_nmi_vec_end;
+ extern char bmips_smp_movevec;
+--- a/arch/mips/kernel/bmips_vec.S
++++ b/arch/mips/kernel/bmips_vec.S
+@@ -13,6 +13,7 @@
+ #include <asm/asm.h>
+ #include <asm/asmmacro.h>
+ #include <asm/cacheops.h>
++#include <asm/cpu.h>
+ #include <asm/regdef.h>
+ #include <asm/mipsregs.h>
+ #include <asm/stackframe.h>
+@@ -93,12 +94,18 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
+       beqz    k0, bmips_smp_entry
+ #if defined(CONFIG_CPU_BMIPS5000)
++      mfc0    k0, CP0_PRID
++      li      k1, PRID_IMP_BMIPS5000
++      andi    k0, 0xff00
++      bne     k0, k1, 1f
++
+       /* if we're not on core 0, this must be the SMP boot signal */
+       li      k1, (3 << 25)
+       mfc0    k0, $22
+       and     k0, k1
+       bnez    k0, bmips_smp_entry
+-#endif
++1:
++#endif /* CONFIG_CPU_BMIPS5000 */
+ #endif /* CONFIG_SMP */
+       /* nope, it's just a regular NMI */
+@@ -141,7 +148,12 @@ bmips_smp_entry:
+       xori    k0, 0x04
+       mtc0    k0, CP0_CONFIG
++      mfc0    k0, CP0_PRID
++      andi    k0, 0xff00
+ #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
++      li      k1, PRID_IMP_BMIPS43XX
++      bne     k0, k1, 2f
++
+       /* initialize CPU1's local I-cache */
+       li      k0, 0x80000000
+       li      k1, 0x80010000
+@@ -152,14 +164,21 @@ bmips_smp_entry:
+ 1:    cache   Index_Store_Tag_I, 0(k0)
+       addiu   k0, 16
+       bne     k0, k1, 1b
+-#elif defined(CONFIG_CPU_BMIPS5000)
++
++      b       3f
++2:
++#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
++#if defined(CONFIG_CPU_BMIPS5000)
+       /* set exception vector base */
++      li      k1, PRID_IMP_BMIPS5000
++      bne     k0, k1, 3f
++
+       la      k0, ebase
+       lw      k0, 0(k0)
+       mtc0    k0, $15, 1
+       BARRIER
+-#endif
+-
++#endif /* CONFIG_CPU_BMIPS5000 */
++3:
+       /* jump back to kseg0 in case we need to remap the kseg1 area */
+       la      k0, 1f
+       jr      k0
+@@ -225,8 +244,18 @@ END(bmips_smp_int_vec)
+ LEAF(bmips_enable_xks01)
+ #if defined(CONFIG_XKS01)
+-
++      mfc0    t0, CP0_PRID
++      andi    t2, t0, 0xff00
+ #if defined(CONFIG_CPU_BMIPS4380)
++      li      t1, PRID_IMP_BMIPS43XX
++      bne     t2, t1, 1f
++
++      andi    t0, 0xff
++      addiu   t1, t0, -PRID_REV_BMIPS4380_HI
++      bgtz    t1, 2f
++      addiu   t0, -PRID_REV_BMIPS4380_LO
++      bltz    t0, 2f
++
+       mfc0    t0, $22, 3
+       li      t1, 0x1ff0
+       li      t2, (1 << 12) | (1 << 9)
+@@ -235,7 +264,13 @@ LEAF(bmips_enable_xks01)
+       or      t0, t2
+       mtc0    t0, $22, 3
+       BARRIER
+-#elif defined(CONFIG_CPU_BMIPS5000)
++      b       2f
++1:
++#endif /* CONFIG_CPU_BMIPS4380 */
++#if defined(CONFIG_CPU_BMIPS5000)
++      li      t1, PRID_IMP_BMIPS5000
++      bne     t2, t1, 2f
++
+       mfc0    t0, $22, 5
+       li      t1, 0x01ff
+       li      t2, (1 << 8) | (1 << 5)
+@@ -244,12 +279,8 @@ LEAF(bmips_enable_xks01)
+       or      t0, t2
+       mtc0    t0, $22, 5
+       BARRIER
+-#else
+-
+-#error Missing XKS01 setup
+-
+-#endif
+-
++#endif /* CONFIG_CPU_BMIPS5000 */
++2:
+ #endif /* defined(CONFIG_XKS01) */
+       jr      ra
+--- a/arch/mips/kernel/smp-bmips.c
++++ b/arch/mips/kernel/smp-bmips.c
+@@ -49,8 +49,10 @@ cpumask_t bmips_booted_mask;
+ unsigned long bmips_smp_boot_sp;
+ unsigned long bmips_smp_boot_gp;
+-static void bmips_send_ipi_single(int cpu, unsigned int action);
+-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
++static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
++static void bmips5000_send_ipi_single(int cpu, unsigned int action);
++static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
++static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
+ /* SW interrupts 0,1 are used for interprocessor signaling */
+ #define IPI0_IRQ                      (MIPS_CPU_IRQ_BASE + 0)
+@@ -64,49 +66,58 @@ static irqreturn_t bmips_ipi_interrupt(i
+ static void __init bmips_smp_setup(void)
+ {
+       int i, cpu = 1, boot_cpu = 0;
+-
+-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+       int cpu_hw_intr;
+-      /* arbitration priority */
+-      clear_c0_brcm_cmt_ctrl(0x30);
+-
+-      /* NBK and weak order flags */
+-      set_c0_brcm_config_0(0x30000);
+-
+-      /* Find out if we are running on TP0 or TP1 */
+-      boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
+-
+-      /*
+-       * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
+-       * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
+-       * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
+-       */
+-      if (boot_cpu == 0)
+-              cpu_hw_intr = 0x02;
+-      else
+-              cpu_hw_intr = 0x1d;
+-
+-      change_c0_brcm_cmt_intr(0xf8018000, (cpu_hw_intr << 27) | (0x03 << 15));
+-
+-      /* single core, 2 threads (2 pipelines) */
+-      max_cpus = 2;
+-#elif defined(CONFIG_CPU_BMIPS5000)
+-      /* enable raceless SW interrupts */
+-      set_c0_brcm_config(0x03 << 22);
+-
+-      /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
+-      change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
+-
+-      /* N cores, 2 threads per core */
+-      max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
++      switch (current_cpu_type()) {
++      case CPU_BMIPS4350:
++      case CPU_BMIPS4380:
++              /* arbitration priority */
++              clear_c0_brcm_cmt_ctrl(0x30);
++
++              /* NBK and weak order flags */
++              set_c0_brcm_config_0(0x30000);
++
++              /* Find out if we are running on TP0 or TP1 */
++              boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
++
++              /*
++               * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
++               * thread
++               * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
++               * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
++               */
++              if (boot_cpu == 0)
++                      cpu_hw_intr = 0x02;
++              else
++                      cpu_hw_intr = 0x1d;
++
++              change_c0_brcm_cmt_intr(0xf8018000,
++                                      (cpu_hw_intr << 27) | (0x03 << 15));
++
++              /* single core, 2 threads (2 pipelines) */
++              max_cpus = 2;
++
++              break;
++      case CPU_BMIPS5000:
++              /* enable raceless SW interrupts */
++              set_c0_brcm_config(0x03 << 22);
++
++              /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
++              change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
++
++              /* N cores, 2 threads per core */
++              max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
++
++              /* clear any pending SW interrupts */
++              for (i = 0; i < max_cpus; i++) {
++                      write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
++                      write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
++              }
+-      /* clear any pending SW interrupts */
+-      for (i = 0; i < max_cpus; i++) {
+-              write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
+-              write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
++              break;
++      default:
++              max_cpus = 1;
+       }
+-#endif
+       if (!bmips_smp_enabled)
+               max_cpus = 1;
+@@ -134,6 +145,20 @@ static void __init bmips_smp_setup(void)
+  */
+ static void bmips_prepare_cpus(unsigned int max_cpus)
+ {
++      irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
++
++      switch (current_cpu_type()) {
++      case CPU_BMIPS4350:
++      case CPU_BMIPS4380:
++              bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
++              break;
++      case CPU_BMIPS5000:
++              bmips_ipi_interrupt = bmips5000_ipi_interrupt;
++              break;
++      default:
++              return;
++      }
++
+       if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
+                       "smp_ipi0", NULL))
+               panic("Can't request IPI0 interrupt\n");
+@@ -168,26 +193,39 @@ static void bmips_boot_secondary(int cpu
+       pr_info("SMP: Booting CPU%d...\n", cpu);
+-      if (cpumask_test_cpu(cpu, &bmips_booted_mask))
+-              bmips_send_ipi_single(cpu, 0);
++      if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
++              switch (current_cpu_type()) {
++              case CPU_BMIPS4350:
++              case CPU_BMIPS4380:
++                      bmips43xx_send_ipi_single(cpu, 0);
++                      break;
++              case CPU_BMIPS5000:
++                      bmips5000_send_ipi_single(cpu, 0);
++                      break;
++              }
++      }
+       else {
+-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+-              /* Reset slave TP1 if booting from TP0 */
+-              if (cpu_logical_map(cpu) == 1)
+-                      set_c0_brcm_cmt_ctrl(0x01);
+-#elif defined(CONFIG_CPU_BMIPS5000)
+-              if (cpu & 0x01)
+-                      write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
+-              else {
+-                      /*
+-                       * core N thread 0 was already booted; just
+-                       * pulse the NMI line
+-                       */
+-                      bmips_write_zscm_reg(0x210, 0xc0000000);
+-                      udelay(10);
+-                      bmips_write_zscm_reg(0x210, 0x00);
++              switch (current_cpu_type()) {
++              case CPU_BMIPS4350:
++              case CPU_BMIPS4380:
++                      /* Reset slave TP1 if booting from TP0 */
++                      if (cpu_logical_map(cpu) == 1)
++                              set_c0_brcm_cmt_ctrl(0x01);
++                      break;
++              case CPU_BMIPS5000:
++                      if (cpu & 0x01)
++                              write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
++                      else {
++                              /*
++                               * core N thread 0 was already booted; just
++                               * pulse the NMI line
++                               */
++                              bmips_write_zscm_reg(0x210, 0xc0000000);
++                              udelay(10);
++                              bmips_write_zscm_reg(0x210, 0x00);
++                      }
++                      break;
+               }
+-#endif
+               cpumask_set_cpu(cpu, &bmips_booted_mask);
+       }
+ }
+@@ -199,26 +237,32 @@ static void bmips_init_secondary(void)
+ {
+       /* move NMI vector to kseg0, in case XKS01 is enabled */
+-#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
+-      void __iomem *cbr = BMIPS_GET_CBR();
++      void __iomem *cbr;
+       unsigned long old_vec;
+       unsigned long relo_vector;
+       int boot_cpu;
+-      boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
+-      relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
+-                        BMIPS_RELO_VECTOR_CONTROL_1;
+-
+-      old_vec = __raw_readl(cbr + relo_vector);
+-      __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
+-
+-      clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
+-#elif defined(CONFIG_CPU_BMIPS5000)
+-      write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
+-              (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
++      switch (current_cpu_type()) {
++      case CPU_BMIPS4350:
++      case CPU_BMIPS4380:
++              cbr = BMIPS_GET_CBR();
++
++              boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
++              relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
++                                BMIPS_RELO_VECTOR_CONTROL_1;
++
++              old_vec = __raw_readl(cbr + relo_vector);
++              __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
++
++              clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
++              break;
++      case CPU_BMIPS5000:
++              write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
++                      (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
+-      write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
+-#endif
++              write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
++              break;
++      }
+ }
+ /*
+@@ -243,8 +287,6 @@ static void bmips_cpus_done(void)
+ {
+ }
+-#if defined(CONFIG_CPU_BMIPS5000)
+-
+ /*
+  * BMIPS5000 raceless IPIs
+  *
+@@ -253,12 +295,12 @@ static void bmips_cpus_done(void)
+  * IPI1 is used for SMP_CALL_FUNCTION
+  */
+-static void bmips_send_ipi_single(int cpu, unsigned int action)
++static void bmips5000_send_ipi_single(int cpu, unsigned int action)
+ {
+       write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
+ }
+-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
++static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
+ {
+       int action = irq - IPI0_IRQ;
+@@ -272,7 +314,14 @@ static irqreturn_t bmips_ipi_interrupt(i
+       return IRQ_HANDLED;
+ }
+-#else
++static void bmips5000_send_ipi_mask(const struct cpumask *mask,
++      unsigned int action)
++{
++      unsigned int i;
++
++      for_each_cpu(i, mask)
++              bmips5000_send_ipi_single(i, action);
++}
+ /*
+  * BMIPS43xx racey IPIs
+@@ -287,7 +336,7 @@ static irqreturn_t bmips_ipi_interrupt(i
+ static DEFINE_SPINLOCK(ipi_lock);
+ static DEFINE_PER_CPU(int, ipi_action_mask);
+-static void bmips_send_ipi_single(int cpu, unsigned int action)
++static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
+ {
+       unsigned long flags;
+@@ -298,7 +347,7 @@ static void bmips_send_ipi_single(int cp
+       spin_unlock_irqrestore(&ipi_lock, flags);
+ }
+-static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
++static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
+ {
+       unsigned long flags;
+       int action, cpu = irq - IPI0_IRQ;
+@@ -317,15 +366,13 @@ static irqreturn_t bmips_ipi_interrupt(i
+       return IRQ_HANDLED;
+ }
+-#endif /* BMIPS type */
+-
+-static void bmips_send_ipi_mask(const struct cpumask *mask,
++static void bmips43xx_send_ipi_mask(const struct cpumask *mask,
+       unsigned int action)
+ {
+       unsigned int i;
+       for_each_cpu(i, mask)
+-              bmips_send_ipi_single(i, action);
++              bmips43xx_send_ipi_single(i, action);
+ }
+ #ifdef CONFIG_HOTPLUG_CPU
+@@ -381,15 +428,30 @@ void __ref play_dead(void)
+ #endif /* CONFIG_HOTPLUG_CPU */
+-struct plat_smp_ops bmips_smp_ops = {
++struct plat_smp_ops bmips43xx_smp_ops = {
++      .smp_setup              = bmips_smp_setup,
++      .prepare_cpus           = bmips_prepare_cpus,
++      .boot_secondary         = bmips_boot_secondary,
++      .smp_finish             = bmips_smp_finish,
++      .init_secondary         = bmips_init_secondary,
++      .cpus_done              = bmips_cpus_done,
++      .send_ipi_single        = bmips43xx_send_ipi_single,
++      .send_ipi_mask          = bmips43xx_send_ipi_mask,
++#ifdef CONFIG_HOTPLUG_CPU
++      .cpu_disable            = bmips_cpu_disable,
++      .cpu_die                = bmips_cpu_die,
++#endif
++};
++
++struct plat_smp_ops bmips5000_smp_ops = {
+       .smp_setup              = bmips_smp_setup,
+       .prepare_cpus           = bmips_prepare_cpus,
+       .boot_secondary         = bmips_boot_secondary,
+       .smp_finish             = bmips_smp_finish,
+       .init_secondary         = bmips_init_secondary,
+       .cpus_done              = bmips_cpus_done,
+-      .send_ipi_single        = bmips_send_ipi_single,
+-      .send_ipi_mask          = bmips_send_ipi_mask,
++      .send_ipi_single        = bmips5000_send_ipi_single,
++      .send_ipi_mask          = bmips5000_send_ipi_mask,
+ #ifdef CONFIG_HOTPLUG_CPU
+       .cpu_disable            = bmips_cpu_disable,
+       .cpu_die                = bmips_cpu_die,
+@@ -427,43 +489,47 @@ void __cpuinit bmips_ebase_setup(void)
+       BUG_ON(ebase != CKSEG0);
+-#if defined(CONFIG_CPU_BMIPS4350)
+-      /*
+-       * BMIPS4350 cannot relocate the normal vectors, but it
+-       * can relocate the BEV=1 vectors.  So CPU1 starts up at
+-       * the relocated BEV=1, IV=0 general exception vector @
+-       * 0xa000_0380.
+-       *
+-       * set_uncached_handler() is used here because:
+-       *  - CPU1 will run this from uncached space
+-       *  - None of the cacheflush functions are set up yet
+-       */
+-      set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
+-              &bmips_smp_int_vec, 0x80);
+-      __sync();
+-      return;
+-#elif defined(CONFIG_CPU_BMIPS4380)
+-      /*
+-       * 0x8000_0000: reset/NMI (initially in kseg1)
+-       * 0x8000_0400: normal vectors
+-       */
+-      new_ebase = 0x80000400;
+-      cbr = BMIPS_GET_CBR();
+-      __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
+-      __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
+-#elif defined(CONFIG_CPU_BMIPS5000)
+-      /*
+-       * 0x8000_0000: reset/NMI (initially in kseg1)
+-       * 0x8000_1000: normal vectors
+-       */
+-      new_ebase = 0x80001000;
+-      write_c0_brcm_bootvec(0xa0088008);
+-      write_c0_ebase(new_ebase);
+-      if (max_cpus > 2)
+-              bmips_write_zscm_reg(0xa0, 0xa008a008);
+-#else
+-      return;
+-#endif
++      switch (current_cpu_type()) {
++      case CPU_BMIPS4350:
++              /*
++               * BMIPS4350 cannot relocate the normal vectors, but it
++               * can relocate the BEV=1 vectors.  So CPU1 starts up at
++               * the relocated BEV=1, IV=0 general exception vector @
++               * 0xa000_0380.
++               *
++               * set_uncached_handler() is used here because:
++               *  - CPU1 will run this from uncached space
++               *  - None of the cacheflush functions are set up yet
++               */
++              set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
++                      &bmips_smp_int_vec, 0x80);
++              __sync();
++              return;
++      case CPU_BMIPS4380:
++              /*
++               * 0x8000_0000: reset/NMI (initially in kseg1)
++               * 0x8000_0400: normal vectors
++               */
++              new_ebase = 0x80000400;
++              cbr = BMIPS_GET_CBR();
++              __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
++              __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
++              break;
++      case CPU_BMIPS5000:
++              /*
++               * 0x8000_0000: reset/NMI (initially in kseg1)
++               * 0x8000_1000: normal vectors
++               */
++              new_ebase = 0x80001000;
++              write_c0_brcm_bootvec(0xa0088008);
++              write_c0_ebase(new_ebase);
++              if (max_cpus > 2)
++                      bmips_write_zscm_reg(0xa0, 0xa008a008);
++              break;
++      default:
++              return;
++      }
++
+       board_nmi_handler_setup = &bmips_nmi_handler_setup;
+       ebase = new_ebase;
+ }
diff --git a/target/linux/brcm63xx/patches-3.10/063-MIPS-BMIPS-merge-CPU-options-into-one-option.patch b/target/linux/brcm63xx/patches-3.10/063-MIPS-BMIPS-merge-CPU-options-into-one-option.patch
new file mode 100644 (file)
index 0000000..136b773
--- /dev/null
@@ -0,0 +1,137 @@
+From 81d6f5e024884ce904b7bd36fec60291d751df48 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 27 Jun 2013 23:57:20 +0200
+Subject: [PATCH V2 04/13] MIPS: BMIPS: merge CPU options into one option
+
+Instead of treating each flavour as an exclusive CPU to select, make
+BMIPS the only option and let SYS_HAS_CPU_BMIPS* decide for which
+flavours to include support.
+
+Run tested on BMIPS3300 and BMIPS4350, only build tested for BMIPS4380
+and BMIPS5000.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+V1 -> V2:
+ * Let the SYS_HAS_CPU_BMIPS* symbols select SYS_HAS_CPU_BMIPS instead of
+   requiring users to select it
+
+ arch/mips/Kconfig | 80 +++++++++++++++++++++++++++----------------------------
+ 1 file changed, 39 insertions(+), 41 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1453,41 +1453,21 @@ config CPU_CAVIUM_OCTEON
+         can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
+         Full details can be found at http://www.caviumnetworks.com.
+-config CPU_BMIPS3300
+-      bool "BMIPS3300"
+-      depends on SYS_HAS_CPU_BMIPS3300
+-      select CPU_BMIPS
+-      help
+-        Broadcom BMIPS3300 processors.
+-
+-config CPU_BMIPS4350
+-      bool "BMIPS4350"
+-      depends on SYS_HAS_CPU_BMIPS4350
+-      select CPU_BMIPS
+-      select SYS_SUPPORTS_SMP
+-      select SYS_SUPPORTS_HOTPLUG_CPU
+-      help
+-        Broadcom BMIPS4350 ("VIPER") processors.
+-
+-config CPU_BMIPS4380
+-      bool "BMIPS4380"
+-      depends on SYS_HAS_CPU_BMIPS4380
+-      select CPU_BMIPS
+-      select SYS_SUPPORTS_SMP
+-      select SYS_SUPPORTS_HOTPLUG_CPU
+-      help
+-        Broadcom BMIPS4380 processors.
+-
+-config CPU_BMIPS5000
+-      bool "BMIPS5000"
+-      depends on SYS_HAS_CPU_BMIPS5000
+-      select CPU_BMIPS
+-      select CPU_SUPPORTS_HIGHMEM
+-      select MIPS_CPU_SCACHE
+-      select SYS_SUPPORTS_SMP
+-      select SYS_SUPPORTS_HOTPLUG_CPU
++config CPU_BMIPS
++      bool "Broadcom BMIPS"
++      depends on SYS_HAS_CPU_BMIPS
++      select CPU_MIPS32
++      select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300
++      select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
++      select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
++      select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
++      select CPU_SUPPORTS_32BIT_KERNEL
++      select DMA_NONCOHERENT
++      select IRQ_CPU
++      select SWAP_IO_SPACE
++      select WEAK_ORDERING
+       help
+-        Broadcom BMIPS5000 processors.
++        Support for BMIPS3300/4350/4380 and BMIPS5000 processors.
+ config CPU_XLR
+       bool "Netlogic XLR SoC"
+@@ -1568,14 +1548,25 @@ config CPU_LOONGSON1
+       select CPU_SUPPORTS_32BIT_KERNEL
+       select CPU_SUPPORTS_HIGHMEM
+-config CPU_BMIPS
++config CPU_BMIPS3300
+       bool
+-      select CPU_MIPS32
+-      select CPU_SUPPORTS_32BIT_KERNEL
+-      select DMA_NONCOHERENT
+-      select IRQ_CPU
+-      select SWAP_IO_SPACE
+-      select WEAK_ORDERING
++
++config CPU_BMIPS4350
++      bool
++      select SYS_SUPPORTS_SMP
++      select SYS_SUPPORTS_HOTPLUG_CPU
++
++config CPU_BMIPS4380
++      bool
++      select SYS_SUPPORTS_SMP
++      select SYS_SUPPORTS_HOTPLUG_CPU
++
++config CPU_BMIPS5000
++      bool
++      select CPU_SUPPORTS_HIGHMEM
++      select MIPS_CPU_SCACHE
++      select SYS_SUPPORTS_SMP
++      select SYS_SUPPORTS_HOTPLUG_CPU
+ config SYS_HAS_CPU_LOONGSON2E
+       bool
+@@ -1649,17 +1640,24 @@ config SYS_HAS_CPU_SB1
+ config SYS_HAS_CPU_CAVIUM_OCTEON
+       bool
++config SYS_HAS_CPU_BMIPS
++      bool
++
+ config SYS_HAS_CPU_BMIPS3300
+       bool
++      select SYS_HAS_CPU_BMIPS
+ config SYS_HAS_CPU_BMIPS4350
+       bool
++      select SYS_HAS_CPU_BMIPS
+ config SYS_HAS_CPU_BMIPS4380
+       bool
++      select SYS_HAS_CPU_BMIPS
+ config SYS_HAS_CPU_BMIPS5000
+       bool
++      select SYS_HAS_CPU_BMIPS
+ config SYS_HAS_CPU_XLR
+       bool
diff --git a/target/linux/brcm63xx/patches-3.10/064-MIPS-BMIPS-select-CPU_SUPPORTS_HIGHMEM.patch b/target/linux/brcm63xx/patches-3.10/064-MIPS-BMIPS-select-CPU_SUPPORTS_HIGHMEM.patch
new file mode 100644 (file)
index 0000000..f10d544
--- /dev/null
@@ -0,0 +1,30 @@
+From 89d4a38dde99a6b141e90860fca594a9ac66336b Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 16 Jul 2013 14:02:57 +0200
+Subject: [PATCH V2 05/13] MIPS: BMIPS: select CPU_SUPPORTS_HIGHMEM
+
+All BMIPS CPUs support HIGHMEM, so it should be selected by CPU_BMIPS.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1466,6 +1466,7 @@ config CPU_BMIPS
+       select IRQ_CPU
+       select SWAP_IO_SPACE
+       select WEAK_ORDERING
++      select CPU_SUPPORTS_HIGHMEM
+       help
+         Support for BMIPS3300/4350/4380 and BMIPS5000 processors.
+@@ -1563,7 +1564,6 @@ config CPU_BMIPS4380
+ config CPU_BMIPS5000
+       bool
+-      select CPU_SUPPORTS_HIGHMEM
+       select MIPS_CPU_SCACHE
+       select SYS_SUPPORTS_SMP
+       select SYS_SUPPORTS_HOTPLUG_CPU
diff --git a/target/linux/brcm63xx/patches-3.10/065-MIPS-BMIPS-select-CPU_HAS_PREFETCH.patch b/target/linux/brcm63xx/patches-3.10/065-MIPS-BMIPS-select-CPU_HAS_PREFETCH.patch
new file mode 100644 (file)
index 0000000..c5c8ecf
--- /dev/null
@@ -0,0 +1,22 @@
+From 58827e709eb7a2e0899260893a5c9c58eb0c5db1 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Tue, 16 Jul 2013 14:04:40 +0200
+Subject: [PATCH V2 06/13] MIPS: BMIPS: select CPU_HAS_PREFETCH
+
+As they are MIPS32 CPUs they do support the prefetch opcode.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1467,6 +1467,7 @@ config CPU_BMIPS
+       select SWAP_IO_SPACE
+       select WEAK_ORDERING
+       select CPU_SUPPORTS_HIGHMEM
++      select CPU_HAS_PREFETCH
+       help
+         Support for BMIPS3300/4350/4380 and BMIPS5000 processors.
diff --git a/target/linux/brcm63xx/patches-3.10/066-MIPS-BMIPS-extend-BMIPS3300-to-include-BMIPS32.patch b/target/linux/brcm63xx/patches-3.10/066-MIPS-BMIPS-extend-BMIPS3300-to-include-BMIPS32.patch
new file mode 100644 (file)
index 0000000..6cdb14a
--- /dev/null
@@ -0,0 +1,52 @@
+From e742d5b77ec18926293ec5d101470522f67ee159 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 15 Aug 2013 12:10:11 +0200
+Subject: [PATCH V2 07/13] MIPS: BMIPS: extend BMIPS3300 to include BMIPS32
+
+Codewise there is no difference between these two, so it does not make
+sense to treat them differently. Also chip families having one of these
+tend to have the other.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1457,7 +1457,7 @@ config CPU_BMIPS
+       bool "Broadcom BMIPS"
+       depends on SYS_HAS_CPU_BMIPS
+       select CPU_MIPS32
+-      select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300
++      select CPU_BMIPS32_3300 if SYS_HAS_CPU_BMIPS32_3300
+       select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
+       select CPU_BMIPS4380 if SYS_HAS_CPU_BMIPS4380
+       select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
+@@ -1469,7 +1469,7 @@ config CPU_BMIPS
+       select CPU_SUPPORTS_HIGHMEM
+       select CPU_HAS_PREFETCH
+       help
+-        Support for BMIPS3300/4350/4380 and BMIPS5000 processors.
++        Support for BMIPS32/3300/4350/4380 and BMIPS5000 processors.
+ config CPU_XLR
+       bool "Netlogic XLR SoC"
+@@ -1550,7 +1550,7 @@ config CPU_LOONGSON1
+       select CPU_SUPPORTS_32BIT_KERNEL
+       select CPU_SUPPORTS_HIGHMEM
+-config CPU_BMIPS3300
++config CPU_BMIPS32_3300
+       bool
+ config CPU_BMIPS4350
+@@ -1644,7 +1644,7 @@ config SYS_HAS_CPU_CAVIUM_OCTEON
+ config SYS_HAS_CPU_BMIPS
+       bool
+-config SYS_HAS_CPU_BMIPS3300
++config SYS_HAS_CPU_BMIPS32_3300
+       bool
+       select SYS_HAS_CPU_BMIPS
diff --git a/target/linux/brcm63xx/patches-3.10/067-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch b/target/linux/brcm63xx/patches-3.10/067-MIPS-BMIPS-add-a-smp-ops-registration-helper.patch
new file mode 100644 (file)
index 0000000..2d4f5cd
--- /dev/null
@@ -0,0 +1,77 @@
+From 0b135a3e8f344061ed0aa66e2514627dd7aa946f Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 23 Jun 2013 14:04:51 +0200
+Subject: [PATCH V2 08/13] MIPS: BMIPS: add a smp ops registration helper
+
+Add a helper similar to the generic register_XXX_smp_ops() for bmips.
+Register SMP UP ops in case of BMIPS32/3300.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+V1 -> V2:
+ * use SMP_UP (ops) in case of BMIPS32_3300
+
+ arch/mips/Kconfig             |  1 +
+ arch/mips/bcm63xx/prom.c      |  2 +-
+ arch/mips/include/asm/bmips.h | 26 ++++++++++++++++++++++++++
+ 3 files changed, 28 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -1551,6 +1551,7 @@ config CPU_LOONGSON1
+       select CPU_SUPPORTS_HIGHMEM
+ config CPU_BMIPS32_3300
++      select SMP_UP if SMP
+       bool
+ config CPU_BMIPS4350
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -61,7 +61,7 @@ void __init prom_init(void)
+       if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
+               /* set up SMP */
+-              register_smp_ops(&bmips43xx_smp_ops);
++              register_bmips_smp_ops();
+               /*
+                * BCM6328 might not have its second CPU enabled, while BCM3368
+--- a/arch/mips/include/asm/bmips.h
++++ b/arch/mips/include/asm/bmips.h
+@@ -46,9 +46,35 @@
+ #include <linux/cpumask.h>
+ #include <asm/r4kcache.h>
++#include <asm/smp-ops.h>
+ extern struct plat_smp_ops bmips43xx_smp_ops;
+ extern struct plat_smp_ops bmips5000_smp_ops;
++
++static inline int register_bmips_smp_ops(void)
++{
++#if IS_ENABLED(CONFIG_CPU_BMIPS) && IS_ENABLED(CONFIG_SMP)
++      switch (current_cpu_type()) {
++      case CPU_BMIPS32:
++      case CPU_BMIPS3300:
++              return register_up_smp_ops();
++      case CPU_BMIPS4350:
++      case CPU_BMIPS4380:
++              register_smp_ops(&bmips43xx_smp_ops);
++              break;
++      case CPU_BMIPS5000:
++              register_smp_ops(&bmips5000_smp_ops);
++              break;
++      default:
++              return -ENODEV;
++      }
++
++      return 0;
++#else
++      return -ENODEV;
++#endif
++}
++
+ extern char bmips_reset_nmi_vec;
+ extern char bmips_reset_nmi_vec_end;
+ extern char bmips_smp_movevec;
diff --git a/target/linux/brcm63xx/patches-3.10/068-MIPS-BCM63XX-always-register-bmips-smp-ops.patch b/target/linux/brcm63xx/patches-3.10/068-MIPS-BCM63XX-always-register-bmips-smp-ops.patch
new file mode 100644 (file)
index 0000000..6590185
--- /dev/null
@@ -0,0 +1,27 @@
+From 08181bee8ee375225129d086656c567022becf41 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Fri, 28 Jun 2013 00:08:16 +0200
+Subject: [PATCH V2 09/13] MIPS: BCM63XX: always register bmips smp ops
+
+Use the return value for guarding further SMP setup.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/bcm63xx/prom.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/mips/bcm63xx/prom.c
++++ b/arch/mips/bcm63xx/prom.c
+@@ -59,10 +59,8 @@ void __init prom_init(void)
+       /* do low level board init */
+       board_prom_init();
+-      if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
+-              /* set up SMP */
+-              register_bmips_smp_ops();
+-
++      /* set up SMP */
++      if (!register_bmips_smp_ops()) {
+               /*
+                * BCM6328 might not have its second CPU enabled, while BCM3368
+                * and BCM6358 need special handling for their shared TLB, so
diff --git a/target/linux/brcm63xx/patches-3.10/069-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch b/target/linux/brcm63xx/patches-3.10/069-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch
new file mode 100644 (file)
index 0000000..3ce160e
--- /dev/null
@@ -0,0 +1,70 @@
+From 949b88531a779af4f6456ff43d3de2d4f74e44ee Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Sun, 23 Jun 2013 12:25:49 +0200
+Subject: [PATCH V2 10/13] MIPS: BCM63XX: let the individual SoCs select the
+ appropriate CPUs
+
+Let each supported chip select the appropirate SYS_HAS_CPU_BMIPS*
+option for its embedded processor, so support will be conditionally
+included.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig         | 1 -
+ arch/mips/bcm63xx/Kconfig | 8 ++++++++
+ 2 files changed, 8 insertions(+), 1 deletion(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -130,7 +130,6 @@ config BCM63XX
+       select DMA_NONCOHERENT
+       select IRQ_CPU
+       select SYS_HAS_CPU_MIPS32_R1
+-      select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
+       select NR_CPUS_DEFAULT_2
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
+--- a/arch/mips/bcm63xx/Kconfig
++++ b/arch/mips/bcm63xx/Kconfig
+@@ -3,33 +3,41 @@ menu "CPU support"
+ config BCM63XX_CPU_3368
+       bool "support 3368 CPU"
++      select SYS_HAS_CPU_BMIPS4350
+       select HW_HAS_PCI
+ config BCM63XX_CPU_6328
+       bool "support 6328 CPU"
++      select SYS_HAS_CPU_BMIPS4350
+       select HW_HAS_PCI
+ config BCM63XX_CPU_6338
+       bool "support 6338 CPU"
++      select SYS_HAS_CPU_BMIPS32_3300
+       select HW_HAS_PCI
+ config BCM63XX_CPU_6345
+       bool "support 6345 CPU"
++      select SYS_HAS_CPU_BMIPS32_3300
+ config BCM63XX_CPU_6348
+       bool "support 6348 CPU"
++      select SYS_HAS_CPU_BMIPS32_3300
+       select HW_HAS_PCI
+ config BCM63XX_CPU_6358
+       bool "support 6358 CPU"
++      select SYS_HAS_CPU_BMIPS4350
+       select HW_HAS_PCI
+ config BCM63XX_CPU_6362
+       bool "support 6362 CPU"
++      select SYS_HAS_CPU_BMIPS4350
+       select HW_HAS_PCI
+ config BCM63XX_CPU_6368
+       bool "support 6368 CPU"
++      select SYS_HAS_CPU_BMIPS4350
+       select HW_HAS_PCI
+ endmenu
diff --git a/target/linux/brcm63xx/patches-3.10/071-MIPS-BCM63XX-drop-SYS_HAS_CPU_MIPS32R1.patch b/target/linux/brcm63xx/patches-3.10/071-MIPS-BCM63XX-drop-SYS_HAS_CPU_MIPS32R1.patch
new file mode 100644 (file)
index 0000000..26a0ada
--- /dev/null
@@ -0,0 +1,24 @@
+From c6c4897703d825c9efea6d9a708aaa080c8c3177 Mon Sep 17 00:00:00 2001
+From: Jonas Gorski <jogo@openwrt.org>
+Date: Thu, 17 Oct 2013 13:16:08 +0200
+Subject: [PATCH V2 13/13] MIPS: BCM63XX: drop SYS_HAS_CPU_MIPS32R1
+
+All MIPS cores on BCM63XX identify as Broadcom, not MIPS, so no need
+to support non-broadcom MIPS CPUs. This also ensures that CPU_BMIPS
+is always selected.
+
+Signed-off-by: Jonas Gorski <jogo@openwrt.org>
+---
+ arch/mips/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/mips/Kconfig
++++ b/arch/mips/Kconfig
+@@ -129,7 +129,6 @@ config BCM63XX
+       select CSRC_R4K
+       select DMA_NONCOHERENT
+       select IRQ_CPU
+-      select SYS_HAS_CPU_MIPS32_R1
+       select NR_CPUS_DEFAULT_2
+       select SYS_SUPPORTS_32BIT_KERNEL
+       select SYS_SUPPORTS_BIG_ENDIAN
index 6f4763420b7bd993fb9f2acfd8d87b2f40c5149b..3eae0fcd1d0cc5caae032688eb24c4f6c7e6cd2e 100644 (file)
@@ -21,7 +21,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
 
 --- a/arch/mips/include/asm/bmips.h
 +++ b/arch/mips/include/asm/bmips.h
-@@ -70,15 +70,15 @@ static inline unsigned long bmips_read_z
+@@ -97,15 +97,15 @@ static inline unsigned long bmips_read_z
                ".set noreorder\n"
                "cache %1, 0(%2)\n"
                "sync\n"
@@ -45,7 +45,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
                ".set pop\n"
                : "=&r" (ret)
                : "i" (Index_Load_Tag_S), "r" (ZSCM_REG_BASE + offset)
-@@ -92,13 +92,13 @@ static inline void bmips_write_zscm_reg(
+@@ -119,13 +119,13 @@ static inline void bmips_write_zscm_reg(
                ".set push\n"
                ".set noreorder\n"
                "mtc0 %0, $28, 3\n"
diff --git a/target/linux/brcm63xx/patches-3.10/101-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch b/target/linux/brcm63xx/patches-3.10/101-MIPS-allow-asm-cpu.h-to-be-included-from-assembly.patch
deleted file mode 100644 (file)
index 27c3b9e..0000000
+++ /dev/null
@@ -1,31 +0,0 @@
-From 520f4bf75026cc60ba47946331966fb670b39cb0 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Thu, 27 Jun 2013 21:32:41 +0200
-Subject: [PATCH 02/10] MIPS: allow asm/cpu.h to be included from assembly
-
-Add guards around the enum to allow including cpu.h from assembly.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/include/asm/cpu.h |    3 +++
- 1 file changed, 3 insertions(+)
-
---- a/arch/mips/include/asm/cpu.h
-+++ b/arch/mips/include/asm/cpu.h
-@@ -225,6 +225,8 @@
- #define FPIR_IMP_NONE         0x0000
-+#if !defined(__ASSEMBLY__)
-+
- enum cpu_type_enum {
-       CPU_UNKNOWN,
-@@ -277,6 +279,7 @@ enum cpu_type_enum {
-       CPU_LAST
- };
-+#endif /* !__ASSEMBLY */
- /*
-  * ISA Level encodings
diff --git a/target/linux/brcm63xx/patches-3.10/102-MIPS-bmips-add-macros-for-testing-the-current-bmips-.patch b/target/linux/brcm63xx/patches-3.10/102-MIPS-bmips-add-macros-for-testing-the-current-bmips-.patch
deleted file mode 100644 (file)
index af38b35..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-From 971b8b3d5101b3bb868e63f3eb96fe69b7110c61 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Thu, 27 Jun 2013 12:40:15 +0200
-Subject: [PATCH 03/10] MIPS: bmips: add macros for testing the current bmips
- CPU
-
-Makes it easy to make code conditionally compiled for supported CPUs
-without directly relying on #ifdefs.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/include/asm/bmips.h |   11 +++++++++++
- 1 file changed, 11 insertions(+)
-
---- a/arch/mips/include/asm/bmips.h
-+++ b/arch/mips/include/asm/bmips.h
-@@ -45,8 +45,19 @@
- #if !defined(__ASSEMBLY__)
- #include <linux/cpumask.h>
-+#include <asm/cpu-features.h>
- #include <asm/r4kcache.h>
-+#define cpu_is_bmips32()      (current_cpu_type() == CPU_BMIPS32)
-+#define cpu_is_bmips3300()    (IS_ENABLED(CONFIG_CPU_BMIPS3300) && \
-+                               current_cpu_type() == CPU_BMIPS3300)
-+#define cpu_is_bmips4350()    (IS_ENABLED(CONFIG_CPU_BMIPS4350) && \
-+                               current_cpu_type() == CPU_BMIPS4350)
-+#define cpu_is_bmips4380()    (IS_ENABLED(CONFIG_CPU_BMIPS4380) && \
-+                               current_cpu_type() == CPU_BMIPS4380)
-+#define cpu_is_bmips5000()    (IS_ENABLED(CONFIG_CPU_BMIPS5000) && \
-+                               current_cpu_type() == CPU_BMIPS5000)
-+
- extern struct plat_smp_ops bmips_smp_ops;
- extern char bmips_reset_nmi_vec;
- extern char bmips_reset_nmi_vec_end;
diff --git a/target/linux/brcm63xx/patches-3.10/103-MIPS-bmips-change-compile-time-checks-to-runtime-che.patch b/target/linux/brcm63xx/patches-3.10/103-MIPS-bmips-change-compile-time-checks-to-runtime-che.patch
deleted file mode 100644 (file)
index d551895..0000000
+++ /dev/null
@@ -1,482 +0,0 @@
-From 12594762fcbec024cb424c9b77efb28402651667 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Thu, 27 Jun 2013 21:33:56 +0200
-Subject: [PATCH 04/10] MIPS: bmips: change compile time checks to runtime
- checks
-
-Allow building for all bmips cpus at the same time by changing ifdefs
-to checks for the cpu type, or adding appropriate checks to the
-assembly.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/kernel/bmips_vec.S |   55 +++++++---
- arch/mips/kernel/smp-bmips.c |  241 ++++++++++++++++++++++--------------------
- 2 files changed, 172 insertions(+), 124 deletions(-)
-
---- a/arch/mips/kernel/bmips_vec.S
-+++ b/arch/mips/kernel/bmips_vec.S
-@@ -13,6 +13,7 @@
- #include <asm/asm.h>
- #include <asm/asmmacro.h>
- #include <asm/cacheops.h>
-+#include <asm/cpu.h>
- #include <asm/regdef.h>
- #include <asm/mipsregs.h>
- #include <asm/stackframe.h>
-@@ -89,12 +90,18 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
-       beqz    k0, bmips_smp_entry
- #if defined(CONFIG_CPU_BMIPS5000)
-+      mfc0    k0, CP0_PRID
-+      li      k1, PRID_IMP_BMIPS5000
-+      andi    k0, 0xff00
-+      bne     k0, k1, 1f
-+
-       /* if we're not on core 0, this must be the SMP boot signal */
-       li      k1, (3 << 25)
-       mfc0    k0, $22
-       and     k0, k1
-       bnez    k0, bmips_smp_entry
--#endif
-+1:
-+#endif /* CONFIG_CPU_BMIPS5000 */
- #endif /* CONFIG_SMP */
-       /* nope, it's just a regular NMI */
-@@ -137,7 +144,12 @@ bmips_smp_entry:
-       xori    k0, 0x04
-       mtc0    k0, CP0_CONFIG
-+      mfc0    k0, CP0_PRID
-+      andi    k0, 0xff00
- #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
-+      li      k1, PRID_IMP_BMIPS43XX
-+      bne     k0, k1, 2f
-+
-       /* initialize CPU1's local I-cache */
-       li      k0, 0x80000000
-       li      k1, 0x80010000
-@@ -148,14 +160,21 @@ bmips_smp_entry:
- 1:    cache   Index_Store_Tag_I, 0(k0)
-       addiu   k0, 16
-       bne     k0, k1, 1b
--#elif defined(CONFIG_CPU_BMIPS5000)
-+
-+      b       3f
-+2:
-+#endif /* CONFIG_CPU_BMIPS4350 || CONFIG_CPU_BMIPS4380 */
-+#if defined(CONFIG_CPU_BMIPS5000)
-       /* set exception vector base */
-+      li      k1, PRID_IMP_BMIPS5000
-+      bne     k0, k1, 3f
-+
-       la      k0, ebase
-       lw      k0, 0(k0)
-       mtc0    k0, $15, 1
-       BARRIER
--#endif
--
-+#endif /* CONFIG_CPU_BMIPS5000 */
-+3:
-       /* jump back to kseg0 in case we need to remap the kseg1 area */
-       la      k0, 1f
-       jr      k0
-@@ -221,8 +240,18 @@ END(bmips_smp_int_vec)
- LEAF(bmips_enable_xks01)
- #if defined(CONFIG_XKS01)
--
-+      mfc0    t0, CP0_PRID
-+      andi    t2, t0, 0xff00
- #if defined(CONFIG_CPU_BMIPS4380)
-+      li      t1, PRID_IMP_BMIPS43XX
-+      bne     t2, t1, 1f
-+
-+      andi    t0, 0xff
-+      addiu   t1, t0, -PRID_REV_BMIPS4380_HI
-+      bgtz    t1, 2f
-+      addiu   t0, -PRID_REV_BMIPS4380_LO
-+      bltz    t0, 2f
-+
-       mfc0    t0, $22, 3
-       li      t1, 0x1ff0
-       li      t2, (1 << 12) | (1 << 9)
-@@ -231,7 +260,13 @@ LEAF(bmips_enable_xks01)
-       or      t0, t2
-       mtc0    t0, $22, 3
-       BARRIER
--#elif defined(CONFIG_CPU_BMIPS5000)
-+      b       2f
-+1:
-+#endif /* CONFIG_CPU_BMIPS4380 */
-+#if defined(CONFIG_CPU_BMIPS5000)
-+      li      t1, PRID_IMP_BMIPS5000
-+      bne     t2, t1, 2f
-+
-       mfc0    t0, $22, 5
-       li      t1, 0x01ff
-       li      t2, (1 << 8) | (1 << 5)
-@@ -240,12 +275,8 @@ LEAF(bmips_enable_xks01)
-       or      t0, t2
-       mtc0    t0, $22, 5
-       BARRIER
--#else
--
--#error Missing XKS01 setup
--
--#endif
--
-+#endif /* CONFIG_CPU_BMIPS5000 */
-+2:
- #endif /* defined(CONFIG_XKS01) */
-       jr      ra
---- a/arch/mips/kernel/smp-bmips.c
-+++ b/arch/mips/kernel/smp-bmips.c
-@@ -49,8 +49,11 @@ cpumask_t bmips_booted_mask;
- unsigned long bmips_smp_boot_sp;
- unsigned long bmips_smp_boot_gp;
-+static void bmips43xx_send_ipi_single(int cpu, unsigned int action);
-+static void bmips5000_send_ipi_single(int cpu, unsigned int action);
- static void bmips_send_ipi_single(int cpu, unsigned int action);
--static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
-+static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id);
-+static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id);
- /* SW interrupts 0,1 are used for interprocessor signaling */
- #define IPI0_IRQ                      (MIPS_CPU_IRQ_BASE + 0)
-@@ -65,48 +68,49 @@ static void __init bmips_smp_setup(void)
- {
-       int i, cpu = 1, boot_cpu = 0;
--#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
--      /* arbitration priority */
--      clear_c0_brcm_cmt_ctrl(0x30);
--
--      /* NBK and weak order flags */
--      set_c0_brcm_config_0(0x30000);
--
--      /* Find out if we are running on TP0 or TP1 */
--      boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
--
--      /*
--       * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
--       * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
--       * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
--       *
--       * If booting from TP1, leave the existing CMT interrupt routing
--       * such that TP0 responds to SW1 and TP1 responds to SW0.
--       */
--      if (boot_cpu == 0)
--              change_c0_brcm_cmt_intr(0xf8018000,
-+      if (cpu_is_bmips4350() || cpu_is_bmips4380()) {
-+              /* arbitration priority */
-+              clear_c0_brcm_cmt_ctrl(0x30);
-+
-+              /* NBK and weak order flags */
-+              set_c0_brcm_config_0(0x30000);
-+
-+              /* Find out if we are running on TP0 or TP1 */
-+              boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
-+
-+              /*
-+               * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other
-+               * thread
-+               * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
-+               * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
-+               *
-+               * If booting from TP1, leave the existing CMT interrupt routing
-+               * such that TP0 responds to SW1 and TP1 responds to SW0.
-+               */
-+              if (boot_cpu == 0)
-+                      change_c0_brcm_cmt_intr(0xf8018000,
-                                       (0x02 << 27) | (0x03 << 15));
--      else
--              change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
--
--      /* single core, 2 threads (2 pipelines) */
--      max_cpus = 2;
--#elif defined(CONFIG_CPU_BMIPS5000)
--      /* enable raceless SW interrupts */
--      set_c0_brcm_config(0x03 << 22);
--
--      /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
--      change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
-+              else
-+                      change_c0_brcm_cmt_intr(0xf8018000, (0x1d << 27));
--      /* N cores, 2 threads per core */
--      max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
--
--      /* clear any pending SW interrupts */
--      for (i = 0; i < max_cpus; i++) {
--              write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
--              write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
-+              /* single core, 2 threads (2 pipelines) */
-+              max_cpus = 2;
-+      } else if (cpu_is_bmips5000()) {
-+              /* enable raceless SW interrupts */
-+              set_c0_brcm_config(0x03 << 22);
-+
-+              /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
-+              change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
-+
-+              /* N cores, 2 threads per core */
-+              max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
-+
-+              /* clear any pending SW interrupts */
-+              for (i = 0; i < max_cpus; i++) {
-+                      write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
-+                      write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
-+              }
-       }
--#endif
-       if (!bmips_smp_enabled)
-               max_cpus = 1;
-@@ -134,6 +138,15 @@ static void __init bmips_smp_setup(void)
-  */
- static void bmips_prepare_cpus(unsigned int max_cpus)
- {
-+      irqreturn_t (*bmips_ipi_interrupt)(int irq, void *dev_id);
-+
-+      if (cpu_is_bmips4350() || cpu_is_bmips4380())
-+              bmips_ipi_interrupt = bmips43xx_ipi_interrupt;
-+      else if (cpu_is_bmips5000())
-+              bmips_ipi_interrupt = bmips5000_ipi_interrupt;
-+      else
-+              return;
-+
-       if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
-                       "smp_ipi0", NULL))
-               panic("Can't request IPI0 interrupt\n");
-@@ -168,26 +181,26 @@ static void bmips_boot_secondary(int cpu
-       pr_info("SMP: Booting CPU%d...\n", cpu);
--      if (cpumask_test_cpu(cpu, &bmips_booted_mask))
-+      if (cpumask_test_cpu(cpu, &bmips_booted_mask)) {
-               bmips_send_ipi_single(cpu, 0);
--      else {
--#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
--              /* Reset slave TP1 if booting from TP0 */
--              if (cpu_logical_map(cpu) == 0)
--                      set_c0_brcm_cmt_ctrl(0x01);
--#elif defined(CONFIG_CPU_BMIPS5000)
--              if (cpu & 0x01)
--                      write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
--              else {
--                      /*
--                       * core N thread 0 was already booted; just
--                       * pulse the NMI line
--                       */
--                      bmips_write_zscm_reg(0x210, 0xc0000000);
--                      udelay(10);
--                      bmips_write_zscm_reg(0x210, 0x00);
-+      } else {
-+              if (cpu_is_bmips4350() || cpu_is_bmips4380()) {
-+                      /* Reset slave TP1 if booting from TP0 */
-+                      if (cpu_logical_map(cpu) == 0)
-+                              set_c0_brcm_cmt_ctrl(0x01);
-+              } else if (cpu_is_bmips5000()) {
-+                      if (cpu & 0x01)
-+                              write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
-+                      else {
-+                              /*
-+                               * core N thread 0 was already booted; just
-+                               * pulse the NMI line
-+                               */
-+                              bmips_write_zscm_reg(0x210, 0xc0000000);
-+                              udelay(10);
-+                              bmips_write_zscm_reg(0x210, 0x00);
-+                      }
-               }
--#endif
-               cpumask_set_cpu(cpu, &bmips_booted_mask);
-       }
- }
-@@ -199,20 +212,21 @@ static void bmips_init_secondary(void)
- {
-       /* move NMI vector to kseg0, in case XKS01 is enabled */
--#if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
--      void __iomem *cbr = BMIPS_GET_CBR();
--      unsigned long old_vec;
--
--      old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
--      __raw_writel(old_vec & ~0x20000000, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
--
--      clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
--#elif defined(CONFIG_CPU_BMIPS5000)
--      write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
--              (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
-+      if (cpu_is_bmips4350() || cpu_is_bmips4380()) {
-+              void __iomem *cbr = BMIPS_GET_CBR();
-+              unsigned long old_vec;
-+
-+              old_vec = __raw_readl(cbr + BMIPS_RELO_VECTOR_CONTROL_1);
-+              __raw_writel(old_vec & ~0x20000000,
-+                      cbr + BMIPS_RELO_VECTOR_CONTROL_1);
-+
-+              clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
-+      } else if (cpu_is_bmips5000()) {
-+              write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
-+                      (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
--      write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
--#endif
-+              write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
-+      }
- }
- /*
-@@ -237,8 +251,6 @@ static void bmips_cpus_done(void)
- {
- }
--#if defined(CONFIG_CPU_BMIPS5000)
--
- /*
-  * BMIPS5000 raceless IPIs
-  *
-@@ -247,12 +259,12 @@ static void bmips_cpus_done(void)
-  * IPI1 is used for SMP_CALL_FUNCTION
-  */
--static void bmips_send_ipi_single(int cpu, unsigned int action)
-+static void bmips5000_send_ipi_single(int cpu, unsigned int action)
- {
-       write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
- }
--static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
-+static irqreturn_t bmips5000_ipi_interrupt(int irq, void *dev_id)
- {
-       int action = irq - IPI0_IRQ;
-@@ -266,8 +278,6 @@ static irqreturn_t bmips_ipi_interrupt(i
-       return IRQ_HANDLED;
- }
--#else
--
- /*
-  * BMIPS43xx racey IPIs
-  *
-@@ -281,7 +291,7 @@ static irqreturn_t bmips_ipi_interrupt(i
- static DEFINE_SPINLOCK(ipi_lock);
- static DEFINE_PER_CPU(int, ipi_action_mask);
--static void bmips_send_ipi_single(int cpu, unsigned int action)
-+static void bmips43xx_send_ipi_single(int cpu, unsigned int action)
- {
-       unsigned long flags;
-@@ -292,7 +302,7 @@ static void bmips_send_ipi_single(int cp
-       spin_unlock_irqrestore(&ipi_lock, flags);
- }
--static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
-+static irqreturn_t bmips43xx_ipi_interrupt(int irq, void *dev_id)
- {
-       unsigned long flags;
-       int action, cpu = irq - IPI0_IRQ;
-@@ -311,7 +321,13 @@ static irqreturn_t bmips_ipi_interrupt(i
-       return IRQ_HANDLED;
- }
--#endif /* BMIPS type */
-+static void bmips_send_ipi_single(int cpu, unsigned int action)
-+{
-+      if (cpu_is_bmips4350() || cpu_is_bmips4380())
-+              bmips43xx_send_ipi_single(cpu, action);
-+      else if (cpu_is_bmips5000())
-+              bmips5000_send_ipi_single(cpu, action);
-+}
- static void bmips_send_ipi_mask(const struct cpumask *mask,
-       unsigned int action)
-@@ -421,43 +437,44 @@ void __cpuinit bmips_ebase_setup(void)
-       BUG_ON(ebase != CKSEG0);
--#if defined(CONFIG_CPU_BMIPS4350)
--      /*
--       * BMIPS4350 cannot relocate the normal vectors, but it
--       * can relocate the BEV=1 vectors.  So CPU1 starts up at
--       * the relocated BEV=1, IV=0 general exception vector @
--       * 0xa000_0380.
--       *
--       * set_uncached_handler() is used here because:
--       *  - CPU1 will run this from uncached space
--       *  - None of the cacheflush functions are set up yet
--       */
--      set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
--              &bmips_smp_int_vec, 0x80);
--      __sync();
--      return;
--#elif defined(CONFIG_CPU_BMIPS4380)
--      /*
--       * 0x8000_0000: reset/NMI (initially in kseg1)
--       * 0x8000_0400: normal vectors
--       */
--      new_ebase = 0x80000400;
--      cbr = BMIPS_GET_CBR();
--      __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
--      __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
--#elif defined(CONFIG_CPU_BMIPS5000)
--      /*
--       * 0x8000_0000: reset/NMI (initially in kseg1)
--       * 0x8000_1000: normal vectors
--       */
--      new_ebase = 0x80001000;
--      write_c0_brcm_bootvec(0xa0088008);
--      write_c0_ebase(new_ebase);
--      if (max_cpus > 2)
--              bmips_write_zscm_reg(0xa0, 0xa008a008);
--#else
--      return;
--#endif
-+      if (cpu_is_bmips4350()) {
-+              /*
-+               * BMIPS4350 cannot relocate the normal vectors, but it
-+               * can relocate the BEV=1 vectors.  So CPU1 starts up at
-+               * the relocated BEV=1, IV=0 general exception vector @
-+               * 0xa000_0380.
-+               *
-+               * set_uncached_handler() is used here because:
-+               *  - CPU1 will run this from uncached space
-+               *  - None of the cacheflush functions are set up yet
-+               */
-+              set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
-+                      &bmips_smp_int_vec, 0x80);
-+              __sync();
-+              return;
-+      } else if (cpu_is_bmips4380()) {
-+              /*
-+               * 0x8000_0000: reset/NMI (initially in kseg1)
-+               * 0x8000_0400: normal vectors
-+               */
-+              new_ebase = 0x80000400;
-+              cbr = BMIPS_GET_CBR();
-+              __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
-+              __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
-+      } else if (cpu_is_bmips5000()) {
-+              /*
-+               * 0x8000_0000: reset/NMI (initially in kseg1)
-+               * 0x8000_1000: normal vectors
-+               */
-+              new_ebase = 0x80001000;
-+              write_c0_brcm_bootvec(0xa0088008);
-+              write_c0_ebase(new_ebase);
-+              if (max_cpus > 2)
-+                      bmips_write_zscm_reg(0xa0, 0xa008a008);
-+      } else {
-+              return;
-+      }
-+
-       board_nmi_handler_setup = &bmips_nmi_handler_setup;
-       ebase = new_ebase;
- }
diff --git a/target/linux/brcm63xx/patches-3.10/104-MIPS-bmips-merge-CPU-options-into-one-option.patch b/target/linux/brcm63xx/patches-3.10/104-MIPS-bmips-merge-CPU-options-into-one-option.patch
deleted file mode 100644 (file)
index e33d94d..0000000
+++ /dev/null
@@ -1,126 +0,0 @@
-From 1ecac776e6c652e3059d4f4d9dd8369e89ebef81 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Thu, 27 Jun 2013 23:57:20 +0200
-Subject: [PATCH 05/10] MIPS: bmips: merge CPU options into one option
-
-Instead of treating each flavour as an exclusive CPU to select, make
-BMIPS the only option and let SYS_HAS_CPU_BMIPS* decide for which
-flavours to include support.
-
-Run tested on BMIPS3300 and BMIPS4350, only build tested for BMIPS4380
-and BMISP5000.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/Kconfig |   77 +++++++++++++++++++++++++----------------------------
- 1 file changed, 36 insertions(+), 41 deletions(-)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -130,6 +130,7 @@ config BCM63XX
-       select DMA_NONCOHERENT
-       select IRQ_CPU
-       select SYS_HAS_CPU_MIPS32_R1
-+      select SYS_HAS_CPU_BMIPS
-       select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
-       select NR_CPUS_DEFAULT_2
-       select SYS_SUPPORTS_32BIT_KERNEL
-@@ -1453,41 +1454,21 @@ config CPU_CAVIUM_OCTEON
-         can have up to 16 Mips64v2 cores and 8 integrated gigabit ethernets.
-         Full details can be found at http://www.caviumnetworks.com.
--config CPU_BMIPS3300
--      bool "BMIPS3300"
--      depends on SYS_HAS_CPU_BMIPS3300
--      select CPU_BMIPS
--      help
--        Broadcom BMIPS3300 processors.
--
--config CPU_BMIPS4350
--      bool "BMIPS4350"
--      depends on SYS_HAS_CPU_BMIPS4350
--      select CPU_BMIPS
--      select SYS_SUPPORTS_SMP
--      select SYS_SUPPORTS_HOTPLUG_CPU
--      help
--        Broadcom BMIPS4350 ("VIPER") processors.
--
--config CPU_BMIPS4380
--      bool "BMIPS4380"
--      depends on SYS_HAS_CPU_BMIPS4380
--      select CPU_BMIPS
--      select SYS_SUPPORTS_SMP
--      select SYS_SUPPORTS_HOTPLUG_CPU
--      help
--        Broadcom BMIPS4380 processors.
--
--config CPU_BMIPS5000
--      bool "BMIPS5000"
--      depends on SYS_HAS_CPU_BMIPS5000
--      select CPU_BMIPS
--      select CPU_SUPPORTS_HIGHMEM
--      select MIPS_CPU_SCACHE
--      select SYS_SUPPORTS_SMP
--      select SYS_SUPPORTS_HOTPLUG_CPU
-+config CPU_BMIPS
-+      bool "Broadcom BMIPS"
-+      depends on SYS_HAS_CPU_BMIPS
-+      select CPU_MIPS32
-+      select CPU_BMIPS3300 if SYS_HAS_CPU_BMIPS3300
-+      select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4350
-+      select CPU_BMIPS4350 if SYS_HAS_CPU_BMIPS4380
-+      select CPU_BMIPS5000 if SYS_HAS_CPU_BMIPS5000
-+      select CPU_SUPPORTS_32BIT_KERNEL
-+      select DMA_NONCOHERENT
-+      select IRQ_CPU
-+      select SWAP_IO_SPACE
-+      select WEAK_ORDERING
-       help
--        Broadcom BMIPS5000 processors.
-+        Support for BMIPS3300/4350/4380 and BMIPS5000 processors.
- config CPU_XLR
-       bool "Netlogic XLR SoC"
-@@ -1568,14 +1549,25 @@ config CPU_LOONGSON1
-       select CPU_SUPPORTS_32BIT_KERNEL
-       select CPU_SUPPORTS_HIGHMEM
--config CPU_BMIPS
-+config CPU_BMIPS3300
-       bool
--      select CPU_MIPS32
--      select CPU_SUPPORTS_32BIT_KERNEL
--      select DMA_NONCOHERENT
--      select IRQ_CPU
--      select SWAP_IO_SPACE
--      select WEAK_ORDERING
-+
-+config CPU_BMIPS4350
-+      bool
-+      select SYS_SUPPORTS_SMP
-+      select SYS_SUPPORTS_HOTPLUG_CPU
-+
-+config CPU_BMIPS4380
-+      bool
-+      select SYS_SUPPORTS_SMP
-+      select SYS_SUPPORTS_HOTPLUG_CPU
-+
-+config CPU_BMIPS5000
-+      bool
-+      select CPU_SUPPORTS_HIGHMEM
-+      select MIPS_CPU_SCACHE
-+      select SYS_SUPPORTS_SMP
-+      select SYS_SUPPORTS_HOTPLUG_CPU
- config SYS_HAS_CPU_LOONGSON2E
-       bool
-@@ -1649,6 +1641,9 @@ config SYS_HAS_CPU_SB1
- config SYS_HAS_CPU_CAVIUM_OCTEON
-       bool
-+config SYS_HAS_CPU_BMIPS
-+      bool
-+
- config SYS_HAS_CPU_BMIPS3300
-       bool
diff --git a/target/linux/brcm63xx/patches-3.10/105-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch b/target/linux/brcm63xx/patches-3.10/105-MIPS-BCM63XX-let-the-individual-SoCs-select-the-appr.patch
deleted file mode 100644 (file)
index cb09abc..0000000
+++ /dev/null
@@ -1,72 +0,0 @@
-From 9d1e9d7abd2f2d067169fb0c62e34cf080bbd7a1 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Sun, 23 Jun 2013 12:25:49 +0200
-Subject: [PATCH 06/10] MIPS: BCM63XX: let the individual SoCs select the
- appropriate CPUs
-
-Let each supported chip select the appropirate SYS_HAS_CPU_BMIPS*
-option for its embedded processor, so support will be conditionally
-included.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
-
-fix bmips selection
----
- arch/mips/Kconfig         |    1 -
- arch/mips/bcm63xx/Kconfig |    8 ++++++++
- 2 files changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -131,7 +131,6 @@ config BCM63XX
-       select IRQ_CPU
-       select SYS_HAS_CPU_MIPS32_R1
-       select SYS_HAS_CPU_BMIPS
--      select SYS_HAS_CPU_BMIPS4350 if !BCM63XX_CPU_6338 && !BCM63XX_CPU_6345 && !BCM63XX_CPU_6348
-       select NR_CPUS_DEFAULT_2
-       select SYS_SUPPORTS_32BIT_KERNEL
-       select SYS_SUPPORTS_BIG_ENDIAN
---- a/arch/mips/bcm63xx/Kconfig
-+++ b/arch/mips/bcm63xx/Kconfig
-@@ -3,33 +3,41 @@ menu "CPU support"
- config BCM63XX_CPU_3368
-       bool "support 3368 CPU"
-+      select SYS_HAS_CPU_BMIPS4350
-       select HW_HAS_PCI
- config BCM63XX_CPU_6328
-       bool "support 6328 CPU"
-+      select SYS_HAS_CPU_BMIPS4350
-       select HW_HAS_PCI
- config BCM63XX_CPU_6338
-       bool "support 6338 CPU"
-+      select SYS_HAS_CPU_BMIPS3300
-       select HW_HAS_PCI
- config BCM63XX_CPU_6345
-       bool "support 6345 CPU"
-+      select SYS_HAS_CPU_BMIPS3300
- config BCM63XX_CPU_6348
-       bool "support 6348 CPU"
-+      select SYS_HAS_CPU_BMIPS3300
-       select HW_HAS_PCI
- config BCM63XX_CPU_6358
-       bool "support 6358 CPU"
-+      select SYS_HAS_CPU_BMIPS4350
-       select HW_HAS_PCI
- config BCM63XX_CPU_6362
-       bool "support 6362 CPU"
-+      select SYS_HAS_CPU_BMIPS4350
-       select HW_HAS_PCI
- config BCM63XX_CPU_6368
-       bool "support 6368 CPU"
-+      select SYS_HAS_CPU_BMIPS4350
-       select HW_HAS_PCI
- endmenu
diff --git a/target/linux/brcm63xx/patches-3.10/106-MIPS-bmips-add-a-helper-function-for-registering-smp.patch b/target/linux/brcm63xx/patches-3.10/106-MIPS-bmips-add-a-helper-function-for-registering-smp.patch
deleted file mode 100644 (file)
index ad357b6..0000000
+++ /dev/null
@@ -1,42 +0,0 @@
-From aa15ac91faccc3bf01a29670b1f9ae1945cea056 Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Sun, 23 Jun 2013 14:04:51 +0200
-Subject: [PATCH 07/10] MIPS: bmips: add a helper function for registering smp
- ops
-
-Add a helper similar to the generic register_XXX_smp_ops() for bmips.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/include/asm/bmips.h |   13 +++++++++++++
- 1 file changed, 13 insertions(+)
-
---- a/arch/mips/include/asm/bmips.h
-+++ b/arch/mips/include/asm/bmips.h
-@@ -47,6 +47,7 @@
- #include <linux/cpumask.h>
- #include <asm/cpu-features.h>
- #include <asm/r4kcache.h>
-+#include <asm/smp-ops.h>
- #define cpu_is_bmips32()      (current_cpu_type() == CPU_BMIPS32)
- #define cpu_is_bmips3300()    (IS_ENABLED(CONFIG_CPU_BMIPS3300) && \
-@@ -59,6 +60,18 @@
-                                current_cpu_type() == CPU_BMIPS5000)
- extern struct plat_smp_ops bmips_smp_ops;
-+
-+static inline int register_bmips_smp_ops(void)
-+{
-+#ifdef CONFIG_CPU_BMIPS
-+      register_smp_ops(&bmips_smp_ops);
-+
-+      return 0;
-+#else
-+      return -ENODEV;
-+#endif
-+}
-+
- extern char bmips_reset_nmi_vec;
- extern char bmips_reset_nmi_vec_end;
- extern char bmips_smp_movevec;
diff --git a/target/linux/brcm63xx/patches-3.10/107-MIPS-BCM63XX-always-register-bmips-smp-ops.patch b/target/linux/brcm63xx/patches-3.10/107-MIPS-BCM63XX-always-register-bmips-smp-ops.patch
deleted file mode 100644 (file)
index 1ea52c4..0000000
+++ /dev/null
@@ -1,26 +0,0 @@
-From c489eace9492d1b8bedb314bdef169e719161bff Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Fri, 28 Jun 2013 00:08:16 +0200
-Subject: [PATCH 08/10] MIPS: BCM63XX: always register bmips smp ops
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/prom.c |    6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/arch/mips/bcm63xx/prom.c
-+++ b/arch/mips/bcm63xx/prom.c
-@@ -59,10 +59,10 @@ void __init prom_init(void)
-       /* do low level board init */
-       board_prom_init();
--      if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
--              /* set up SMP */
--              register_smp_ops(&bmips_smp_ops);
-+      /* set up SMP */
-+      register_bmips_smp_ops();
-+      if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
-               /*
-                * BCM6328 might not have its second CPU enabled, while BCM6358
-                * needs special handling for its shared TLB, so disable SMP
diff --git a/target/linux/brcm63xx/patches-3.10/108-MIPS-BCM63XX-change-the-guard-to-a-BMIPS4350-check.patch b/target/linux/brcm63xx/patches-3.10/108-MIPS-BCM63XX-change-the-guard-to-a-BMIPS4350-check.patch
deleted file mode 100644 (file)
index 7572985..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-From 3a862fd3cc4f477ad2232370abfceca1ec2145ae Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Fri, 28 Jun 2013 00:10:07 +0200
-Subject: [PATCH 09/10] MIPS: BCM63XX: change the guard to a BMIPS4350 check
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/prom.c |    2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
---- a/arch/mips/bcm63xx/prom.c
-+++ b/arch/mips/bcm63xx/prom.c
-@@ -62,7 +62,7 @@ void __init prom_init(void)
-       /* set up SMP */
-       register_bmips_smp_ops();
--      if (IS_ENABLED(CONFIG_CPU_BMIPS4350) && IS_ENABLED(CONFIG_SMP)) {
-+      if (cpu_is_bmips4350()) {
-               /*
-                * BCM6328 might not have its second CPU enabled, while BCM6358
-                * needs special handling for its shared TLB, so disable SMP
diff --git a/target/linux/brcm63xx/patches-3.10/109-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch b/target/linux/brcm63xx/patches-3.10/109-MIPS-BCM63XX-disable-SMP-also-on-BCM3368.patch
deleted file mode 100644 (file)
index dbb2ae4..0000000
+++ /dev/null
@@ -1,36 +0,0 @@
-From 32d4b03c0aedb96022e86a67a560f6eaf488200a Mon Sep 17 00:00:00 2001
-From: Jonas Gorski <jogo@openwrt.org>
-Date: Fri, 28 Jun 2013 00:25:13 +0200
-Subject: [PATCH 10/10] MIPS: BCM63XX: disable SMP also on BCM3368
-
-BCM3368 has the same shared TLB as BCM6358.
-
-Signed-off-by: Jonas Gorski <jogo@openwrt.org>
----
- arch/mips/bcm63xx/prom.c |    8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
---- a/arch/mips/bcm63xx/prom.c
-+++ b/arch/mips/bcm63xx/prom.c
-@@ -64,9 +64,9 @@ void __init prom_init(void)
-       if (cpu_is_bmips4350()) {
-               /*
--               * BCM6328 might not have its second CPU enabled, while BCM6358
--               * needs special handling for its shared TLB, so disable SMP
--               * for now.
-+               * BCM6328 might not have its second CPU enabled, while BCM3368
-+               * and BCM6358 need special handling for their shared TLB, so
-+               * disable SMP for now.
-                */
-               if (BCMCPU_IS_6328()) {
-                       reg = bcm_readl(BCM_6328_OTP_BASE +
-@@ -74,7 +74,7 @@ void __init prom_init(void)
-                       if (reg & OTP_6328_REG3_TP1_DISABLED)
-                               bmips_smp_enabled = 0;
--              } else if (BCMCPU_IS_6358()) {
-+              } else if (BCMCPU_IS_3368() || BCMCPU_IS_6358()) {
-                       bmips_smp_enabled = 0;
-               }
index 03fa41c41007037b84602ea01cfb2855cf59adbf..768dccac5ed68d5f58d14d9af64848ee0f28bd8a 100644 (file)
@@ -36,7 +36,7 @@ Signed-off-by: Florian Fainelli <florian@openwrt.org>
        bool "support 6338 CPU"
 @@ -24,21 +31,25 @@ config BCM63XX_CPU_6348
        bool "support 6348 CPU"
-       select SYS_HAS_CPU_BMIPS3300
+       select SYS_HAS_CPU_BMIPS32_3300
        select HW_HAS_PCI
 +      select BCM63XX_OHCI
  
index 4e48e7760ff105efed55966a1f3e9edf81d3e258..8afdf5e40d8d5dab95c248b46f26696defec773c 100644 (file)
@@ -1,7 +1,3 @@
-CONFIG_CPU_BMIPS=y
-CONFIG_CPU_BMIPS3300=y
-CONFIG_CPU_BMIPS4350=y
-# CONFIG_CPU_MIPS32_R1 is not set
 CONFIG_CPU_RMAP=y
 # CONFIG_KEXEC is not set
 CONFIG_MUTEX_SPIN_ON_OWNER=y
@@ -10,10 +6,8 @@ CONFIG_RCU_STALL_COMMON=y
 CONFIG_RFS_ACCEL=y
 CONFIG_RPS=y
 CONFIG_SMP=y
+CONFIG_SMP_UP=y
 CONFIG_STOP_MACHINE=y
-CONFIG_SYS_SUPPORTS_HOTPLUG_CPU=y
-CONFIG_SYS_SUPPORTS_SMP=y
 CONFIG_TREE_RCU=y
 CONFIG_USE_GENERIC_SMP_HELPERS=y
-CONFIG_WEAK_ORDERING=y
 CONFIG_XPS=y