3 Broadcom BCM43xx wireless driver
5 Copyright (c) 2005 Martin Langer <martin-langer@gmx.de>
6 Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
7 Copyright (c) 2005, 2006 Michael Buesch <mb@bu3sch.de>
8 Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
9 Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
11 Some parts of the code in this file are derived from the ipw2200
12 driver Copyright(c) 2003 - 2004 Intel Corporation.
14 This program is free software; you can redistribute it and/or modify
15 it under the terms of the GNU General Public License as published by
16 the Free Software Foundation; either version 2 of the License, or
17 (at your option) any later version.
19 This program is distributed in the hope that it will be useful,
20 but WITHOUT ANY WARRANTY; without even the implied warranty of
21 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 GNU General Public License for more details.
24 You should have received a copy of the GNU General Public License
25 along with this program; see the file COPYING. If not, write to
26 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
27 Boston, MA 02110-1301, USA.
31 #include <linux/delay.h>
32 #include <linux/init.h>
33 #include <linux/moduleparam.h>
34 #include <linux/if_arp.h>
35 #include <linux/etherdevice.h>
36 #include <linux/version.h>
37 #include <linux/firmware.h>
38 #include <linux/wireless.h>
39 #include <linux/workqueue.h>
40 #include <linux/skbuff.h>
41 #include <linux/dma-mapping.h>
44 #include "bcm43xx_main.h"
45 #include "bcm43xx_debugfs.h"
46 #include "bcm43xx_phy.h"
47 #include "bcm43xx_dma.h"
48 #include "bcm43xx_pio.h"
49 #include "bcm43xx_power.h"
50 #include "bcm43xx_sysfs.h"
51 #include "bcm43xx_xmit.h"
52 #include "bcm43xx_sysfs.h"
53 #include "bcm43xx_lo.h"
54 #include "bcm43xx_pcmcia.h"
57 MODULE_DESCRIPTION("Broadcom BCM43xx wireless driver");
58 MODULE_AUTHOR("Martin Langer");
59 MODULE_AUTHOR("Stefano Brivio");
60 MODULE_AUTHOR("Michael Buesch");
61 MODULE_LICENSE("GPL");
64 extern char *nvram_get(char *name
);
67 #if defined(CONFIG_BCM43XX_MAC80211_DMA) && defined(CONFIG_BCM43XX_MAC80211_PIO)
68 static int modparam_pio
;
69 module_param_named(pio
, modparam_pio
, int, 0444);
70 MODULE_PARM_DESC(pio
, "enable(1) / disable(0) PIO mode");
71 #elif defined(CONFIG_BCM43XX_MAC80211_DMA)
72 # define modparam_pio 0
73 #elif defined(CONFIG_BCM43XX_MAC80211_PIO)
74 # define modparam_pio 1
77 static int modparam_bad_frames_preempt
;
78 module_param_named(bad_frames_preempt
, modparam_bad_frames_preempt
, int, 0444);
79 MODULE_PARM_DESC(bad_frames_preempt
, "enable(1) / disable(0) Bad Frames Preemption");
81 static int modparam_short_retry
= BCM43xx_DEFAULT_SHORT_RETRY_LIMIT
;
82 module_param_named(short_retry
, modparam_short_retry
, int, 0444);
83 MODULE_PARM_DESC(short_retry
, "Short-Retry-Limit (0 - 15)");
85 static int modparam_long_retry
= BCM43xx_DEFAULT_LONG_RETRY_LIMIT
;
86 module_param_named(long_retry
, modparam_long_retry
, int, 0444);
87 MODULE_PARM_DESC(long_retry
, "Long-Retry-Limit (0 - 15)");
89 static int modparam_noleds
;
90 module_param_named(noleds
, modparam_noleds
, int, 0444);
91 MODULE_PARM_DESC(noleds
, "Turn off all LED activity");
93 static char modparam_fwpostfix
[16];
94 module_param_string(fwpostfix
, modparam_fwpostfix
, 16, 0444);
95 MODULE_PARM_DESC(fwpostfix
, "Postfix for the .fw files to load.");
97 static int modparam_mon_keep_bad
;
98 module_param_named(mon_keep_bad
, modparam_mon_keep_bad
, int, 0444);
99 MODULE_PARM_DESC(mon_keep_bad
, "Keep bad frames in monitor mode");
101 static int modparam_mon_keep_badplcp
;
102 module_param_named(mon_keep_badplcp
, modparam_mon_keep_bad
, int, 0444);
103 MODULE_PARM_DESC(mon_keep_badplcp
, "Keep frames with bad PLCP in monitor mode");
106 static const struct ssb_device_id bcm43xx_ssb_tbl
[] = {
107 SSB_DEVICE(SSB_VENDOR_BROADCOM
, SSB_DEV_80211
, SSB_ANY_REV
),
110 MODULE_DEVICE_TABLE(ssb
, bcm43xx_ssb_tbl
);
113 /* Channel and ratetables are shared for all devices.
114 * They can't be const, because ieee80211 puts some precalculated
115 * data in there. This data is the same for all devices, so we don't
116 * get concurrency issues */
117 #define RATETAB_ENT(_rateid, _flags) \
119 .rate = BCM43xx_RATE_TO_BASE100KBPS(_rateid), \
124 static struct ieee80211_rate __bcm43xx_ratetable
[] = {
125 RATETAB_ENT(BCM43xx_CCK_RATE_1MB
, IEEE80211_RATE_CCK
),
126 RATETAB_ENT(BCM43xx_CCK_RATE_2MB
, IEEE80211_RATE_CCK_2
),
127 RATETAB_ENT(BCM43xx_CCK_RATE_5MB
, IEEE80211_RATE_CCK_2
),
128 RATETAB_ENT(BCM43xx_CCK_RATE_11MB
, IEEE80211_RATE_CCK_2
),
129 RATETAB_ENT(BCM43xx_OFDM_RATE_6MB
, IEEE80211_RATE_OFDM
),
130 RATETAB_ENT(BCM43xx_OFDM_RATE_9MB
, IEEE80211_RATE_OFDM
),
131 RATETAB_ENT(BCM43xx_OFDM_RATE_12MB
, IEEE80211_RATE_OFDM
),
132 RATETAB_ENT(BCM43xx_OFDM_RATE_18MB
, IEEE80211_RATE_OFDM
),
133 RATETAB_ENT(BCM43xx_OFDM_RATE_24MB
, IEEE80211_RATE_OFDM
),
134 RATETAB_ENT(BCM43xx_OFDM_RATE_36MB
, IEEE80211_RATE_OFDM
),
135 RATETAB_ENT(BCM43xx_OFDM_RATE_48MB
, IEEE80211_RATE_OFDM
),
136 RATETAB_ENT(BCM43xx_OFDM_RATE_54MB
, IEEE80211_RATE_OFDM
),
138 #define bcm43xx_a_ratetable (__bcm43xx_ratetable + 4)
139 #define bcm43xx_a_ratetable_size 8
140 #define bcm43xx_b_ratetable (__bcm43xx_ratetable + 0)
141 #define bcm43xx_b_ratetable_size 4
142 #define bcm43xx_g_ratetable (__bcm43xx_ratetable + 0)
143 #define bcm43xx_g_ratetable_size 12
145 #define CHANTAB_ENT(_chanid, _freq) \
150 .flag = IEEE80211_CHAN_W_SCAN | \
151 IEEE80211_CHAN_W_ACTIVE_SCAN | \
152 IEEE80211_CHAN_W_IBSS, \
153 .power_level = 0xFF, \
154 .antenna_max = 0xFF, \
156 static struct ieee80211_channel bcm43xx_bg_chantable
[] = {
157 CHANTAB_ENT(1, 2412),
158 CHANTAB_ENT(2, 2417),
159 CHANTAB_ENT(3, 2422),
160 CHANTAB_ENT(4, 2427),
161 CHANTAB_ENT(5, 2432),
162 CHANTAB_ENT(6, 2437),
163 CHANTAB_ENT(7, 2442),
164 CHANTAB_ENT(8, 2447),
165 CHANTAB_ENT(9, 2452),
166 CHANTAB_ENT(10, 2457),
167 CHANTAB_ENT(11, 2462),
168 CHANTAB_ENT(12, 2467),
169 CHANTAB_ENT(13, 2472),
170 CHANTAB_ENT(14, 2484),
172 #define bcm43xx_bg_chantable_size ARRAY_SIZE(bcm43xx_bg_chantable)
173 static struct ieee80211_channel bcm43xx_a_chantable
[] = {
174 CHANTAB_ENT(36, 5180),
175 CHANTAB_ENT(40, 5200),
176 CHANTAB_ENT(44, 5220),
177 CHANTAB_ENT(48, 5240),
178 CHANTAB_ENT(52, 5260),
179 CHANTAB_ENT(56, 5280),
180 CHANTAB_ENT(60, 5300),
181 CHANTAB_ENT(64, 5320),
182 CHANTAB_ENT(149, 5745),
183 CHANTAB_ENT(153, 5765),
184 CHANTAB_ENT(157, 5785),
185 CHANTAB_ENT(161, 5805),
186 CHANTAB_ENT(165, 5825),
188 #define bcm43xx_a_chantable_size ARRAY_SIZE(bcm43xx_a_chantable)
191 static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev
*dev
);
192 static int bcm43xx_wireless_core_init(struct bcm43xx_wldev
*dev
);
193 static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev
*dev
);
194 static int bcm43xx_wireless_core_start(struct bcm43xx_wldev
*dev
);
197 static void bcm43xx_ram_write(struct bcm43xx_wldev
*dev
, u16 offset
, u32 val
)
201 assert(offset
% 4 == 0);
203 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
204 if (status
& BCM43xx_SBF_XFER_REG_BYTESWAP
)
207 bcm43xx_write32(dev
, BCM43xx_MMIO_RAM_CONTROL
, offset
);
209 bcm43xx_write32(dev
, BCM43xx_MMIO_RAM_DATA
, val
);
213 void bcm43xx_shm_control_word(struct bcm43xx_wldev
*dev
,
214 u16 routing
, u16 offset
)
218 /* "offset" is the WORD offset. */
223 bcm43xx_write32(dev
, BCM43xx_MMIO_SHM_CONTROL
, control
);
226 u32
bcm43xx_shm_read32(struct bcm43xx_wldev
*dev
,
227 u16 routing
, u16 offset
)
231 if (routing
== BCM43xx_SHM_SHARED
) {
232 assert((offset
& 0x0001) == 0);
233 if (offset
& 0x0003) {
234 /* Unaligned access */
235 bcm43xx_shm_control_word(dev
, routing
, offset
>> 2);
236 ret
= bcm43xx_read16(dev
,
237 BCM43xx_MMIO_SHM_DATA_UNALIGNED
);
239 bcm43xx_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
240 ret
|= bcm43xx_read16(dev
,
241 BCM43xx_MMIO_SHM_DATA
);
247 bcm43xx_shm_control_word(dev
, routing
, offset
);
248 ret
= bcm43xx_read32(dev
, BCM43xx_MMIO_SHM_DATA
);
253 u16
bcm43xx_shm_read16(struct bcm43xx_wldev
*dev
,
254 u16 routing
, u16 offset
)
258 if (routing
== BCM43xx_SHM_SHARED
) {
259 assert((offset
& 0x0001) == 0);
260 if (offset
& 0x0003) {
261 /* Unaligned access */
262 bcm43xx_shm_control_word(dev
, routing
, offset
>> 2);
263 ret
= bcm43xx_read16(dev
,
264 BCM43xx_MMIO_SHM_DATA_UNALIGNED
);
270 bcm43xx_shm_control_word(dev
, routing
, offset
);
271 ret
= bcm43xx_read16(dev
, BCM43xx_MMIO_SHM_DATA
);
276 void bcm43xx_shm_write32(struct bcm43xx_wldev
*dev
,
277 u16 routing
, u16 offset
,
280 if (routing
== BCM43xx_SHM_SHARED
) {
281 assert((offset
& 0x0001) == 0);
282 if (offset
& 0x0003) {
283 /* Unaligned access */
284 bcm43xx_shm_control_word(dev
, routing
, offset
>> 2);
286 bcm43xx_write16(dev
, BCM43xx_MMIO_SHM_DATA_UNALIGNED
,
287 (value
>> 16) & 0xffff);
289 bcm43xx_shm_control_word(dev
, routing
, (offset
>> 2) + 1);
291 bcm43xx_write16(dev
, BCM43xx_MMIO_SHM_DATA
,
297 bcm43xx_shm_control_word(dev
, routing
, offset
);
299 bcm43xx_write32(dev
, BCM43xx_MMIO_SHM_DATA
, value
);
302 void bcm43xx_shm_write16(struct bcm43xx_wldev
*dev
,
303 u16 routing
, u16 offset
,
306 if (routing
== BCM43xx_SHM_SHARED
) {
307 assert((offset
& 0x0001) == 0);
308 if (offset
& 0x0003) {
309 /* Unaligned access */
310 bcm43xx_shm_control_word(dev
, routing
, offset
>> 2);
312 bcm43xx_write16(dev
, BCM43xx_MMIO_SHM_DATA_UNALIGNED
,
318 bcm43xx_shm_control_word(dev
, routing
, offset
);
320 bcm43xx_write16(dev
, BCM43xx_MMIO_SHM_DATA
, value
);
324 u32
bcm43xx_hf_read(struct bcm43xx_wldev
*dev
)
328 ret
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
329 BCM43xx_SHM_SH_HOSTFHI
);
331 ret
|= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
332 BCM43xx_SHM_SH_HOSTFLO
);
337 /* Write HostFlags */
338 void bcm43xx_hf_write(struct bcm43xx_wldev
*dev
, u32 value
)
340 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
341 BCM43xx_SHM_SH_HOSTFLO
,
342 (value
& 0x0000FFFF));
343 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
344 BCM43xx_SHM_SH_HOSTFHI
,
345 ((value
& 0xFFFF0000) >> 16));
348 void bcm43xx_tsf_read(struct bcm43xx_wldev
*dev
, u64
*tsf
)
350 /* We need to be careful. As we read the TSF from multiple
351 * registers, we should take care of register overflows.
352 * In theory, the whole tsf read process should be atomic.
353 * We try to be atomic here, by restaring the read process,
354 * if any of the high registers changed (overflew).
356 if (dev
->dev
->id
.revision
>= 3) {
357 u32 low
, high
, high2
;
360 high
= bcm43xx_read32(dev
, BCM43xx_MMIO_REV3PLUS_TSF_HIGH
);
361 low
= bcm43xx_read32(dev
, BCM43xx_MMIO_REV3PLUS_TSF_LOW
);
362 high2
= bcm43xx_read32(dev
, BCM43xx_MMIO_REV3PLUS_TSF_HIGH
);
363 } while (unlikely(high
!= high2
));
371 u16 test1
, test2
, test3
;
374 v3
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_3
);
375 v2
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_2
);
376 v1
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_1
);
377 v0
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_0
);
379 test3
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_3
);
380 test2
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_2
);
381 test1
= bcm43xx_read16(dev
, BCM43xx_MMIO_TSF_1
);
382 } while (v3
!= test3
|| v2
!= test2
|| v1
!= test1
);
396 static void bcm43xx_time_lock(struct bcm43xx_wldev
*dev
)
400 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
401 status
|= BCM43xx_SBF_TIME_UPDATE
;
402 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
406 static void bcm43xx_time_unlock(struct bcm43xx_wldev
*dev
)
410 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
411 status
&= ~BCM43xx_SBF_TIME_UPDATE
;
412 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, status
);
415 static void bcm43xx_tsf_write_locked(struct bcm43xx_wldev
*dev
, u64 tsf
)
417 /* Be careful with the in-progress timer.
418 * First zero out the low register, so we have a full
419 * register-overflow duration to complete the operation.
421 if (dev
->dev
->id
.revision
>= 3) {
422 u32 lo
= (tsf
& 0x00000000FFFFFFFFULL
);
423 u32 hi
= (tsf
& 0xFFFFFFFF00000000ULL
) >> 32;
425 bcm43xx_write32(dev
, BCM43xx_MMIO_REV3PLUS_TSF_LOW
, 0);
427 bcm43xx_write32(dev
, BCM43xx_MMIO_REV3PLUS_TSF_HIGH
, hi
);
429 bcm43xx_write32(dev
, BCM43xx_MMIO_REV3PLUS_TSF_LOW
, lo
);
431 u16 v0
= (tsf
& 0x000000000000FFFFULL
);
432 u16 v1
= (tsf
& 0x00000000FFFF0000ULL
) >> 16;
433 u16 v2
= (tsf
& 0x0000FFFF00000000ULL
) >> 32;
434 u16 v3
= (tsf
& 0xFFFF000000000000ULL
) >> 48;
436 bcm43xx_write16(dev
, BCM43xx_MMIO_TSF_0
, 0);
438 bcm43xx_write16(dev
, BCM43xx_MMIO_TSF_3
, v3
);
440 bcm43xx_write16(dev
, BCM43xx_MMIO_TSF_2
, v2
);
442 bcm43xx_write16(dev
, BCM43xx_MMIO_TSF_1
, v1
);
444 bcm43xx_write16(dev
, BCM43xx_MMIO_TSF_0
, v0
);
448 void bcm43xx_tsf_write(struct bcm43xx_wldev
*dev
, u64 tsf
)
450 bcm43xx_time_lock(dev
);
451 bcm43xx_tsf_write_locked(dev
, tsf
);
452 bcm43xx_time_unlock(dev
);
455 static void bcm43xx_measure_channel_change_time(struct bcm43xx_wldev
*dev
)
459 u8 oldchan
, testchan
;
461 /* We (ab)use the bcm43xx TSF timer to measure the time needed
462 * to switch channels. This information is handed over to
463 * the ieee80211 subsystem.
464 * Time is measured in microseconds.
467 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
468 oldchan
= dev
->phy
.channel
;
469 testchan
= (oldchan
== 6) ? 7 : 6;
470 bcm43xx_tsf_read(dev
, &start
);
471 bcm43xx_radio_selectchannel(dev
, testchan
, 0);
472 bcm43xx_tsf_read(dev
, &stop
);
473 bcm43xx_radio_selectchannel(dev
, oldchan
, 0);
474 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
476 assert(stop
> start
);
477 dev
->wl
->hw
->channel_change_time
= stop
- start
;
481 void bcm43xx_macfilter_set(struct bcm43xx_wldev
*dev
,
488 bcm43xx_write16(dev
, BCM43xx_MMIO_MACFILTER_CONTROL
, offset
);
492 bcm43xx_write16(dev
, BCM43xx_MMIO_MACFILTER_DATA
, data
);
495 bcm43xx_write16(dev
, BCM43xx_MMIO_MACFILTER_DATA
, data
);
498 bcm43xx_write16(dev
, BCM43xx_MMIO_MACFILTER_DATA
, data
);
501 static void bcm43xx_macfilter_clear(struct bcm43xx_wldev
*dev
,
504 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
506 bcm43xx_macfilter_set(dev
, offset
, zero_addr
);
509 static void bcm43xx_write_mac_bssid_templates(struct bcm43xx_wldev
*dev
)
511 static const u8 zero_addr
[ETH_ALEN
] = { 0 };
514 u8 mac_bssid
[ETH_ALEN
* 2];
518 bssid
= dev
->wl
->bssid
;
521 mac
= dev
->wl
->mac_addr
;
525 memcpy(mac_bssid
, mac
, ETH_ALEN
);
526 memcpy(mac_bssid
+ ETH_ALEN
, bssid
, ETH_ALEN
);
528 /* Write our MAC address and BSSID to template ram */
529 for (i
= 0; i
< ARRAY_SIZE(mac_bssid
); i
+= sizeof(u32
)) {
530 tmp
= (u32
)(mac_bssid
[i
+ 0]);
531 tmp
|= (u32
)(mac_bssid
[i
+ 1]) << 8;
532 tmp
|= (u32
)(mac_bssid
[i
+ 2]) << 16;
533 tmp
|= (u32
)(mac_bssid
[i
+ 3]) << 24;
534 bcm43xx_ram_write(dev
, 0x20 + i
, tmp
);
538 static void bcm43xx_set_slot_time(struct bcm43xx_wldev
*dev
, u16 slot_time
)
540 /* slot_time is in usec. */
541 if (dev
->phy
.type
!= BCM43xx_PHYTYPE_G
)
543 bcm43xx_write16(dev
, 0x684, 510 + slot_time
);
544 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0010, slot_time
);
547 static void bcm43xx_short_slot_timing_enable(struct bcm43xx_wldev
*dev
)
549 bcm43xx_set_slot_time(dev
, 9);
553 static void bcm43xx_short_slot_timing_disable(struct bcm43xx_wldev
*dev
)
555 bcm43xx_set_slot_time(dev
, 20);
559 /* Enable a Generic IRQ. "mask" is the mask of which IRQs to enable.
560 * Returns the _previously_ enabled IRQ mask.
562 static inline u32
bcm43xx_interrupt_enable(struct bcm43xx_wldev
*dev
, u32 mask
)
566 old_mask
= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_MASK
);
567 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_MASK
, old_mask
| mask
);
572 /* Disable a Generic IRQ. "mask" is the mask of which IRQs to disable.
573 * Returns the _previously_ enabled IRQ mask.
575 static inline u32
bcm43xx_interrupt_disable(struct bcm43xx_wldev
*dev
, u32 mask
)
579 old_mask
= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_MASK
);
580 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_MASK
, old_mask
& ~mask
);
585 /* Synchronize IRQ top- and bottom-half.
586 * IRQs must be masked before calling this.
587 * This must not be called with the irq_lock held.
589 static void bcm43xx_synchronize_irq(struct bcm43xx_wldev
*dev
)
591 synchronize_irq(dev
->dev
->irq
);
592 tasklet_kill(&dev
->isr_tasklet
);
595 /* DummyTransmission function, as documented on
596 * http://bcm-specs.sipsolutions.net/DummyTransmission
598 void bcm43xx_dummy_transmission(struct bcm43xx_wldev
*dev
)
600 struct bcm43xx_phy
*phy
= &dev
->phy
;
601 unsigned int i
, max_loop
;
612 case BCM43xx_PHYTYPE_A
:
614 buffer
[0] = 0x000201CC;
616 case BCM43xx_PHYTYPE_B
:
617 case BCM43xx_PHYTYPE_G
:
619 buffer
[0] = 0x000B846E;
626 for (i
= 0; i
< 5; i
++)
627 bcm43xx_ram_write(dev
, i
* 4, buffer
[i
]);
629 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
); /* dummy read */
631 bcm43xx_write16(dev
, 0x0568, 0x0000);
632 bcm43xx_write16(dev
, 0x07C0, 0x0000);
633 value
= ((phy
->type
== BCM43xx_PHYTYPE_A
) ? 1 : 0);
634 bcm43xx_write16(dev
, 0x050C, value
);
635 bcm43xx_write16(dev
, 0x0508, 0x0000);
636 bcm43xx_write16(dev
, 0x050A, 0x0000);
637 bcm43xx_write16(dev
, 0x054C, 0x0000);
638 bcm43xx_write16(dev
, 0x056A, 0x0014);
639 bcm43xx_write16(dev
, 0x0568, 0x0826);
640 bcm43xx_write16(dev
, 0x0500, 0x0000);
641 bcm43xx_write16(dev
, 0x0502, 0x0030);
643 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
644 bcm43xx_radio_write16(dev
, 0x0051, 0x0017);
645 for (i
= 0x00; i
< max_loop
; i
++) {
646 value
= bcm43xx_read16(dev
, 0x050E);
651 for (i
= 0x00; i
< 0x0A; i
++) {
652 value
= bcm43xx_read16(dev
, 0x050E);
657 for (i
= 0x00; i
< 0x0A; i
++) {
658 value
= bcm43xx_read16(dev
, 0x0690);
659 if (!(value
& 0x0100))
663 if (phy
->radio_ver
== 0x2050 && phy
->radio_rev
<= 0x5)
664 bcm43xx_radio_write16(dev
, 0x0051, 0x0037);
667 static void key_write(struct bcm43xx_wldev
*dev
,
668 u8 index
, u8 algorithm
, const u8
*key
)
675 /* Key index/algo block */
676 kidx
= bcm43xx_kidx_to_fw(dev
, index
);
677 value
= ((kidx
<< 4) | algorithm
);
678 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
679 BCM43xx_SHM_SH_KEYIDXBLOCK
+
682 /* Write the key to the Key Table Pointer offset */
683 offset
= dev
->ktp
+ (index
* BCM43xx_SEC_KEYSIZE
);
684 for (i
= 0; i
< BCM43xx_SEC_KEYSIZE
; i
+= 2) {
686 value
|= (u16
)(key
[i
+ 1]) << 8;
687 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
692 static void keymac_write(struct bcm43xx_wldev
*dev
,
693 u8 index
, const u8
*addr
)
697 assert(index
>= 4 + 4);
698 memcpy(dev
->key
[index
].address
, addr
, 6);
699 /* We have two default TX keys and two default RX keys.
700 * Physical mac 0 is mapped to physical key 8.
701 * So we must adjust the index here.
705 addrtmp
[0] = addr
[0];
706 addrtmp
[0] |= ((u32
)(addr
[1]) << 8);
707 addrtmp
[0] |= ((u32
)(addr
[2]) << 16);
708 addrtmp
[0] |= ((u32
)(addr
[3]) << 24);
709 addrtmp
[1] = addr
[4];
710 addrtmp
[1] |= ((u32
)(addr
[5]) << 8);
712 if (dev
->dev
->id
.revision
>= 5) {
713 /* Receive match transmitter address mechanism */
714 bcm43xx_shm_write32(dev
, BCM43xx_SHM_RCMTA
,
715 (index
* 2) + 0, addrtmp
[0]);
716 bcm43xx_shm_write16(dev
, BCM43xx_SHM_RCMTA
,
717 (index
* 2) + 1, addrtmp
[1]);
719 /* RXE (Receive Engine) and
720 * PSM (Programmable State Machine) mechanism
723 /* TODO write to RCM 16, 19, 22 and 25 */
726 bcm43xx_shm_write32(dev
, BCM43xx_SHM_SHARED
,
727 BCM43xx_SHM_SH_PSM
+ (index
* 6) + 0,
729 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
730 BCM43xx_SHM_SH_PSM
+ (index
* 6) + 4,
736 static void do_key_write(struct bcm43xx_wldev
*dev
,
737 u8 index
, u8 algorithm
,
738 const u8
*key
, size_t key_len
,
741 u8 buf
[BCM43xx_SEC_KEYSIZE
];
743 assert(index
< dev
->max_nr_keys
);
744 assert(key_len
<= BCM43xx_SEC_KEYSIZE
);
746 memset(buf
, 0, sizeof(buf
));
748 keymac_write(dev
, index
, buf
); /* First zero out mac. */
749 memcpy(buf
, key
, key_len
);
750 key_write(dev
, index
, algorithm
, buf
);
752 keymac_write(dev
, index
, mac_addr
);
754 dev
->key
[index
].algorithm
= algorithm
;
757 static int bcm43xx_key_write(struct bcm43xx_wldev
*dev
,
758 int index
, u8 algorithm
,
759 const u8
*key
, size_t key_len
,
761 struct ieee80211_key_conf
*keyconf
)
766 if (key_len
> BCM43xx_SEC_KEYSIZE
)
769 /* Per station key with associated MAC address.
770 * Look if it already exists, if yes update, otherwise
771 * allocate a new key.
773 if (bcm43xx_new_kidx_api(dev
))
777 for (i
= sta_keys_start
; i
< dev
->max_nr_keys
; i
++) {
778 if (compare_ether_addr(dev
->key
[i
].address
, mac_addr
) == 0) {
785 for (i
= sta_keys_start
; i
< dev
->max_nr_keys
; i
++) {
786 if (!dev
->key
[i
].enabled
) {
794 dprintk(KERN_ERR PFX
"Out of hw key memory\n");
800 do_key_write(dev
, index
, algorithm
, key
, key_len
, mac_addr
);
801 if ((index
<= 3) && !bcm43xx_new_kidx_api(dev
)) {
803 assert(mac_addr
== NULL
);
804 do_key_write(dev
, index
+ 4, algorithm
, key
, key_len
, NULL
);
806 keyconf
->hw_key_idx
= index
;
811 static void bcm43xx_clear_keys(struct bcm43xx_wldev
*dev
)
813 static const u8 zero
[BCM43xx_SEC_KEYSIZE
] = { 0 };
816 BUILD_BUG_ON(BCM43xx_SEC_KEYSIZE
< ETH_ALEN
);
817 for (i
= 0; i
< dev
->max_nr_keys
; i
++) {
818 do_key_write(dev
, i
, BCM43xx_SEC_ALGO_NONE
,
819 zero
, BCM43xx_SEC_KEYSIZE
,
821 dev
->key
[i
].enabled
= 0;
825 /* Turn the Analog ON/OFF */
826 static void bcm43xx_switch_analog(struct bcm43xx_wldev
*dev
, int on
)
828 bcm43xx_write16(dev
, BCM43xx_MMIO_PHY0
, on
? 0 : 0xF4);
831 void bcm43xx_wireless_core_reset(struct bcm43xx_wldev
*dev
, u32 flags
)
836 flags
|= BCM43xx_TMSLOW_PHYCLKEN
;
837 flags
|= BCM43xx_TMSLOW_PHYRESET
;
838 ssb_device_enable(dev
->dev
, flags
);
839 msleep(2); /* Wait for the PLL to turn on. */
841 /* Now take the PHY out of Reset again */
842 tmslow
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
843 tmslow
|= SSB_TMSLOW_FGC
;
844 tmslow
&= ~BCM43xx_TMSLOW_PHYRESET
;
845 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
846 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
848 tmslow
&= ~SSB_TMSLOW_FGC
;
849 ssb_write32(dev
->dev
, SSB_TMSLOW
, tmslow
);
850 ssb_read32(dev
->dev
, SSB_TMSLOW
); /* flush */
854 bcm43xx_switch_analog(dev
, 1);
856 macctl
= bcm43xx_read32(dev
, BCM43xx_MMIO_MACCTL
);
857 macctl
&= ~BCM43xx_MACCTL_GMODE
;
858 if (flags
& BCM43xx_TMSLOW_GMODE
)
859 macctl
|= BCM43xx_MACCTL_GMODE
;
860 macctl
|= BCM43xx_MACCTL_IHR_ENABLED
;
861 bcm43xx_write32(dev
, BCM43xx_MMIO_MACCTL
, macctl
);
864 static void handle_irq_transmit_status(struct bcm43xx_wldev
*dev
)
868 struct bcm43xx_txstatus stat
;
871 v0
= bcm43xx_read32(dev
, BCM43xx_MMIO_XMITSTAT_0
);
872 if (!(v0
& 0x00000001))
874 v1
= bcm43xx_read32(dev
, BCM43xx_MMIO_XMITSTAT_1
);
876 stat
.cookie
= (v0
>> 16);
877 stat
.seq
= (v1
& 0x0000FFFF);
878 stat
.phy_stat
= ((v1
& 0x00FF0000) >> 16);
879 tmp
= (v0
& 0x0000FFFF);
880 stat
.frame_count
= ((tmp
& 0xF000) >> 12);
881 stat
.rts_count
= ((tmp
& 0x0F00) >> 8);
882 stat
.supp_reason
= ((tmp
& 0x001C) >> 2);
883 stat
.pm_indicated
= !!(tmp
& 0x0080);
884 stat
.intermediate
= !!(tmp
& 0x0040);
885 stat
.for_ampdu
= !!(tmp
& 0x0020);
886 stat
.acked
= !!(tmp
& 0x0002);
888 bcm43xx_handle_txstatus(dev
, &stat
);
892 static void drain_txstatus_queue(struct bcm43xx_wldev
*dev
)
896 if (dev
->dev
->id
.revision
< 5)
898 /* Read all entries from the microcode TXstatus FIFO
899 * and throw them away.
902 dummy
= bcm43xx_read32(dev
, BCM43xx_MMIO_XMITSTAT_0
);
903 if (!(dummy
& 0x00000001))
905 dummy
= bcm43xx_read32(dev
, BCM43xx_MMIO_XMITSTAT_1
);
909 static u32
bcm43xx_jssi_read(struct bcm43xx_wldev
*dev
)
913 val
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x08A);
915 val
|= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x088);
920 static void bcm43xx_jssi_write(struct bcm43xx_wldev
*dev
, u32 jssi
)
922 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x088,
923 (jssi
& 0x0000FFFF));
924 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x08A,
925 (jssi
& 0xFFFF0000) >> 16);
928 static void bcm43xx_generate_noise_sample(struct bcm43xx_wldev
*dev
)
930 bcm43xx_jssi_write(dev
, 0x7F7F7F7F);
931 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
,
932 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
)
934 assert(dev
->noisecalc
.channel_at_start
== dev
->phy
.channel
);
937 static void bcm43xx_calculate_link_quality(struct bcm43xx_wldev
*dev
)
939 /* Top half of Link Quality calculation. */
941 if (dev
->noisecalc
.calculation_running
)
943 dev
->noisecalc
.channel_at_start
= dev
->phy
.channel
;
944 dev
->noisecalc
.calculation_running
= 1;
945 dev
->noisecalc
.nr_samples
= 0;
947 bcm43xx_generate_noise_sample(dev
);
950 static void handle_irq_noise(struct bcm43xx_wldev
*dev
)
952 struct bcm43xx_phy
*phy
= &dev
->phy
;
958 /* Bottom half of Link Quality calculation. */
960 assert(dev
->noisecalc
.calculation_running
);
961 if (dev
->noisecalc
.channel_at_start
!= phy
->channel
)
962 goto drop_calculation
;
963 *((u32
*)noise
) = cpu_to_le32(bcm43xx_jssi_read(dev
));
964 if (noise
[0] == 0x7F || noise
[1] == 0x7F ||
965 noise
[2] == 0x7F || noise
[3] == 0x7F)
968 /* Get the noise samples. */
969 assert(dev
->noisecalc
.nr_samples
< 8);
970 i
= dev
->noisecalc
.nr_samples
;
971 noise
[0] = limit_value(noise
[0], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
972 noise
[1] = limit_value(noise
[1], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
973 noise
[2] = limit_value(noise
[2], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
974 noise
[3] = limit_value(noise
[3], 0, ARRAY_SIZE(phy
->nrssi_lt
) - 1);
975 dev
->noisecalc
.samples
[i
][0] = phy
->nrssi_lt
[noise
[0]];
976 dev
->noisecalc
.samples
[i
][1] = phy
->nrssi_lt
[noise
[1]];
977 dev
->noisecalc
.samples
[i
][2] = phy
->nrssi_lt
[noise
[2]];
978 dev
->noisecalc
.samples
[i
][3] = phy
->nrssi_lt
[noise
[3]];
979 dev
->noisecalc
.nr_samples
++;
980 if (dev
->noisecalc
.nr_samples
== 8) {
981 /* Calculate the Link Quality by the noise samples. */
983 for (i
= 0; i
< 8; i
++) {
984 for (j
= 0; j
< 4; j
++)
985 average
+= dev
->noisecalc
.samples
[i
][j
];
991 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, 0x40C);
992 tmp
= (tmp
/ 128) & 0x1F;
1002 dev
->stats
.link_noise
= average
;
1004 dev
->noisecalc
.calculation_running
= 0;
1008 bcm43xx_generate_noise_sample(dev
);
1011 static void handle_irq_tbtt_indication(struct bcm43xx_wldev
*dev
)
1013 if (bcm43xx_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
)) {
1016 if (1/*FIXME: the last PSpoll frame was sent successfully */)
1017 bcm43xx_power_saving_ctl_bits(dev
, -1, -1);
1019 dev
->reg124_set_0x4
= 0;
1020 if (bcm43xx_is_mode(dev
->wl
, IEEE80211_IF_TYPE_IBSS
))
1021 dev
->reg124_set_0x4
= 1;
1024 static void handle_irq_atim_end(struct bcm43xx_wldev
*dev
)
1026 if (!dev
->reg124_set_0x4
/*FIXME rename this variable*/)
1028 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
,
1029 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
)
1033 static void handle_irq_pmq(struct bcm43xx_wldev
*dev
)
1040 tmp
= bcm43xx_read32(dev
, BCM43xx_MMIO_PS_STATUS
);
1041 if (!(tmp
& 0x00000008))
1044 /* 16bit write is odd, but correct. */
1045 bcm43xx_write16(dev
, BCM43xx_MMIO_PS_STATUS
, 0x0002);
1048 static void bcm43xx_write_template_common(struct bcm43xx_wldev
*dev
,
1049 const u8
* data
, u16 size
,
1051 u16 shm_size_offset
, u8 rate
)
1054 struct bcm43xx_plcp_hdr4 plcp
;
1057 bcm43xx_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1058 bcm43xx_ram_write(dev
, ram_offset
, le32_to_cpu(plcp
.data
));
1059 ram_offset
+= sizeof(u32
);
1060 /* The PLCP is 6 bytes long, but we only wrote 4 bytes, yet.
1061 * So leave the first two bytes of the next write blank.
1063 tmp
= (u32
)(data
[0]) << 16;
1064 tmp
|= (u32
)(data
[1]) << 24;
1065 bcm43xx_ram_write(dev
, ram_offset
, tmp
);
1066 ram_offset
+= sizeof(u32
);
1067 for (i
= 2; i
< size
; i
+= sizeof(u32
)) {
1068 tmp
= (u32
)(data
[i
+ 0]);
1070 tmp
|= (u32
)(data
[i
+ 1]) << 8;
1072 tmp
|= (u32
)(data
[i
+ 2]) << 16;
1074 tmp
|= (u32
)(data
[i
+ 3]) << 24;
1075 bcm43xx_ram_write(dev
, ram_offset
+ i
- 2, tmp
);
1077 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, shm_size_offset
,
1078 size
+ sizeof(struct bcm43xx_plcp_hdr6
));
1081 static void bcm43xx_write_beacon_template(struct bcm43xx_wldev
*dev
,
1083 u16 shm_size_offset
, u8 rate
)
1088 assert(dev
->cached_beacon
);
1089 len
= min((size_t)dev
->cached_beacon
->len
,
1090 0x200 - sizeof(struct bcm43xx_plcp_hdr6
));
1091 data
= (const u8
*)(dev
->cached_beacon
->data
);
1092 bcm43xx_write_template_common(dev
, data
,
1094 shm_size_offset
, rate
);
1097 static void bcm43xx_write_probe_resp_plcp(struct bcm43xx_wldev
*dev
,
1098 u16 shm_offset
, u16 size
, u8 rate
)
1100 struct bcm43xx_plcp_hdr4 plcp
;
1105 bcm43xx_generate_plcp_hdr(&plcp
, size
+ FCS_LEN
, rate
);
1107 * 144 + 48 + 10 = preamble + PLCP + SIFS,
1108 * taken from mac80211 timings calculation.
1110 * FIXME: long preamble assumed!
1113 packet_time
= 202 + (size
+ FCS_LEN
) * 16 / rate
;
1114 if ((size
+ FCS_LEN
) * 16 % rate
>= rate
/ 2)
1117 /* Write PLCP in two parts and timing for packet transfer */
1118 tmp
= le32_to_cpu(plcp
.data
);
1119 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, shm_offset
,
1121 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, shm_offset
+ 2,
1123 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, shm_offset
+ 6,
1127 /* Instead of using custom probe response template, this function
1128 * just patches custom beacon template by:
1129 * 1) Changing packet type
1130 * 2) Patching duration field
1133 static u8
* bcm43xx_generate_probe_resp(struct bcm43xx_wldev
*dev
,
1134 u16
* dest_size
, u8 rate
)
1138 u16 src_size
, elem_size
, src_pos
, dest_pos
, tmp
;
1140 assert(dev
->cached_beacon
);
1141 src_size
= dev
->cached_beacon
->len
;
1142 src_data
= (const u8
*)dev
->cached_beacon
->data
;
1144 if (unlikely(src_size
< 0x24)) {
1145 dprintk(KERN_ERR PFX
"bcm43xx_generate_probe_resp: "
1146 "invalid beacon\n");
1150 dest_data
= kmalloc(src_size
, GFP_ATOMIC
);
1151 if (unlikely(!dest_data
))
1154 /* 0x24 is offset of first variable-len Information-Element
1157 memcpy(dest_data
, src_data
, 0x24);
1158 src_pos
= dest_pos
= 0x24;
1159 for ( ; src_pos
< src_size
- 2; src_pos
+= elem_size
) {
1160 elem_size
= src_data
[src_pos
+ 1] + 2;
1161 if (src_data
[src_pos
] != 0x05) { /* TIM */
1162 memcpy(dest_data
+ dest_pos
, src_data
+ src_pos
,
1164 dest_pos
+= elem_size
;
1167 *dest_size
= dest_pos
;
1169 /* Set the frame control. */
1170 dest_data
[0] = (IEEE80211_FTYPE_MGMT
|
1171 IEEE80211_STYPE_PROBE_RESP
);
1174 /* Set the duration field.
1176 * 144 + 48 + 10 = preamble + PLCP + SIFS,
1177 * taken from mac80211 timings calculation.
1179 * FIXME: long preamble assumed!
1182 tmp
= 202 + (14 + FCS_LEN
) * 16 / rate
;
1183 if ((14 + FCS_LEN
) * 16 % rate
>= rate
/ 2)
1186 dest_data
[2] = tmp
& 0xFF;
1187 dest_data
[3] = (tmp
>> 8) & 0xFF;
1192 static void bcm43xx_write_probe_resp_template(struct bcm43xx_wldev
*dev
,
1194 u16 shm_size_offset
, u8 rate
)
1196 u8
* probe_resp_data
;
1199 assert(dev
->cached_beacon
);
1200 size
= dev
->cached_beacon
->len
;
1201 probe_resp_data
= bcm43xx_generate_probe_resp(dev
, &size
, rate
);
1202 if (unlikely(!probe_resp_data
))
1205 /* Looks like PLCP headers plus packet timings are stored for
1206 * all possible basic rates
1208 bcm43xx_write_probe_resp_plcp(dev
, 0x31A, size
,
1209 BCM43xx_CCK_RATE_1MB
);
1210 bcm43xx_write_probe_resp_plcp(dev
, 0x32C, size
,
1211 BCM43xx_CCK_RATE_2MB
);
1212 bcm43xx_write_probe_resp_plcp(dev
, 0x33E, size
,
1213 BCM43xx_CCK_RATE_5MB
);
1214 bcm43xx_write_probe_resp_plcp(dev
, 0x350, size
,
1215 BCM43xx_CCK_RATE_11MB
);
1217 size
= min((size_t)size
,
1218 0x200 - sizeof(struct bcm43xx_plcp_hdr6
));
1219 bcm43xx_write_template_common(dev
, probe_resp_data
,
1221 shm_size_offset
, rate
);
1222 kfree(probe_resp_data
);
1225 static int bcm43xx_refresh_cached_beacon(struct bcm43xx_wldev
*dev
,
1226 struct sk_buff
*beacon
)
1228 if (dev
->cached_beacon
)
1229 kfree_skb(dev
->cached_beacon
);
1230 dev
->cached_beacon
= beacon
;
1235 static void bcm43xx_update_templates(struct bcm43xx_wldev
*dev
)
1239 assert(dev
->cached_beacon
);
1241 bcm43xx_write_beacon_template(dev
, 0x68, 0x18,
1242 BCM43xx_CCK_RATE_1MB
);
1243 bcm43xx_write_beacon_template(dev
, 0x468, 0x1A,
1244 BCM43xx_CCK_RATE_1MB
);
1245 bcm43xx_write_probe_resp_template(dev
, 0x268, 0x4A,
1246 BCM43xx_CCK_RATE_11MB
);
1248 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
);
1250 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
, status
);
1253 static void bcm43xx_refresh_templates(struct bcm43xx_wldev
*dev
,
1254 struct sk_buff
*beacon
)
1258 err
= bcm43xx_refresh_cached_beacon(dev
, beacon
);
1261 bcm43xx_update_templates(dev
);
1264 static void bcm43xx_set_ssid(struct bcm43xx_wldev
*dev
,
1265 const u8
*ssid
, u8 ssid_len
)
1270 len
= min((u16
)ssid_len
, (u16
)0x100);
1271 for (i
= 0; i
< len
; i
+= sizeof(u32
)) {
1272 tmp
= (u32
)(ssid
[i
+ 0]);
1274 tmp
|= (u32
)(ssid
[i
+ 1]) << 8;
1276 tmp
|= (u32
)(ssid
[i
+ 2]) << 16;
1278 tmp
|= (u32
)(ssid
[i
+ 3]) << 24;
1279 bcm43xx_shm_write32(dev
, BCM43xx_SHM_SHARED
,
1282 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
1286 static void bcm43xx_set_beacon_int(struct bcm43xx_wldev
*dev
, u16 beacon_int
)
1288 bcm43xx_time_lock(dev
);
1289 if (dev
->dev
->id
.revision
>= 3) {
1290 bcm43xx_write32(dev
, 0x188, (beacon_int
<< 16));
1292 bcm43xx_write16(dev
, 0x606, (beacon_int
>> 6));
1293 bcm43xx_write16(dev
, 0x610, beacon_int
);
1295 bcm43xx_time_unlock(dev
);
1298 static void handle_irq_beacon(struct bcm43xx_wldev
*dev
)
1302 if (!bcm43xx_is_mode(dev
->wl
, IEEE80211_IF_TYPE_AP
))
1305 dev
->irq_savedstate
&= ~BCM43xx_IRQ_BEACON
;
1306 status
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
);
1308 if (!dev
->cached_beacon
|| ((status
& 0x1) && (status
& 0x2))) {
1309 /* ACK beacon IRQ. */
1310 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
,
1311 BCM43xx_IRQ_BEACON
);
1312 dev
->irq_savedstate
|= BCM43xx_IRQ_BEACON
;
1313 if (dev
->cached_beacon
)
1314 kfree_skb(dev
->cached_beacon
);
1315 dev
->cached_beacon
= NULL
;
1318 if (!(status
& 0x1)) {
1319 bcm43xx_write_beacon_template(dev
, 0x68, 0x18,
1320 BCM43xx_CCK_RATE_1MB
);
1322 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
,
1325 if (!(status
& 0x2)) {
1326 bcm43xx_write_beacon_template(dev
, 0x468, 0x1A,
1327 BCM43xx_CCK_RATE_1MB
);
1329 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS2_BITFIELD
,
1334 static void handle_irq_ucode_debug(struct bcm43xx_wldev
*dev
)
1339 /* Interrupt handler bottom-half */
1340 static void bcm43xx_interrupt_tasklet(struct bcm43xx_wldev
*dev
)
1343 u32 dma_reason
[ARRAY_SIZE(dev
->dma_reason
)];
1344 u32 merged_dma_reason
= 0;
1345 int i
, activity
= 0;
1346 unsigned long flags
;
1348 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
1350 assert(bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
);
1351 assert(dev
->started
);
1353 reason
= dev
->irq_reason
;
1354 for (i
= 0; i
< ARRAY_SIZE(dma_reason
); i
++) {
1355 dma_reason
[i
] = dev
->dma_reason
[i
];
1356 merged_dma_reason
|= dma_reason
[i
];
1359 if (unlikely(reason
& BCM43xx_IRQ_MAC_TXERR
))
1360 printkl(KERN_ERR PFX
"MAC transmission error\n");
1362 if (unlikely(reason
& BCM43xx_IRQ_PHY_TXERR
))
1363 printkl(KERN_ERR PFX
"PHY transmission error\n");
1365 if (unlikely(merged_dma_reason
& (BCM43xx_DMAIRQ_FATALMASK
|
1366 BCM43xx_DMAIRQ_NONFATALMASK
))) {
1367 if (merged_dma_reason
& BCM43xx_DMAIRQ_FATALMASK
) {
1368 printkl(KERN_ERR PFX
"FATAL ERROR: Fatal DMA error: "
1369 "0x%08X, 0x%08X, 0x%08X, "
1370 "0x%08X, 0x%08X, 0x%08X\n",
1371 dma_reason
[0], dma_reason
[1],
1372 dma_reason
[2], dma_reason
[3],
1373 dma_reason
[4], dma_reason
[5]);
1374 bcm43xx_controller_restart(dev
, "DMA error");
1376 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1379 if (merged_dma_reason
& BCM43xx_DMAIRQ_NONFATALMASK
) {
1380 printkl(KERN_ERR PFX
"DMA error: "
1381 "0x%08X, 0x%08X, 0x%08X, "
1382 "0x%08X, 0x%08X, 0x%08X\n",
1383 dma_reason
[0], dma_reason
[1],
1384 dma_reason
[2], dma_reason
[3],
1385 dma_reason
[4], dma_reason
[5]);
1389 if (unlikely(reason
& BCM43xx_IRQ_UCODE_DEBUG
))
1390 handle_irq_ucode_debug(dev
);
1391 if (reason
& BCM43xx_IRQ_TBTT_INDI
)
1392 handle_irq_tbtt_indication(dev
);
1393 if (reason
& BCM43xx_IRQ_ATIM_END
)
1394 handle_irq_atim_end(dev
);
1395 if (reason
& BCM43xx_IRQ_BEACON
)
1396 handle_irq_beacon(dev
);
1397 if (reason
& BCM43xx_IRQ_PMQ
)
1398 handle_irq_pmq(dev
);
1399 if (reason
& BCM43xx_IRQ_TXFIFO_FLUSH_OK
)
1401 if (reason
& BCM43xx_IRQ_NOISESAMPLE_OK
)
1402 handle_irq_noise(dev
);
1404 /* Check the DMA reason registers for received data. */
1405 if (dma_reason
[0] & BCM43xx_DMAIRQ_RX_DONE
) {
1406 if (bcm43xx_using_pio(dev
))
1407 bcm43xx_pio_rx(dev
->pio
.queue0
);
1409 bcm43xx_dma_rx(dev
->dma
.rx_ring0
);
1410 /* We intentionally don't set "activity" to 1, here. */
1412 assert(!(dma_reason
[1] & BCM43xx_DMAIRQ_RX_DONE
));
1413 assert(!(dma_reason
[2] & BCM43xx_DMAIRQ_RX_DONE
));
1414 if (dma_reason
[3] & BCM43xx_DMAIRQ_RX_DONE
) {
1415 if (bcm43xx_using_pio(dev
))
1416 bcm43xx_pio_rx(dev
->pio
.queue3
);
1418 bcm43xx_dma_rx(dev
->dma
.rx_ring3
);
1421 assert(!(dma_reason
[4] & BCM43xx_DMAIRQ_RX_DONE
));
1422 assert(!(dma_reason
[5] & BCM43xx_DMAIRQ_RX_DONE
));
1424 if (reason
& BCM43xx_IRQ_TX_OK
) {
1425 handle_irq_transmit_status(dev
);
1427 //TODO: In AP mode, this also causes sending of powersave responses.
1430 if (!modparam_noleds
)
1431 bcm43xx_leds_update(dev
, activity
);
1432 bcm43xx_interrupt_enable(dev
, dev
->irq_savedstate
);
1434 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
1437 static void pio_irq_workaround(struct bcm43xx_wldev
*dev
,
1438 u16 base
, int queueidx
)
1442 rxctl
= bcm43xx_read16(dev
, base
+ BCM43xx_PIO_RXCTL
);
1443 if (rxctl
& BCM43xx_PIO_RXCTL_DATAAVAILABLE
)
1444 dev
->dma_reason
[queueidx
] |= BCM43xx_DMAIRQ_RX_DONE
;
1446 dev
->dma_reason
[queueidx
] &= ~BCM43xx_DMAIRQ_RX_DONE
;
1449 static void bcm43xx_interrupt_ack(struct bcm43xx_wldev
*dev
, u32 reason
)
1451 if (bcm43xx_using_pio(dev
) &&
1452 (dev
->dev
->id
.revision
< 3) &&
1453 (!(reason
& BCM43xx_IRQ_PIO_WORKAROUND
))) {
1454 /* Apply a PIO specific workaround to the dma_reasons */
1455 pio_irq_workaround(dev
, BCM43xx_MMIO_PIO1_BASE
, 0);
1456 pio_irq_workaround(dev
, BCM43xx_MMIO_PIO2_BASE
, 1);
1457 pio_irq_workaround(dev
, BCM43xx_MMIO_PIO3_BASE
, 2);
1458 pio_irq_workaround(dev
, BCM43xx_MMIO_PIO4_BASE
, 3);
1461 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
, reason
);
1463 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA0_REASON
,
1464 dev
->dma_reason
[0]);
1465 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA1_REASON
,
1466 dev
->dma_reason
[1]);
1467 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA2_REASON
,
1468 dev
->dma_reason
[2]);
1469 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA3_REASON
,
1470 dev
->dma_reason
[3]);
1471 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA4_REASON
,
1472 dev
->dma_reason
[4]);
1473 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA5_REASON
,
1474 dev
->dma_reason
[5]);
1477 /* Interrupt handler top-half */
1478 static irqreturn_t
bcm43xx_interrupt_handler(int irq
, void *dev_id
)
1480 irqreturn_t ret
= IRQ_HANDLED
;
1481 struct bcm43xx_wldev
*dev
= dev_id
;
1487 spin_lock(&dev
->wl
->irq_lock
);
1489 reason
= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
);
1490 if (reason
== 0xffffffff) {
1491 /* irq not for us (shared irq) */
1495 reason
&= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_MASK
);
1499 assert(bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
);
1500 assert(dev
->started
);
1502 dev
->dma_reason
[0] = bcm43xx_read32(dev
, BCM43xx_MMIO_DMA0_REASON
)
1504 dev
->dma_reason
[1] = bcm43xx_read32(dev
, BCM43xx_MMIO_DMA1_REASON
)
1506 dev
->dma_reason
[2] = bcm43xx_read32(dev
, BCM43xx_MMIO_DMA2_REASON
)
1508 dev
->dma_reason
[3] = bcm43xx_read32(dev
, BCM43xx_MMIO_DMA3_REASON
)
1510 dev
->dma_reason
[4] = bcm43xx_read32(dev
, BCM43xx_MMIO_DMA4_REASON
)
1512 dev
->dma_reason
[5] = bcm43xx_read32(dev
, BCM43xx_MMIO_DMA5_REASON
)
1515 bcm43xx_interrupt_ack(dev
, reason
);
1516 /* disable all IRQs. They are enabled again in the bottom half. */
1517 dev
->irq_savedstate
= bcm43xx_interrupt_disable(dev
, BCM43xx_IRQ_ALL
);
1518 /* save the reason code and call our bottom half. */
1519 dev
->irq_reason
= reason
;
1520 tasklet_schedule(&dev
->isr_tasklet
);
1523 spin_unlock(&dev
->wl
->irq_lock
);
1528 static void bcm43xx_release_firmware(struct bcm43xx_wldev
*dev
)
1530 release_firmware(dev
->fw
.ucode
);
1531 dev
->fw
.ucode
= NULL
;
1532 release_firmware(dev
->fw
.pcm
);
1534 release_firmware(dev
->fw
.initvals0
);
1535 dev
->fw
.initvals0
= NULL
;
1536 release_firmware(dev
->fw
.initvals1
);
1537 dev
->fw
.initvals1
= NULL
;
1540 static int bcm43xx_request_firmware(struct bcm43xx_wldev
*dev
)
1542 u8 rev
= dev
->dev
->id
.revision
;
1545 char buf
[22 + sizeof(modparam_fwpostfix
) - 1] = { 0 };
1547 if (!dev
->fw
.ucode
) {
1548 snprintf(buf
, ARRAY_SIZE(buf
), "bcm43xx_microcode%d%s.fw",
1549 (rev
>= 5 ? 5 : rev
),
1550 modparam_fwpostfix
);
1551 err
= request_firmware(&dev
->fw
.ucode
, buf
, dev
->dev
->dev
);
1554 "Error: Microcode \"%s\" not available or load failed.\n",
1561 snprintf(buf
, ARRAY_SIZE(buf
),
1562 "bcm43xx_pcm%d%s.fw",
1564 modparam_fwpostfix
);
1565 err
= request_firmware(&dev
->fw
.pcm
, buf
, dev
->dev
->dev
);
1568 "Error: PCM \"%s\" not available or load failed.\n",
1574 if (!dev
->fw
.initvals0
) {
1575 if (rev
== 2 || rev
== 4) {
1576 switch (dev
->phy
.type
) {
1577 case BCM43xx_PHYTYPE_A
:
1580 case BCM43xx_PHYTYPE_B
:
1581 case BCM43xx_PHYTYPE_G
:
1588 } else if (rev
>= 5) {
1589 switch (dev
->phy
.type
) {
1590 case BCM43xx_PHYTYPE_A
:
1593 case BCM43xx_PHYTYPE_B
:
1594 case BCM43xx_PHYTYPE_G
:
1602 snprintf(buf
, ARRAY_SIZE(buf
), "bcm43xx_initval%02d%s.fw",
1603 nr
, modparam_fwpostfix
);
1605 err
= request_firmware(&dev
->fw
.initvals0
, buf
, dev
->dev
->dev
);
1608 "Error: InitVals \"%s\" not available or load failed.\n",
1612 if (dev
->fw
.initvals0
->size
% sizeof(struct bcm43xx_initval
)) {
1613 printk(KERN_ERR PFX
"InitVals fileformat error.\n");
1618 if (!dev
->fw
.initvals1
) {
1622 switch (dev
->phy
.type
) {
1623 case BCM43xx_PHYTYPE_A
:
1624 sbtmstatehigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
1625 if (sbtmstatehigh
& 0x00010000)
1630 case BCM43xx_PHYTYPE_B
:
1631 case BCM43xx_PHYTYPE_G
:
1637 snprintf(buf
, ARRAY_SIZE(buf
), "bcm43xx_initval%02d%s.fw",
1638 nr
, modparam_fwpostfix
);
1640 err
= request_firmware(&dev
->fw
.initvals1
, buf
, dev
->dev
->dev
);
1643 "Error: InitVals \"%s\" not available or load failed.\n",
1647 if (dev
->fw
.initvals1
->size
% sizeof(struct bcm43xx_initval
)) {
1648 printk(KERN_ERR PFX
"InitVals fileformat error.\n");
1657 bcm43xx_release_firmware(dev
);
1660 printk(KERN_ERR PFX
"Error: No InitVals available!\n");
1665 static int bcm43xx_upload_microcode(struct bcm43xx_wldev
*dev
)
1668 unsigned int i
, len
;
1669 u16 fwrev
, fwpatch
, fwdate
, fwtime
;
1673 /* Upload Microcode. */
1674 data
= (__be32
*)(dev
->fw
.ucode
->data
);
1675 len
= dev
->fw
.ucode
->size
/ sizeof(__be32
);
1676 bcm43xx_shm_control_word(dev
,
1677 BCM43xx_SHM_UCODE
| BCM43xx_SHM_AUTOINC_W
,
1679 for (i
= 0; i
< len
; i
++) {
1680 bcm43xx_write32(dev
, BCM43xx_MMIO_SHM_DATA
,
1681 be32_to_cpu(data
[i
]));
1685 /* Upload PCM data. */
1686 data
= (__be32
*)(dev
->fw
.pcm
->data
);
1687 len
= dev
->fw
.pcm
->size
/ sizeof(__be32
);
1688 bcm43xx_shm_control_word(dev
, BCM43xx_SHM_HW
, 0x01EA);
1689 bcm43xx_write32(dev
, BCM43xx_MMIO_SHM_DATA
, 0x00004000);
1690 /* No need for autoinc bit in SHM_HW */
1691 bcm43xx_shm_control_word(dev
, BCM43xx_SHM_HW
, 0x01EB);
1692 for (i
= 0; i
< len
; i
++) {
1693 bcm43xx_write32(dev
, BCM43xx_MMIO_SHM_DATA
,
1694 be32_to_cpu(data
[i
]));
1698 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
, BCM43xx_IRQ_ALL
);
1699 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, 0x00020402);
1701 /* Wait for the microcode to load and respond */
1704 tmp
= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
);
1705 if (tmp
== BCM43xx_IRQ_MAC_SUSPENDED
)
1708 if (i
>= BCM43xx_IRQWAIT_MAX_RETRIES
) {
1709 printk(KERN_ERR PFX
"Microcode not responding\n");
1715 bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
); /* dummy read */
1717 /* Get and check the revisions. */
1718 fwrev
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
1719 BCM43xx_SHM_SH_UCODEREV
);
1720 fwpatch
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
1721 BCM43xx_SHM_SH_UCODEPATCH
);
1722 fwdate
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
1723 BCM43xx_SHM_SH_UCODEDATE
);
1724 fwtime
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
1725 BCM43xx_SHM_SH_UCODETIME
);
1727 if (fwrev
<= 0x128) {
1728 printk(KERN_ERR PFX
"YOUR FIRMWARE IS TOO OLD. Firmware from "
1729 "binary drivers older than version 4.x is unsupported. "
1730 "You must upgrade your firmware files.\n");
1731 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, 0);
1735 printk(KERN_DEBUG PFX
"Loading firmware version %u.%u "
1736 "(20%.2i-%.2i-%.2i %.2i:%.2i:%.2i)\n",
1738 (fwdate
>> 12) & 0xF, (fwdate
>> 8) & 0xF, fwdate
& 0xFF,
1739 (fwtime
>> 11) & 0x1F, (fwtime
>> 5) & 0x3F, fwtime
& 0x1F);
1741 dev
->fw
.rev
= fwrev
;
1742 dev
->fw
.patch
= fwpatch
;
1748 static int bcm43xx_write_initvals(struct bcm43xx_wldev
*dev
,
1749 const struct bcm43xx_initval
*data
,
1750 const unsigned int len
)
1756 for (i
= 0; i
< len
; i
++) {
1757 offset
= be16_to_cpu(data
[i
].offset
);
1758 size
= be16_to_cpu(data
[i
].size
);
1759 value
= be32_to_cpu(data
[i
].value
);
1761 if (unlikely(offset
>= 0x1000))
1764 if (unlikely(value
& 0xFFFF0000))
1766 bcm43xx_write16(dev
, offset
, (u16
)value
);
1767 } else if (size
== 4) {
1768 bcm43xx_write32(dev
, offset
, value
);
1776 printk(KERN_ERR PFX
"InitVals (bcm43xx_initvalXX.fw) file-format error. "
1777 "Please fix your bcm43xx firmware files.\n");
1781 static int bcm43xx_upload_initvals(struct bcm43xx_wldev
*dev
)
1785 err
= bcm43xx_write_initvals(dev
, (struct bcm43xx_initval
*)dev
->fw
.initvals0
->data
,
1786 dev
->fw
.initvals0
->size
/ sizeof(struct bcm43xx_initval
));
1789 if (dev
->fw
.initvals1
) {
1790 err
= bcm43xx_write_initvals(dev
, (struct bcm43xx_initval
*)dev
->fw
.initvals1
->data
,
1791 dev
->fw
.initvals1
->size
/ sizeof(struct bcm43xx_initval
));
1799 /* Initialize the GPIOs
1800 * http://bcm-specs.sipsolutions.net/GPIO
1802 static int bcm43xx_gpio_init(struct bcm43xx_wldev
*dev
)
1804 struct ssb_bus
*bus
= dev
->dev
->bus
;
1805 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1808 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
,
1809 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
)
1812 bcm43xx_leds_switch_all(dev
, 0);
1813 bcm43xx_write16(dev
, BCM43xx_MMIO_GPIO_MASK
,
1814 bcm43xx_read16(dev
, BCM43xx_MMIO_GPIO_MASK
)
1819 if (dev
->dev
->bus
->chip_id
== 0x4301) {
1823 if (0 /* FIXME: conditional unknown */) {
1824 bcm43xx_write16(dev
, BCM43xx_MMIO_GPIO_MASK
,
1825 bcm43xx_read16(dev
, BCM43xx_MMIO_GPIO_MASK
)
1830 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_PACTRL
) {
1831 bcm43xx_write16(dev
, BCM43xx_MMIO_GPIO_MASK
,
1832 bcm43xx_read16(dev
, BCM43xx_MMIO_GPIO_MASK
)
1837 if (dev
->dev
->id
.revision
>= 2)
1838 mask
|= 0x0010; /* FIXME: This is redundant. */
1840 #ifdef CONFIG_SSB_DRIVER_PCICORE
1841 pcidev
= bus
->pcicore
.dev
;
1843 gpiodev
= bus
->chipco
.dev
? : pcidev
;
1846 ssb_write32(gpiodev
, BCM43xx_GPIO_CONTROL
,
1847 (ssb_read32(gpiodev
, BCM43xx_GPIO_CONTROL
)
1853 /* Turn off all GPIO stuff. Call this on module unload, for example. */
1854 static void bcm43xx_gpio_cleanup(struct bcm43xx_wldev
*dev
)
1856 struct ssb_bus
*bus
= dev
->dev
->bus
;
1857 struct ssb_device
*gpiodev
, *pcidev
= NULL
;
1859 #ifdef CONFIG_SSB_DRIVER_PCICORE
1860 pcidev
= bus
->pcicore
.dev
;
1862 gpiodev
= bus
->chipco
.dev
? : pcidev
;
1865 ssb_write32(gpiodev
, BCM43xx_GPIO_CONTROL
, 0);
1868 /* http://bcm-specs.sipsolutions.net/EnableMac */
1869 void bcm43xx_mac_enable(struct bcm43xx_wldev
*dev
)
1871 dev
->mac_suspended
--;
1872 assert(dev
->mac_suspended
>= 0);
1873 if (dev
->mac_suspended
== 0) {
1874 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
,
1875 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
)
1876 | BCM43xx_SBF_MAC_ENABLED
);
1877 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
,
1878 BCM43xx_IRQ_MAC_SUSPENDED
);
1879 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
); /* dummy read */
1880 bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
); /* dummy read */
1881 bcm43xx_power_saving_ctl_bits(dev
, -1, -1);
1885 /* http://bcm-specs.sipsolutions.net/SuspendMAC */
1886 void bcm43xx_mac_suspend(struct bcm43xx_wldev
*dev
)
1891 assert(dev
->mac_suspended
>= 0);
1892 if (dev
->mac_suspended
== 0) {
1893 bcm43xx_power_saving_ctl_bits(dev
, -1, 1);
1894 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
,
1895 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
)
1896 & ~BCM43xx_SBF_MAC_ENABLED
);
1897 bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
); /* dummy read */
1898 for (i
= 10000; i
; i
--) {
1899 tmp
= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
);
1900 if (tmp
& BCM43xx_IRQ_MAC_SUSPENDED
)
1904 printkl(KERN_ERR PFX
"MAC suspend failed\n");
1907 dev
->mac_suspended
++;
1910 static void bcm43xx_adjust_opmode(struct bcm43xx_wldev
*dev
)
1912 struct bcm43xx_wl
*wl
= dev
->wl
;
1916 ctl
= bcm43xx_read32(dev
, BCM43xx_MMIO_MACCTL
);
1917 /* Reset status to STA infrastructure mode. */
1918 ctl
&= ~BCM43xx_MACCTL_AP
;
1919 ctl
&= ~BCM43xx_MACCTL_KEEP_CTL
;
1920 ctl
&= ~BCM43xx_MACCTL_KEEP_BADPLCP
;
1921 ctl
&= ~BCM43xx_MACCTL_KEEP_BAD
;
1922 ctl
&= ~BCM43xx_MACCTL_PROMISC
;
1923 ctl
|= BCM43xx_MACCTL_INFRA
;
1925 if (wl
->operating
) {
1926 switch (wl
->if_type
) {
1927 case IEEE80211_IF_TYPE_AP
:
1928 ctl
|= BCM43xx_MACCTL_AP
;
1930 case IEEE80211_IF_TYPE_IBSS
:
1931 ctl
&= ~BCM43xx_MACCTL_INFRA
;
1933 case IEEE80211_IF_TYPE_STA
:
1934 case IEEE80211_IF_TYPE_MNTR
:
1935 case IEEE80211_IF_TYPE_WDS
:
1942 ctl
|= BCM43xx_MACCTL_PROMISC
;
1943 ctl
|= BCM43xx_MACCTL_KEEP_CTL
;
1944 if (modparam_mon_keep_bad
)
1945 ctl
|= BCM43xx_MACCTL_KEEP_BAD
;
1946 if (modparam_mon_keep_badplcp
)
1947 ctl
|= BCM43xx_MACCTL_KEEP_BADPLCP
;
1950 ctl
|= BCM43xx_MACCTL_PROMISC
;
1952 bcm43xx_write32(dev
, BCM43xx_MMIO_MACCTL
, ctl
);
1955 if ((ctl
& BCM43xx_MACCTL_INFRA
) &&
1956 !(ctl
& BCM43xx_MACCTL_AP
)) {
1957 if (dev
->dev
->bus
->chip_id
== 0x4306 &&
1958 dev
->dev
->bus
->chip_rev
== 3)
1963 bcm43xx_write16(dev
, 0x612, cfp_pretbtt
);
1966 static void bcm43xx_rate_memory_write(struct bcm43xx_wldev
*dev
,
1974 offset
+= (bcm43xx_plcp_get_ratecode_ofdm(rate
) & 0x000F) * 2;
1977 offset
+= (bcm43xx_plcp_get_ratecode_cck(rate
) & 0x000F) * 2;
1979 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, offset
+ 0x20,
1980 bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
, offset
));
1983 static void bcm43xx_rate_memory_init(struct bcm43xx_wldev
*dev
)
1985 switch (dev
->phy
.type
) {
1986 case BCM43xx_PHYTYPE_A
:
1987 case BCM43xx_PHYTYPE_G
:
1988 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_6MB
, 1);
1989 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_12MB
, 1);
1990 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_18MB
, 1);
1991 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_24MB
, 1);
1992 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_36MB
, 1);
1993 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_48MB
, 1);
1994 bcm43xx_rate_memory_write(dev
, BCM43xx_OFDM_RATE_54MB
, 1);
1995 case BCM43xx_PHYTYPE_B
:
1996 bcm43xx_rate_memory_write(dev
, BCM43xx_CCK_RATE_1MB
, 0);
1997 bcm43xx_rate_memory_write(dev
, BCM43xx_CCK_RATE_2MB
, 0);
1998 bcm43xx_rate_memory_write(dev
, BCM43xx_CCK_RATE_5MB
, 0);
1999 bcm43xx_rate_memory_write(dev
, BCM43xx_CCK_RATE_11MB
, 0);
2006 /* Set the TX-Antenna for management frames sent by firmware. */
2007 static void bcm43xx_mgmtframe_txantenna(struct bcm43xx_wldev
*dev
,
2014 case BCM43xx_ANTENNA0
:
2015 ant
|= BCM43xx_TX4_PHY_ANT0
;
2017 case BCM43xx_ANTENNA1
:
2018 ant
|= BCM43xx_TX4_PHY_ANT1
;
2020 case BCM43xx_ANTENNA_AUTO
:
2021 ant
|= BCM43xx_TX4_PHY_ANTLAST
;
2027 /* FIXME We also need to set the other flags of the PHY control field somewhere. */
2030 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
2031 BCM43xx_SHM_SH_BEACPHYCTL
);
2032 tmp
= (tmp
& ~BCM43xx_TX4_PHY_ANT
) | ant
;
2033 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
2034 BCM43xx_SHM_SH_BEACPHYCTL
, tmp
);
2036 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
2037 BCM43xx_SHM_SH_ACKCTSPHYCTL
);
2038 tmp
= (tmp
& ~BCM43xx_TX4_PHY_ANT
) | ant
;
2039 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
2040 BCM43xx_SHM_SH_ACKCTSPHYCTL
, tmp
);
2041 /* For Probe Resposes */
2042 tmp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
2043 BCM43xx_SHM_SH_PRPHYCTL
);
2044 tmp
= (tmp
& ~BCM43xx_TX4_PHY_ANT
) | ant
;
2045 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
2046 BCM43xx_SHM_SH_PRPHYCTL
, tmp
);
2049 /* This is the opposite of bcm43xx_chip_init() */
2050 static void bcm43xx_chip_exit(struct bcm43xx_wldev
*dev
)
2052 bcm43xx_radio_turn_off(dev
);
2053 if (!modparam_noleds
)
2054 bcm43xx_leds_exit(dev
);
2055 bcm43xx_gpio_cleanup(dev
);
2056 /* firmware is released later */
2059 /* Initialize the chip
2060 * http://bcm-specs.sipsolutions.net/ChipInit
2062 static int bcm43xx_chip_init(struct bcm43xx_wldev
*dev
)
2064 struct bcm43xx_phy
*phy
= &dev
->phy
;
2069 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
,
2070 BCM43xx_SBF_CORE_READY
2073 err
= bcm43xx_request_firmware(dev
);
2076 err
= bcm43xx_upload_microcode(dev
);
2078 goto out
; /* firmware is released later */
2080 err
= bcm43xx_gpio_init(dev
);
2082 goto out
; /* firmware is released later */
2083 err
= bcm43xx_upload_initvals(dev
);
2085 goto err_gpio_cleanup
;
2086 bcm43xx_radio_turn_on(dev
);
2087 dev
->radio_hw_enable
= bcm43xx_is_hw_radio_enabled(dev
);
2088 dprintk(KERN_INFO PFX
"Radio %s by hardware\n",
2089 (dev
->radio_hw_enable
== 0) ? "disabled" : "enabled");
2091 bcm43xx_write16(dev
, 0x03E6, 0x0000);
2092 err
= bcm43xx_phy_init(dev
);
2096 /* Select initial Interference Mitigation. */
2097 tmp
= phy
->interfmode
;
2098 phy
->interfmode
= BCM43xx_INTERFMODE_NONE
;
2099 bcm43xx_radio_set_interference_mitigation(dev
, tmp
);
2101 bcm43xx_set_rx_antenna(dev
, BCM43xx_ANTENNA_DEFAULT
);
2102 bcm43xx_mgmtframe_txantenna(dev
, BCM43xx_ANTENNA_DEFAULT
);
2104 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
2105 value16
= bcm43xx_read16(dev
, 0x005E);
2107 bcm43xx_write16(dev
, 0x005E, value16
);
2109 bcm43xx_write32(dev
, 0x0100, 0x01000000);
2110 if (dev
->dev
->id
.revision
< 5)
2111 bcm43xx_write32(dev
, 0x010C, 0x01000000);
2113 value32
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
2114 value32
&= ~ BCM43xx_SBF_MODE_NOTADHOC
;
2115 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2116 value32
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
2117 value32
|= BCM43xx_SBF_MODE_NOTADHOC
;
2118 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2120 value32
= bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
);
2121 value32
|= 0x100000;
2122 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
, value32
);
2124 if (bcm43xx_using_pio(dev
)) {
2125 bcm43xx_write32(dev
, 0x0210, 0x00000100);
2126 bcm43xx_write32(dev
, 0x0230, 0x00000100);
2127 bcm43xx_write32(dev
, 0x0250, 0x00000100);
2128 bcm43xx_write32(dev
, 0x0270, 0x00000100);
2129 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0034, 0x0000);
2132 /* Probe Response Timeout value */
2133 /* FIXME: Default to 0, has to be set by ioctl probably... :-/ */
2134 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0074, 0x0000);
2136 /* Initially set the wireless operation mode. */
2137 bcm43xx_adjust_opmode(dev
);
2139 if (dev
->dev
->id
.revision
< 3) {
2140 bcm43xx_write16(dev
, 0x060E, 0x0000);
2141 bcm43xx_write16(dev
, 0x0610, 0x8000);
2142 bcm43xx_write16(dev
, 0x0604, 0x0000);
2143 bcm43xx_write16(dev
, 0x0606, 0x0200);
2145 bcm43xx_write32(dev
, 0x0188, 0x80000000);
2146 bcm43xx_write32(dev
, 0x018C, 0x02000000);
2148 bcm43xx_write32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
, 0x00004000);
2149 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA0_IRQ_MASK
, 0x0001DC00);
2150 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA1_IRQ_MASK
, 0x0000DC00);
2151 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA2_IRQ_MASK
, 0x0000DC00);
2152 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA3_IRQ_MASK
, 0x0001DC00);
2153 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA4_IRQ_MASK
, 0x0000DC00);
2154 bcm43xx_write32(dev
, BCM43xx_MMIO_DMA5_IRQ_MASK
, 0x0000DC00);
2156 value32
= ssb_read32(dev
->dev
, SSB_TMSLOW
);
2157 value32
|= 0x00100000;
2158 ssb_write32(dev
->dev
, SSB_TMSLOW
, value32
);
2160 bcm43xx_write16(dev
, BCM43xx_MMIO_POWERUP_DELAY
,
2161 dev
->dev
->bus
->chipco
.fast_pwrup_delay
);
2164 dprintk(KERN_INFO PFX
"Chip initialized\n");
2169 bcm43xx_radio_turn_off(dev
);
2171 bcm43xx_gpio_cleanup(dev
);
2175 static void bcm43xx_periodic_every120sec(struct bcm43xx_wldev
*dev
)
2177 struct bcm43xx_phy
*phy
= &dev
->phy
;
2179 if (phy
->type
!= BCM43xx_PHYTYPE_G
|| phy
->rev
< 2)
2182 bcm43xx_mac_suspend(dev
);
2183 bcm43xx_lo_g_measure(dev
);
2184 bcm43xx_mac_enable(dev
);
2187 static void bcm43xx_periodic_every60sec(struct bcm43xx_wldev
*dev
)
2189 bcm43xx_lo_g_ctl_mark_all_unused(dev
);
2190 if (dev
->dev
->bus
->sprom
.r1
.boardflags_lo
& BCM43xx_BFL_RSSI
) {
2191 bcm43xx_mac_suspend(dev
);
2192 bcm43xx_calc_nrssi_slope(dev
);
2193 bcm43xx_mac_enable(dev
);
2197 static void bcm43xx_periodic_every30sec(struct bcm43xx_wldev
*dev
)
2199 /* Update device statistics. */
2200 bcm43xx_calculate_link_quality(dev
);
2203 static void bcm43xx_periodic_every15sec(struct bcm43xx_wldev
*dev
)
2205 struct bcm43xx_phy
*phy
= &dev
->phy
;
2207 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
2208 //TODO: update_aci_moving_average
2209 if (phy
->aci_enable
&& phy
->aci_wlan_automatic
) {
2210 bcm43xx_mac_suspend(dev
);
2211 if (!phy
->aci_enable
&& 1 /*TODO: not scanning? */) {
2212 if (0 /*TODO: bunch of conditions*/) {
2213 bcm43xx_radio_set_interference_mitigation(dev
,
2214 BCM43xx_INTERFMODE_MANUALWLAN
);
2216 } else if (1/*TODO*/) {
2218 if ((aci_average > 1000) && !(bcm43xx_radio_aci_scan(dev))) {
2219 bcm43xx_radio_set_interference_mitigation(dev,
2220 BCM43xx_INTERFMODE_NONE);
2224 bcm43xx_mac_enable(dev
);
2225 } else if (phy
->interfmode
== BCM43xx_INTERFMODE_NONWLAN
&&
2227 //TODO: implement rev1 workaround
2230 bcm43xx_phy_xmitpower(dev
); //FIXME: unless scanning?
2231 //TODO for APHY (temperature?)
2234 static void bcm43xx_periodic_every1sec(struct bcm43xx_wldev
*dev
)
2236 int radio_hw_enable
;
2238 /* check if radio hardware enabled status changed */
2239 radio_hw_enable
= bcm43xx_is_hw_radio_enabled(dev
);
2240 if (unlikely(dev
->radio_hw_enable
!= radio_hw_enable
)) {
2241 dev
->radio_hw_enable
= radio_hw_enable
;
2242 dprintk(KERN_INFO PFX
"Radio hardware status changed to %s\n",
2243 (radio_hw_enable
== 0) ? "disabled" : "enabled");
2244 bcm43xx_leds_update(dev
, 0);
2248 static void do_periodic_work(struct bcm43xx_wldev
*dev
)
2252 state
= dev
->periodic_state
;
2253 if (state
% 120 == 0)
2254 bcm43xx_periodic_every120sec(dev
);
2255 if (state
% 60 == 0)
2256 bcm43xx_periodic_every60sec(dev
);
2257 if (state
% 30 == 0)
2258 bcm43xx_periodic_every30sec(dev
);
2259 if (state
% 15 == 0)
2260 bcm43xx_periodic_every15sec(dev
);
2261 bcm43xx_periodic_every1sec(dev
);
2263 dev
->periodic_state
= state
+ 1;
2265 schedule_delayed_work(&dev
->periodic_work
, HZ
);
2268 /* Estimate a "Badness" value based on the periodic work
2269 * state-machine state. "Badness" is worse (bigger), if the
2270 * periodic work will take longer.
2272 static int estimate_periodic_work_badness(unsigned int state
)
2276 if (state
% 120 == 0) /* every 120 sec */
2278 if (state
% 60 == 0) /* every 60 sec */
2280 if (state
% 30 == 0) /* every 30 sec */
2282 if (state
% 15 == 0) /* every 15 sec */
2285 #define BADNESS_LIMIT 4
2289 static void bcm43xx_periodic_work_handler(struct work_struct
*work
)
2291 struct bcm43xx_wldev
*dev
=
2292 container_of(work
, struct bcm43xx_wldev
, periodic_work
.work
);
2293 unsigned long flags
;
2297 mutex_lock(&dev
->wl
->mutex
);
2298 badness
= estimate_periodic_work_badness(dev
->periodic_state
);
2299 if (badness
> BADNESS_LIMIT
) {
2300 /* Periodic work will take a long time, so we want it to
2303 ieee80211_stop_queues(dev
->wl
->hw
);
2304 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
2305 bcm43xx_mac_suspend(dev
);
2306 if (bcm43xx_using_pio(dev
))
2307 bcm43xx_pio_freeze_txqueues(dev
);
2308 savedirqs
= bcm43xx_interrupt_disable(dev
, BCM43xx_IRQ_ALL
);
2309 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
2310 bcm43xx_synchronize_irq(dev
);
2312 /* Periodic work should take short time, so we want low
2315 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
2318 do_periodic_work(dev
);
2320 if (badness
> BADNESS_LIMIT
) {
2321 spin_lock_irqsave(&dev
->wl
->irq_lock
, flags
);
2322 bcm43xx_interrupt_enable(dev
, savedirqs
);
2323 if (bcm43xx_using_pio(dev
))
2324 bcm43xx_pio_thaw_txqueues(dev
);
2325 bcm43xx_mac_enable(dev
);
2326 ieee80211_start_queues(dev
->wl
->hw
);
2329 spin_unlock_irqrestore(&dev
->wl
->irq_lock
, flags
);
2330 mutex_unlock(&dev
->wl
->mutex
);
2333 static void bcm43xx_periodic_tasks_delete(struct bcm43xx_wldev
*dev
)
2335 cancel_rearming_delayed_work(&dev
->periodic_work
);
2338 static void bcm43xx_periodic_tasks_setup(struct bcm43xx_wldev
*dev
)
2340 struct delayed_work
*work
= &dev
->periodic_work
;
2342 assert(bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
);
2343 dev
->periodic_state
= 0;
2344 INIT_DELAYED_WORK(work
, bcm43xx_periodic_work_handler
);
2345 schedule_delayed_work(work
, 0);
2348 /* Validate access to the chip (SHM) */
2349 static int bcm43xx_validate_chipaccess(struct bcm43xx_wldev
*dev
)
2354 shm_backup
= bcm43xx_shm_read32(dev
, BCM43xx_SHM_SHARED
, 0);
2355 bcm43xx_shm_write32(dev
, BCM43xx_SHM_SHARED
, 0, 0xAA5555AA);
2356 if (bcm43xx_shm_read32(dev
, BCM43xx_SHM_SHARED
, 0) != 0xAA5555AA)
2358 bcm43xx_shm_write32(dev
, BCM43xx_SHM_SHARED
, 0, 0x55AAAA55);
2359 if (bcm43xx_shm_read32(dev
, BCM43xx_SHM_SHARED
, 0) != 0x55AAAA55)
2361 bcm43xx_shm_write32(dev
, BCM43xx_SHM_SHARED
, 0, shm_backup
);
2363 value
= bcm43xx_read32(dev
, BCM43xx_MMIO_MACCTL
);
2364 if ((value
| BCM43xx_MACCTL_GMODE
) !=
2365 (BCM43xx_MACCTL_GMODE
| BCM43xx_MACCTL_IHR_ENABLED
))
2368 value
= bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_REASON
);
2374 printk(KERN_ERR PFX
"Failed to validate the chipaccess\n");
2378 static void bcm43xx_security_init(struct bcm43xx_wldev
*dev
)
2380 dev
->max_nr_keys
= (dev
->dev
->id
.revision
>= 5) ? 58 : 20;
2381 assert(dev
->max_nr_keys
<= ARRAY_SIZE(dev
->key
));
2382 dev
->ktp
= bcm43xx_shm_read16(dev
, BCM43xx_SHM_SHARED
,
2383 BCM43xx_SHM_SH_KTP
);
2384 /* KTP is a word address, but we address SHM bytewise.
2385 * So multiply by two.
2388 if (dev
->dev
->id
.revision
>= 5) {
2389 /* Number of RCMTA address slots */
2390 bcm43xx_write16(dev
, BCM43xx_MMIO_RCMTA_COUNT
,
2391 dev
->max_nr_keys
- 8);
2393 bcm43xx_clear_keys(dev
);
2396 static int bcm43xx_rng_read(struct hwrng
*rng
, u32
*data
)
2398 struct bcm43xx_wl
*wl
= (struct bcm43xx_wl
*)rng
->priv
;
2399 unsigned long flags
;
2401 /* Don't take wl->mutex here, as it could deadlock with
2402 * hwrng internal locking. It's not needed to take
2403 * wl->mutex here, anyway. */
2405 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2406 *data
= bcm43xx_read16(wl
->current_dev
, BCM43xx_MMIO_RNG
);
2407 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2409 return (sizeof(u16
));
2412 static void bcm43xx_rng_exit(struct bcm43xx_wl
*wl
)
2414 if (wl
->rng_initialized
)
2415 hwrng_unregister(&wl
->rng
);
2418 static int bcm43xx_rng_init(struct bcm43xx_wl
*wl
)
2422 snprintf(wl
->rng_name
, ARRAY_SIZE(wl
->rng_name
),
2423 "%s_%s", KBUILD_MODNAME
, wiphy_name(wl
->hw
->wiphy
));
2424 wl
->rng
.name
= wl
->rng_name
;
2425 wl
->rng
.data_read
= bcm43xx_rng_read
;
2426 wl
->rng
.priv
= (unsigned long)wl
;
2427 wl
->rng_initialized
= 1;
2428 err
= hwrng_register(&wl
->rng
);
2430 wl
->rng_initialized
= 0;
2431 printk(KERN_ERR PFX
"Failed to register the random "
2432 "number generator (%d)\n", err
);
2438 static int bcm43xx_tx(struct ieee80211_hw
*hw
,
2439 struct sk_buff
*skb
,
2440 struct ieee80211_tx_control
*ctl
)
2442 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2443 struct bcm43xx_wldev
*dev
= wl
->current_dev
;
2445 unsigned long flags
;
2449 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2450 if (likely(bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
)) {
2451 if (bcm43xx_using_pio(dev
))
2452 err
= bcm43xx_pio_tx(dev
, skb
, ctl
);
2454 err
= bcm43xx_dma_tx(dev
, skb
, ctl
);
2456 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2459 return NETDEV_TX_BUSY
;
2460 return NETDEV_TX_OK
;
2463 static int bcm43xx_conf_tx(struct ieee80211_hw
*hw
,
2465 const struct ieee80211_tx_queue_params
*params
)
2470 static int bcm43xx_get_tx_stats(struct ieee80211_hw
*hw
,
2471 struct ieee80211_tx_queue_stats
*stats
)
2473 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2474 struct bcm43xx_wldev
*dev
= wl
->current_dev
;
2475 unsigned long flags
;
2480 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2481 if (likely(bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
)) {
2482 if (bcm43xx_using_pio(dev
))
2483 bcm43xx_pio_get_tx_stats(dev
, stats
);
2485 bcm43xx_dma_get_tx_stats(dev
, stats
);
2488 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2493 static int bcm43xx_get_stats(struct ieee80211_hw
*hw
,
2494 struct ieee80211_low_level_stats
*stats
)
2496 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2497 unsigned long flags
;
2499 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2500 memcpy(stats
, &wl
->ieee_stats
, sizeof(*stats
));
2501 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2506 static int bcm43xx_dev_reset(struct ieee80211_hw
*hw
)
2508 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2509 struct bcm43xx_wldev
*dev
= wl
->current_dev
;
2510 unsigned long flags
;
2514 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2515 bcm43xx_controller_restart(dev
, "Reset by ieee80211 subsystem");
2516 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2521 static const char * phymode_to_string(unsigned int phymode
)
2524 case BCM43xx_PHYMODE_A
:
2526 case BCM43xx_PHYMODE_B
:
2528 case BCM43xx_PHYMODE_G
:
2536 static int find_wldev_for_phymode(struct bcm43xx_wl
*wl
,
2537 unsigned int phymode
,
2538 struct bcm43xx_wldev
**dev
,
2541 struct bcm43xx_wldev
*d
;
2543 list_for_each_entry(d
, &wl
->devlist
, list
) {
2544 if (d
->phy
.possible_phymodes
& phymode
) {
2545 /* Ok, this device supports the PHY-mode.
2546 * Now figure out how the gmode bit has to be
2547 * set to support it. */
2548 if (phymode
== BCM43xx_PHYMODE_A
)
2561 static void bcm43xx_put_phy_into_reset(struct bcm43xx_wldev
*dev
)
2563 struct ssb_device
*sdev
= dev
->dev
;
2566 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2567 tmslow
&= ~BCM43xx_TMSLOW_GMODE
;
2568 tmslow
|= BCM43xx_TMSLOW_PHYRESET
;
2569 tmslow
|= SSB_TMSLOW_FGC
;
2570 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2573 tmslow
= ssb_read32(sdev
, SSB_TMSLOW
);
2574 tmslow
&= ~SSB_TMSLOW_FGC
;
2575 tmslow
|= BCM43xx_TMSLOW_PHYRESET
;
2576 ssb_write32(sdev
, SSB_TMSLOW
, tmslow
);
2580 static int bcm43xx_switch_phymode(struct bcm43xx_wl
*wl
,
2581 unsigned int new_mode
)
2583 struct bcm43xx_wldev
*up_dev
;
2584 struct bcm43xx_wldev
*down_dev
;
2587 int old_was_started
= 0;
2588 int old_was_inited
= 0;
2590 err
= find_wldev_for_phymode(wl
, new_mode
, &up_dev
, &gmode
);
2592 printk(KERN_INFO PFX
"Could not find a device for %s-PHY mode\n",
2593 phymode_to_string(new_mode
));
2596 assert(gmode
== 0 || gmode
== 1);
2597 if ((up_dev
== wl
->current_dev
) &&
2598 (wl
->current_dev
->phy
.gmode
== gmode
)) {
2599 /* This device is already running. */
2602 dprintk(KERN_INFO PFX
"Reconfiguring PHYmode to %s-PHY\n",
2603 phymode_to_string(new_mode
));
2604 down_dev
= wl
->current_dev
;
2606 /* Shutdown the currently running core. */
2607 if (down_dev
->started
) {
2608 old_was_started
= 1;
2609 bcm43xx_wireless_core_stop(down_dev
);
2611 if (bcm43xx_status(down_dev
) == BCM43xx_STAT_INITIALIZED
) {
2613 bcm43xx_wireless_core_exit(down_dev
);
2616 if (down_dev
!= up_dev
) {
2617 /* We switch to a different core, so we put PHY into
2618 * RESET on the old core. */
2619 bcm43xx_put_phy_into_reset(down_dev
);
2622 /* Now start the new core. */
2623 up_dev
->phy
.gmode
= gmode
;
2624 if (old_was_inited
) {
2625 err
= bcm43xx_wireless_core_init(up_dev
);
2627 printk(KERN_INFO PFX
"Fatal: Could not initialize device for "
2628 "new selected %s-PHY mode\n",
2629 phymode_to_string(new_mode
));
2633 if (old_was_started
) {
2634 assert(old_was_inited
);
2635 err
= bcm43xx_wireless_core_start(up_dev
);
2637 printk(KERN_INFO PFX
"Fatal: Coult not start device for "
2638 "new selected %s-PHY mode\n",
2639 phymode_to_string(new_mode
));
2640 bcm43xx_wireless_core_exit(up_dev
);
2645 wl
->current_dev
= up_dev
;
2650 static int bcm43xx_antenna_from_ieee80211(u8 antenna
)
2653 case 0: /* default/diversity */
2654 return BCM43xx_ANTENNA_DEFAULT
;
2655 case 1: /* Antenna 0 */
2656 return BCM43xx_ANTENNA0
;
2657 case 2: /* Antenna 1 */
2658 return BCM43xx_ANTENNA1
;
2660 return BCM43xx_ANTENNA_DEFAULT
;
2664 static int bcm43xx_dev_config(struct ieee80211_hw
*hw
,
2665 struct ieee80211_conf
*conf
)
2667 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2668 struct bcm43xx_wldev
*dev
;
2669 struct bcm43xx_phy
*phy
;
2670 unsigned long flags
;
2671 unsigned int new_phymode
= 0xFFFF;
2676 antenna_tx
= bcm43xx_antenna_from_ieee80211(conf
->antenna_sel_tx
);
2677 antenna_rx
= bcm43xx_antenna_from_ieee80211(conf
->antenna_sel_rx
);
2679 mutex_lock(&wl
->mutex
);
2681 /* Switch the PHY mode (if necessary). */
2682 switch (conf
->phymode
) {
2683 case MODE_IEEE80211A
:
2684 new_phymode
= BCM43xx_PHYMODE_A
;
2686 case MODE_IEEE80211B
:
2687 new_phymode
= BCM43xx_PHYMODE_B
;
2689 case MODE_IEEE80211G
:
2690 new_phymode
= BCM43xx_PHYMODE_G
;
2695 err
= bcm43xx_switch_phymode(wl
, new_phymode
);
2697 goto out_unlock_mutex
;
2698 dev
= wl
->current_dev
;
2701 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2702 if (bcm43xx_status(dev
) != BCM43xx_STAT_INITIALIZED
)
2705 /* Switch to the requested channel. */
2706 if (conf
->channel_val
!= phy
->channel
)
2707 bcm43xx_radio_selectchannel(dev
, conf
->channel_val
, 0);
2709 /* Enable/Disable ShortSlot timing. */
2710 if (!!(conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
) != dev
->short_slot
) {
2711 assert(phy
->type
== BCM43xx_PHYTYPE_G
);
2712 if (conf
->flags
& IEEE80211_CONF_SHORT_SLOT_TIME
)
2713 bcm43xx_short_slot_timing_enable(dev
);
2715 bcm43xx_short_slot_timing_disable(dev
);
2718 /* Adjust the desired TX power level. */
2719 if (conf
->power_level
!= 0) {
2720 if (conf
->power_level
!= phy
->power_level
) {
2721 phy
->power_level
= conf
->power_level
;
2722 bcm43xx_phy_xmitpower(dev
);
2726 /* Hide/Show the SSID (AP mode only). */
2727 if (conf
->flags
& IEEE80211_CONF_SSID_HIDDEN
) {
2728 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
,
2729 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
)
2730 | BCM43xx_SBF_NO_SSID_BCAST
);
2732 bcm43xx_write32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
,
2733 bcm43xx_read32(dev
, BCM43xx_MMIO_STATUS_BITFIELD
)
2734 & ~BCM43xx_SBF_NO_SSID_BCAST
);
2737 /* Antennas for RX and management frame TX. */
2738 bcm43xx_mgmtframe_txantenna(dev
, antenna_tx
);
2739 bcm43xx_set_rx_antenna(dev
, antenna_rx
);
2741 /* Update templates for AP mode. */
2742 if (bcm43xx_is_mode(wl
, IEEE80211_IF_TYPE_AP
))
2743 bcm43xx_set_beacon_int(dev
, conf
->beacon_int
);
2746 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2748 mutex_unlock(&wl
->mutex
);
2753 static int bcm43xx_dev_set_key(struct ieee80211_hw
*hw
,
2756 struct ieee80211_key_conf
*key
,
2759 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2760 struct bcm43xx_wldev
*dev
= wl
->current_dev
;
2761 unsigned long flags
;
2771 algorithm
= BCM43xx_SEC_ALGO_NONE
;
2774 if (key
->keylen
== 5)
2775 algorithm
= BCM43xx_SEC_ALGO_WEP40
;
2777 algorithm
= BCM43xx_SEC_ALGO_WEP104
;
2780 algorithm
= BCM43xx_SEC_ALGO_TKIP
;
2783 algorithm
= BCM43xx_SEC_ALGO_AES
;
2790 index
= (u8
)(key
->keyidx
);
2794 mutex_lock(&wl
->mutex
);
2795 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2797 if (bcm43xx_status(dev
) != BCM43xx_STAT_INITIALIZED
) {
2804 key
->flags
&= ~IEEE80211_KEY_FORCE_SW_ENCRYPT
;
2806 if (algorithm
== BCM43xx_SEC_ALGO_TKIP
) {
2807 /* FIXME: No TKIP hardware encryption for now. */
2808 key
->flags
|= IEEE80211_KEY_FORCE_SW_ENCRYPT
;
2811 if (is_broadcast_ether_addr(addr
)) {
2812 /* addr is FF:FF:FF:FF:FF:FF for default keys */
2813 err
= bcm43xx_key_write(dev
, index
, algorithm
,
2814 key
->key
, key
->keylen
,
2817 err
= bcm43xx_key_write(dev
, -1, algorithm
,
2818 key
->key
, key
->keylen
,
2822 key
->flags
|= IEEE80211_KEY_FORCE_SW_ENCRYPT
;
2825 dev
->key
[key
->hw_key_idx
].enabled
= 1;
2827 if (algorithm
== BCM43xx_SEC_ALGO_WEP40
||
2828 algorithm
== BCM43xx_SEC_ALGO_WEP104
) {
2829 bcm43xx_hf_write(dev
,
2830 bcm43xx_hf_read(dev
) |
2831 BCM43xx_HF_USEDEFKEYS
);
2833 bcm43xx_hf_write(dev
,
2834 bcm43xx_hf_read(dev
) &
2835 ~BCM43xx_HF_USEDEFKEYS
);
2839 static const u8 zero
[BCM43xx_SEC_KEYSIZE
] = { 0 };
2841 algorithm
= BCM43xx_SEC_ALGO_NONE
;
2842 if (is_broadcast_ether_addr(addr
)) {
2843 err
= bcm43xx_key_write(dev
, index
, algorithm
,
2844 zero
, BCM43xx_SEC_KEYSIZE
,
2847 err
= bcm43xx_key_write(dev
, -1, algorithm
,
2848 zero
, BCM43xx_SEC_KEYSIZE
,
2851 dev
->key
[key
->hw_key_idx
].enabled
= 0;
2854 case REMOVE_ALL_KEYS
:
2855 bcm43xx_clear_keys(dev
);
2862 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2863 mutex_unlock(&wl
->mutex
);
2866 dprintk(KERN_DEBUG PFX
"Using %s based encryption for keyidx: %d, "
2867 "mac: " MAC_FMT
"\n",
2868 (key
->flags
& IEEE80211_KEY_FORCE_SW_ENCRYPT
) ?
2869 "software" : "hardware",
2870 key
->keyidx
, MAC_ARG(addr
));
2875 static void bcm43xx_set_multicast_list(struct ieee80211_hw
*hw
,
2876 unsigned short netflags
,
2879 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2880 struct bcm43xx_wldev
*dev
= wl
->current_dev
;
2881 unsigned long flags
;
2885 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2886 if (wl
->promisc
!= !!(netflags
& IFF_PROMISC
)) {
2887 wl
->promisc
= !!(netflags
& IFF_PROMISC
);
2888 if (bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
)
2889 bcm43xx_adjust_opmode(dev
);
2891 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2894 static int bcm43xx_config_interface(struct ieee80211_hw
*hw
,
2896 struct ieee80211_if_conf
*conf
)
2898 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
2899 struct bcm43xx_wldev
*dev
= wl
->current_dev
;
2900 unsigned long flags
;
2904 mutex_lock(&wl
->mutex
);
2905 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2906 if (conf
->type
!= IEEE80211_IF_TYPE_MNTR
) {
2907 assert(wl
->if_id
== if_id
);
2908 wl
->bssid
= conf
->bssid
;
2909 if (bcm43xx_is_mode(wl
, IEEE80211_IF_TYPE_AP
)) {
2910 assert(conf
->type
== IEEE80211_IF_TYPE_AP
);
2911 bcm43xx_set_ssid(dev
, conf
->ssid
, conf
->ssid_len
);
2913 bcm43xx_refresh_templates(dev
, conf
->beacon
);
2916 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2917 mutex_unlock(&wl
->mutex
);
2922 /* Locking: wl->mutex */
2923 static void bcm43xx_wireless_core_stop(struct bcm43xx_wldev
*dev
)
2925 struct bcm43xx_wl
*wl
= dev
->wl
;
2926 unsigned long flags
;
2931 mutex_unlock(&wl
->mutex
);
2932 bcm43xx_periodic_tasks_delete(dev
);
2933 flush_scheduled_work();
2934 mutex_lock(&wl
->mutex
);
2936 ieee80211_stop_queues(wl
->hw
);
2938 /* Disable and sync interrupts. */
2939 spin_lock_irqsave(&wl
->irq_lock
, flags
);
2940 dev
->irq_savedstate
= bcm43xx_interrupt_disable(dev
, BCM43xx_IRQ_ALL
);
2941 bcm43xx_read32(dev
, BCM43xx_MMIO_GEN_IRQ_MASK
); /* flush */
2942 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
2943 bcm43xx_synchronize_irq(dev
);
2945 bcm43xx_mac_suspend(dev
);
2946 free_irq(dev
->dev
->irq
, dev
);
2948 dprintk(KERN_INFO PFX
"Wireless interface stopped\n");
2951 /* Locking: wl->mutex */
2952 static int bcm43xx_wireless_core_start(struct bcm43xx_wldev
*dev
)
2954 struct bcm43xx_wl
*wl
= dev
->wl
;
2957 assert(!dev
->started
);
2959 drain_txstatus_queue(dev
);
2960 err
= request_irq(dev
->dev
->irq
, bcm43xx_interrupt_handler
,
2961 IRQF_SHARED
, KBUILD_MODNAME
, dev
);
2963 printk(KERN_ERR PFX
"Cannot request IRQ-%d\n",
2968 bcm43xx_interrupt_enable(dev
, dev
->irq_savedstate
);
2969 bcm43xx_mac_enable(dev
);
2971 ieee80211_start_queues(wl
->hw
);
2972 bcm43xx_periodic_tasks_setup(dev
);
2973 dprintk(KERN_INFO PFX
"Wireless interface started\n");
2978 /* Get PHY and RADIO versioning numbers */
2979 static int bcm43xx_phy_versioning(struct bcm43xx_wldev
*dev
)
2981 struct bcm43xx_phy
*phy
= &dev
->phy
;
2989 int unsupported
= 0;
2991 /* Get PHY versioning */
2992 tmp
= bcm43xx_read16(dev
, BCM43xx_MMIO_PHY_VER
);
2993 analog_type
= (tmp
& BCM43xx_PHYVER_ANALOG
) >> BCM43xx_PHYVER_ANALOG_SHIFT
;
2994 phy_type
= (tmp
& BCM43xx_PHYVER_TYPE
) >> BCM43xx_PHYVER_TYPE_SHIFT
;
2995 phy_rev
= (tmp
& BCM43xx_PHYVER_VERSION
);
2997 case BCM43xx_PHYTYPE_A
:
3001 case BCM43xx_PHYTYPE_B
:
3002 if (phy_rev
!= 2 && phy_rev
!= 4 && phy_rev
!= 6 && phy_rev
!= 7)
3005 case BCM43xx_PHYTYPE_G
:
3013 printk(KERN_ERR PFX
"FOUND UNSUPPORTED PHY "
3014 "(Analog %u, Type %u, Revision %u)\n",
3015 analog_type
, phy_type
, phy_rev
);
3018 dprintk(KERN_INFO PFX
"Found PHY: Analog %u, Type %u, Revision %u\n",
3019 analog_type
, phy_type
, phy_rev
);
3022 /* Get RADIO versioning */
3023 if (dev
->dev
->bus
->chip_id
== 0x4317) {
3024 if (dev
->dev
->bus
->chip_rev
== 0)
3026 else if (dev
->dev
->bus
->chip_rev
== 1)
3031 bcm43xx_write16(dev
, BCM43xx_MMIO_RADIO_CONTROL
,
3032 BCM43xx_RADIOCTL_ID
);
3033 tmp
= bcm43xx_read16(dev
, BCM43xx_MMIO_RADIO_DATA_HIGH
);
3035 bcm43xx_write16(dev
, BCM43xx_MMIO_RADIO_CONTROL
,
3036 BCM43xx_RADIOCTL_ID
);
3037 tmp
|= bcm43xx_read16(dev
, BCM43xx_MMIO_RADIO_DATA_LOW
);
3039 radio_manuf
= (tmp
& 0x00000FFF);
3040 radio_ver
= (tmp
& 0x0FFFF000) >> 12;
3041 radio_rev
= (tmp
& 0xF0000000) >> 28;
3043 case BCM43xx_PHYTYPE_A
:
3044 if (radio_ver
!= 0x2060)
3048 if (radio_manuf
!= 0x17F)
3051 case BCM43xx_PHYTYPE_B
:
3052 if ((radio_ver
& 0xFFF0) != 0x2050)
3055 case BCM43xx_PHYTYPE_G
:
3056 if (radio_ver
!= 0x2050)
3063 printk(KERN_ERR PFX
"FOUND UNSUPPORTED RADIO "
3064 "(Manuf 0x%X, Version 0x%X, Revision %u)\n",
3065 radio_manuf
, radio_ver
, radio_rev
);
3068 dprintk(KERN_INFO PFX
"Found Radio: Manuf 0x%X, Version 0x%X, Revision %u\n",
3069 radio_manuf
, radio_ver
, radio_rev
);
3072 phy
->radio_manuf
= radio_manuf
;
3073 phy
->radio_ver
= radio_ver
;
3074 phy
->radio_rev
= radio_rev
;
3076 phy
->analog
= analog_type
;
3077 phy
->type
= phy_type
;
3083 static void setup_struct_phy_for_init(struct bcm43xx_wldev
*dev
,
3084 struct bcm43xx_phy
*phy
)
3086 struct bcm43xx_txpower_lo_control
*lo
;
3089 memset(phy
->minlowsig
, 0xFF, sizeof(phy
->minlowsig
));
3090 memset(phy
->minlowsigpos
, 0, sizeof(phy
->minlowsigpos
));
3095 phy
->aci_enable
= 0;
3096 phy
->aci_wlan_automatic
= 0;
3097 phy
->aci_hw_rssi
= 0;
3099 lo
= phy
->lo_control
;
3101 memset(lo
, 0, sizeof(*(phy
->lo_control
)));
3105 phy
->max_lb_gain
= 0;
3106 phy
->trsw_rx_gain
= 0;
3108 /* Set default attenuation values. */
3109 phy
->bbatt
= bcm43xx_default_baseband_attenuation(dev
);
3110 phy
->rfatt
= bcm43xx_default_radio_attenuation(dev
);
3111 phy
->txctl1
= bcm43xx_default_txctl1(dev
);
3112 phy
->txpwr_offset
= 0;
3115 phy
->nrssislope
= 0;
3116 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi
); i
++)
3117 phy
->nrssi
[i
] = -1000;
3118 for (i
= 0; i
< ARRAY_SIZE(phy
->nrssi_lt
); i
++)
3119 phy
->nrssi_lt
[i
] = i
;
3121 phy
->lofcal
= 0xFFFF;
3122 phy
->initval
= 0xFFFF;
3124 spin_lock_init(&phy
->lock
);
3125 phy
->interfmode
= BCM43xx_INTERFMODE_NONE
;
3126 phy
->channel
= 0xFF;
3129 static void setup_struct_wldev_for_init(struct bcm43xx_wldev
*dev
)
3132 dev
->reg124_set_0x4
= 0;
3135 memset(&dev
->stats
, 0, sizeof(dev
->stats
));
3137 setup_struct_phy_for_init(dev
, &dev
->phy
);
3139 /* IRQ related flags */
3140 dev
->irq_reason
= 0;
3141 memset(dev
->dma_reason
, 0, sizeof(dev
->dma_reason
));
3142 dev
->irq_savedstate
= BCM43xx_IRQ_MASKTEMPLATE
;
3144 dev
->mac_suspended
= 1;
3146 /* Noise calculation context */
3147 memset(&dev
->noisecalc
, 0, sizeof(dev
->noisecalc
));
3150 static void bcm43xx_bluetooth_coext_enable(struct bcm43xx_wldev
*dev
)
3152 struct ssb_sprom
*sprom
= &dev
->dev
->bus
->sprom
;
3155 if (!(sprom
->r1
.boardflags_lo
& BCM43xx_BFL_BTCOEXIST
))
3157 if (dev
->phy
.type
!= BCM43xx_PHYTYPE_B
&& !dev
->phy
.gmode
)
3160 hf
= bcm43xx_hf_read(dev
);
3161 if (sprom
->r1
.boardflags_lo
& BCM43xx_BFL_BTCMOD
)
3162 hf
|= BCM43xx_HF_BTCOEXALT
;
3164 hf
|= BCM43xx_HF_BTCOEX
;
3165 bcm43xx_hf_write(dev
, hf
);
3169 static void bcm43xx_bluetooth_coext_disable(struct bcm43xx_wldev
*dev
)
3173 static void bcm43xx_imcfglo_timeouts_workaround(struct bcm43xx_wldev
*dev
)
3175 #ifdef CONFIG_SSB_DRIVER_PCICORE
3176 struct ssb_bus
*bus
= dev
->dev
->bus
;
3179 if (bus
->pcicore
.dev
&&
3180 bus
->pcicore
.dev
->id
.coreid
== SSB_DEV_PCI
&&
3181 bus
->pcicore
.dev
->id
.revision
<= 5) {
3182 /* IMCFGLO timeouts workaround. */
3183 tmp
= ssb_read32(dev
->dev
, SSB_IMCFGLO
);
3184 tmp
&= ~SSB_IMCFGLO_REQTO
;
3185 tmp
&= ~SSB_IMCFGLO_SERTO
;
3186 switch (bus
->bustype
) {
3187 case SSB_BUSTYPE_PCI
:
3188 case SSB_BUSTYPE_PCMCIA
:
3191 case SSB_BUSTYPE_SSB
:
3195 ssb_write32(dev
->dev
, SSB_IMCFGLO
, tmp
);
3197 #endif /* CONFIG_SSB_DRIVER_PCICORE */
3200 /* Shutdown a wireless core */
3201 static void bcm43xx_wireless_core_exit(struct bcm43xx_wldev
*dev
)
3203 struct bcm43xx_phy
*phy
= &dev
->phy
;
3205 if (bcm43xx_status(dev
) != BCM43xx_STAT_INITIALIZED
)
3208 bcm43xx_rng_exit(dev
->wl
);
3209 bcm43xx_pio_free(dev
);
3210 bcm43xx_dma_free(dev
);
3211 bcm43xx_chip_exit(dev
);
3212 bcm43xx_radio_turn_off(dev
);
3213 bcm43xx_switch_analog(dev
, 0);
3214 if (phy
->dyn_tssi_tbl
)
3215 kfree(phy
->tssi2dbm
);
3216 kfree(phy
->lo_control
);
3217 phy
->lo_control
= NULL
;
3218 ssb_device_disable(dev
->dev
, 0);
3219 ssb_bus_may_powerdown(dev
->dev
->bus
);
3220 bcm43xx_set_status(dev
, BCM43xx_STAT_UNINIT
);
3223 /* Initialize a wireless core */
3224 static int bcm43xx_wireless_core_init(struct bcm43xx_wldev
*dev
)
3226 struct bcm43xx_wl
*wl
= dev
->wl
;
3227 struct ssb_bus
*bus
= dev
->dev
->bus
;
3228 struct ssb_sprom
*sprom
= &bus
->sprom
;
3229 struct bcm43xx_phy
*phy
= &dev
->phy
;
3233 assert(bcm43xx_status(dev
) == BCM43xx_STAT_UNINIT
);
3234 bcm43xx_set_status(dev
, BCM43xx_STAT_INITIALIZING
);
3236 err
= ssb_bus_powerup(bus
, 0);
3239 if (!ssb_device_is_enabled(dev
->dev
)) {
3240 tmp
= phy
->gmode
? BCM43xx_TMSLOW_GMODE
: 0;
3241 bcm43xx_wireless_core_reset(dev
, tmp
);
3244 if ((phy
->type
== BCM43xx_PHYTYPE_B
) || (phy
->type
== BCM43xx_PHYTYPE_G
)) {
3245 phy
->lo_control
= kzalloc(sizeof(*(phy
->lo_control
)), GFP_KERNEL
);
3246 if (!phy
->lo_control
) {
3251 setup_struct_wldev_for_init(dev
);
3253 err
= bcm43xx_phy_init_tssi2dbm_table(dev
);
3255 goto err_kfree_lo_control
;
3257 /* Enable IRQ routing to this device. */
3258 ssb_pcicore_dev_irqvecs_enable(&bus
->pcicore
, dev
->dev
);
3260 bcm43xx_imcfglo_timeouts_workaround(dev
);
3261 bcm43xx_bluetooth_coext_disable(dev
);
3262 bcm43xx_phy_early_init(dev
);
3263 err
= bcm43xx_chip_init(dev
);
3265 goto err_kfree_tssitbl
;
3266 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
3267 BCM43xx_SHM_SH_WLCOREREV
,
3268 dev
->dev
->id
.revision
);
3269 hf
= bcm43xx_hf_read(dev
);
3270 if (phy
->type
== BCM43xx_PHYTYPE_G
) {
3271 hf
|= BCM43xx_HF_SYMW
;
3273 hf
|= BCM43xx_HF_GDCW
;
3274 if (sprom
->r1
.boardflags_lo
& BCM43xx_BFL_PACTRL
)
3275 hf
|= BCM43xx_HF_OFDMPABOOST
;
3276 } else if (phy
->type
== BCM43xx_PHYTYPE_B
) {
3277 hf
|= BCM43xx_HF_SYMW
;
3278 if (phy
->rev
>= 2 && phy
->radio_ver
== 0x2050)
3279 hf
&= ~BCM43xx_HF_GDCW
;
3281 bcm43xx_hf_write(dev
, hf
);
3283 /* Short/Long Retry Limit.
3284 * The retry-limit is a 4-bit counter. Enforce this to avoid overflowing
3285 * the chip-internal counter.
3287 tmp
= limit_value(modparam_short_retry
, 0, 0xF);
3288 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SCRATCH
,
3289 BCM43xx_SHM_SC_SRLIMIT
, tmp
);
3290 tmp
= limit_value(modparam_long_retry
, 0, 0xF);
3291 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SCRATCH
,
3292 BCM43xx_SHM_SC_LRLIMIT
, tmp
);
3294 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
3295 BCM43xx_SHM_SH_SFFBLIM
, 3);
3296 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
,
3297 BCM43xx_SHM_SH_LFFBLIM
, 2);
3299 bcm43xx_rate_memory_init(dev
);
3301 /* Minimum Contention Window */
3302 if (phy
->type
== BCM43xx_PHYTYPE_B
) {
3303 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SCRATCH
,
3304 BCM43xx_SHM_SC_MINCONT
, 0x1F);
3306 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SCRATCH
,
3307 BCM43xx_SHM_SC_MINCONT
, 0xF);
3309 /* Maximum Contention Window */
3310 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SCRATCH
,
3311 BCM43xx_SHM_SC_MAXCONT
, 0x3FF);
3313 bcm43xx_write_mac_bssid_templates(dev
);
3316 if (bcm43xx_using_pio(dev
))
3317 err
= bcm43xx_pio_init(dev
);
3319 err
= bcm43xx_dma_init(dev
);
3320 } while (err
== -EAGAIN
);
3326 bcm43xx_write16(dev
, 0x0612, 0x0050);
3327 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0416, 0x0050);
3328 bcm43xx_shm_write16(dev
, BCM43xx_SHM_SHARED
, 0x0414, 0x01F4);
3331 bcm43xx_bluetooth_coext_enable(dev
);
3333 ssb_bus_powerup(bus
, 1); /* Enable dynamic PCTL */
3334 bcm43xx_macfilter_clear(dev
, BCM43xx_MACFILTER_ASSOC
);
3335 bcm43xx_macfilter_set(dev
, BCM43xx_MACFILTER_SELF
,
3336 (u8
*)(wl
->hw
->wiphy
->perm_addr
));
3337 bcm43xx_security_init(dev
);
3338 bcm43xx_measure_channel_change_time(dev
);
3339 bcm43xx_rng_init(wl
);
3341 bcm43xx_set_status(dev
, BCM43xx_STAT_INITIALIZED
);
3347 bcm43xx_chip_exit(dev
);
3349 if (phy
->dyn_tssi_tbl
)
3350 kfree(phy
->tssi2dbm
);
3351 err_kfree_lo_control
:
3352 kfree(phy
->lo_control
);
3353 phy
->lo_control
= NULL
;
3355 ssb_bus_may_powerdown(bus
);
3356 bcm43xx_set_status(dev
, BCM43xx_STAT_UNINIT
);
3360 static int bcm43xx_add_interface(struct ieee80211_hw
*hw
,
3361 struct ieee80211_if_init_conf
*conf
)
3363 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
3364 struct bcm43xx_wldev
*dev
;
3365 unsigned long flags
;
3366 int err
= -EOPNOTSUPP
;
3369 mutex_lock(&wl
->mutex
);
3370 if ((conf
->type
!= IEEE80211_IF_TYPE_MNTR
) &&
3372 goto out_mutex_unlock
;
3374 dprintk(KERN_INFO PFX
"Adding Interface type %d\n", conf
->type
);
3376 dev
= wl
->current_dev
;
3377 if (bcm43xx_status(dev
) == BCM43xx_STAT_UNINIT
) {
3378 err
= bcm43xx_wireless_core_init(dev
);
3380 goto out_mutex_unlock
;
3383 if (!dev
->started
) {
3384 err
= bcm43xx_wireless_core_start(dev
);
3387 bcm43xx_wireless_core_exit(dev
);
3388 goto out_mutex_unlock
;
3392 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3393 switch (conf
->type
) {
3394 case IEEE80211_IF_TYPE_MNTR
:
3399 wl
->if_id
= conf
->if_id
;
3400 wl
->mac_addr
= conf
->mac_addr
;
3401 wl
->if_type
= conf
->type
;
3403 bcm43xx_adjust_opmode(dev
);
3404 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3408 mutex_unlock(&wl
->mutex
);
3413 static void bcm43xx_remove_interface(struct ieee80211_hw
*hw
,
3414 struct ieee80211_if_init_conf
*conf
)
3416 struct bcm43xx_wl
*wl
= hw_to_bcm43xx_wl(hw
);
3417 struct bcm43xx_wldev
*dev
;
3418 unsigned long flags
;
3420 dprintk(KERN_INFO PFX
"Removing Interface type %d\n", conf
->type
);
3422 mutex_lock(&wl
->mutex
);
3423 if (conf
->type
== IEEE80211_IF_TYPE_MNTR
) {
3425 assert(wl
->monitor
>= 0);
3427 assert(wl
->operating
);
3431 dev
= wl
->current_dev
;
3432 if (!wl
->operating
&& wl
->monitor
== 0) {
3434 bcm43xx_wireless_core_stop(dev
);
3435 bcm43xx_wireless_core_exit(dev
);
3437 spin_lock_irqsave(&wl
->irq_lock
, flags
);
3438 bcm43xx_adjust_opmode(dev
);
3439 spin_unlock_irqrestore(&wl
->irq_lock
, flags
);
3441 mutex_unlock(&wl
->mutex
);
3445 static const struct ieee80211_ops bcm43xx_hw_ops
= {
3447 .conf_tx
= bcm43xx_conf_tx
,
3448 .add_interface
= bcm43xx_add_interface
,
3449 .remove_interface
= bcm43xx_remove_interface
,
3450 .reset
= bcm43xx_dev_reset
,
3451 .config
= bcm43xx_dev_config
,
3452 .config_interface
= bcm43xx_config_interface
,
3453 .set_multicast_list
= bcm43xx_set_multicast_list
,
3454 .set_key
= bcm43xx_dev_set_key
,
3455 .get_stats
= bcm43xx_get_stats
,
3456 .get_tx_stats
= bcm43xx_get_tx_stats
,
3459 /* Hard-reset the chip. Do not call this directly.
3460 * Use bcm43xx_controller_restart()
3462 static void bcm43xx_chip_reset(struct work_struct
*work
)
3464 struct bcm43xx_wldev
*dev
=
3465 container_of(work
, struct bcm43xx_wldev
, restart_work
);
3466 struct bcm43xx_wl
*wl
= dev
->wl
;
3468 int was_started
= 0;
3471 mutex_lock(&wl
->mutex
);
3473 /* Bring the device down... */
3476 bcm43xx_wireless_core_stop(dev
);
3478 if (bcm43xx_status(dev
) == BCM43xx_STAT_INITIALIZED
) {
3480 bcm43xx_wireless_core_exit(dev
);
3483 /* ...and up again. */
3485 err
= bcm43xx_wireless_core_init(dev
);
3491 err
= bcm43xx_wireless_core_start(dev
);
3493 bcm43xx_wireless_core_exit(dev
);
3498 mutex_unlock(&wl
->mutex
);
3500 printk(KERN_ERR PFX
"Controller restart FAILED\n");
3502 printk(KERN_INFO PFX
"Controller restarted\n");
3505 static int bcm43xx_setup_modes(struct bcm43xx_wldev
*dev
,
3510 struct ieee80211_hw
*hw
= dev
->wl
->hw
;
3511 struct ieee80211_hw_mode
*mode
;
3512 struct bcm43xx_phy
*phy
= &dev
->phy
;
3516 /*FIXME: Don't tell ieee80211 about an A-PHY, because we currently don't support A-PHY. */
3519 phy
->possible_phymodes
= 0;
3522 assert(cnt
< BCM43xx_MAX_PHYHWMODES
);
3523 mode
= &phy
->hwmodes
[cnt
];
3525 mode
->mode
= MODE_IEEE80211A
;
3526 mode
->num_channels
= bcm43xx_a_chantable_size
;
3527 mode
->channels
= bcm43xx_a_chantable
;
3528 mode
->num_rates
= bcm43xx_a_ratetable_size
;
3529 mode
->rates
= bcm43xx_a_ratetable
;
3530 err
= ieee80211_register_hwmode(hw
, mode
);
3534 phy
->possible_phymodes
|= BCM43xx_PHYMODE_A
;
3539 assert(cnt
< BCM43xx_MAX_PHYHWMODES
);
3540 mode
= &phy
->hwmodes
[cnt
];
3542 mode
->mode
= MODE_IEEE80211B
;
3543 mode
->num_channels
= bcm43xx_bg_chantable_size
;
3544 mode
->channels
= bcm43xx_bg_chantable
;
3545 mode
->num_rates
= bcm43xx_b_ratetable_size
;
3546 mode
->rates
= bcm43xx_b_ratetable
;
3547 err
= ieee80211_register_hwmode(hw
, mode
);
3551 phy
->possible_phymodes
|= BCM43xx_PHYMODE_B
;
3556 assert(cnt
< BCM43xx_MAX_PHYHWMODES
);
3557 mode
= &phy
->hwmodes
[cnt
];
3559 mode
->mode
= MODE_IEEE80211G
;
3560 mode
->num_channels
= bcm43xx_bg_chantable_size
;
3561 mode
->channels
= bcm43xx_bg_chantable
;
3562 mode
->num_rates
= bcm43xx_g_ratetable_size
;
3563 mode
->rates
= bcm43xx_g_ratetable
;
3564 err
= ieee80211_register_hwmode(hw
, mode
);
3568 phy
->possible_phymodes
|= BCM43xx_PHYMODE_G
;
3578 static void bcm43xx_wireless_core_detach(struct bcm43xx_wldev
*dev
)
3580 /* We release firmware that late to not be required to re-request
3581 * is all the time when we reinit the core. */
3582 bcm43xx_release_firmware(dev
);
3585 static int bcm43xx_wireless_core_attach(struct bcm43xx_wldev
*dev
)
3587 struct bcm43xx_wl
*wl
= dev
->wl
;
3588 struct ssb_bus
*bus
= dev
->dev
->bus
;
3589 struct pci_dev
*pdev
= bus
->host_pci
;
3591 int have_aphy
= 0, have_bphy
= 0, have_gphy
= 0;
3594 /* Do NOT do any device initialization here.
3595 * Do it in wireless_core_init() instead.
3596 * This function is for gathering basic information about the HW, only.
3597 * Also some structs may be set up here. But most likely you want to have
3598 * that in core_init(), too.
3601 /* Get the PHY type. */
3602 if (dev
->dev
->id
.revision
>= 5) {
3605 tmshigh
= ssb_read32(dev
->dev
, SSB_TMSHIGH
);
3606 have_aphy
= !!(tmshigh
& BCM43xx_TMSHIGH_APHY
);
3607 have_gphy
= !!(tmshigh
& BCM43xx_TMSHIGH_GPHY
);
3608 if (!have_aphy
&& !have_gphy
)
3610 } else if (dev
->dev
->id
.revision
== 4) {
3616 /* Initialize LEDs structs. */
3617 err
= bcm43xx_leds_init(dev
);
3621 dev
->phy
.gmode
= (have_gphy
|| have_bphy
);
3622 tmp
= dev
->phy
.gmode
? BCM43xx_TMSLOW_GMODE
: 0;
3623 bcm43xx_wireless_core_reset(dev
, tmp
);
3625 err
= bcm43xx_phy_versioning(dev
);
3628 /* Check if this device supports multiband. */
3630 (pdev
->device
!= 0x4312 &&
3631 pdev
->device
!= 0x4319 &&
3632 pdev
->device
!= 0x4324)) {
3633 /* No multiband support. */
3637 switch (dev
->phy
.type
) {
3638 case BCM43xx_PHYTYPE_A
:
3641 case BCM43xx_PHYTYPE_B
:
3644 case BCM43xx_PHYTYPE_G
:
3651 dev
->phy
.gmode
= (have_gphy
|| have_bphy
);
3652 tmp
= dev
->phy
.gmode
? BCM43xx_TMSLOW_GMODE
: 0;
3653 bcm43xx_wireless_core_reset(dev
, tmp
);
3655 err
= bcm43xx_validate_chipaccess(dev
);
3658 err
= bcm43xx_setup_modes(dev
, have_aphy
,
3659 have_bphy
, have_gphy
);
3663 /* Now set some default "current_dev" */
3664 if (!wl
->current_dev
)
3665 wl
->current_dev
= dev
;
3666 INIT_WORK(&dev
->restart_work
, bcm43xx_chip_reset
);
3668 bcm43xx_radio_turn_off(dev
);
3669 bcm43xx_switch_analog(dev
, 0);
3670 ssb_device_disable(dev
->dev
, 0);
3671 ssb_bus_may_powerdown(bus
);
3677 bcm43xx_leds_exit(dev
);
3681 static void bcm43xx_one_core_detach(struct ssb_device
*dev
)
3683 struct bcm43xx_wldev
*wldev
;
3684 struct bcm43xx_wl
*wl
;
3686 wldev
= ssb_get_drvdata(dev
);
3688 bcm43xx_debugfs_remove_device(wldev
);
3689 bcm43xx_wireless_core_detach(wldev
);
3690 list_del(&wldev
->list
);
3692 ssb_set_drvdata(dev
, NULL
);
3696 static int bcm43xx_one_core_attach(struct ssb_device
*dev
,
3697 struct bcm43xx_wl
*wl
)
3699 struct bcm43xx_wldev
*wldev
;
3700 struct pci_dev
*pdev
;
3703 if (!list_empty(&wl
->devlist
)) {
3704 /* We are not the first core on this chip. */
3705 pdev
= dev
->bus
->host_pci
;
3706 /* Only special chips support more than one wireless
3707 * core, although some of the other chips have more than
3708 * one wireless core as well. Check for this and
3712 ((pdev
->device
!= 0x4321) &&
3713 (pdev
->device
!= 0x4313) &&
3714 (pdev
->device
!= 0x431A))) {
3715 dprintk(KERN_INFO PFX
"Ignoring unconnected 802.11 core\n");
3720 wldev
= kzalloc(sizeof(*wldev
), GFP_KERNEL
);
3726 bcm43xx_set_status(wldev
, BCM43xx_STAT_UNINIT
);
3727 wldev
->bad_frames_preempt
= modparam_bad_frames_preempt
;
3728 tasklet_init(&wldev
->isr_tasklet
,
3729 (void (*)(unsigned long))bcm43xx_interrupt_tasklet
,
3730 (unsigned long)wldev
);
3732 wldev
->__using_pio
= 1;
3733 INIT_LIST_HEAD(&wldev
->list
);
3735 err
= bcm43xx_wireless_core_attach(wldev
);
3737 goto err_kfree_wldev
;
3739 list_add(&wldev
->list
, &wl
->devlist
);
3741 ssb_set_drvdata(dev
, wldev
);
3742 bcm43xx_debugfs_add_device(wldev
);
3752 static void bcm43xx_sprom_fixup(struct ssb_bus
*bus
)
3754 /* boardflags workarounds */
3755 if (bus
->board_vendor
== SSB_BOARDVENDOR_DELL
&&
3756 bus
->chip_id
== 0x4301 &&
3757 bus
->board_rev
== 0x74)
3758 bus
->sprom
.r1
.boardflags_lo
|= BCM43xx_BFL_BTCOEXIST
;
3759 if (bus
->board_vendor
== PCI_VENDOR_ID_APPLE
&&
3760 bus
->board_type
== 0x4E &&
3761 bus
->board_rev
> 0x40)
3762 bus
->sprom
.r1
.boardflags_lo
|= BCM43xx_BFL_PACTRL
;
3764 /* Convert Antennagain values to Q5.2 */
3765 bus
->sprom
.r1
.antenna_gain_a
<<= 2;
3766 bus
->sprom
.r1
.antenna_gain_bg
<<= 2;
3769 static void bcm43xx_wireless_exit(struct ssb_device
*dev
,
3770 struct bcm43xx_wl
*wl
)
3772 struct ieee80211_hw
*hw
= wl
->hw
;
3774 ssb_set_devtypedata(dev
, NULL
);
3775 ieee80211_free_hw(hw
);
3778 static int bcm43xx_wireless_init(struct ssb_device
*dev
)
3780 struct ssb_sprom
*sprom
= &dev
->bus
->sprom
;
3781 struct ieee80211_hw
*hw
;
3782 struct bcm43xx_wl
*wl
;
3785 bcm43xx_sprom_fixup(dev
->bus
);
3787 hw
= ieee80211_alloc_hw(sizeof(*wl
), &bcm43xx_hw_ops
);
3789 printk(KERN_ERR PFX
"Could not allocate ieee80211 device\n");
3794 hw
->flags
= IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE
|
3795 IEEE80211_HW_MONITOR_DURING_OPER
|
3796 IEEE80211_HW_DEVICE_HIDES_WEP
|
3797 IEEE80211_HW_WEP_INCLUDE_IV
;
3798 hw
->max_signal
= 100;
3799 hw
->max_rssi
= -110;
3800 hw
->max_noise
= -110;
3802 SET_IEEE80211_DEV(hw
, dev
->dev
);
3803 if (is_valid_ether_addr(sprom
->r1
.et1mac
))
3804 SET_IEEE80211_PERM_ADDR(hw
, sprom
->r1
.et1mac
);
3806 SET_IEEE80211_PERM_ADDR(hw
, sprom
->r1
.il0mac
);
3808 /* Get and initialize struct bcm43xx_wl */
3809 wl
= hw_to_bcm43xx_wl(hw
);
3810 memset(wl
, 0, sizeof(*wl
));
3812 spin_lock_init(&wl
->irq_lock
);
3813 spin_lock_init(&wl
->leds_lock
);
3814 mutex_init(&wl
->mutex
);
3815 INIT_LIST_HEAD(&wl
->devlist
);
3817 ssb_set_devtypedata(dev
, wl
);
3818 printk(KERN_INFO PFX
"Broadcom %04X WLAN found\n", dev
->bus
->chip_id
);
3824 static int bcm43xx_probe(struct ssb_device
*dev
,
3825 const struct ssb_device_id
*id
)
3827 struct bcm43xx_wl
*wl
;
3831 wl
= ssb_get_devtypedata(dev
);
3833 /* Probing the first core. Must setup common struct bcm43xx_wl */
3835 err
= bcm43xx_wireless_init(dev
);
3838 wl
= ssb_get_devtypedata(dev
);
3841 err
= bcm43xx_one_core_attach(dev
, wl
);
3843 goto err_wireless_exit
;
3846 err
= ieee80211_register_hw(wl
->hw
);
3848 goto err_one_core_detach
;
3854 err_one_core_detach
:
3855 bcm43xx_one_core_detach(dev
);
3858 bcm43xx_wireless_exit(dev
, wl
);
3862 static void bcm43xx_remove(struct ssb_device
*dev
)
3864 struct bcm43xx_wl
*wl
= ssb_get_devtypedata(dev
);
3865 struct bcm43xx_wldev
*wldev
= ssb_get_drvdata(dev
);
3868 if (wl
->current_dev
== wldev
)
3869 ieee80211_unregister_hw(wl
->hw
);
3871 bcm43xx_one_core_detach(dev
);
3873 if (list_empty(&wl
->devlist
)) {
3874 /* Last core on the chip unregistered.
3875 * We can destroy common struct bcm43xx_wl.
3877 bcm43xx_wireless_exit(dev
, wl
);
3881 /* Hard-reset the chip.
3882 * This can be called from interrupt or process context.
3883 * dev->irq_lock must be locked.
3885 void bcm43xx_controller_restart(struct bcm43xx_wldev
*dev
, const char *reason
)
3887 if (bcm43xx_status(dev
) != BCM43xx_STAT_INITIALIZED
)
3889 printk(KERN_ERR PFX
"Controller RESET (%s) ...\n", reason
);
3890 schedule_work(&dev
->restart_work
);
3895 static int bcm43xx_suspend(struct ssb_device
*dev
, pm_message_t state
)
3897 struct bcm43xx_wldev
*wldev
= ssb_get_drvdata(dev
);
3898 struct bcm43xx_wl
*wl
= wldev
->wl
;
3900 dprintk(KERN_INFO PFX
"Suspending...\n");
3902 mutex_lock(&wl
->mutex
);
3903 wldev
->was_started
= !!wldev
->started
;
3904 wldev
->was_initialized
= (bcm43xx_status(wldev
) == BCM43xx_STAT_INITIALIZED
);
3906 bcm43xx_wireless_core_stop(wldev
);
3907 if (bcm43xx_status(wldev
) == BCM43xx_STAT_INITIALIZED
)
3908 bcm43xx_wireless_core_exit(wldev
);
3910 mutex_unlock(&wl
->mutex
);
3912 dprintk(KERN_INFO PFX
"Device suspended.\n");
3917 static int bcm43xx_resume(struct ssb_device
*dev
)
3919 struct bcm43xx_wldev
*wldev
= ssb_get_drvdata(dev
);
3922 dprintk(KERN_INFO PFX
"Resuming...\n");
3924 if (wldev
->was_initialized
) {
3925 err
= bcm43xx_wireless_core_init(wldev
);
3927 printk(KERN_ERR PFX
"Resume failed at core init\n");
3931 if (wldev
->was_started
) {
3932 assert(wldev
->was_initialized
);
3933 err
= bcm43xx_wireless_core_start(wldev
);
3935 printk(KERN_ERR PFX
"Resume failed at core start\n");
3940 dprintk(KERN_INFO PFX
"Device resumed.\n");
3945 #else /* CONFIG_PM */
3946 # define bcm43xx_suspend NULL
3947 # define bcm43xx_resume NULL
3948 #endif /* CONFIG_PM */
3950 static struct ssb_driver bcm43xx_ssb_driver
= {
3951 .name
= KBUILD_MODNAME
,
3952 .id_table
= bcm43xx_ssb_tbl
,
3953 .probe
= bcm43xx_probe
,
3954 .remove
= bcm43xx_remove
,
3955 .suspend
= bcm43xx_suspend
,
3956 .resume
= bcm43xx_resume
,
3959 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3960 /* The PCI frontend stub */
3961 static const struct pci_device_id bcm43xx_pci_tbl
[] = {
3962 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4307) },
3963 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4311) },
3964 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4312) },
3965 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4318) },
3966 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4319) },
3967 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4320) },
3968 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4321) },
3969 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4324) },
3970 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM
, 0x4325) },
3973 MODULE_DEVICE_TABLE(pci
, bcm43xx_pci_tbl
);
3975 static struct pci_driver bcm43xx_pci_driver
= {
3976 .name
= "bcm43xx-pci",
3977 .id_table
= bcm43xx_pci_tbl
,
3979 #endif /* CONFIG_BCM43XX_MAC80211_PCI */
3981 static int __init
bcm43xx_init(void)
3985 bcm43xx_debugfs_init();
3986 #ifdef CONFIG_BCM43XX_MAC80211_PCI
3987 err
= ssb_pcihost_register(&bcm43xx_pci_driver
);
3991 err
= bcm43xx_pcmcia_init();
3994 err
= ssb_driver_register(&bcm43xx_ssb_driver
);
3996 goto err_pcmcia_exit
;
4001 bcm43xx_pcmcia_exit();
4003 #ifdef CONFIG_BCM43XX_MAC80211_PCI
4004 ssb_pcihost_unregister(&bcm43xx_pci_driver
);
4007 bcm43xx_debugfs_exit();
4011 static void __exit
bcm43xx_exit(void)
4013 ssb_driver_unregister(&bcm43xx_ssb_driver
);
4014 bcm43xx_pcmcia_exit();
4015 #ifdef CONFIG_BCM43XX_MAC80211_PCI
4016 ssb_pcihost_unregister(&bcm43xx_pci_driver
);
4018 bcm43xx_debugfs_exit();
4021 module_init(bcm43xx_init
)
4022 module_exit(bcm43xx_exit
)