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uboot-lantiq: vrx200 - add support for dual nor flash
[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0014-MIPS-add-support-for-Lantiq-XWAY-SoCs.patch
1 From 11553b0de8992ded6240d034bd49f561d17bea53 Mon Sep 17 00:00:00 2001
2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
3 Date: Thu, 13 Jun 2013 01:18:02 +0200
4 Subject: MIPS: add support for Lantiq XWAY SoCs
5
6 Signed-off-by: Luka Perkov <luka@openwrt.org>
7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
8
9 --- a/.gitignore
10 +++ b/.gitignore
11 @@ -49,6 +49,13 @@
12 /u-boot.sb
13 /u-boot.bd
14 /u-boot.geany
15 +/u-boot.bin.lzma
16 +/u-boot.bin.lzo
17 +/u-boot.ltq.lzma.norspl
18 +/u-boot.ltq.lzo.norspl
19 +/u-boot.ltq.norspl
20 +/u-boot.lzma.img
21 +/u-boot.lzo.img
22
23 #
24 # Generated files
25 --- a/Makefile
26 +++ b/Makefile
27 @@ -435,6 +435,12 @@ $(obj)u-boot.bin: $(obj)u-boot
28 $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
29 $(BOARD_SIZE_CHECK)
30
31 +$(obj)u-boot.bin.lzma: $(obj)u-boot.bin
32 + cat $< | lzma -9 -f - > $@
33 +
34 +$(obj)u-boot.bin.lzo: $(obj)u-boot.bin
35 + cat $< | lzop -9 -f - > $@
36 +
37 $(obj)u-boot.ldr: $(obj)u-boot
38 $(CREATE_LDR_ENV)
39 $(LDR) -T $(CONFIG_BFIN_CPU) -c $@ $< $(LDR_FLAGS)
40 @@ -454,13 +460,23 @@ ifndef CONFIG_SYS_UBOOT_START
41 CONFIG_SYS_UBOOT_START := 0
42 endif
43
44 -$(obj)u-boot.img: $(obj)u-boot.bin
45 - $(obj)tools/mkimage -A $(ARCH) -T firmware -C none \
46 +define GEN_UBOOT_IMAGE
47 + $(obj)tools/mkimage -A $(ARCH) -T firmware -C $(1) \
48 -O u-boot -a $(CONFIG_SYS_TEXT_BASE) \
49 -e $(CONFIG_SYS_UBOOT_START) \
50 -n $(shell sed -n -e 's/.*U_BOOT_VERSION//p' $(VERSION_FILE) | \
51 sed -e 's/"[ ]*$$/ for $(BOARD) board"/') \
52 -d $< $@
53 +endef
54 +
55 +$(obj)u-boot.img: $(obj)u-boot.bin
56 + $(call GEN_UBOOT_IMAGE,none)
57 +
58 +$(obj)u-boot.lzma.img: $(obj)u-boot.bin.lzma
59 + $(call GEN_UBOOT_IMAGE,lzma)
60 +
61 +$(obj)u-boot.lzo.img: $(obj)u-boot.bin.lzo
62 + $(call GEN_UBOOT_IMAGE,lzo)
63
64 $(obj)u-boot.imx: $(obj)u-boot.bin depend
65 $(MAKE) -C $(SRCTREE)/arch/arm/imx-common $(OBJTREE)/u-boot.imx
66 @@ -571,6 +587,27 @@ $(obj)u-boot-img-spl-at-end.bin: $(obj)s
67 conv=notrunc 2>/dev/null
68 cat $(obj)u-boot-pad.img $(obj)spl/u-boot-spl.bin > $@
69
70 +$(obj)u-boot.ltq.sfspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
71 + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
72 + -s $(obj)spl/u-boot-spl.bin -u $< -o $@
73 +
74 +$(obj)u-boot.ltq.lzo.sfspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin
75 + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
76 + -s $(obj)spl/u-boot-spl.bin -u $< -o $@
77 +
78 +$(obj)u-boot.ltq.lzma.sfspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
79 + $(obj)tools/ltq-boot-image -t sfspl -e $(CONFIG_SPL_TEXT_BASE) \
80 + -s $(obj)spl/u-boot-spl.bin -u $< -o $@
81 +
82 +$(obj)u-boot.ltq.norspl: $(obj)u-boot.img $(obj)spl/u-boot-spl.bin
83 + cat $(obj)spl/u-boot-spl.bin $< > $@
84 +
85 +$(obj)u-boot.ltq.lzo.norspl: $(obj)u-boot.lzo.img $(obj)spl/u-boot-spl.bin
86 + cat $(obj)spl/u-boot-spl.bin $< > $@
87 +
88 +$(obj)u-boot.ltq.lzma.norspl: $(obj)u-boot.lzma.img $(obj)spl/u-boot-spl.bin
89 + cat $(obj)spl/u-boot-spl.bin $< > $@
90 +
91 ifeq ($(CONFIG_SANDBOX),y)
92 GEN_UBOOT = \
93 cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
94 --- a/README
95 +++ b/README
96 @@ -468,6 +468,11 @@ The following options need to be configu
97 CONF_CM_CACHABLE_CUW
98 CONF_CM_CACHABLE_ACCELERATED
99
100 + CONFIG_SYS_MIPS_CACHE_EXT_INIT
101 +
102 + Enable this to use extended cache initialization for recent
103 + MIPS CPU cores.
104 +
105 CONFIG_SYS_XWAY_EBU_BOOTCFG
106
107 Special option for Lantiq XWAY SoCs for booting from NOR flash.
108 --- a/arch/mips/config.mk
109 +++ b/arch/mips/config.mk
110 @@ -45,9 +45,13 @@ PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__M
111 # On the other hand, we want PIC in the U-Boot code to relocate it from ROM
112 # to RAM. $28 is always used as gp.
113 #
114 -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS)
115 +PF_ABICALLS ?= -mabicalls
116 +PF_PIC ?= -fpic
117 +PF_PIE ?= -pie
118 +
119 +PLATFORM_CPPFLAGS += -G 0 $(PF_ABICALLS) $(PF_PIC) $(ENDIANNESS)
120 PLATFORM_CPPFLAGS += -msoft-float
121 PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS)
122 PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
123 -LDFLAGS_FINAL += --gc-sections -pie
124 +LDFLAGS_FINAL += --gc-sections $(PF_PIE)
125 OBJCFLAGS += --remove-section=.dynsym
126 --- a/arch/mips/cpu/mips32/cache.S
127 +++ b/arch/mips/cpu/mips32/cache.S
128 @@ -29,7 +29,11 @@
129 */
130 #define MIPS_MAX_CACHE_SIZE 0x10000
131
132 +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
133 +#define INDEX_BASE 0x9fc00000
134 +#else
135 #define INDEX_BASE CKSEG0
136 +#endif
137
138 .macro cache_op op addr
139 .set push
140 @@ -65,7 +69,11 @@
141 */
142 LEAF(mips_init_icache)
143 blez a1, 9f
144 +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
145 + mtc0 zero, CP0_ITAGLO
146 +#else
147 mtc0 zero, CP0_TAGLO
148 +#endif
149 /* clear tag to invalidate */
150 PTR_LI t0, INDEX_BASE
151 PTR_ADDU t1, t0, a1
152 @@ -90,7 +98,11 @@ LEAF(mips_init_icache)
153 */
154 LEAF(mips_init_dcache)
155 blez a1, 9f
156 +#ifdef CONFIG_SYS_MIPS_CACHE_EXT_INIT
157 + mtc0 zero, CP0_DTAGLO
158 +#else
159 mtc0 zero, CP0_TAGLO
160 +#endif
161 /* clear all tags */
162 PTR_LI t0, INDEX_BASE
163 PTR_ADDU t1, t0, a1
164 --- /dev/null
165 +++ b/arch/mips/cpu/mips32/danube/Makefile
166 @@ -0,0 +1,31 @@
167 +#
168 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
169 +#
170 +# SPDX-License-Identifier: GPL-2.0+
171 +#
172 +
173 +include $(TOPDIR)/config.mk
174 +
175 +LIB = $(obj)lib$(SOC).o
176 +
177 +COBJS-y += cgu.o chipid.o ebu.o mem.o pmu.o rcu.o
178 +SOBJS-y += cgu_init.o mem_init.o
179 +
180 +COBJS := $(COBJS-y)
181 +SOBJS := $(SOBJS-y)
182 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
183 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
184 +
185 +all: $(LIB)
186 +
187 +$(LIB): $(obj).depend $(OBJS)
188 + $(call cmd_link_o_target, $(OBJS))
189 +
190 +#########################################################################
191 +
192 +# defines $(obj).depend target
193 +include $(SRCTREE)/rules.mk
194 +
195 +sinclude $(obj).depend
196 +
197 +#########################################################################
198 --- /dev/null
199 +++ b/arch/mips/cpu/mips32/danube/cgu.c
200 @@ -0,0 +1,117 @@
201 +/*
202 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
203 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
204 + *
205 + * SPDX-License-Identifier: GPL-2.0+
206 + */
207 +
208 +#include <common.h>
209 +#include <asm/arch/soc.h>
210 +#include <asm/lantiq/clk.h>
211 +#include <asm/lantiq/io.h>
212 +
213 +#define LTQ_CGU_SYS_DDR_MASK 0x0003
214 +#define LTQ_CGU_SYS_DDR_SHIFT 0
215 +#define LTQ_CGU_SYS_CPU0_MASK 0x000C
216 +#define LTQ_CGU_SYS_CPU0_SHIFT 2
217 +#define LTQ_CGU_SYS_FPI_MASK 0x0040
218 +#define LTQ_CGU_SYS_FPI_SHIFT 6
219 +
220 +struct ltq_cgu_regs {
221 + u32 rsvd0;
222 + u32 pll0_cfg; /* PLL0 config */
223 + u32 pll1_cfg; /* PLL1 config */
224 + u32 pll2_cfg; /* PLL2 config */
225 + u32 sys; /* System clock */
226 + u32 update; /* CGU update control */
227 + u32 if_clk; /* Interface clock */
228 + u32 osc_con; /* Update OSC Control */
229 + u32 smd; /* SDRAM Memory Control */
230 + u32 rsvd1[3];
231 + u32 pcm_cr; /* PCM control */
232 + u32 pci_cr; /* PCI clock control */
233 +};
234 +
235 +static struct ltq_cgu_regs *ltq_cgu_regs =
236 + (struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);
237 +
238 +static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)
239 +{
240 + return (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;
241 +}
242 +
243 +unsigned long ltq_get_io_region_clock(void)
244 +{
245 + u32 ddr_sel;
246 + unsigned long clk;
247 +
248 + ddr_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_DDR_MASK,
249 + LTQ_CGU_SYS_DDR_SHIFT);
250 +
251 + switch (ddr_sel) {
252 + case 0:
253 + clk = CLOCK_166_MHZ;
254 + break;
255 + case 1:
256 + clk = CLOCK_133_MHZ;
257 + break;
258 + case 2:
259 + clk = CLOCK_111_MHZ;
260 + break;
261 + case 3:
262 + clk = CLOCK_83_MHZ;
263 + break;
264 + default:
265 + clk = 0;
266 + break;
267 + }
268 +
269 + return clk;
270 +}
271 +
272 +unsigned long ltq_get_cpu_clock(void)
273 +{
274 + u32 cpu0_sel;
275 + unsigned long clk;
276 +
277 + cpu0_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_CPU0_MASK,
278 + LTQ_CGU_SYS_CPU0_SHIFT);
279 +
280 + switch (cpu0_sel) {
281 + /* Same as PLL0 output (333,33 MHz) */
282 + case 0:
283 + clk = CLOCK_333_MHZ;
284 + break;
285 + /* 1/1 fixed ratio to DDR clock */
286 + case 1:
287 + clk = ltq_get_io_region_clock();
288 + break;
289 + /* 1/2 fixed ratio to DDR clock */
290 + case 2:
291 + clk = ltq_get_io_region_clock() << 1;
292 + break;
293 + default:
294 + clk = 0;
295 + break;
296 + }
297 +
298 + return clk;
299 +}
300 +
301 +unsigned long ltq_get_bus_clock(void)
302 +{
303 + u32 fpi_sel;
304 + unsigned long clk;
305 +
306 + fpi_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_FPI_MASK,
307 + LTQ_CGU_SYS_FPI_SHIFT);
308 +
309 + if (fpi_sel)
310 + /* Half the DDR clock */
311 + clk = ltq_get_io_region_clock() >> 1;
312 + else
313 + /* Same as DDR clock */
314 + clk = ltq_get_io_region_clock();
315 +
316 + return clk;
317 +}
318 --- /dev/null
319 +++ b/arch/mips/cpu/mips32/danube/cgu_init.S
320 @@ -0,0 +1,142 @@
321 +/*
322 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
323 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
324 + *
325 + * SPDX-License-Identifier: GPL-2.0+
326 + */
327 +
328 +#include <config.h>
329 +#include <asm/asm.h>
330 +#include <asm/regdef.h>
331 +#include <asm/addrspace.h>
332 +#include <asm/arch/soc.h>
333 +
334 +/* RCU module register */
335 +#define LTQ_RCU_RST_REQ 0x0010
336 +#define LTQ_RCU_RST_STAT 0x0014
337 +#define LTQ_RCU_RST_REQ_VALUE 0x40000008
338 +#define LTQ_RCU_RST_STAT_XTAL_F 0x20000
339 +
340 +/* CGU module register */
341 +#define LTQ_CGU_PLL0_CFG 0x0004 /* PLL0 config */
342 +#define LTQ_CGU_PLL1_CFG 0x0008 /* PLL1 config */
343 +#define LTQ_CGU_PLL2_CFG 0x000C /* PLL2 config */
344 +#define LTQ_CGU_SYS 0x0010 /* System clock */
345 +
346 +/* Valid SYS.CPU0/1 values */
347 +#define LTQ_CGU_SYS_CPU0_SHIFT 2
348 +#define LTQ_CGU_SYS_CPU1_SHIFT 4
349 +#define LTQ_CGU_SYS_CPU_PLL0 0x0
350 +#define LTQ_CGU_SYS_CPU_DDR_EQUAL 0x1
351 +#define LTQ_CGU_SYS_CPU_DDR_TWICE 0x2
352 +
353 +/* Valid SYS.DDR values */
354 +#define LTQ_CGU_SYS_DDR_SHIFT 0
355 +#define LTQ_CGU_SYS_DDR_167_MHZ 0x0
356 +#define LTQ_CGU_SYS_DDR_133_MHZ 0x1
357 +#define LTQ_CGU_SYS_DDR_111_MHZ 0x2
358 +#define LTQ_CGU_SYS_DDR_83_MHZ 0x3
359 +
360 +/* Valid SYS.FPI values */
361 +#define LTQ_CGU_SYS_FPI_SHIFT 6
362 +#define LTQ_CGU_SYS_FPI_DDR_EQUAL 0x0
363 +#define LTQ_CGU_SYS_FPI_DDR_HALF 0x1
364 +
365 +/* Valid SYS.PPE values */
366 +#define LTQ_CGU_SYS_PPE_SHIFT 7
367 +#define LTQ_CGU_SYS_PPE_266_MHZ 0x0
368 +#define LTQ_CGU_SYS_PPE_240_MHZ 0x1
369 +#define LTQ_CGU_SYS_PPE_222_MHZ 0x2
370 +#define LTQ_CGU_SYS_PPE_133_MHZ 0x3
371 +
372 +#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_333_DDR_167)
373 +#define LTQ_CGU_SYS_CPU_CONFIG LTQ_CGU_SYS_CPU_DDR_TWICE
374 +#define LTQ_CGU_SYS_DDR_CONFIG LTQ_CGU_SYS_DDR_167_MHZ
375 +#define LTQ_CGU_SYS_FPI_CONFIG LTQ_CGU_SYS_FPI_DDR_HALF
376 +#define LTQ_CGU_SYS_PPE_CONFIG LTQ_CGU_SYS_PPE_266_MHZ
377 +#elif (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_111_DDR_111)
378 +#define LTQ_CGU_SYS_CPU_CONFIG LTQ_CGU_SYS_CPU_DDR_EQUAL
379 +#define LTQ_CGU_SYS_DDR_CONFIG LTQ_CGU_SYS_DDR_111_MHZ
380 +#define LTQ_CGU_SYS_FPI_CONFIG LTQ_CGU_SYS_FPI_DDR_HALF
381 +#define LTQ_CGU_SYS_PPE_CONFIG LTQ_CGU_SYS_PPE_133_MHZ
382 +#else
383 +#error "Invalid system clock configuration!"
384 +#endif
385 +
386 +/* Build register values */
387 +#define LTQ_CGU_SYS_VALUE ((LTQ_CGU_SYS_PPE_CONFIG << \
388 + LTQ_CGU_SYS_PPE_SHIFT) | \
389 + (LTQ_CGU_SYS_FPI_CONFIG << \
390 + LTQ_CGU_SYS_FPI_SHIFT) | \
391 + (LTQ_CGU_SYS_CPU_CONFIG << \
392 + LTQ_CGU_SYS_CPU1_SHIFT) | \
393 + (LTQ_CGU_SYS_CPU_CONFIG << \
394 + LTQ_CGU_SYS_CPU0_SHIFT) | \
395 + LTQ_CGU_SYS_DDR_CONFIG)
396 +
397 +/* Reset values for PLL registers for usage with 35.328 MHz crystal */
398 +#define PLL0_35MHZ_CONFIG 0x9D861059
399 +#define PLL1_35MHZ_CONFIG 0x1A260CD9
400 +#define PLL2_35MHZ_CONFIG 0x8000f1e5
401 +
402 +/* Reset values for PLL registers for usage with 36 MHz crystal */
403 +#define PLL0_36MHZ_CONFIG 0x1000125D
404 +#define PLL1_36MHZ_CONFIG 0x1B1E0C99
405 +#define PLL2_36MHZ_CONFIG 0x8002f2a1
406 +
407 +LEAF(ltq_cgu_init)
408 + /* Load current CGU register value */
409 + li t0, (LTQ_CGU_BASE | KSEG1)
410 + lw t1, LTQ_CGU_SYS(t0)
411 +
412 + /* Load target CGU register values */
413 + li t3, LTQ_CGU_SYS_VALUE
414 +
415 + /* Only update registers if values differ */
416 + beq t1, t3, finished
417 +
418 + /*
419 + * Check whether the XTAL_F bit in RST_STAT register is set or not.
420 + * This bit is latched in via pin strapping. If bit is set then
421 + * clock source is a 36 MHz crystal. Otherwise a 35.328 MHz crystal.
422 + */
423 + li t1, (LTQ_RCU_BASE | KSEG1)
424 + lw t2, LTQ_RCU_RST_STAT(t1)
425 + and t2, t2, LTQ_RCU_RST_STAT_XTAL_F
426 + beq t2, LTQ_RCU_RST_STAT_XTAL_F, boot_36mhz
427 +
428 +boot_35mhz:
429 + /* Configure PLL for 35.328 MHz */
430 + li t2, PLL0_35MHZ_CONFIG
431 + sw t2, LTQ_CGU_PLL0_CFG(t0)
432 + li t2, PLL1_35MHZ_CONFIG
433 + sw t2, LTQ_CGU_PLL1_CFG(t0)
434 + li t2, PLL2_35MHZ_CONFIG
435 + sw t2, LTQ_CGU_PLL2_CFG(t0)
436 +
437 + b do_reset
438 +
439 +boot_36mhz:
440 + /* Configure PLL for 36 MHz */
441 + li t2, PLL0_36MHZ_CONFIG
442 + sw t2, LTQ_CGU_PLL0_CFG(t0)
443 + li t2, PLL1_36MHZ_CONFIG
444 + sw t2, LTQ_CGU_PLL1_CFG(t0)
445 + li t2, PLL2_36MHZ_CONFIG
446 + sw t2, LTQ_CGU_PLL2_CFG(t0)
447 +
448 +do_reset:
449 + /* Store new clock config */
450 + sw t3, LTQ_CGU_SYS(t0)
451 +
452 + /* Perform software reset to activate new clock config */
453 + li t2, LTQ_RCU_RST_REQ_VALUE
454 + sw t2, LTQ_RCU_RST_REQ(t1)
455 +
456 +wait_reset:
457 + b wait_reset
458 +
459 +finished:
460 + jr ra
461 +
462 + END(ltq_cgu_init)
463 --- /dev/null
464 +++ b/arch/mips/cpu/mips32/danube/chipid.c
465 @@ -0,0 +1,59 @@
466 +/*
467 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
468 + *
469 + * SPDX-License-Identifier: GPL-2.0+
470 + */
471 +
472 +#include <common.h>
473 +#include <asm/lantiq/io.h>
474 +#include <asm/lantiq/chipid.h>
475 +#include <asm/arch/soc.h>
476 +
477 +#define LTQ_CHIPID_VERSION_SHIFT 28
478 +#define LTQ_CHIPID_VERSION_MASK (0xF << LTQ_CHIPID_VERSION_SHIFT)
479 +#define LTQ_CHIPID_PNUM_SHIFT 12
480 +#define LTQ_CHIPID_PNUM_MASK (0xFFFF << LTQ_CHIPID_PNUM_SHIFT)
481 +
482 +struct ltq_chipid_regs {
483 + u32 manid; /* Manufacturer identification */
484 + u32 chipid; /* Chip identification */
485 +};
486 +
487 +static struct ltq_chipid_regs *ltq_chipid_regs =
488 + (struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);
489 +
490 +unsigned int ltq_chip_version_get(void)
491 +{
492 + u32 chipid;
493 +
494 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
495 +
496 + return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;
497 +}
498 +
499 +unsigned int ltq_chip_partnum_get(void)
500 +{
501 + u32 chipid;
502 +
503 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
504 +
505 + return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;
506 +}
507 +
508 +const char *ltq_chip_partnum_str(void)
509 +{
510 + enum ltq_chip_partnum partnum = ltq_chip_partnum_get();
511 +
512 + switch (partnum) {
513 + case LTQ_SOC_DANUBE:
514 + return "Danube";
515 + case LTQ_SOC_DANUBE_S:
516 + return "Danube-S";
517 + case LTQ_SOC_TWINPASS:
518 + return "Twinpass";
519 + default:
520 + printf("Unknown partnum: %x\n", partnum);
521 + }
522 +
523 + return "";
524 +}
525 --- /dev/null
526 +++ b/arch/mips/cpu/mips32/danube/config.mk
527 @@ -0,0 +1,25 @@
528 +#
529 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
530 +#
531 +# SPDX-License-Identifier: GPL-2.0+
532 +#
533 +
534 +PF_CPPFLAGS_DANUBE := $(call cc-option,-mtune=24kec,)
535 +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_DANUBE)
536 +
537 +ifdef CONFIG_SPL_BUILD
538 +PF_ABICALLS := -mno-abicalls
539 +PF_PIC := -fno-pic
540 +PF_PIE :=
541 +USE_PRIVATE_LIBGCC := yes
542 +endif
543 +
544 +LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
545 +
546 +ifndef CONFIG_SPL_BUILD
547 +ifdef CONFIG_SYS_BOOT_NORSPL
548 +ALL-y += $(obj)u-boot.ltq.norspl
549 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
550 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
551 +endif
552 +endif
553 --- /dev/null
554 +++ b/arch/mips/cpu/mips32/danube/ebu.c
555 @@ -0,0 +1,105 @@
556 +/*
557 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
558 + *
559 + * SPDX-License-Identifier: GPL-2.0+
560 + */
561 +
562 +#include <common.h>
563 +#include <asm/arch/soc.h>
564 +#include <asm/lantiq/io.h>
565 +
566 +#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4)
567 +#define EBU_ADDRSEL_REGEN (1 << 0)
568 +
569 +#define EBU_CON_WRDIS (1 << 31)
570 +#define EBU_CON_AGEN_DEMUX (0x0 << 24)
571 +#define EBU_CON_AGEN_MUX (0x2 << 24)
572 +#define EBU_CON_SETUP (1 << 22)
573 +#define EBU_CON_WAIT_DIS (0x0 << 20)
574 +#define EBU_CON_WAIT_ASYNC (0x1 << 20)
575 +#define EBU_CON_WAIT_SYNC (0x2 << 20)
576 +#define EBU_CON_WINV (1 << 19)
577 +#define EBU_CON_PW_8BIT (0x0 << 16)
578 +#define EBU_CON_PW_16BIT (0x1 << 16)
579 +#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14)
580 +#define EBU_CON_BCGEN_CS (0x0 << 12)
581 +#define EBU_CON_BCGEN_INTEL (0x1 << 12)
582 +#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12)
583 +#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8)
584 +#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6)
585 +#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4)
586 +#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2)
587 +#define EBU_CON_CMULT_1 0x0
588 +#define EBU_CON_CMULT_4 0x1
589 +#define EBU_CON_CMULT_8 0x2
590 +#define EBU_CON_CMULT_16 0x3
591 +
592 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
593 +#define ebu_region0_enable 1
594 +#else
595 +#define ebu_region0_enable 0
596 +#endif
597 +
598 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
599 +#define ebu_region1_enable 1
600 +#else
601 +#define ebu_region1_enable 0
602 +#endif
603 +
604 +struct ltq_ebu_regs {
605 + u32 clc;
606 + u32 rsvd0[3];
607 + u32 con;
608 + u32 rsvd1[3];
609 + u32 addr_sel_0;
610 + u32 addr_sel_1;
611 + u32 rsvd2[14];
612 + u32 con_0;
613 + u32 con_1;
614 +};
615 +
616 +static struct ltq_ebu_regs *ltq_ebu_regs =
617 + (struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);
618 +
619 +void ltq_ebu_init(void)
620 +{
621 + if (ebu_region0_enable) {
622 + /*
623 + * Map EBU region 0 to range 0x10000000-0x13ffffff and enable
624 + * region control. This supports up to 32 MiB NOR flash in
625 + * bank 0.
626 + */
627 + ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
628 + EBU_ADDRSEL_MASK(1) | EBU_ADDRSEL_REGEN);
629 +
630 + ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
631 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
632 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
633 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
634 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
635 + EBU_CON_CMULT_16);
636 + } else
637 + ltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);
638 +
639 + if (ebu_region1_enable) {
640 + /*
641 + * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
642 + * region control. This supports NAND flash in bank 1.
643 + */
644 + ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
645 + EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
646 +
647 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
648 + EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
649 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
650 + EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
651 + EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
652 + EBU_CON_CMULT_4);
653 + } else
654 + ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
655 +}
656 +
657 +void *flash_swap_addr(unsigned long addr)
658 +{
659 + return (void *)(addr ^ 2);
660 +}
661 --- /dev/null
662 +++ b/arch/mips/cpu/mips32/danube/mem.c
663 @@ -0,0 +1,30 @@
664 +/*
665 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
666 + *
667 + * SPDX-License-Identifier: GPL-2.0+
668 + */
669 +
670 +#include <common.h>
671 +#include <asm/arch/soc.h>
672 +#include <asm/lantiq/io.h>
673 +
674 +static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);
675 +
676 +static inline u32 ltq_mc_dc_read(u32 index)
677 +{
678 + return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_DC_OFFSET(index));
679 +}
680 +
681 +phys_size_t initdram(int board_type)
682 +{
683 + u32 col, row, dc04, dc19, dc20;
684 +
685 + dc04 = ltq_mc_dc_read(4);
686 + dc19 = ltq_mc_dc_read(19);
687 + dc20 = ltq_mc_dc_read(20);
688 +
689 + row = (dc04 & 0xF) - ((dc19 & 0x700) >> 8);
690 + col = ((dc04 & 0xF00) >> 8) - (dc20 & 0x7);
691 +
692 + return (1 << (row + col)) * 4 * 2;
693 +}
694 --- /dev/null
695 +++ b/arch/mips/cpu/mips32/danube/mem_init.S
696 @@ -0,0 +1,114 @@
697 +/*
698 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
699 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
700 + *
701 + * SPDX-License-Identifier: GPL-2.0+
702 + */
703 +
704 +#include <config.h>
705 +#include <asm/asm.h>
706 +#include <asm/regdef.h>
707 +#include <asm/addrspace.h>
708 +#include <asm/arch/soc.h>
709 +
710 +/* Must be configured in BOARDDIR */
711 +#include <ddr_settings.h>
712 +
713 +#define LTQ_MC_GEN_ERRCAUSE 0x0010
714 +#define LTQ_MC_GEN_ERRADDR 0x0020
715 +#define LTQ_MC_GEN_CON 0x0060
716 +#define LTQ_MC_GEN_STAT 0x0070
717 +#define LTQ_MC_GEN_CON_SRAM_DDR_ENABLE 0x5
718 +#define LTQ_MC_GEN_STAT_DLCK_PWRON 0xC
719 +
720 +#define LTQ_MC_DDR_DC03_MC_START 0x100
721 +
722 + /* Store given value in MC DDR CCRx register */
723 + .macro dc_sw num, val
724 + li t2, \val
725 + sw t2, LTQ_MC_DDR_DC_OFFSET(\num)(t1)
726 + .endm
727 +
728 +LEAF(ltq_mem_init)
729 + /* Load MC General and MC DDR module base */
730 + li t0, (LTQ_MC_GEN_BASE | KSEG1)
731 + li t1, (LTQ_MC_DDR_BASE | KSEG1)
732 +
733 + /* Clear access error log registers */
734 + sw zero, LTQ_MC_GEN_ERRCAUSE(t0)
735 + sw zero, LTQ_MC_GEN_ERRADDR(t0)
736 +
737 + /* Enable DDR and SRAM module in memory controller */
738 + li t2, LTQ_MC_GEN_CON_SRAM_DDR_ENABLE
739 + sw t2, LTQ_MC_GEN_CON(t0)
740 +
741 + /* Clear start bit of DDR memory controller */
742 + sw zero, LTQ_MC_DDR_DC_OFFSET(3)(t1)
743 +
744 + /* Init memory controller registers with values ddr_settings.h */
745 + dc_sw 0, MC_DC00_VALUE
746 + dc_sw 1, MC_DC01_VALUE
747 + dc_sw 2, MC_DC02_VALUE
748 + dc_sw 4, MC_DC04_VALUE
749 + dc_sw 5, MC_DC05_VALUE
750 + dc_sw 6, MC_DC06_VALUE
751 + dc_sw 7, MC_DC07_VALUE
752 + dc_sw 8, MC_DC08_VALUE
753 + dc_sw 9, MC_DC09_VALUE
754 +
755 + dc_sw 10, MC_DC10_VALUE
756 + dc_sw 11, MC_DC11_VALUE
757 + dc_sw 12, MC_DC12_VALUE
758 + dc_sw 13, MC_DC13_VALUE
759 + dc_sw 14, MC_DC14_VALUE
760 + dc_sw 15, MC_DC15_VALUE
761 + dc_sw 16, MC_DC16_VALUE
762 + dc_sw 17, MC_DC17_VALUE
763 + dc_sw 18, MC_DC18_VALUE
764 + dc_sw 19, MC_DC19_VALUE
765 +
766 + dc_sw 20, MC_DC20_VALUE
767 + dc_sw 21, MC_DC21_VALUE
768 + dc_sw 22, MC_DC22_VALUE
769 + dc_sw 23, MC_DC23_VALUE
770 + dc_sw 24, MC_DC24_VALUE
771 + dc_sw 25, MC_DC25_VALUE
772 + dc_sw 26, MC_DC26_VALUE
773 + dc_sw 27, MC_DC27_VALUE
774 + dc_sw 28, MC_DC28_VALUE
775 + dc_sw 29, MC_DC29_VALUE
776 +
777 + dc_sw 30, MC_DC30_VALUE
778 + dc_sw 31, MC_DC31_VALUE
779 + dc_sw 32, MC_DC32_VALUE
780 + dc_sw 33, MC_DC33_VALUE
781 + dc_sw 34, MC_DC34_VALUE
782 + dc_sw 35, MC_DC35_VALUE
783 + dc_sw 36, MC_DC36_VALUE
784 + dc_sw 37, MC_DC37_VALUE
785 + dc_sw 38, MC_DC38_VALUE
786 + dc_sw 39, MC_DC39_VALUE
787 +
788 + dc_sw 40, MC_DC40_VALUE
789 + dc_sw 41, MC_DC41_VALUE
790 + dc_sw 42, MC_DC42_VALUE
791 + dc_sw 43, MC_DC43_VALUE
792 + dc_sw 44, MC_DC44_VALUE
793 + dc_sw 45, MC_DC45_VALUE
794 + dc_sw 46, MC_DC46_VALUE
795 +
796 + /* Set start bit of DDR memory controller */
797 + li t2, LTQ_MC_DDR_DC03_MC_START
798 + sw t2, LTQ_MC_DDR_DC_OFFSET(3)(t1)
799 +
800 + /* Wait until DLL has locked and core is ready for data transfers */
801 +wait_ready:
802 + lw t2, LTQ_MC_GEN_STAT(t0)
803 + li t3, LTQ_MC_GEN_STAT_DLCK_PWRON
804 + and t2, t3
805 + bne t2, t3, wait_ready
806 +
807 +finished:
808 + jr ra
809 +
810 + END(ltq_mem_init)
811 --- /dev/null
812 +++ b/arch/mips/cpu/mips32/danube/pmu.c
813 @@ -0,0 +1,117 @@
814 +/*
815 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
816 + *
817 + * SPDX-License-Identifier: GPL-2.0+
818 + */
819 +
820 +#include <common.h>
821 +#include <asm/lantiq/io.h>
822 +#include <asm/lantiq/pm.h>
823 +#include <asm/arch/soc.h>
824 +
825 +#define LTQ_PMU_PWDCR_RESERVED 0xFD0C001C
826 +
827 +#define LTQ_PMU_PWDCR_TDM (1 << 25)
828 +#define LTQ_PMU_PWDCR_PPE_ENET0 (1 << 23)
829 +#define LTQ_PMU_PWDCR_PPE_ENET1 (1 << 22)
830 +#define LTQ_PMU_PWDCR_PPE_TC (1 << 21)
831 +#define LTQ_PMU_PWDCR_DEU (1 << 20)
832 +#define LTQ_PMU_PWDCR_UART1 (1 << 17)
833 +#define LTQ_PMU_PWDCR_SDIO (1 << 16)
834 +#define LTQ_PMU_PWDCR_AHB (1 << 15)
835 +#define LTQ_PMU_PWDCR_FPI0 (1 << 14)
836 +#define LTQ_PMU_PWDCR_PPE (1 << 13)
837 +#define LTQ_PMU_PWDCR_GPTC (1 << 12)
838 +#define LTQ_PMU_PWDCR_LEDC (1 << 11)
839 +#define LTQ_PMU_PWDCR_EBU (1 << 10)
840 +#define LTQ_PMU_PWDCR_DSL (1 << 9)
841 +#define LTQ_PMU_PWDCR_SPI (1 << 8)
842 +#define LTQ_PMU_PWDCR_UART0 (1 << 7)
843 +#define LTQ_PMU_PWDCR_USB (1 << 6)
844 +#define LTQ_PMU_PWDCR_DMA (1 << 5)
845 +#define LTQ_PMU_PWDCR_FPI1 (1 << 1)
846 +#define LTQ_PMU_PWDCR_USB_PHY (1 << 0)
847 +
848 +struct ltq_pmu_regs {
849 + u32 rsvd0[7];
850 + u32 pwdcr;
851 + u32 sr;
852 + u32 pwdcr1;
853 + u32 sr1;
854 +};
855 +
856 +static struct ltq_pmu_regs *ltq_pmu_regs =
857 + (struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);
858 +
859 +u32 ltq_pm_map(enum ltq_pm_modules module)
860 +{
861 + u32 val;
862 +
863 + switch (module) {
864 + case LTQ_PM_CORE:
865 + val = LTQ_PMU_PWDCR_UART1 | LTQ_PMU_PWDCR_FPI0 |
866 + LTQ_PMU_PWDCR_LEDC | LTQ_PMU_PWDCR_EBU;
867 + break;
868 + case LTQ_PM_DMA:
869 + val = LTQ_PMU_PWDCR_DMA;
870 + break;
871 + case LTQ_PM_ETH:
872 + val = LTQ_PMU_PWDCR_PPE_ENET0 | LTQ_PMU_PWDCR_PPE_TC |
873 + LTQ_PMU_PWDCR_PPE;
874 + break;
875 + case LTQ_PM_SPI:
876 + val = LTQ_PMU_PWDCR_SPI;
877 + break;
878 + default:
879 + val = 0;
880 + break;
881 + }
882 +
883 + return val;
884 +}
885 +
886 +int ltq_pm_enable(enum ltq_pm_modules module)
887 +{
888 + const unsigned long timeout = 1000;
889 + unsigned long timebase;
890 + u32 sr, val;
891 +
892 + val = ltq_pm_map(module);
893 + if (unlikely(!val))
894 + return 1;
895 +
896 + ltq_clrbits(&ltq_pmu_regs->pwdcr, val);
897 +
898 + timebase = get_timer(0);
899 +
900 + do {
901 + sr = ltq_readl(&ltq_pmu_regs->sr);
902 + if (~sr & val)
903 + return 0;
904 + } while (get_timer(timebase) < timeout);
905 +
906 + return 1;
907 +}
908 +
909 +int ltq_pm_disable(enum ltq_pm_modules module)
910 +{
911 + u32 val;
912 +
913 + val = ltq_pm_map(module);
914 + if (unlikely(!val))
915 + return 1;
916 +
917 + ltq_setbits(&ltq_pmu_regs->pwdcr, val);
918 +
919 + return 0;
920 +}
921 +
922 +void ltq_pmu_init(void)
923 +{
924 + u32 set, clr;
925 +
926 + clr = ltq_pm_map(LTQ_PM_CORE);
927 + set = ~(LTQ_PMU_PWDCR_RESERVED | clr);
928 +
929 + ltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);
930 +}
931 --- /dev/null
932 +++ b/arch/mips/cpu/mips32/danube/rcu.c
933 @@ -0,0 +1,125 @@
934 +/*
935 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
936 + *
937 + * SPDX-License-Identifier: GPL-2.0+
938 + */
939 +
940 +#include <common.h>
941 +#include <asm/lantiq/io.h>
942 +#include <asm/lantiq/reset.h>
943 +#include <asm/lantiq/cpu.h>
944 +#include <asm/arch/soc.h>
945 +
946 +#define LTQ_RCU_RD_SRST (1 << 30) /* Global SW Reset */
947 +#define LTQ_RCU_RD_MC (1 << 14) /* Memory Controller */
948 +#define LTQ_RCU_RD_PCI (1 << 13) /* PCI core */
949 +#define LTQ_RCU_RD_DFE_AFE (1 << 12) /* Voice DFE/AFE */
950 +#define LTQ_RCU_RD_DSL_AFE (1 << 11) /* DSL AFE */
951 +#define LTQ_RCU_RD_SDIO (1 << 10) /* SDIO core */
952 +#define LTQ_RCU_RD_DMA (1 << 9) /* DMA core */
953 +#define LTQ_RCU_RD_PPE (1 << 8) /* PPE core */
954 +#define LTQ_RCU_RD_ARC_DFE (1 << 7) /* ARC/DFE core */
955 +#define LTQ_RCU_RD_AHB (1 << 6) /* AHB bus */
956 +#define LTQ_RCU_RD_ENET_MAC1 (1 << 5) /* Ethernet MAC1 */
957 +#define LTQ_RCU_RD_USB (1 << 4) /* USB and Phy core */
958 +#define LTQ_RCU_RD_CPU1 (1 << 3) /* CPU1 subsystem */
959 +#define LTQ_RCU_RD_FPI (1 << 2) /* FPI bus */
960 +#define LTQ_RCU_RD_CPU0 (1 << 1) /* CPU0 subsystem */
961 +#define LTQ_RCU_RD_HRST (1 << 0) /* HW reset via HRST pin */
962 +
963 +#define LTQ_RCU_STAT_BOOT_SHIFT 18
964 +#define LTQ_RCU_STAT_BOOT_MASK (0x7 << LTQ_RCU_STAT_BOOT_SHIFT)
965 +
966 +struct ltq_rcu_regs {
967 + u32 rsvd0[4];
968 + u32 req; /* Reset request */
969 + u32 stat; /* Reset status */
970 + u32 usb_cfg; /* USB configure */
971 + u32 rsvd1[2];
972 + u32 pci_rdy; /* PCI boot ready */
973 +};
974 +
975 +static struct ltq_rcu_regs *ltq_rcu_regs =
976 + (struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);
977 +
978 +u32 ltq_reset_map(enum ltq_reset_modules module)
979 +{
980 + u32 val;
981 +
982 + switch (module) {
983 + case LTQ_RESET_CORE:
984 + case LTQ_RESET_SOFT:
985 + val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU1;
986 + break;
987 + case LTQ_RESET_DMA:
988 + val = LTQ_RCU_RD_DMA;
989 + break;
990 + case LTQ_RESET_ETH:
991 + val = LTQ_RCU_RD_PPE;
992 + break;
993 + case LTQ_RESET_HARD:
994 + val = LTQ_RCU_RD_HRST;
995 + break;
996 + default:
997 + val = 0;
998 + break;
999 + }
1000 +
1001 + return val;
1002 +}
1003 +
1004 +int ltq_reset_activate(enum ltq_reset_modules module)
1005 +{
1006 + u32 val;
1007 +
1008 + val = ltq_reset_map(module);
1009 + if (unlikely(!val))
1010 + return 1;
1011 +
1012 + ltq_setbits(&ltq_rcu_regs->req, val);
1013 +
1014 + return 0;
1015 +}
1016 +
1017 +int ltq_reset_deactivate(enum ltq_reset_modules module)
1018 +{
1019 + u32 val;
1020 +
1021 + val = ltq_reset_map(module);
1022 + if (unlikely(!val))
1023 + return 1;
1024 +
1025 + ltq_clrbits(&ltq_rcu_regs->req, val);
1026 +
1027 + return 0;
1028 +}
1029 +
1030 +enum ltq_boot_select ltq_boot_select(void)
1031 +{
1032 + u32 stat;
1033 + unsigned int bootstrap;
1034 +
1035 + stat = ltq_readl(&ltq_rcu_regs->stat);
1036 + bootstrap = (stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT;
1037 +
1038 + switch (bootstrap) {
1039 + case 0:
1040 + return BOOT_NOR_NO_BOOTROM;
1041 + case 1:
1042 + return BOOT_NOR;
1043 + case 2:
1044 + return BOOT_MII0;
1045 + case 3:
1046 + return BOOT_PCI;
1047 + case 4:
1048 + return BOOT_UART;
1049 + case 5:
1050 + return BOOT_SPI;
1051 + case 6:
1052 + return BOOT_NAND;
1053 + case 7:
1054 + return BOOT_RMII0;
1055 + default:
1056 + return BOOT_UNKNOWN;
1057 + }
1058 +}
1059 --- /dev/null
1060 +++ b/arch/mips/cpu/mips32/lantiq-common/Makefile
1061 @@ -0,0 +1,34 @@
1062 +#
1063 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
1064 +#
1065 +# SPDX-License-Identifier: GPL-2.0+
1066 +#
1067 +
1068 +include $(TOPDIR)/config.mk
1069 +
1070 +LIB = $(obj)liblantiq-common.o
1071 +
1072 +START = start.o
1073 +COBJS-y = cpu.o pmu.o
1074 +COBJS-$(CONFIG_SPL_BUILD) += spl.o
1075 +SOBJS-y = lowlevel_init.o
1076 +
1077 +COBJS := $(COBJS-y)
1078 +SOBJS := $(SOBJS-y)
1079 +SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
1080 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1081 +START := $(addprefix $(obj),$(START))
1082 +
1083 +all: $(LIB)
1084 +
1085 +$(LIB): $(obj).depend $(OBJS)
1086 + $(call cmd_link_o_target, $(OBJS))
1087 +
1088 +#########################################################################
1089 +
1090 +# defines $(obj).depend target
1091 +include $(SRCTREE)/rules.mk
1092 +
1093 +sinclude $(obj).depend
1094 +
1095 +#########################################################################
1096 --- /dev/null
1097 +++ b/arch/mips/cpu/mips32/lantiq-common/cpu.c
1098 @@ -0,0 +1,59 @@
1099 +/*
1100 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1101 + *
1102 + * SPDX-License-Identifier: GPL-2.0+
1103 + */
1104 +
1105 +#include <common.h>
1106 +#include <asm/lantiq/chipid.h>
1107 +#include <asm/lantiq/clk.h>
1108 +#include <asm/lantiq/reset.h>
1109 +#include <asm/lantiq/cpu.h>
1110 +
1111 +static const char ltq_bootsel_strings[][16] = {
1112 + "NOR",
1113 + "NOR w/o BootROM",
1114 + "UART",
1115 + "UART w/o EEPROM",
1116 + "SPI",
1117 + "NAND",
1118 + "PCI",
1119 + "MII0",
1120 + "RMII0",
1121 + "RGMII1",
1122 + "unknown",
1123 +};
1124 +
1125 +const char *ltq_boot_select_str(void)
1126 +{ enum ltq_boot_select bootsel = ltq_boot_select();
1127 +
1128 + if (bootsel > BOOT_UNKNOWN)
1129 + bootsel = BOOT_UNKNOWN;
1130 +
1131 + return ltq_bootsel_strings[bootsel];
1132 +}
1133 +
1134 +void ltq_chip_print_info(void)
1135 +{
1136 + char buf[32];
1137 +
1138 + printf("SoC: Lantiq %s v1.%u\n", ltq_chip_partnum_str(),
1139 + ltq_chip_version_get());
1140 + printf("CPU: %s MHz\n", strmhz(buf, ltq_get_cpu_clock()));
1141 + printf("IO: %s MHz\n", strmhz(buf, ltq_get_io_region_clock()));
1142 + printf("BUS: %s MHz\n", strmhz(buf, ltq_get_bus_clock()));
1143 + printf("BOOT: %s\n", ltq_boot_select_str());
1144 +}
1145 +
1146 +int arch_cpu_init(void)
1147 +{
1148 + ltq_pmu_init();
1149 + ltq_ebu_init();
1150 +
1151 + return 0;
1152 +}
1153 +
1154 +void _machine_restart(void)
1155 +{
1156 + ltq_reset_activate(LTQ_RESET_CORE);
1157 +}
1158 --- /dev/null
1159 +++ b/arch/mips/cpu/mips32/lantiq-common/lowlevel_init.S
1160 @@ -0,0 +1,20 @@
1161 +/*
1162 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1163 + *
1164 + * SPDX-License-Identifier: GPL-2.0+
1165 + */
1166 +
1167 +#include <asm/asm.h>
1168 +#include <asm/regdef.h>
1169 +
1170 +NESTED(lowlevel_init, 0, ra)
1171 + move t8, ra
1172 +
1173 + la t7, ltq_cgu_init
1174 + jalr t7
1175 +
1176 + la t7, ltq_mem_init
1177 + jalr t7
1178 +
1179 + jr t8
1180 + END(lowlevel_init)
1181 --- /dev/null
1182 +++ b/arch/mips/cpu/mips32/lantiq-common/pmu.c
1183 @@ -0,0 +1,9 @@
1184 +/*
1185 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1186 + *
1187 + * SPDX-License-Identifier: GPL-2.0+
1188 + */
1189 +
1190 +#include <common.h>
1191 +#include <asm/lantiq/pm.h>
1192 +
1193 --- /dev/null
1194 +++ b/arch/mips/cpu/mips32/lantiq-common/spl.c
1195 @@ -0,0 +1,403 @@
1196 +/*
1197 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1198 + *
1199 + * SPDX-License-Identifier: GPL-2.0+
1200 + */
1201 +
1202 +#include <common.h>
1203 +#include <image.h>
1204 +#include <version.h>
1205 +#include <spi_flash.h>
1206 +#include <linux/compiler.h>
1207 +#include <lzma/LzmaDec.h>
1208 +#include <linux/lzo.h>
1209 +#include <asm/mipsregs.h>
1210 +
1211 +#if defined(CONFIG_LTQ_SPL_CONSOLE)
1212 +#define spl_has_console 1
1213 +
1214 +#if defined(CONFIG_LTQ_SPL_DEBUG)
1215 +#define spl_has_debug 1
1216 +#else
1217 +#define spl_has_debug 0
1218 +#endif
1219 +
1220 +#else
1221 +#define spl_has_console 0
1222 +#define spl_has_debug 0
1223 +#endif
1224 +
1225 +#define spl_debug(fmt, args...) \
1226 + do { \
1227 + if (spl_has_debug) \
1228 + printf(fmt, ##args); \
1229 + } while (0)
1230 +
1231 +#define spl_puts(msg) \
1232 + do { \
1233 + if (spl_has_console) \
1234 + puts(msg); \
1235 + } while (0)
1236 +
1237 +#if defined(CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH) && defined(CONFIG_SYS_BOOT_SFSPL)
1238 +#define spl_boot_spi_flash 1
1239 +#else
1240 +#define spl_boot_spi_flash 0
1241 +#ifndef CONFIG_SPL_SPI_BUS
1242 +#define CONFIG_SPL_SPI_BUS 0
1243 +#endif
1244 +#ifndef CONFIG_SPL_SPI_CS
1245 +#define CONFIG_SPL_SPI_CS 0
1246 +#endif
1247 +#ifndef CONFIG_SPL_SPI_MAX_HZ
1248 +#define CONFIG_SPL_SPI_MAX_HZ 0
1249 +#endif
1250 +#ifndef CONFIG_SPL_SPI_MODE
1251 +#define CONFIG_SPL_SPI_MODE 0
1252 +#endif
1253 +#endif
1254 +
1255 +#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)
1256 +#define spl_boot_nor_flash 1
1257 +#else
1258 +#define spl_boot_nor_flash 0
1259 +#endif
1260 +
1261 +#define spl_sync() __asm__ __volatile__("sync");
1262 +
1263 +struct spl_image {
1264 + ulong data_addr;
1265 + ulong entry_addr;
1266 + ulong data_size;
1267 + ulong entry_size;
1268 + ulong data_crc;
1269 + u8 comp;
1270 +};
1271 +
1272 +DECLARE_GLOBAL_DATA_PTR;
1273 +
1274 +/* Emulated malloc area needed for LZMA allocator in BSS */
1275 +static u8 *spl_mem_ptr __maybe_unused;
1276 +static size_t spl_mem_size __maybe_unused;
1277 +
1278 +static int spl_is_comp_lzma(const struct spl_image *spl)
1279 +{
1280 +#if defined(CONFIG_LTQ_SPL_COMP_LZMA)
1281 + return spl->comp == IH_COMP_LZMA;
1282 +#else
1283 + return 0;
1284 +#endif
1285 +}
1286 +
1287 +static int spl_is_comp_lzo(const struct spl_image *spl)
1288 +{
1289 +#if defined(CONFIG_LTQ_SPL_COMP_LZO)
1290 + return spl->comp == IH_COMP_LZO;
1291 +#else
1292 + return 0;
1293 +#endif
1294 +}
1295 +
1296 +static int spl_is_compressed(const struct spl_image *spl)
1297 +{
1298 + if (spl_is_comp_lzma(spl))
1299 + return 1;
1300 +
1301 + if (spl_is_comp_lzo(spl))
1302 + return 1;
1303 +
1304 + return 0;
1305 +}
1306 +
1307 +static void spl_console_init(void)
1308 +{
1309 + if (!spl_has_console)
1310 + return;
1311 +
1312 + gd->flags |= GD_FLG_RELOC;
1313 + gd->baudrate = CONFIG_BAUDRATE;
1314 +
1315 + serial_init();
1316 +
1317 + gd->have_console = 1;
1318 +
1319 + spl_puts("\nU-Boot SPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \
1320 + U_BOOT_TIME ")\n");
1321 +}
1322 +
1323 +static int spl_parse_image(const image_header_t *hdr, struct spl_image *spl)
1324 +{
1325 + spl_puts("SPL: checking U-Boot image\n");
1326 +
1327 + if (!image_check_magic(hdr)) {
1328 + spl_puts("SPL: invalid magic\n");
1329 + return -1;
1330 + }
1331 +
1332 + if (!image_check_hcrc(hdr)) {
1333 + spl_puts("SPL: invalid header CRC\n");
1334 + return -1;
1335 + }
1336 +
1337 + spl->data_addr += image_get_header_size();
1338 + spl->entry_addr = image_get_load(hdr);
1339 + spl->data_size = image_get_data_size(hdr);
1340 + spl->data_crc = image_get_dcrc(hdr);
1341 + spl->comp = image_get_comp(hdr);
1342 +
1343 + spl_debug("SPL: data %08lx, size %lu, entry %08lx, comp %u\n",
1344 + spl->data_addr, spl->data_size, spl->entry_addr, spl->comp);
1345 +
1346 + return 0;
1347 +}
1348 +
1349 +static int spl_check_data(const struct spl_image *spl, ulong loadaddr)
1350 +{
1351 + ulong dcrc = crc32(0, (unsigned char *)loadaddr, spl->data_size);
1352 +
1353 + if (dcrc != spl->data_crc) {
1354 + spl_puts("SPL: invalid data CRC\n");
1355 + return 0;
1356 + }
1357 +
1358 + return 1;
1359 +}
1360 +
1361 +static void *spl_lzma_alloc(void *p, size_t size)
1362 +{
1363 + u8 *ret;
1364 +
1365 + if (size > spl_mem_size)
1366 + return NULL;
1367 +
1368 + ret = spl_mem_ptr;
1369 + spl_mem_ptr += size;
1370 + spl_mem_size -= size;
1371 +
1372 + return ret;
1373 +}
1374 +
1375 +static void spl_lzma_free(void *p, void *addr)
1376 +{
1377 +}
1378 +
1379 +static int spl_copy_image(struct spl_image *spl)
1380 +{
1381 + spl_puts("SPL: copying U-Boot to RAM\n");
1382 +
1383 + memcpy((void *) spl->entry_addr, (const void *) spl->data_addr,
1384 + spl->data_size);
1385 +
1386 + spl->entry_size = spl->data_size;
1387 +
1388 + return 0;
1389 +}
1390 +
1391 +static int spl_uncompress_lzma(struct spl_image *spl, unsigned long loadaddr)
1392 +{
1393 + SRes res;
1394 + const Byte *prop = (const Byte *) loadaddr;
1395 + const Byte *src = (const Byte *) loadaddr + LZMA_PROPS_SIZE +
1396 + sizeof(uint64_t);
1397 + Byte *dest = (Byte *) spl->entry_addr;
1398 + SizeT dest_len = 0xFFFFFFFF;
1399 + SizeT src_len = spl->data_size - LZMA_PROPS_SIZE;
1400 + ELzmaStatus status = 0;
1401 + ISzAlloc alloc;
1402 +
1403 + spl_puts("SPL: decompressing U-Boot with LZMA\n");
1404 +
1405 + alloc.Alloc = spl_lzma_alloc;
1406 + alloc.Free = spl_lzma_free;
1407 + spl_mem_ptr = (u8 *) CONFIG_SPL_MALLOC_BASE;
1408 + spl_mem_size = CONFIG_SPL_MALLOC_MAX_SIZE;
1409 +
1410 + res = LzmaDecode(dest, &dest_len, src, &src_len, prop, LZMA_PROPS_SIZE,
1411 + LZMA_FINISH_ANY, &status, &alloc);
1412 + if (res != SZ_OK)
1413 + return 1;
1414 +
1415 + spl->entry_size = dest_len;
1416 +
1417 + return 0;
1418 +}
1419 +
1420 +static int spl_uncompress_lzo(struct spl_image *spl, unsigned long loadaddr)
1421 +{
1422 + size_t len;
1423 + int ret;
1424 +
1425 + spl_puts("SPL: decompressing U-Boot with LZO\n");
1426 +
1427 + ret = lzop_decompress(
1428 + (const unsigned char*) loadaddr, spl->data_size,
1429 + (unsigned char *) spl->entry_addr, &len);
1430 +
1431 + spl->entry_size = len;
1432 +
1433 + return ret;
1434 +}
1435 +
1436 +static int spl_uncompress(struct spl_image *spl, unsigned long loadaddr)
1437 +{
1438 + int ret;
1439 +
1440 + if (spl_is_comp_lzma(spl))
1441 + ret = spl_uncompress_lzma(spl, loadaddr);
1442 + else if (spl_is_comp_lzo(spl))
1443 + ret = spl_uncompress_lzo(spl, loadaddr);
1444 + else
1445 + ret = 1;
1446 +
1447 + return ret;
1448 +}
1449 +
1450 +static int spl_load_spi_flash(struct spl_image *spl)
1451 +{
1452 + struct spi_flash sf = { 0 };
1453 + image_header_t hdr;
1454 + int ret;
1455 + unsigned long loadaddr;
1456 +
1457 + /*
1458 + * Image format:
1459 + *
1460 + * - 12 byte non-volatile bootstrap header
1461 + * - SPL binary
1462 + * - 12 byte non-volatile bootstrap header
1463 + * - 64 byte U-Boot mkimage header
1464 + * - U-Boot binary
1465 + */
1466 + spl->data_addr = image_copy_end() - CONFIG_SPL_TEXT_BASE + 24;
1467 +
1468 + spl_puts("SPL: probing SPI flash\n");
1469 +
1470 + spi_init();
1471 + ret = spl_spi_flash_probe(&sf);
1472 + if (ret)
1473 + return ret;
1474 +
1475 + spl_debug("SPL: reading image header at offset %lx\n", spl->data_addr);
1476 +
1477 + ret = spi_flash_read(&sf, spl->data_addr, sizeof(hdr), &hdr);
1478 + if (ret)
1479 + return ret;
1480 +
1481 + spl_debug("SPL: checking image header at offset %lx\n", spl->data_addr);
1482 +
1483 + ret = spl_parse_image(&hdr, spl);
1484 + if (ret)
1485 + return ret;
1486 +
1487 + if (spl_is_compressed(spl))
1488 + loadaddr = CONFIG_LOADADDR;
1489 + else
1490 + loadaddr = spl->entry_addr;
1491 +
1492 + spl_puts("SPL: loading U-Boot to RAM\n");
1493 +
1494 + ret = spi_flash_read(&sf, spl->data_addr, spl->data_size,
1495 + (void *) loadaddr);
1496 +
1497 + if (!spl_check_data(spl, loadaddr))
1498 + return -1;
1499 +
1500 + if (spl_is_compressed(spl))
1501 + ret = spl_uncompress(spl, loadaddr);
1502 +
1503 + return ret;
1504 +}
1505 +
1506 +static int spl_load_nor_flash(struct spl_image *spl)
1507 +{
1508 + const image_header_t *hdr;
1509 + int ret;
1510 +
1511 + /*
1512 + * Image format:
1513 + *
1514 + * - SPL binary
1515 + * - 64 byte U-Boot mkimage header
1516 + * - U-Boot binary
1517 + */
1518 + spl->data_addr = image_copy_end();
1519 + hdr = (const image_header_t *) image_copy_end();
1520 +
1521 + spl_debug("SPL: checking image header at address %p\n", hdr);
1522 +
1523 + ret = spl_parse_image(hdr, spl);
1524 + if (ret)
1525 + return ret;
1526 +
1527 + if (spl_is_compressed(spl))
1528 + ret = spl_uncompress(spl, spl->data_addr);
1529 + else
1530 + ret = spl_copy_image(spl);
1531 +
1532 + return ret;
1533 +}
1534 +
1535 +static int spl_load(struct spl_image *spl)
1536 +{
1537 + int ret;
1538 +
1539 + if (spl_boot_spi_flash)
1540 + ret = spl_load_spi_flash(spl);
1541 + else if (spl_boot_nor_flash)
1542 + ret = spl_load_nor_flash(spl);
1543 + else
1544 + ret = 1;
1545 +
1546 + return ret;
1547 +}
1548 +
1549 +void __noreturn spl_lantiq_init(void)
1550 +{
1551 + void (*uboot)(void) __noreturn;
1552 + struct spl_image spl;
1553 + gd_t gd_data;
1554 + int ret;
1555 +
1556 + gd = &gd_data;
1557 + barrier();
1558 + memset((void *)gd, 0, sizeof(gd_t));
1559 +
1560 + spl_console_init();
1561 +
1562 + spl_debug("SPL: initializing\n");
1563 +
1564 +#if 0
1565 + spl_debug("CP0_CONFIG: %08x\n", read_c0_config());
1566 + spl_debug("CP0_CONFIG1: %08x\n", read_c0_config1());
1567 + spl_debug("CP0_CONFIG2: %08x\n", read_c0_config2());
1568 + spl_debug("CP0_CONFIG3: %08x\n", read_c0_config3());
1569 + spl_debug("CP0_CONFIG6: %08x\n", read_c0_config6());
1570 + spl_debug("CP0_CONFIG7: %08x\n", read_c0_config7());
1571 + spl_debug("CP0_STATUS: %08x\n", read_c0_status());
1572 + spl_debug("CP0_PRID: %08x\n", read_c0_prid());
1573 +#endif
1574 +
1575 + board_early_init_f();
1576 + timer_init();
1577 +
1578 + memset(&spl, 0, sizeof(spl));
1579 +
1580 + ret = spl_load(&spl);
1581 + if (ret)
1582 + goto hang;
1583 +
1584 + spl_debug("SPL: U-Boot entry %08lx\n", spl.entry_addr);
1585 + spl_puts("SPL: jumping to U-Boot\n");
1586 +
1587 + flush_cache(spl.entry_addr, spl.entry_size);
1588 + spl_sync();
1589 +
1590 + uboot = (void *) spl.entry_addr;
1591 + uboot();
1592 +
1593 +hang:
1594 + spl_puts("SPL: cannot start U-Boot\n");
1595 +
1596 + for (;;)
1597 + ;
1598 +}
1599 --- /dev/null
1600 +++ b/arch/mips/cpu/mips32/lantiq-common/start.S
1601 @@ -0,0 +1,143 @@
1602 +/*
1603 + * Copyright (C) 2010 Lantiq Deutschland GmbH
1604 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1605 + *
1606 + * SPDX-License-Identifier: GPL-2.0+
1607 + */
1608 +
1609 +#include <config.h>
1610 +#include <asm/regdef.h>
1611 +#include <asm/mipsregs.h>
1612 +
1613 +#define S_PRIdCoID 16 /* Company ID (R) */
1614 +#define M_PRIdCoID (0xff << S_PRIdCoID)
1615 +#define S_PRIdImp 8 /* Implementation ID (R) */
1616 +#define M_PRIdImp (0xff << S_PRIdImp)
1617 +
1618 +#define K_CacheAttrCWTnWA 0 /* Cacheable, write-thru, no write allocate */
1619 +#define K_CacheAttrCWTWA 1 /* Cacheable, write-thru, write allocate */
1620 +#define K_CacheAttrU 2 /* Uncached */
1621 +#define K_CacheAttrC 3 /* Cacheable */
1622 +#define K_CacheAttrCN 3 /* Cacheable, non-coherent */
1623 +#define K_CacheAttrCCE 4 /* Cacheable, coherent, exclusive */
1624 +#define K_CacheAttrCCS 5 /* Cacheable, coherent, shared */
1625 +#define K_CacheAttrCCU 6 /* Cacheable, coherent, update */
1626 +#define K_CacheAttrUA 7 /* Uncached accelerated */
1627 +
1628 +#define S_ConfigK23 28 /* Kseg2/3 coherency algorithm (FM MMU only) (R/W) */
1629 +#define M_ConfigK23 (0x7 << S_ConfigK23)
1630 +#define W_ConfigK23 3
1631 +#define S_ConfigKU 25 /* Kuseg coherency algorithm (FM MMU only) (R/W) */
1632 +#define M_ConfigKU (0x7 << S_ConfigKU)
1633 +#define W_ConfigKU 3
1634 +
1635 +#define S_ConfigMM 18 /* Merge mode (implementation specific) */
1636 +#define M_ConfigMM (0x1 << S_ConfigMM)
1637 +
1638 +#define S_StatusBEV 22 /* Enable Boot Exception Vectors (R/W) */
1639 +#define M_StatusBEV (0x1 << S_StatusBEV)
1640 +
1641 +#define S_StatusFR 26 /* Enable 64-bit FPRs (R/W) */
1642 +#define M_StatusFR (0x1 << S_StatusFR)
1643 +
1644 +#define S_ConfigK0 0 /* Kseg0 coherency algorithm (R/W) */
1645 +#define M_ConfigK0 (0x7 << S_ConfigK0)
1646 +
1647 +#define CONFIG0_MIPS32_64_MSK 0x8000ffff
1648 +#define STATUS_MIPS32_64_MSK 0xfffcffff
1649 +
1650 +#define STATUS_MIPS24K 0
1651 +#define CONFIG0_MIPS24K ((K_CacheAttrCN << S_ConfigK23) |\
1652 + (K_CacheAttrCN << S_ConfigKU) |\
1653 + (M_ConfigMM))
1654 +
1655 +#define STATUS_MIPS34K 0
1656 +#define CONFIG0_MIPS34K ((K_CacheAttrCN << S_ConfigK23) |\
1657 + (K_CacheAttrCN << S_ConfigKU) |\
1658 + (M_ConfigMM))
1659 +
1660 +#define STATUS_MIPS32_64 (M_StatusBEV | M_StatusFR)
1661 +#define CONFIG0_MIPS32_64 (K_CacheAttrCN << S_ConfigK0)
1662 +
1663 +#ifdef CONFIG_SOC_XWAY_DANUBE
1664 +#define CONFIG0_LANTIQ (CONFIG0_MIPS24K | CONFIG0_MIPS32_64)
1665 +#define STATUS_LANTIQ (STATUS_MIPS24K | STATUS_MIPS32_64)
1666 +#endif
1667 +
1668 +#ifdef CONFIG_SOC_XWAY_VRX200
1669 +#define CONFIG0_LANTIQ (CONFIG0_MIPS34K | CONFIG0_MIPS32_64)
1670 +#define STATUS_LANTIQ (STATUS_MIPS34K | STATUS_MIPS32_64)
1671 +#endif
1672 +
1673 +
1674 + .set noreorder
1675 +
1676 + .globl _start
1677 + .text
1678 +_start:
1679 + /* Entry point */
1680 + b main
1681 + nop
1682 +
1683 + /* Lantiq SoC Boot config word */
1684 + .org 0x10
1685 +#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
1686 + .word CONFIG_SYS_XWAY_EBU_BOOTCFG
1687 +#else
1688 + .word 0
1689 +#endif
1690 + .word 0
1691 +
1692 + .align 4
1693 +main:
1694 +
1695 + /* Init Timer */
1696 + mtc0 zero, CP0_COUNT
1697 + mtc0 zero, CP0_COMPARE
1698 +
1699 + /* Setup MIPS24K/MIPS34K specifics (implementation dependent fields) */
1700 + mfc0 t0, CP0_CONFIG
1701 + li t1, CONFIG0_MIPS32_64_MSK
1702 + and t0, t1
1703 + li t1, CONFIG0_LANTIQ
1704 + or t0, t1
1705 + mtc0 t0, CP0_CONFIG
1706 +
1707 + mfc0 t0, CP0_STATUS
1708 + li t1, STATUS_MIPS32_64_MSK
1709 + and t0, t1
1710 + li t1, STATUS_LANTIQ
1711 + or t0, t1
1712 + mtc0 t0, CP0_STATUS
1713 +
1714 + /* Initialize CGU */
1715 + la t9, ltq_cgu_init
1716 + jalr t9
1717 + nop
1718 +
1719 + /* Initialize memory controller */
1720 + la t9, ltq_mem_init
1721 + jalr t9
1722 + nop
1723 +
1724 + /* Initialize caches... */
1725 + la t9, mips_cache_reset
1726 + jalr t9
1727 + nop
1728 +
1729 + /* Clear BSS */
1730 + la t1, __bss_start
1731 + la t2, __bss_end
1732 + sub t1, 4
1733 +1:
1734 + addi t1, 4
1735 + bltl t1, t2, 1b
1736 + sw zero, 0(t1)
1737 +
1738 + /* Setup stack pointer and force alignment on a 16 byte boundary */
1739 + li t0, (CONFIG_SPL_STACK_BASE & ~0xF)
1740 + la sp, 0(t0)
1741 +
1742 + la t9, spl_lantiq_init
1743 + jr t9
1744 + nop
1745 --- /dev/null
1746 +++ b/arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds
1747 @@ -0,0 +1,48 @@
1748 +/*
1749 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1750 + *
1751 + * SPDX-License-Identifier: GPL-2.0+
1752 + */
1753 +
1754 +MEMORY { .spl_mem : ORIGIN = CONFIG_SPL_TEXT_BASE, \
1755 + LENGTH = CONFIG_SPL_MAX_SIZE }
1756 +MEMORY { .bss_mem : ORIGIN = CONFIG_SPL_BSS_BASE, \
1757 + LENGTH = CONFIG_SPL_BSS_MAX_SIZE }
1758 +
1759 +OUTPUT_FORMAT("elf32-tradbigmips", "elf32-tradbigmips", "elf32-tradlittlemips")
1760 +OUTPUT_ARCH(mips)
1761 +ENTRY(_start)
1762 +SECTIONS
1763 +{
1764 + . = ALIGN(4);
1765 + .text : {
1766 + *(.text*)
1767 + } > .spl_mem
1768 +
1769 + . = ALIGN(4);
1770 + .rodata : {
1771 + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
1772 + } > .spl_mem
1773 +
1774 + . = ALIGN(4);
1775 + .data : {
1776 + *(SORT_BY_ALIGNMENT(.data*))
1777 + *(SORT_BY_ALIGNMENT(.sdata*))
1778 + } > .spl_mem
1779 +
1780 + . = ALIGN(4);
1781 + __image_copy_end = .;
1782 + uboot_end_data = .;
1783 +
1784 + .bss : {
1785 + __bss_start = .;
1786 + *(.bss*)
1787 + *(.sbss*)
1788 + . = ALIGN(4);
1789 + __bss_end = .;
1790 + } > .bss_mem
1791 +
1792 + . = ALIGN(4);
1793 + __end = .;
1794 + uboot_end = .;
1795 +}
1796 --- a/arch/mips/cpu/mips32/start.S
1797 +++ b/arch/mips/cpu/mips32/start.S
1798 @@ -105,7 +105,7 @@ reset:
1799 mtc0 zero, CP0_COUNT
1800 mtc0 zero, CP0_COMPARE
1801
1802 -#ifndef CONFIG_SKIP_LOWLEVEL_INIT
1803 +#if !defined(CONFIG_SKIP_LOWLEVEL_INIT) || defined(CONFIG_SYS_DISABLE_CACHE)
1804 /* CONFIG0 register */
1805 li t0, CONF_CM_UNCACHED
1806 mtc0 t0, CP0_CONFIG
1807 --- /dev/null
1808 +++ b/arch/mips/cpu/mips32/vrx200/Makefile
1809 @@ -0,0 +1,32 @@
1810 +#
1811 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
1812 +#
1813 +# SPDX-License-Identifier: GPL-2.0+
1814 +#
1815 +
1816 +include $(TOPDIR)/config.mk
1817 +
1818 +LIB = $(obj)lib$(SOC).o
1819 +
1820 +COBJS-y += cgu.o chipid.o dcdc.o ebu.o gphy.o mem.o pmu.o rcu.o
1821 +SOBJS-y += cgu_init.o mem_init.o
1822 +SOBJS-y += gphy_fw.o
1823 +
1824 +COBJS := $(COBJS-y)
1825 +SOBJS := $(SOBJS-y)
1826 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
1827 +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
1828 +
1829 +all: $(LIB)
1830 +
1831 +$(LIB): $(obj).depend $(OBJS)
1832 + $(call cmd_link_o_target, $(OBJS))
1833 +
1834 +#########################################################################
1835 +
1836 +# defines $(obj).depend target
1837 +include $(SRCTREE)/rules.mk
1838 +
1839 +sinclude $(obj).depend
1840 +
1841 +#########################################################################
1842 --- /dev/null
1843 +++ b/arch/mips/cpu/mips32/vrx200/cgu.c
1844 @@ -0,0 +1,208 @@
1845 +/*
1846 + * Copyright (C) 2010 Lantiq Deutschland GmbH
1847 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
1848 + *
1849 + * SPDX-License-Identifier: GPL-2.0+
1850 + */
1851 +
1852 +#include <common.h>
1853 +#include <asm/arch/soc.h>
1854 +#include <asm/arch/gphy.h>
1855 +#include <asm/lantiq/clk.h>
1856 +#include <asm/lantiq/io.h>
1857 +
1858 +#define LTQ_CGU_PLL1_PLLN_SHIFT 6
1859 +#define LTQ_CGU_PLL1_PLLN_MASK (0x3F << LTQ_CGU_PLL1_PLLN_SHIFT)
1860 +#define LTQ_CGU_PLL1_PLLM_SHIFT 2
1861 +#define LTQ_CGU_PLL1_PLLM_MASK (0xF << LTQ_CGU_PLL1_PLLM_SHIFT)
1862 +#define LTQ_CGU_PLL1_PLLL (1 << 1)
1863 +#define LTQ_CGU_PLL1_PLL_EN 1
1864 +
1865 +#define LTQ_CGU_SYS_OCP_SHIFT 0
1866 +#define LTQ_CGU_SYS_OCP_MASK (0x3 << LTQ_CGU_SYS_OCP_SHIFT)
1867 +#define LTQ_CGU_SYS_CPU_SHIFT 4
1868 +#define LTQ_CGU_SYS_CPU_MASK (0xF << LTQ_CGU_SYS_CPU_SHIFT)
1869 +
1870 +#define LTQ_CGU_UPDATE 1
1871 +
1872 +#define LTQ_CGU_IFCLK_GPHY_SEL_SHIFT 2
1873 +#define LTQ_CGU_IFCLK_GPHY_SEL_MASK (0x7 << LTQ_CGU_IFCLK_GPHY_SEL_SHIFT)
1874 +
1875 +struct ltq_cgu_regs {
1876 + u32 rsvd0;
1877 + u32 pll0_cfg; /* PLL0 config */
1878 + u32 pll1_cfg; /* PLL1 config */
1879 + u32 sys; /* System clock */
1880 + u32 clk_fsr; /* Clock frequency select */
1881 + u32 clk_gsr; /* Clock gating status */
1882 + u32 clk_gcr0; /* Clock gating control 0 */
1883 + u32 clk_gcr1; /* Clock gating control 1 */
1884 + u32 update; /* CGU update control */
1885 + u32 if_clk; /* Interface clock */
1886 + u32 ddr; /* DDR memory control */
1887 + u32 ct1_sr; /* CT status 1 */
1888 + u32 ct_kval; /* CT K value */
1889 + u32 pcm_cr; /* PCM control */
1890 + u32 pci_cr; /* PCI clock control */
1891 + u32 rsvd1;
1892 + u32 gphy1_cfg; /* GPHY1 config */
1893 + u32 gphy0_cfg; /* GPHY0 config */
1894 + u32 rsvd2[6];
1895 + u32 pll2_cfg; /* PLL2 config */
1896 +};
1897 +
1898 +static struct ltq_cgu_regs *ltq_cgu_regs =
1899 + (struct ltq_cgu_regs *) CKSEG1ADDR(LTQ_CGU_BASE);
1900 +
1901 +static inline u32 ltq_cgu_sys_readl(u32 mask, u32 shift)
1902 +{
1903 + return (ltq_readl(&ltq_cgu_regs->sys) & mask) >> shift;
1904 +}
1905 +
1906 +unsigned long ltq_get_io_region_clock(void)
1907 +{
1908 + unsigned int ocp_sel;
1909 + unsigned long clk, cpu_clk;
1910 +
1911 + cpu_clk = ltq_get_cpu_clock();
1912 +
1913 + ocp_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_OCP_MASK,
1914 + LTQ_CGU_SYS_OCP_SHIFT);
1915 +
1916 + switch (ocp_sel) {
1917 + case 0:
1918 + /* OCP ratio 1 */
1919 + clk = cpu_clk;
1920 + break;
1921 + case 2:
1922 + /* OCP ratio 2 */
1923 + clk = cpu_clk / 2;
1924 + break;
1925 + case 3:
1926 + /* OCP ratio 2.5 */
1927 + clk = (cpu_clk * 2) / 5;
1928 + break;
1929 + case 4:
1930 + /* OCP ratio 3 */
1931 + clk = cpu_clk / 3;
1932 + break;
1933 + default:
1934 + clk = 0;
1935 + break;
1936 + }
1937 +
1938 + return clk;
1939 +}
1940 +
1941 +unsigned long ltq_get_cpu_clock(void)
1942 +{
1943 + unsigned int cpu_sel;
1944 + unsigned long clk;
1945 +
1946 + cpu_sel = ltq_cgu_sys_readl(LTQ_CGU_SYS_CPU_MASK,
1947 + LTQ_CGU_SYS_CPU_SHIFT);
1948 +
1949 + switch (cpu_sel) {
1950 + case 0:
1951 + clk = CLOCK_600_MHZ;
1952 + break;
1953 + case 1:
1954 + clk = CLOCK_500_MHZ;
1955 + break;
1956 + case 2:
1957 + clk = CLOCK_393_MHZ;
1958 + break;
1959 + case 3:
1960 + clk = CLOCK_333_MHZ;
1961 + break;
1962 + case 5:
1963 + case 6:
1964 + clk = CLOCK_197_MHZ;
1965 + break;
1966 + case 7:
1967 + clk = CLOCK_166_MHZ;
1968 + break;
1969 + case 4:
1970 + case 8:
1971 + case 9:
1972 + clk = CLOCK_125_MHZ;
1973 + break;
1974 + default:
1975 + clk = 0;
1976 + break;
1977 + }
1978 +
1979 + return clk;
1980 +}
1981 +
1982 +unsigned long ltq_get_bus_clock(void)
1983 +{
1984 + return ltq_get_io_region_clock();
1985 +}
1986 +
1987 +void ltq_cgu_gphy_clk_src(enum ltq_gphy_clk clk)
1988 +{
1989 + ltq_clrbits(&ltq_cgu_regs->if_clk, LTQ_CGU_IFCLK_GPHY_SEL_MASK);
1990 + ltq_setbits(&ltq_cgu_regs->if_clk, clk << LTQ_CGU_IFCLK_GPHY_SEL_SHIFT);
1991 +}
1992 +
1993 +static inline int ltq_cgu_pll1_locked(void)
1994 +{
1995 + u32 pll1_cfg = ltq_readl(&ltq_cgu_regs->pll1_cfg);
1996 +
1997 + return pll1_cfg & LTQ_CGU_PLL1_PLLL;
1998 +}
1999 +
2000 +static inline void ltq_cgu_pll1_restart(unsigned m, unsigned n)
2001 +{
2002 + u32 pll1_cfg;
2003 +
2004 + ltq_clrbits(&ltq_cgu_regs->pll1_cfg, LTQ_CGU_PLL1_PLL_EN);
2005 + ltq_setbits(&ltq_cgu_regs->update, LTQ_CGU_UPDATE);
2006 +
2007 + pll1_cfg = ltq_readl(&ltq_cgu_regs->pll1_cfg);
2008 + pll1_cfg &= ~(LTQ_CGU_PLL1_PLLN_MASK | LTQ_CGU_PLL1_PLLM_MASK);
2009 + pll1_cfg |= n << LTQ_CGU_PLL1_PLLN_SHIFT;
2010 + pll1_cfg |= m << LTQ_CGU_PLL1_PLLM_SHIFT;
2011 + pll1_cfg |= LTQ_CGU_PLL1_PLL_EN;
2012 + ltq_writel(&ltq_cgu_regs->pll1_cfg, pll1_cfg);
2013 + ltq_setbits(&ltq_cgu_regs->update, LTQ_CGU_UPDATE);
2014 +
2015 + __udelay(1000);
2016 +}
2017 +
2018 +/*
2019 + * From chapter 9 in errata sheet:
2020 + *
2021 + * Under certain condition, the PLL1 may failed to enter into lock
2022 + * status by hardware default N, M setting.
2023 + *
2024 + * Since system always starts from PLL0, the system software can run
2025 + * and re-program the PLL1 settings.
2026 + */
2027 +static void ltq_cgu_pll1_init(void)
2028 +{
2029 + unsigned i;
2030 + const unsigned pll1_m[] = { 1, 2, 3, 4 };
2031 + const unsigned pll1_n[] = { 21, 32, 43, 54 };
2032 +
2033 + /* Check if PLL1 has locked with hardware default settings */
2034 + if (ltq_cgu_pll1_locked())
2035 + return;
2036 +
2037 + for (i = 0; i < 4; i++) {
2038 + ltq_cgu_pll1_restart(pll1_m[i], pll1_n[i]);
2039 +
2040 + if (ltq_cgu_pll1_locked())
2041 + goto done;
2042 + }
2043 +
2044 +done:
2045 + /* Restart with hardware default values M=5, N=64 */
2046 + ltq_cgu_pll1_restart(5, 64);
2047 +}
2048 +
2049 +void ltq_pll_init(void)
2050 +{
2051 + ltq_cgu_pll1_init();
2052 +}
2053 --- /dev/null
2054 +++ b/arch/mips/cpu/mips32/vrx200/cgu_init.S
2055 @@ -0,0 +1,119 @@
2056 +/*
2057 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2058 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2059 + *
2060 + * SPDX-License-Identifier: GPL-2.0+
2061 + */
2062 +
2063 +#include <config.h>
2064 +#include <asm/asm.h>
2065 +#include <asm/regdef.h>
2066 +#include <asm/addrspace.h>
2067 +#include <asm/arch/soc.h>
2068 +
2069 +/* RCU module register */
2070 +#define LTQ_RCU_RST_REQ 0x0010 /* Reset request */
2071 +#define LTQ_RCU_RST_REQ_VALUE ((1 << 14) | (1 << 1))
2072 +
2073 +/* CGU module register */
2074 +#define LTQ_CGU_PLL0_CFG 0x0004 /* PLL0 config */
2075 +#define LTQ_CGU_PLL1_CFG 0x0008 /* PLL1 config */
2076 +#define LTQ_CGU_PLL2_CFG 0x0060 /* PLL2 config */
2077 +#define LTQ_CGU_SYS 0x000C /* System clock */
2078 +#define LTQ_CGU_CLK_FSR 0x0010 /* Clock frequency select */
2079 +#define LTQ_CGU_UPDATE 0x0020 /* Clock update control */
2080 +
2081 +/* Valid SYS.CPU values */
2082 +#define LTQ_CGU_SYS_CPU_SHIFT 4
2083 +#define LTQ_CGU_SYS_CPU_600_MHZ 0x0
2084 +#define LTQ_CGU_SYS_CPU_500_MHZ 0x1
2085 +#define LTQ_CGU_SYS_CPU_393_MHZ 0x2
2086 +#define LTQ_CGU_SYS_CPU_333_MHZ 0x3
2087 +#define LTQ_CGU_SYS_CPU_197_MHZ 0x5
2088 +#define LTQ_CGU_SYS_CPU_166_MHZ 0x7
2089 +#define LTQ_CGU_SYS_CPU_125_MHZ 0x9
2090 +
2091 +/* Valid SYS.OCP values */
2092 +#define LTQ_CGU_SYS_OCP_SHIFT 0
2093 +#define LTQ_CGU_SYS_OCP_1 0x0
2094 +#define LTQ_CGU_SYS_OCP_2 0x2
2095 +#define LTQ_CGU_SYS_OCP_2_5 0x3
2096 +#define LTQ_CGU_SYS_OCP_3 0x4
2097 +
2098 +/* Valid CLK_FSR.ETH values */
2099 +#define LTQ_CGU_CLK_FSR_ETH_SHIFT 24
2100 +#define LTQ_CGU_CLK_FSR_ETH_50_MHZ 0x0
2101 +#define LTQ_CGU_CLK_FSR_ETH_25_MHZ 0x1
2102 +#define LTQ_CGU_CLK_FSR_ETH_2_5_MHZ 0x2
2103 +#define LTQ_CGU_CLK_FSR_ETH_125_MHZ 0x3
2104 +
2105 +/* Valid CLK_FSR.PPE values */
2106 +#define LTQ_CGU_CLK_FSR_PPE_SHIFT 16
2107 +#define LTQ_CGU_CLK_FSR_PPE_500_MHZ 0x0 /* Overclock frequency */
2108 +#define LTQ_CGU_CLK_FSR_PPE_450_MHZ 0x1 /* High frequency */
2109 +#define LTQ_CGU_CLK_FSR_PPE_400_MHZ 0x2 /* Low frequency */
2110 +
2111 +#if (CONFIG_SYS_CLOCK_MODE == LTQ_CLK_CPU_500_DDR_250)
2112 +#define LTQ_CGU_SYS_CPU_CONFIG LTQ_CGU_SYS_CPU_500_MHZ
2113 +#define LTQ_CGU_SYS_OCP_CONFIG LTQ_CGU_SYS_OCP_2
2114 +#define LTQ_CGU_CLK_FSR_ETH_CONFIG LTQ_CGU_CLK_FSR_ETH_125_MHZ
2115 +#define LTQ_CGU_CLK_FSR_PPE_CONFIG LTQ_CGU_CLK_FSR_PPE_450_MHZ
2116 +#else
2117 +#error "Invalid system clock configuration!"
2118 +#endif
2119 +
2120 +/* Build register values */
2121 +#define LTQ_CGU_SYS_VALUE ((LTQ_CGU_SYS_CPU_CONFIG << \
2122 + LTQ_CGU_SYS_CPU_SHIFT) | \
2123 + LTQ_CGU_SYS_OCP_CONFIG)
2124 +
2125 +#define LTQ_CGU_CLK_FSR_VALUE ((LTQ_CGU_CLK_FSR_ETH_CONFIG << \
2126 + LTQ_CGU_CLK_FSR_ETH_SHIFT) | \
2127 + (LTQ_CGU_CLK_FSR_PPE_CONFIG << \
2128 + LTQ_CGU_CLK_FSR_PPE_SHIFT))
2129 +
2130 + .set noreorder
2131 +
2132 +LEAF(ltq_cgu_init)
2133 + /* Load current CGU register values */
2134 + li t0, (LTQ_CGU_BASE | KSEG1)
2135 + lw t1, LTQ_CGU_SYS(t0)
2136 + lw t2, LTQ_CGU_CLK_FSR(t0)
2137 +
2138 + /* Load target CGU register values */
2139 + li t3, LTQ_CGU_SYS_VALUE
2140 + li t4, LTQ_CGU_CLK_FSR_VALUE
2141 +
2142 + /* Only update registers if values differ */
2143 + bne t1, t3, update
2144 + nop
2145 + beq t2, t4, finished
2146 + nop
2147 +
2148 +update:
2149 + /* Store target register values */
2150 + sw t3, LTQ_CGU_SYS(t0)
2151 + sw t4, LTQ_CGU_CLK_FSR(t0)
2152 +
2153 + /* Perform software reset to activate new clock config */
2154 +#if 0
2155 + li t0, (LTQ_RCU_BASE | KSEG1)
2156 + lw t1, LTQ_RCU_RST_REQ(t0)
2157 + or t1, LTQ_RCU_RST_REQ_VALUE
2158 + sw t1, LTQ_RCU_RST_REQ(t0)
2159 +#else
2160 + li t1, 1
2161 + sw t1, LTQ_CGU_UPDATE(t0)
2162 +#endif
2163 +
2164 +#if 0
2165 +wait_reset:
2166 + b wait_reset
2167 + nop
2168 +#endif
2169 +
2170 +finished:
2171 + jr ra
2172 + nop
2173 +
2174 + END(ltq_cgu_init)
2175 --- /dev/null
2176 +++ b/arch/mips/cpu/mips32/vrx200/chipid.c
2177 @@ -0,0 +1,62 @@
2178 +/*
2179 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2180 + *
2181 + * SPDX-License-Identifier: GPL-2.0+
2182 + */
2183 +
2184 +#include <common.h>
2185 +#include <asm/lantiq/io.h>
2186 +#include <asm/lantiq/chipid.h>
2187 +#include <asm/arch/soc.h>
2188 +
2189 +#define LTQ_CHIPID_VERSION_SHIFT 28
2190 +#define LTQ_CHIPID_VERSION_MASK (0x7 << LTQ_CHIPID_VERSION_SHIFT)
2191 +#define LTQ_CHIPID_PNUM_SHIFT 12
2192 +#define LTQ_CHIPID_PNUM_MASK (0xFFFF << LTQ_CHIPID_PNUM_SHIFT)
2193 +
2194 +struct ltq_chipid_regs {
2195 + u32 manid; /* Manufacturer identification */
2196 + u32 chipid; /* Chip identification */
2197 +};
2198 +
2199 +static struct ltq_chipid_regs *ltq_chipid_regs =
2200 + (struct ltq_chipid_regs *) CKSEG1ADDR(LTQ_CHIPID_BASE);
2201 +
2202 +unsigned int ltq_chip_version_get(void)
2203 +{
2204 + u32 chipid;
2205 +
2206 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
2207 +
2208 + return (chipid & LTQ_CHIPID_VERSION_MASK) >> LTQ_CHIPID_VERSION_SHIFT;
2209 +}
2210 +
2211 +unsigned int ltq_chip_partnum_get(void)
2212 +{
2213 + u32 chipid;
2214 +
2215 + chipid = ltq_readl(&ltq_chipid_regs->chipid);
2216 +
2217 + return (chipid & LTQ_CHIPID_PNUM_MASK) >> LTQ_CHIPID_PNUM_SHIFT;
2218 +}
2219 +
2220 +const char *ltq_chip_partnum_str(void)
2221 +{
2222 + enum ltq_chip_partnum partnum = ltq_chip_partnum_get();
2223 +
2224 + switch (partnum) {
2225 + case LTQ_SOC_VRX268:
2226 + case LTQ_SOC_VRX268_2:
2227 + return "VRX268";
2228 + case LTQ_SOC_VRX288:
2229 + case LTQ_SOC_VRX288_2:
2230 + return "VRX288";
2231 + case LTQ_SOC_GRX288:
2232 + case LTQ_SOC_GRX288_2:
2233 + return "GRX288";
2234 + default:
2235 + printf("Unknown partnum: %x\n", partnum);
2236 + }
2237 +
2238 + return "";
2239 +}
2240 --- /dev/null
2241 +++ b/arch/mips/cpu/mips32/vrx200/config.mk
2242 @@ -0,0 +1,30 @@
2243 +#
2244 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2245 +#
2246 +# SPDX-License-Identifier: GPL-2.0+
2247 +#
2248 +
2249 +PF_CPPFLAGS_XRX := $(call cc-option,-mtune=34kc,)
2250 +PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_XRX)
2251 +
2252 +ifdef CONFIG_SPL_BUILD
2253 +PF_ABICALLS := -mno-abicalls
2254 +PF_PIC := -fno-pic
2255 +PF_PIE :=
2256 +USE_PRIVATE_LIBGCC := yes
2257 +endif
2258 +
2259 +LIBS-y += $(CPUDIR)/lantiq-common/liblantiq-common.o
2260 +
2261 +ifndef CONFIG_SPL_BUILD
2262 +ifdef CONFIG_SYS_BOOT_SFSPL
2263 +ALL-y += $(obj)u-boot.ltq.sfspl
2264 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.sfspl
2265 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.sfspl
2266 +endif
2267 +ifdef CONFIG_SYS_BOOT_NORSPL
2268 +ALL-y += $(obj)u-boot.ltq.norspl
2269 +ALL-$(CONFIG_SPL_LZO_SUPPORT) += $(obj)u-boot.ltq.lzo.norspl
2270 +ALL-$(CONFIG_SPL_LZMA_SUPPORT) += $(obj)u-boot.ltq.lzma.norspl
2271 +endif
2272 +endif
2273 --- /dev/null
2274 +++ b/arch/mips/cpu/mips32/vrx200/dcdc.c
2275 @@ -0,0 +1,106 @@
2276 +/*
2277 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2278 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2279 + *
2280 + * SPDX-License-Identifier: GPL-2.0+
2281 + */
2282 +
2283 +#include <common.h>
2284 +#include <asm/arch/soc.h>
2285 +#include <asm/lantiq/io.h>
2286 +
2287 +#define LTQ_DCDC_CLK_SET0_CLK_SEL_P (1 << 6)
2288 +#define LTQ_DCDC_CLK_SET1_SEL_DIV25 (1 << 5)
2289 +#define LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE (1 << 5)
2290 +
2291 +struct ltq_dcdc_regs {
2292 + u8 b0_coeh; /* Coefficient b0 */
2293 + u8 b0_coel; /* Coefficient b0 */
2294 + u8 b1_coeh; /* Coefficient b1 */
2295 + u8 b1_coel; /* Coefficient b1 */
2296 + u8 b2_coeh; /* Coefficient b2 */
2297 + u8 b2_coel; /* Coefficient b2 */
2298 + u8 clk_set0; /* Clock setup */
2299 + u8 clk_set1; /* Clock setup */
2300 + u8 pwm_confh; /* Configure PWM */
2301 + u8 pwm_confl; /* Configure PWM */
2302 + u8 bias_vreg0; /* Bias and regulator setup */
2303 + u8 bias_vreg1; /* Bias and regulator setup */
2304 + u8 adc_gen0; /* ADC and general control */
2305 + u8 adc_gen1; /* ADC and general control */
2306 + u8 adc_con0; /* ADC and general config */
2307 + u8 adc_con1; /* ADC and general config */
2308 + u8 conf_test_ana; /* not documented */
2309 + u8 conf_test_dig; /* not documented */
2310 + u8 dcdc_status; /* not documented */
2311 + u8 pid_status; /* not documented */
2312 + u8 duty_cycle; /* not documented */
2313 + u8 non_ov_delay; /* not documented */
2314 + u8 analog_gain; /* not documented */
2315 + u8 duty_cycle_max_sat; /* not documented */
2316 + u8 duty_cycle_min_sat; /* not documented */
2317 + u8 duty_cycle_max; /* not documented */
2318 + u8 duty_cycle_min; /* not documented */
2319 + u8 error_max; /* not documented */
2320 + u8 error_read; /* not documented */
2321 + u8 delay_deglitch; /* not documented */
2322 + u8 latch_control; /* not documented */
2323 + u8 rsvd[240];
2324 + u8 osc_conf; /* OSC general config */
2325 + u8 osc_stat; /* OSC general status */
2326 +};
2327 +
2328 +static struct ltq_dcdc_regs *ltq_dcdc_regs =
2329 + (struct ltq_dcdc_regs *) CKSEG1ADDR(LTQ_DCDC_BASE);
2330 +
2331 +void ltq_dcdc_init(unsigned int dig_ref)
2332 +{
2333 + u8 dig_ref_cur, val;
2334 +
2335 + /* Set duty cycle max sat. to 70/90, enable PID freeze */
2336 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_max_sat, 0x5A);
2337 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_min_sat, 0x46);
2338 + val = ltq_readb(&ltq_dcdc_regs->conf_test_dig);
2339 + val |= LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE;
2340 + ltq_writeb(&ltq_dcdc_regs->conf_test_dig, val);
2341 +
2342 + /* Program new coefficients */
2343 + ltq_writeb(&ltq_dcdc_regs->b0_coeh, 0x00);
2344 + ltq_writeb(&ltq_dcdc_regs->b0_coel, 0x00);
2345 + ltq_writeb(&ltq_dcdc_regs->b1_coeh, 0xFF);
2346 + ltq_writeb(&ltq_dcdc_regs->b1_coel, 0xE6);
2347 + ltq_writeb(&ltq_dcdc_regs->b2_coeh, 0x00);
2348 + ltq_writeb(&ltq_dcdc_regs->b2_coel, 0x1B);
2349 + ltq_writeb(&ltq_dcdc_regs->non_ov_delay, 0x8B);
2350 +
2351 + /* Set duty cycle max sat. to 60/108, disable PID freeze */
2352 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_max_sat, 0x6C);
2353 + ltq_writeb(&ltq_dcdc_regs->duty_cycle_min_sat, 0x3C);
2354 + val = ltq_readb(&ltq_dcdc_regs->conf_test_dig);
2355 + val &= ~LTQ_DCDC_CONF_TEST_DIG_PID_FREEZE;
2356 + ltq_writeb(&ltq_dcdc_regs->conf_test_dig, val);
2357 +
2358 + /* Init clock and DLL settings */
2359 + val = ltq_readb(&ltq_dcdc_regs->clk_set0);
2360 + val |= LTQ_DCDC_CLK_SET0_CLK_SEL_P;
2361 + ltq_writeb(&ltq_dcdc_regs->clk_set0, val);
2362 + val = ltq_readb(&ltq_dcdc_regs->clk_set1);
2363 + val |= LTQ_DCDC_CLK_SET1_SEL_DIV25;
2364 + ltq_writeb(&ltq_dcdc_regs->clk_set1, val);
2365 + ltq_writeb(&ltq_dcdc_regs->pwm_confh, 0xF9);
2366 +
2367 + wmb();
2368 +
2369 + /* Adapt value of digital reference of DCDC converter */
2370 + dig_ref_cur = ltq_readb(&ltq_dcdc_regs->bias_vreg1);
2371 +
2372 + while (dig_ref_cur != dig_ref) {
2373 + if (dig_ref >= dig_ref_cur)
2374 + dig_ref_cur++;
2375 + else if (dig_ref < dig_ref_cur)
2376 + dig_ref_cur--;
2377 +
2378 + ltq_writeb(&ltq_dcdc_regs->bias_vreg1, dig_ref_cur);
2379 + __udelay(1000);
2380 + }
2381 +}
2382 --- /dev/null
2383 +++ b/arch/mips/cpu/mips32/vrx200/ebu.c
2384 @@ -0,0 +1,126 @@
2385 +/*
2386 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2387 + *
2388 + * SPDX-License-Identifier: GPL-2.0+
2389 + */
2390 +
2391 +#include <common.h>
2392 +#include <asm/arch/soc.h>
2393 +#include <asm/lantiq/io.h>
2394 +
2395 +#define EBU_ADDRSEL_MASK(mask) ((mask & 0xf) << 4)
2396 +#define EBU_ADDRSEL_REGEN (1 << 0)
2397 +
2398 +#define EBU_CON_WRDIS (1 << 31)
2399 +#define EBU_CON_AGEN_DEMUX (0x0 << 24)
2400 +#define EBU_CON_AGEN_MUX (0x2 << 24)
2401 +#define EBU_CON_SETUP (1 << 22)
2402 +#define EBU_CON_WAIT_DIS (0x0 << 20)
2403 +#define EBU_CON_WAIT_ASYNC (0x1 << 20)
2404 +#define EBU_CON_WAIT_SYNC (0x2 << 20)
2405 +#define EBU_CON_WINV (1 << 19)
2406 +#define EBU_CON_PW_8BIT (0x0 << 16)
2407 +#define EBU_CON_PW_16BIT (0x1 << 16)
2408 +#define EBU_CON_ALEC(cycles) ((cycles & 0x3) << 14)
2409 +#define EBU_CON_BCGEN_CS (0x0 << 12)
2410 +#define EBU_CON_BCGEN_INTEL (0x1 << 12)
2411 +#define EBU_CON_BCGEN_MOTOROLA (0x2 << 12)
2412 +#define EBU_CON_WAITWRC(cycles) ((cycles & 0x7) << 8)
2413 +#define EBU_CON_WAITRDC(cycles) ((cycles & 0x3) << 6)
2414 +#define EBU_CON_HOLDC(cycles) ((cycles & 0x3) << 4)
2415 +#define EBU_CON_RECOVC(cycles) ((cycles & 0x3) << 2)
2416 +#define EBU_CON_CMULT_1 0x0
2417 +#define EBU_CON_CMULT_4 0x1
2418 +#define EBU_CON_CMULT_8 0x2
2419 +#define EBU_CON_CMULT_16 0x3
2420 +
2421 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
2422 +#define ebu_region0_enable 1
2423 +#else
2424 +#define ebu_region0_enable 0
2425 +#endif
2426 +
2427 +#if ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )
2428 +#define ebu_region0_addrsel_mask 3
2429 +#else
2430 +#define ebu_region0_addrsel_mask 1
2431 +#endif
2432 +
2433 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH) || ((CONFIG_SYS_MAX_FLASH_BANKS == 2) && defined(CONFIG_LTQ_SUPPORT_NOR_FLASH) )
2434 +#define ebu_region1_enable 1
2435 +#else
2436 +#define ebu_region1_enable 0
2437 +#endif
2438 +
2439 +struct ltq_ebu_regs {
2440 + u32 clc;
2441 + u32 rsvd0;
2442 + u32 id;
2443 + u32 rsvd1;
2444 + u32 con;
2445 + u32 rsvd2[3];
2446 + u32 addr_sel_0;
2447 + u32 addr_sel_1;
2448 + u32 addr_sel_2;
2449 + u32 addr_sel_3;
2450 + u32 rsvd3[12];
2451 + u32 con_0;
2452 + u32 con_1;
2453 + u32 con_2;
2454 + u32 con_3;
2455 +};
2456 +
2457 +static struct ltq_ebu_regs *ltq_ebu_regs =
2458 + (struct ltq_ebu_regs *) CKSEG1ADDR(LTQ_EBU_BASE);
2459 +
2460 +void ltq_ebu_init(void)
2461 +{
2462 + if (ebu_region0_enable) {
2463 + /*
2464 + * Map EBU region 0 to range 0x10000000-0x13ffffff and enable
2465 + * region control. This supports up to 32 MiB NOR flash in
2466 + * bank 0.
2467 + */
2468 + ltq_writel(&ltq_ebu_regs->addr_sel_0, LTQ_EBU_REGION0_BASE |
2469 + EBU_ADDRSEL_MASK(ebu_region0_addrsel_mask) | EBU_ADDRSEL_REGEN);
2470 +
2471 + ltq_writel(&ltq_ebu_regs->con_0, EBU_CON_AGEN_DEMUX |
2472 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
2473 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
2474 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
2475 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
2476 + EBU_CON_CMULT_16);
2477 + } else
2478 + ltq_clrbits(&ltq_ebu_regs->addr_sel_0, EBU_ADDRSEL_REGEN);
2479 +
2480 + if (ebu_region1_enable) {
2481 + /*
2482 + * Map EBU region 1 to range 0x14000000-0x13ffffff and enable
2483 + * region control. This supports NAND flash in bank 1. (and NOR flash in bank 2)
2484 + */
2485 + ltq_writel(&ltq_ebu_regs->addr_sel_1, LTQ_EBU_REGION1_BASE |
2486 + EBU_ADDRSEL_MASK(3) | EBU_ADDRSEL_REGEN);
2487 +
2488 + if (ebu_region0_addrsel_mask == 1)
2489 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
2490 + EBU_CON_SETUP | EBU_CON_WAIT_DIS | EBU_CON_PW_8BIT |
2491 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
2492 + EBU_CON_WAITWRC(2) | EBU_CON_WAITRDC(2) |
2493 + EBU_CON_HOLDC(1) | EBU_CON_RECOVC(1) |
2494 + EBU_CON_CMULT_4);
2495 +
2496 + if (ebu_region0_addrsel_mask == 3)
2497 + ltq_writel(&ltq_ebu_regs->con_1, EBU_CON_AGEN_DEMUX |
2498 + EBU_CON_WAIT_DIS | EBU_CON_PW_16BIT |
2499 + EBU_CON_ALEC(3) | EBU_CON_BCGEN_INTEL |
2500 + EBU_CON_WAITWRC(7) | EBU_CON_WAITRDC(3) |
2501 + EBU_CON_HOLDC(3) | EBU_CON_RECOVC(3) |
2502 + EBU_CON_CMULT_16);
2503 + } else
2504 + ltq_clrbits(&ltq_ebu_regs->addr_sel_1, EBU_ADDRSEL_REGEN);
2505 +}
2506 +
2507 +void *flash_swap_addr(unsigned long addr)
2508 +{
2509 + return (void *)(addr ^ 2);
2510 +}
2511 --- /dev/null
2512 +++ b/arch/mips/cpu/mips32/vrx200/gphy.c
2513 @@ -0,0 +1,58 @@
2514 +/*
2515 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2516 + *
2517 + * SPDX-License-Identifier: GPL-2.0+
2518 + */
2519 +
2520 +#include <common.h>
2521 +#include <asm/lantiq/io.h>
2522 +#include <asm/arch/soc.h>
2523 +#include <asm/arch/gphy.h>
2524 +
2525 +static inline void ltq_gphy_copy(const void *fw_start, const void *fw_end,
2526 + ulong dst_addr)
2527 +{
2528 + const ulong fw_len = (ulong) fw_end - (ulong) fw_start;
2529 + const ulong addr = CKSEG1ADDR(dst_addr);
2530 +
2531 + debug("ltq_gphy_copy: addr %08lx, fw_start %p, fw_end %p\n",
2532 + addr, fw_start, fw_end);
2533 +
2534 + memcpy((void *) addr, fw_start, fw_len);
2535 +}
2536 +
2537 +void ltq_gphy_phy11g_a1x_load(ulong addr)
2538 +{
2539 + extern ulong __ltq_fw_phy11g_a1x_start;
2540 + extern ulong __ltq_fw_phy11g_a1x_end;
2541 +
2542 + ltq_gphy_copy(&__ltq_fw_phy11g_a1x_start, &__ltq_fw_phy11g_a1x_end,
2543 + addr);
2544 +}
2545 +
2546 +void ltq_gphy_phy11g_a2x_load(ulong addr)
2547 +{
2548 + extern ulong __ltq_fw_phy11g_a2x_start;
2549 + extern ulong __ltq_fw_phy11g_a2x_end;
2550 +
2551 + ltq_gphy_copy(&__ltq_fw_phy11g_a2x_start, &__ltq_fw_phy11g_a2x_end,
2552 + addr);
2553 +}
2554 +
2555 +void ltq_gphy_phy22f_a1x_load(ulong addr)
2556 +{
2557 + extern ulong __ltq_fw_phy22f_a1x_start;
2558 + extern ulong __ltq_fw_phy22f_a1x_end;
2559 +
2560 + ltq_gphy_copy(&__ltq_fw_phy22f_a1x_start, &__ltq_fw_phy22f_a1x_end,
2561 + addr);
2562 +}
2563 +
2564 +void ltq_gphy_phy22f_a2x_load(ulong addr)
2565 +{
2566 + extern ulong __ltq_fw_phy22f_a2x_start;
2567 + extern ulong __ltq_fw_phy22f_a2x_end;
2568 +
2569 + ltq_gphy_copy(&__ltq_fw_phy22f_a2x_start, &__ltq_fw_phy22f_a2x_end,
2570 + addr);
2571 +}
2572 --- /dev/null
2573 +++ b/arch/mips/cpu/mips32/vrx200/gphy_fw.S
2574 @@ -0,0 +1,27 @@
2575 +/*
2576 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2577 + *
2578 + * SPDX-License-Identifier: GPL-2.0+
2579 + */
2580 +
2581 +#include <asm/asm.h>
2582 +
2583 + .section .rodata.__ltq_fw_phy11g_a1x
2584 +EXPORT(__ltq_fw_phy11g_a1x_start)
2585 + .incbin "fw_phy11g_a1x.blob"
2586 +EXPORT(__ltq_fw_phy11g_a1x_end)
2587 +
2588 + .section .rodata.__ltq_fw_phy11g_a2x
2589 +EXPORT(__ltq_fw_phy11g_a2x_start)
2590 + .incbin "fw_phy11g_a2x.blob"
2591 +EXPORT(__ltq_fw_phy11g_a2x_end)
2592 +
2593 + .section .rodata.__ltq_fw_phy22f_a1x
2594 +EXPORT(__ltq_fw_phy22f_a1x_start)
2595 + .incbin "fw_phy22f_a1x.blob"
2596 +EXPORT(__ltq_fw_phy22f_a1x_end)
2597 +
2598 + .section .rodata.__ltq_fw_phy22f_a2x
2599 +EXPORT(__ltq_fw_phy22f_a2x_start)
2600 + .incbin "fw_phy22f_a2x.blob"
2601 +EXPORT(__ltq_fw_phy22f_a2x_end)
2602 --- /dev/null
2603 +++ b/arch/mips/cpu/mips32/vrx200/mem.c
2604 @@ -0,0 +1,57 @@
2605 +/*
2606 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2607 + *
2608 + * SPDX-License-Identifier: GPL-2.0+
2609 + */
2610 +
2611 +#include <common.h>
2612 +#include <asm/arch/soc.h>
2613 +#include <asm/lantiq/io.h>
2614 +
2615 +#define LTQ_CCR03_EIGHT_BANK_MODE (1 << 0)
2616 +#define LTQ_CCR08_CS_MAP_SHIFT 24
2617 +#define LTQ_CCR08_CS_MAP_MASK (0x3 << LTQ_CCR08_CS_MAP_SHIFT)
2618 +#define LTQ_CCR11_COLUMN_SIZE_SHIFT 24
2619 +#define LTQ_CCR11_COLUMN_SIZE_MASK (0x7 << LTQ_CCR11_COLUMN_SIZE_SHIFT)
2620 +#define LTQ_CCR11_ADDR_PINS_MASK 0x7
2621 +#define LTQ_CCR15_MAX_COL_REG_SHIFT 24
2622 +#define LTQ_CCR15_MAX_COL_REG_MASK (0xF << LTQ_CCR15_MAX_COL_REG_SHIFT)
2623 +#define LTQ_CCR16_MAX_ROW_REG_MASK 0xF
2624 +
2625 +static void *ltq_mc_ddr_base = (void *) CKSEG1ADDR(LTQ_MC_DDR_BASE);
2626 +
2627 +static inline u32 ltq_mc_ccr_read(u32 index)
2628 +{
2629 + return ltq_readl(ltq_mc_ddr_base + LTQ_MC_DDR_CCR_OFFSET(index));
2630 +}
2631 +
2632 +phys_size_t initdram(int board_type)
2633 +{
2634 + u32 max_col_reg, max_row_reg, column_size, addr_pins;
2635 + u32 banks, cs_map;
2636 + phys_size_t size;
2637 +
2638 + banks = (ltq_mc_ccr_read(3) & LTQ_CCR03_EIGHT_BANK_MODE) ? 8 : 4;
2639 +
2640 + cs_map = (ltq_mc_ccr_read(8) & LTQ_CCR08_CS_MAP_MASK) >>
2641 + LTQ_CCR08_CS_MAP_SHIFT;
2642 +
2643 + column_size = (ltq_mc_ccr_read(11) & LTQ_CCR11_COLUMN_SIZE_MASK) >>
2644 + LTQ_CCR11_COLUMN_SIZE_SHIFT;
2645 +
2646 + addr_pins = ltq_mc_ccr_read(11) & LTQ_CCR11_ADDR_PINS_MASK;
2647 +
2648 + max_col_reg = (ltq_mc_ccr_read(15) & LTQ_CCR15_MAX_COL_REG_MASK) >>
2649 + LTQ_CCR15_MAX_COL_REG_SHIFT;
2650 +
2651 + max_row_reg = ltq_mc_ccr_read(16) & LTQ_CCR16_MAX_ROW_REG_MASK;
2652 +
2653 + /*
2654 + * size (bytes) = 2 ^ rowsize * 2 ^ colsize * banks * chipselects
2655 + * * datawidth (bytes)
2656 + */
2657 + size = (2 << (max_col_reg - column_size - 1)) *
2658 + (2 << (max_row_reg - addr_pins - 1)) * banks * cs_map * 2;
2659 +
2660 + return size;
2661 +}
2662 --- /dev/null
2663 +++ b/arch/mips/cpu/mips32/vrx200/mem_init.S
2664 @@ -0,0 +1,233 @@
2665 +/*
2666 + * Copyright (C) 2010 Lantiq Deutschland GmbH
2667 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2668 + *
2669 + * SPDX-License-Identifier: GPL-2.0+
2670 + */
2671 +
2672 +#include <config.h>
2673 +#include <asm/asm.h>
2674 +#include <asm/regdef.h>
2675 +#include <asm/addrspace.h>
2676 +#include <asm/arch/soc.h>
2677 +
2678 +/* Must be configured in BOARDDIR */
2679 +#include <ddr_settings.h>
2680 +
2681 +#define LTQ_MC_DDR_START (1 << 8)
2682 +#define LTQ_MC_DDR_DLL_LOCK_IND 1
2683 +
2684 +#define CCS_ALWAYS_LAST 0x0430
2685 +#define CCS_AHBM_CR_BURST_EN (1 << 2)
2686 +#define CCS_FPIM_CR_BURST_EN (1 << 1)
2687 +
2688 +#define CCR03_EIGHT_BANK_MODE (1 << 0)
2689 +
2690 + /* Store given value in MC DDR CCRx register */
2691 + .macro ccr_sw num, val
2692 + li t1, \val
2693 + sw t1, LTQ_MC_DDR_CCR_OFFSET(\num)(t0)
2694 + .endm
2695 +
2696 +LEAF(ltq_mem_init)
2697 + /* Load MC DDR module base */
2698 + li t0, (LTQ_MC_DDR_BASE | KSEG1)
2699 +
2700 + /* Put memory controller in inactive mode */
2701 + sw zero, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2702 +
2703 + /* Init MC DDR CCR registers with values from ddr_settings.h */
2704 + ccr_sw 0, MC_CCR00_VALUE
2705 + ccr_sw 1, MC_CCR01_VALUE
2706 + ccr_sw 2, MC_CCR02_VALUE
2707 + ccr_sw 3, MC_CCR03_VALUE
2708 + ccr_sw 4, MC_CCR04_VALUE
2709 + ccr_sw 5, MC_CCR05_VALUE
2710 + ccr_sw 6, MC_CCR06_VALUE
2711 + ccr_sw 7, MC_CCR07_VALUE
2712 + ccr_sw 8, MC_CCR08_VALUE
2713 + ccr_sw 9, MC_CCR09_VALUE
2714 +
2715 + ccr_sw 10, MC_CCR10_VALUE
2716 + ccr_sw 11, MC_CCR11_VALUE
2717 + ccr_sw 12, MC_CCR12_VALUE
2718 + ccr_sw 13, MC_CCR13_VALUE
2719 + ccr_sw 14, MC_CCR14_VALUE
2720 + ccr_sw 15, MC_CCR15_VALUE
2721 + ccr_sw 16, MC_CCR16_VALUE
2722 + ccr_sw 17, MC_CCR17_VALUE
2723 + ccr_sw 18, MC_CCR18_VALUE
2724 + ccr_sw 19, MC_CCR19_VALUE
2725 +
2726 + ccr_sw 20, MC_CCR20_VALUE
2727 + ccr_sw 21, MC_CCR21_VALUE
2728 + ccr_sw 22, MC_CCR22_VALUE
2729 + ccr_sw 23, MC_CCR23_VALUE
2730 + ccr_sw 24, MC_CCR24_VALUE
2731 + ccr_sw 25, MC_CCR25_VALUE
2732 + ccr_sw 26, MC_CCR26_VALUE
2733 + ccr_sw 27, MC_CCR27_VALUE
2734 + ccr_sw 28, MC_CCR28_VALUE
2735 + ccr_sw 29, MC_CCR29_VALUE
2736 +
2737 + ccr_sw 30, MC_CCR30_VALUE
2738 + ccr_sw 31, MC_CCR31_VALUE
2739 + ccr_sw 32, MC_CCR32_VALUE
2740 + ccr_sw 33, MC_CCR33_VALUE
2741 + ccr_sw 34, MC_CCR34_VALUE
2742 + ccr_sw 35, MC_CCR35_VALUE
2743 + ccr_sw 36, MC_CCR36_VALUE
2744 + ccr_sw 37, MC_CCR37_VALUE
2745 + ccr_sw 38, MC_CCR38_VALUE
2746 + ccr_sw 39, MC_CCR39_VALUE
2747 +
2748 + ccr_sw 40, MC_CCR40_VALUE
2749 + ccr_sw 41, MC_CCR41_VALUE
2750 + ccr_sw 42, MC_CCR42_VALUE
2751 + ccr_sw 43, MC_CCR43_VALUE
2752 + ccr_sw 44, MC_CCR44_VALUE
2753 + ccr_sw 45, MC_CCR45_VALUE
2754 + ccr_sw 46, MC_CCR46_VALUE
2755 +
2756 + ccr_sw 52, MC_CCR52_VALUE
2757 + ccr_sw 53, MC_CCR53_VALUE
2758 + ccr_sw 54, MC_CCR54_VALUE
2759 + ccr_sw 55, MC_CCR55_VALUE
2760 + ccr_sw 56, MC_CCR56_VALUE
2761 + ccr_sw 57, MC_CCR57_VALUE
2762 + ccr_sw 58, MC_CCR58_VALUE
2763 + ccr_sw 59, MC_CCR59_VALUE
2764 +
2765 + ccr_sw 60, MC_CCR60_VALUE
2766 + ccr_sw 61, MC_CCR61_VALUE
2767 +
2768 + /* Disable bursts between FPI Master bus and XBAR bus */
2769 + li t4, (LTQ_MC_GLOBAL_BASE | KSEG1)
2770 + li t5, CCS_AHBM_CR_BURST_EN
2771 + sw t5, CCS_ALWAYS_LAST(t4)
2772 +
2773 + /* Init abort condition for DRAM probe */
2774 + move t4, zero
2775 +
2776 + /*
2777 + * Put memory controller in active mode and start initialitation
2778 + * sequence for connected DDR-SDRAM device
2779 + */
2780 +mc_start:
2781 + lw t1, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2782 + li t2, LTQ_MC_DDR_START
2783 + or t1, t1, t2
2784 + sw t1, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2785 +
2786 + /*
2787 + * Wait until DLL has locked and core is ready for data transfers.
2788 + * DLL lock indication is in register CCR47 and CCR48
2789 + */
2790 +wait_ready:
2791 + li t1, LTQ_MC_DDR_DLL_LOCK_IND
2792 + lw t2, LTQ_MC_DDR_CCR_OFFSET(47)(t0)
2793 + and t2, t2, t1
2794 + bne t1, t2, wait_ready
2795 +
2796 + lw t2, LTQ_MC_DDR_CCR_OFFSET(48)(t0)
2797 + and t2, t2, t1
2798 + bne t1, t2, wait_ready
2799 +
2800 +#ifdef CONFIG_SYS_DRAM_PROBE
2801 +dram_probe:
2802 + /* Initialization is finished after the second MC start */
2803 + bnez t4, mc_finished
2804 +
2805 + /*
2806 + * Preload register values for CCR03 and CCR11. Initial settings
2807 + * are 8-bank mode enabled, 14 use address row bits, 10 used
2808 + * column address bits.
2809 + */
2810 + li t1, CONFIG_SYS_SDRAM_BASE_UC
2811 + li t5, MC_CCR03_VALUE
2812 + li t6, MC_CCR11_VALUE
2813 + addi t4, t4, 1
2814 +
2815 + /*
2816 + * Store test values to DRAM at offsets 0 and 2^13 (bit 2 in bank select
2817 + * address BA[3]) and read back the value at offset 0. If the resulting
2818 + * value is equal to 1 we can skip to the next test. Otherwise
2819 + * the 8-bank mode does not work with the current DRAM device,
2820 + * thus we need to clear the according bit in register CCR03.
2821 + */
2822 + li t2, 1
2823 + sw t2, 0x0(t1)
2824 + li t3, (1 << 13)
2825 + add t3, t3, t1
2826 + sw zero, 0(t3)
2827 + lw t3, 0(t1)
2828 + bnez t3, row_col_test
2829 +
2830 + /* Clear CCR03.EIGHT_BANK_MODE */
2831 + li t3, ~CCR03_EIGHT_BANK_MODE
2832 + and t5, t5, t3
2833 +
2834 +row_col_test:
2835 + /*
2836 + * Store test values to DRAM at offsets 0, 2^27 (bit 13 of row address
2837 + * RA[14]) and 2^26 (bit 12 of RA[14]). The chosen test values
2838 + * represent the difference between max. row address bits (14) and used
2839 + * row address bits. Then the read back value at offset 0 indicates
2840 + * the useable row address bits with the current DRAM device. This
2841 + * value must be set in the CCR11 register.
2842 + */
2843 + sw zero, 0(t1)
2844 +
2845 + li t2, 1
2846 + li t3, (1 << 27)
2847 + add t3, t3, t1
2848 + sw t2, 0(t3)
2849 +
2850 + li t2, 2
2851 + li t3, (1 << 26)
2852 + add t3, t3, t1
2853 + sw t2, 0(t3)
2854 +
2855 + /* Update CCR11.ADDR_PINS */
2856 + lw t3, 0(t1)
2857 + add t6, t6, t3
2858 +
2859 + /*
2860 + * Store test values to DRAM at offsets 0, 2^10 (bit 9 of column address
2861 + * CA[10]) and 2^9 (bit 8 of CA[10]). The chosen test values represent
2862 + * the difference between max. column address bits (12) and used
2863 + * column address bits. Then the read back value at offset 0 indicates
2864 + * the useable column address bits with the current DRAM device. This
2865 + * value must be set in the CCR11 register.
2866 + */
2867 + sw zero, 0(t1)
2868 +
2869 + li t2, 1
2870 + li t3, (1 << 10)
2871 + add t3, t3, t1
2872 + sw t2, 0(t3)
2873 +
2874 + li t2, 2
2875 + li t3, (1 << 9)
2876 + add t3, t3, t1
2877 + sw t2, 0(t3)
2878 +
2879 + /* Update CCR11.COLUMN_SIZE */
2880 + lw t3, 0(t1)
2881 + sll t3, t3, 24
2882 + add t6, t6, t3
2883 +
2884 + /* Put memory controller in inactive mode */
2885 + sw zero, LTQ_MC_DDR_CCR_OFFSET(7)(t0)
2886 +
2887 + /* Update CCR03 and CCR11 and restart memory controller initialiation */
2888 + sw t5, LTQ_MC_DDR_CCR_OFFSET(3)(t0)
2889 + sw t6, LTQ_MC_DDR_CCR_OFFSET(11)(t0)
2890 + b mc_start
2891 +
2892 +mc_finished:
2893 +#endif /* CONFIG_SYS_DRAM_PROBE */
2894 +
2895 + jr ra
2896 +
2897 + END(ltq_mem_init)
2898 --- /dev/null
2899 +++ b/arch/mips/cpu/mips32/vrx200/pmu.c
2900 @@ -0,0 +1,130 @@
2901 +/*
2902 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
2903 + *
2904 + * SPDX-License-Identifier: GPL-2.0+
2905 + */
2906 +
2907 +#include <common.h>
2908 +#include <asm/lantiq/io.h>
2909 +#include <asm/lantiq/pm.h>
2910 +#include <asm/arch/soc.h>
2911 +
2912 +#define LTQ_PMU_PWDCR_RESERVED ((1 << 13) | (1 << 4))
2913 +
2914 +#define LTQ_PMU_PWDCR_PCIELOC_EN (1 << 31)
2915 +#define LTQ_PMU_PWDCR_GPHY (1 << 30)
2916 +#define LTQ_PMU_PWDCR_PPE_TOP (1 << 29)
2917 +#define LTQ_PMU_PWDCR_SWITCH (1 << 28)
2918 +#define LTQ_PMU_PWDCR_USB1 (1 << 27)
2919 +#define LTQ_PMU_PWDCR_USB1_PHY (1 << 26)
2920 +#define LTQ_PMU_PWDCR_TDM (1 << 25)
2921 +#define LTQ_PMU_PWDCR_PPE_DPLUS (1 << 24)
2922 +#define LTQ_PMU_PWDCR_PPE_DPLUM (1 << 23)
2923 +#define LTQ_PMU_PWDCR_PPE_EMA (1 << 22)
2924 +#define LTQ_PMU_PWDCR_PPE_TC (1 << 21)
2925 +#define LTQ_PMU_PWDCR_DEU (1 << 20)
2926 +#define LTQ_PMU_PWDCR_PPE_SLL01 (1 << 19)
2927 +#define LTQ_PMU_PWDCR_PPE_QSB (1 << 18)
2928 +#define LTQ_PMU_PWDCR_UART1 (1 << 17)
2929 +#define LTQ_PMU_PWDCR_SDIO (1 << 16)
2930 +#define LTQ_PMU_PWDCR_AHBM (1 << 15)
2931 +#define LTQ_PMU_PWDCR_FPIM (1 << 14)
2932 +#define LTQ_PMU_PWDCR_GPTC (1 << 12)
2933 +#define LTQ_PMU_PWDCR_LEDC (1 << 11)
2934 +#define LTQ_PMU_PWDCR_EBU (1 << 10)
2935 +#define LTQ_PMU_PWDCR_DSL (1 << 9)
2936 +#define LTQ_PMU_PWDCR_SPI (1 << 8)
2937 +#define LTQ_PMU_PWDCR_USIF (1 << 7)
2938 +#define LTQ_PMU_PWDCR_USB0 (1 << 6)
2939 +#define LTQ_PMU_PWDCR_DMA (1 << 5)
2940 +#define LTQ_PMU_PWDCR_DFEV1 (1 << 3)
2941 +#define LTQ_PMU_PWDCR_DFEV0 (1 << 2)
2942 +#define LTQ_PMU_PWDCR_FPIS (1 << 1)
2943 +#define LTQ_PMU_PWDCR_USB0_PHY (1 << 0)
2944 +
2945 +struct ltq_pmu_regs {
2946 + u32 rsvd0[7];
2947 + u32 pwdcr; /* Power down control */
2948 + u32 sr; /* Power down status */
2949 + u32 pwdcr1; /* Power down control 1 */
2950 + u32 sr1; /* Power down status 1 */
2951 +};
2952 +
2953 +static struct ltq_pmu_regs *ltq_pmu_regs =
2954 + (struct ltq_pmu_regs *) CKSEG1ADDR(LTQ_PMU_BASE);
2955 +
2956 +u32 ltq_pm_map(enum ltq_pm_modules module)
2957 +{
2958 + u32 val;
2959 +
2960 + switch (module) {
2961 + case LTQ_PM_CORE:
2962 + val = LTQ_PMU_PWDCR_UART1 | LTQ_PMU_PWDCR_FPIM |
2963 + LTQ_PMU_PWDCR_LEDC | LTQ_PMU_PWDCR_EBU;
2964 + break;
2965 + case LTQ_PM_DMA:
2966 + val = LTQ_PMU_PWDCR_DMA;
2967 + break;
2968 + case LTQ_PM_ETH:
2969 + val = LTQ_PMU_PWDCR_GPHY | LTQ_PMU_PWDCR_PPE_TOP |
2970 + LTQ_PMU_PWDCR_SWITCH | LTQ_PMU_PWDCR_PPE_DPLUS |
2971 + LTQ_PMU_PWDCR_PPE_DPLUM | LTQ_PMU_PWDCR_PPE_EMA |
2972 + LTQ_PMU_PWDCR_PPE_TC | LTQ_PMU_PWDCR_PPE_SLL01 |
2973 + LTQ_PMU_PWDCR_PPE_QSB;
2974 + break;
2975 + case LTQ_PM_SPI:
2976 + val = LTQ_PMU_PWDCR_SPI;
2977 + break;
2978 + default:
2979 + val = 0;
2980 + break;
2981 + }
2982 +
2983 + return val;
2984 +}
2985 +
2986 +int ltq_pm_enable(enum ltq_pm_modules module)
2987 +{
2988 + const unsigned long timeout = 1000;
2989 + unsigned long timebase;
2990 + u32 sr, val;
2991 +
2992 + val = ltq_pm_map(module);
2993 + if (unlikely(!val))
2994 + return 1;
2995 +
2996 + ltq_clrbits(&ltq_pmu_regs->pwdcr, val);
2997 +
2998 + timebase = get_timer(0);
2999 +
3000 + do {
3001 + sr = ltq_readl(&ltq_pmu_regs->sr);
3002 + if (~sr & val)
3003 + return 0;
3004 + } while (get_timer(timebase) < timeout);
3005 +
3006 + return 1;
3007 +}
3008 +
3009 +int ltq_pm_disable(enum ltq_pm_modules module)
3010 +{
3011 + u32 val;
3012 +
3013 + val = ltq_pm_map(module);
3014 + if (unlikely(!val))
3015 + return 1;
3016 +
3017 + ltq_setbits(&ltq_pmu_regs->pwdcr, val);
3018 +
3019 + return 0;
3020 +}
3021 +
3022 +void ltq_pmu_init(void)
3023 +{
3024 + u32 set, clr;
3025 +
3026 + clr = ltq_pm_map(LTQ_PM_CORE);
3027 + set = ~(LTQ_PMU_PWDCR_RESERVED | clr);
3028 +
3029 + ltq_clrsetbits(&ltq_pmu_regs->pwdcr, clr, set);
3030 +}
3031 --- /dev/null
3032 +++ b/arch/mips/cpu/mips32/vrx200/rcu.c
3033 @@ -0,0 +1,194 @@
3034 +/*
3035 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3036 + *
3037 + * SPDX-License-Identifier: GPL-2.0+
3038 + */
3039 +
3040 +#include <common.h>
3041 +#include <asm/lantiq/io.h>
3042 +#include <asm/lantiq/reset.h>
3043 +#include <asm/lantiq/cpu.h>
3044 +#include <asm/arch/soc.h>
3045 +
3046 +#define LTQ_RCU_RD_GPHY0 (1 << 31) /* GPHY0 */
3047 +#define LTQ_RCU_RD_SRST (1 << 30) /* Global SW Reset */
3048 +#define LTQ_RCU_RD_GPHY1 (1 << 29) /* GPHY1 */
3049 +#define LTQ_RCU_RD_ENMIP2 (1 << 28) /* Enable NMI of PLL2 */
3050 +#define LTQ_RCU_RD_REG25_PD (1 << 26) /* Power down 2.5V regulator */
3051 +#define LTQ_RCU_RD_ENDINIT (1 << 25) /* FPI slave bus access */
3052 +#define LTQ_RCU_RD_PPE_ATM_TC (1 << 23) /* PPE ATM TC */
3053 +#define LTQ_RCU_RD_PCIE (1 << 22) /* PCI-E core */
3054 +#define LTQ_RCU_RD_ETHSW (1 << 21) /* Ethernet switch */
3055 +#define LTQ_RCU_RD_DSP_DEN (1 << 20) /* Enable DSP JTAG */
3056 +#define LTQ_RCU_RD_TDM (1 << 19) /* TDM module interface */
3057 +#define LTQ_RCU_RD_ENMIP1 (1 << 18) /* Enable NMI of PLL1 */
3058 +#define LTQ_RCU_RD_SWBCK (1 << 17) /* Switch backward compat */
3059 +#define LTQ_RCU_RD_HSNAND (1 << 16) /* HSNAND controller */
3060 +#define LTQ_RCU_RD_ENMIP0 (1 << 15) /* Enable NMI of PLL0 */
3061 +#define LTQ_RCU_RD_MC (1 << 14) /* Memory Controller */
3062 +#define LTQ_RCU_RD_PCI (1 << 13) /* PCI core */
3063 +#define LTQ_RCU_RD_PCIE_PHY (1 << 12) /* PCI-E Phy */
3064 +#define LTQ_RCU_RD_DFE_CORE (1 << 11) /* DFE core */
3065 +#define LTQ_RCU_RD_SDIO (1 << 10) /* SDIO core */
3066 +#define LTQ_RCU_RD_DMA (1 << 9) /* DMA core */
3067 +#define LTQ_RCU_RD_PPE (1 << 8) /* PPE core */
3068 +#define LTQ_RCU_RD_DFE (1 << 7) /* DFE core */
3069 +#define LTQ_RCU_RD_AHB (1 << 6) /* AHB bus */
3070 +#define LTQ_RCU_RD_HRST_CFG (1 << 5) /* HW reset configuration */
3071 +#define LTQ_RCU_RD_USB (1 << 4) /* USB and Phy core */
3072 +#define LTQ_RCU_RD_PPE_DSP (1 << 3) /* PPE DSP interface */
3073 +#define LTQ_RCU_RD_FPI (1 << 2) /* FPI bus */
3074 +#define LTQ_RCU_RD_CPU (1 << 1) /* CPU subsystem */
3075 +#define LTQ_RCU_RD_HRST (1 << 0) /* HW reset via HRST pin */
3076 +
3077 +#define LTQ_RCU_STAT_BOOT_SHIFT 17
3078 +#define LTQ_RCU_STAT_BOOT_MASK (0xF << LTQ_RCU_STAT_BOOT_SHIFT)
3079 +#define LTQ_RCU_STAT_BOOT_H (1 << 12)
3080 +
3081 +#define LTQ_RCU_GP_STRAP_CLOCKSOURCE (1 << 15)
3082 +
3083 +struct ltq_rcu_regs {
3084 + u32 rsvd0[4];
3085 + u32 req; /* Reset request */
3086 + u32 stat; /* Reset status */
3087 + u32 usb0_cfg; /* USB0 configure */
3088 + u32 gp_strap; /* GPIO strapping */
3089 + u32 gfs_add0; /* GPHY0 firmware base addr */
3090 + u32 stat2; /* SLIC and USB reset status */
3091 + u32 pci_rdy; /* PCI boot ready */
3092 + u32 ppe_conf; /* PPE ethernet config */
3093 + u32 pcie_phy_con; /* PCIE PHY config/status */
3094 + u32 usb1_cfg; /* USB1 configure */
3095 + u32 usb_ana_cfg1a; /* USB analog config 1a */
3096 + u32 usb_ana_cfg1b; /* USB analog config 1b */
3097 + u32 rsvd1;
3098 + u32 gf_mdio_add; /* GPHY0/1 MDIO address */
3099 + u32 req2; /* SLIC and USB reset request */
3100 + u32 ahb_endian; /* AHB bus endianess */
3101 + u32 rsvd2[4];
3102 + u32 gcc; /* General CPU config */
3103 + u32 rsvd3;
3104 + u32 gfs_add1; /* GPHY1 firmware base addr */
3105 +};
3106 +
3107 +static struct ltq_rcu_regs *ltq_rcu_regs =
3108 + (struct ltq_rcu_regs *) CKSEG1ADDR(LTQ_RCU_BASE);
3109 +
3110 +u32 ltq_reset_map(enum ltq_reset_modules module)
3111 +{
3112 + u32 val;
3113 +
3114 + switch (module) {
3115 + case LTQ_RESET_CORE:
3116 + case LTQ_RESET_SOFT:
3117 + val = LTQ_RCU_RD_SRST | LTQ_RCU_RD_CPU | LTQ_RCU_RD_ENMIP2 |
3118 + LTQ_RCU_RD_GPHY1 | LTQ_RCU_RD_GPHY0;
3119 + break;
3120 + case LTQ_RESET_DMA:
3121 + val = LTQ_RCU_RD_DMA;
3122 + break;
3123 + case LTQ_RESET_ETH:
3124 + val = LTQ_RCU_RD_PPE | LTQ_RCU_RD_ETHSW;
3125 + break;
3126 + case LTQ_RESET_PHY:
3127 + val = LTQ_RCU_RD_GPHY1 | LTQ_RCU_RD_GPHY0;
3128 + break;
3129 + case LTQ_RESET_HARD:
3130 + val = LTQ_RCU_RD_HRST;
3131 + break;
3132 + default:
3133 + val = 0;
3134 + break;
3135 + }
3136 +
3137 + return val;
3138 +}
3139 +
3140 +int ltq_reset_activate(enum ltq_reset_modules module)
3141 +{
3142 + u32 val;
3143 +
3144 + val = ltq_reset_map(module);
3145 + if (unlikely(!val))
3146 + return 1;
3147 +
3148 + ltq_setbits(&ltq_rcu_regs->req, val);
3149 +
3150 + return 0;
3151 +}
3152 +
3153 +int ltq_reset_deactivate(enum ltq_reset_modules module)
3154 +{
3155 + u32 val;
3156 +
3157 + val = ltq_reset_map(module);
3158 + if (unlikely(!val))
3159 + return 1;
3160 +
3161 + ltq_clrbits(&ltq_rcu_regs->req, val);
3162 +
3163 + return 0;
3164 +}
3165 +
3166 +enum ltq_boot_select ltq_boot_select(void)
3167 +{
3168 + u32 stat;
3169 + unsigned int bootstrap;
3170 +
3171 + /*
3172 + * Boot select value is built from bits 20-17 and bit 12.
3173 + * The bit sequence is read as 4-2-1-0-3.
3174 + */
3175 + stat = ltq_readl(&ltq_rcu_regs->stat);
3176 + bootstrap = ((stat & LTQ_RCU_STAT_BOOT_H) << 4) |
3177 + ((stat & LTQ_RCU_STAT_BOOT_MASK) >> LTQ_RCU_STAT_BOOT_SHIFT);
3178 +
3179 + switch (bootstrap) {
3180 + case 0:
3181 + return BOOT_NOR_NO_BOOTROM;
3182 + case 1:
3183 + return BOOT_RGMII1;
3184 + case 2:
3185 + return BOOT_NOR;
3186 + case 4:
3187 + return BOOT_UART_NO_EEPROM;
3188 + case 6:
3189 + return BOOT_PCI;
3190 + case 8:
3191 + return BOOT_UART;
3192 + case 10:
3193 + return BOOT_SPI;
3194 + case 12:
3195 + return BOOT_NAND;
3196 + default:
3197 + return BOOT_UNKNOWN;
3198 + }
3199 +}
3200 +
3201 +void ltq_rcu_gphy_boot(unsigned int id, ulong addr)
3202 +{
3203 + u32 module;
3204 + void *gfs_add;
3205 +
3206 + switch (id) {
3207 + case 0:
3208 + module = LTQ_RCU_RD_GPHY0;
3209 + gfs_add = &ltq_rcu_regs->gfs_add0;
3210 + break;
3211 + case 1:
3212 + module = LTQ_RCU_RD_GPHY1;
3213 + gfs_add = &ltq_rcu_regs->gfs_add1;
3214 + break;
3215 + default:
3216 + BUG();
3217 + }
3218 +
3219 + /* Stop and reset GPHY */
3220 + ltq_setbits(&ltq_rcu_regs->req, module);
3221 +
3222 + /* Configure firmware and boot address */
3223 + ltq_writel(gfs_add, CPHYSADDR(addr & 0xFFFFC000));
3224 +
3225 + /* Start GPHY by releasing reset */
3226 + ltq_clrbits(&ltq_rcu_regs->req, module);
3227 +}
3228 --- /dev/null
3229 +++ b/arch/mips/include/asm/arch-danube/config.h
3230 @@ -0,0 +1,163 @@
3231 +/*
3232 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
3233 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3234 + *
3235 + * SPDX-License-Identifier: GPL-2.0+
3236 + *
3237 + * Common board configuration for Lantiq XWAY Danube family
3238 + *
3239 + * Use following defines in your board config to enable specific features
3240 + * and drivers for this SoC:
3241 + *
3242 + * CONFIG_LTQ_SUPPORT_UART
3243 + * - support the Danube ASC/UART interface and console
3244 + *
3245 + * CONFIG_LTQ_SUPPORT_NOR_FLASH
3246 + * - support a parallel NOR flash via the CFI interface in flash bank 0
3247 + *
3248 + * CONFIG_LTQ_SUPPORT_ETHERNET
3249 + * - support the Danube ETOP and MAC interface
3250 + *
3251 + * CONFIG_LTQ_SUPPORT_SPI_FLASH
3252 + * - support the Danube SPI interface and serial flash drivers
3253 + * - specific SPI flash drivers must be configured separately
3254 + */
3255 +
3256 +#ifndef __DANUBE_CONFIG_H__
3257 +#define __DANUBE_CONFIG_H__
3258 +
3259 +/* CPU and SoC type */
3260 +#define CONFIG_SOC_LANTIQ
3261 +#define CONFIG_SOC_XWAY_DANUBE
3262 +
3263 +/* Cache configuration */
3264 +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
3265 +#define CONFIG_SYS_DCACHE_SIZE (16 * 1024)
3266 +#define CONFIG_SYS_ICACHE_SIZE (16 * 1024)
3267 +#define CONFIG_SYS_CACHELINE_SIZE 32
3268 +#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
3269 +
3270 +/*
3271 + * Supported clock modes
3272 + * PLL0 clock output is 333 MHz
3273 + * PLL1 clock output is 262.144 MHz
3274 + */
3275 +#define LTQ_CLK_CPU_333_DDR_167 0 /* Base PLL0, OCP 2 */
3276 +#define LTQ_CLK_CPU_111_DDR_111 1 /* Base PLL0, OCP 1 */
3277 +
3278 +/* CPU speed */
3279 +#define CONFIG_SYS_CLOCK_MODE LTQ_CLK_CPU_333_DDR_167
3280 +#define CONFIG_SYS_MIPS_TIMER_FREQ 166666667
3281 +#define CONFIG_SYS_HZ 1000
3282 +
3283 +/* RAM */
3284 +#define CONFIG_NR_DRAM_BANKS 1
3285 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
3286 +#define CONFIG_SYS_MEMTEST_START 0x81000000
3287 +#define CONFIG_SYS_MEMTEST_END 0x82000000
3288 +#define CONFIG_SYS_LOAD_ADDR 0x81000000
3289 +#define CONFIG_SYS_INIT_SP_OFFSET 0x4000
3290 +
3291 +/* SRAM */
3292 +#define CONFIG_SYS_SRAM_BASE 0xBE1A0000
3293 +#define CONFIG_SYS_SRAM_SIZE 0x10000
3294 +
3295 +/* ASC/UART driver and console */
3296 +#define CONFIG_LANTIQ_SERIAL
3297 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3298 +
3299 +/* GPIO */
3300 +#define CONFIG_LANTIQ_GPIO
3301 +#define CONFIG_LTQ_GPIO_MAX_BANKS 2
3302 +
3303 +/* FLASH driver */
3304 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
3305 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
3306 +#define CONFIG_SYS_MAX_FLASH_SECT 256
3307 +#define CONFIG_SYS_FLASH_BASE 0xB0000000
3308 +#define CONFIG_FLASH_16BIT
3309 +#define CONFIG_SYS_FLASH_CFI
3310 +#define CONFIG_FLASH_CFI_DRIVER
3311 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
3312 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
3313 +#define CONFIG_FLASH_SHOW_PROGRESS 50
3314 +#define CONFIG_SYS_FLASH_PROTECTION
3315 +#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP
3316 +
3317 +#define CONFIG_CMD_FLASH
3318 +#else
3319 +#define CONFIG_SYS_NO_FLASH
3320 +#endif /* CONFIG_NOR_FLASH */
3321 +
3322 +#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)
3323 +#define CONFIG_LANTIQ_SPI
3324 +#define CONFIG_SPI_FLASH
3325 +
3326 +#define CONFIG_CMD_SF
3327 +#define CONFIG_CMD_SPI
3328 +#endif
3329 +
3330 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
3331 +#define CONFIG_NAND_LANTIQ
3332 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
3333 +#define CONFIG_SYS_NAND_BASE 0xB4000000
3334 +
3335 +#define CONFIG_CMD_NAND
3336 +#endif
3337 +
3338 +#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
3339 +#define CONFIG_LANTIQ_DMA
3340 +#define CONFIG_LANTIQ_DANUBE_ETOP
3341 +
3342 +#define CONFIG_PHYLIB
3343 +#define CONFIG_MII
3344 +
3345 +#define CONFIG_CMD_MII
3346 +#define CONFIG_CMD_NET
3347 +#endif
3348 +
3349 +#define CONFIG_SPL_MAX_SIZE (32 * 1024)
3350 +#define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024)
3351 +#define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024)
3352 +#define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024)
3353 +/*#define CONFIG_SPL_STACK_BSS_IN_SRAM*/
3354 +
3355 +#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)
3356 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SRAM_BASE + \
3357 + CONFIG_SPL_MAX_SIZE + \
3358 + CONFIG_SPL_STACK_MAX_SIZE - 1)
3359 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
3360 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SYS_SDRAM_BASE + \
3361 + CONFIG_SYS_INIT_SP_OFFSET)
3362 +#else
3363 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SDRAM_BASE + \
3364 + CONFIG_SYS_INIT_SP_OFFSET + \
3365 + CONFIG_SPL_STACK_MAX_SIZE - 1)
3366 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
3367 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SPL_BSS_BASE + \
3368 + CONFIG_SPL_BSS_MAX_SIZE)
3369 +#endif
3370 +
3371 +#if defined(CONFIG_SYS_BOOT_RAM)
3372 +#define CONFIG_SYS_TEXT_BASE 0xa0100000
3373 +#define CONFIG_SKIP_LOWLEVEL_INIT
3374 +#define CONFIG_SYS_DISABLE_CACHE
3375 +#endif
3376 +
3377 +#if defined(CONFIG_SYS_BOOT_NOR)
3378 +#define CONFIG_SYS_TEXT_BASE 0xB0000000
3379 +#endif
3380 +
3381 +#if defined(CONFIG_SYS_BOOT_NORSPL)
3382 +#define CONFIG_SYS_TEXT_BASE 0x80100000
3383 +#define CONFIG_SPL_TEXT_BASE 0xB0000000
3384 +#endif
3385 +
3386 +#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)
3387 +#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x688C688C
3388 +#define CONFIG_XWAY_SWAP_BYTES
3389 +#endif
3390 +
3391 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
3392 +
3393 +#endif /* __DANUBE_CONFIG_H__ */
3394 --- /dev/null
3395 +++ b/arch/mips/include/asm/arch-danube/gpio.h
3396 @@ -0,0 +1,12 @@
3397 +/*
3398 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3399 + *
3400 + * SPDX-License-Identifier: GPL-2.0+
3401 + */
3402 +
3403 +#ifndef __DANUBE_GPIO_H__
3404 +#define __DANUBE_GPIO_H__
3405 +
3406 +#include <asm/lantiq/gpio.h>
3407 +
3408 +#endif /* __DANUBE_GPIO_H__ */
3409 --- /dev/null
3410 +++ b/arch/mips/include/asm/arch-danube/nand.h
3411 @@ -0,0 +1,13 @@
3412 +/*
3413 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3414 + *
3415 + * SPDX-License-Identifier: GPL-2.0+
3416 + */
3417 +
3418 +#ifndef __DANUBE_NAND_H__
3419 +#define __DANUBE_NAND_H__
3420 +
3421 +struct nand_chip;
3422 +int ltq_nand_init(struct nand_chip *nand);
3423 +
3424 +#endif /* __DANUBE_NAND_H__ */
3425 --- /dev/null
3426 +++ b/arch/mips/include/asm/arch-danube/soc.h
3427 @@ -0,0 +1,38 @@
3428 +/*
3429 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
3430 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3431 + *
3432 + * SPDX-License-Identifier: GPL-2.0+
3433 + */
3434 +
3435 +#ifndef __DANUBE_SOC_H__
3436 +#define __DANUBE_SOC_H__
3437 +
3438 +#define LTQ_ASC0_BASE 0x1E100400
3439 +#define LTQ_SPI_BASE 0x1E100800
3440 +#define LTQ_GPIO_BASE 0x1E100B00
3441 +#define LTQ_SSIO_BASE 0x1E100BB0
3442 +#define LTQ_ASC1_BASE 0x1E100C00
3443 +#define LTQ_DMA_BASE 0x1E104100
3444 +
3445 +#define LTQ_EBU_BASE 0x1E105300
3446 +#define LTQ_EBU_REGION0_BASE 0x10000000
3447 +#define LTQ_EBU_REGION1_BASE 0x14000000
3448 +#define LTQ_EBU_NAND_BASE (LTQ_EBU_BASE + 0xB0)
3449 +
3450 +#define LTQ_PPE_BASE 0x1E180000
3451 +#define LTQ_PPE_ETOP_BASE (LTQ_PPE_BASE + 0x11800)
3452 +#define LTQ_PPE_ENET0_BASE (LTQ_PPE_BASE + 0x11840)
3453 +
3454 +#define LTQ_PMU_BASE 0x1F102000
3455 +#define LTQ_CGU_BASE 0x1F103000
3456 +#define LTQ_MPS_BASE 0x1F107000
3457 +#define LTQ_CHIPID_BASE (LTQ_MPS_BASE + 0x340)
3458 +#define LTQ_RCU_BASE 0x1F203000
3459 +
3460 +#define LTQ_MC_GEN_BASE 0x1F800000
3461 +#define LTQ_MC_SDR_BASE 0x1F800200
3462 +#define LTQ_MC_DDR_BASE 0x1F801000
3463 +#define LTQ_MC_DDR_DC_OFFSET(x) (x * 0x10)
3464 +
3465 +#endif /* __DANUBE_SOC_H__ */
3466 --- /dev/null
3467 +++ b/arch/mips/include/asm/arch-vrx200/config.h
3468 @@ -0,0 +1,187 @@
3469 +/*
3470 + * Copyright (C) 2010 Lantiq Deutschland GmbH
3471 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3472 + *
3473 + * SPDX-License-Identifier: GPL-2.0+
3474 + *
3475 + * Common board configuration for Lantiq XWAY VRX200 family
3476 + *
3477 + * Use following defines in your board config to enable specific features
3478 + * and drivers for this SoC:
3479 + *
3480 + * CONFIG_LTQ_SUPPORT_UART
3481 + * - support the VRX200 ASC/UART interface and console
3482 + *
3483 + * CONFIG_LTQ_SUPPORT_NOR_FLASH
3484 + * - support a parallel NOR flash via the CFI interface in flash bank 0
3485 + *
3486 + * CONFIG_LTQ_SUPPORT_ETHERNET
3487 + * - support the VRX200 internal switch
3488 + *
3489 + * CONFIG_LTQ_SUPPORT_SPI_FLASH
3490 + * - support the VRX200 SPI interface and serial flash drivers
3491 + * - specific SPI flash drivers must be configured separately
3492 + *
3493 + * CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH
3494 + * - build a preloader that runs in the internal SRAM and loads
3495 + * the U-Boot from SPI flash into RAM
3496 + */
3497 +
3498 +#ifndef __VRX200_CONFIG_H__
3499 +#define __VRX200_CONFIG_H__
3500 +
3501 +/* CPU and SoC type */
3502 +#define CONFIG_SOC_LANTIQ
3503 +#define CONFIG_SOC_XWAY_VRX200
3504 +
3505 +/* Cache configuration */
3506 +#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
3507 +#define CONFIG_SYS_DCACHE_SIZE (32 * 1024)
3508 +#define CONFIG_SYS_ICACHE_SIZE (32 * 1024)
3509 +#define CONFIG_SYS_CACHELINE_SIZE 32
3510 +#define CONFIG_SYS_MIPS_CACHE_EXT_INIT
3511 +
3512 +/*
3513 + * Supported clock modes
3514 + * PLL0 clock output is 1000 MHz
3515 + * PLL1 clock output is 393.219 MHz
3516 + */
3517 +#define LTQ_CLK_CPU_600_DDR_300 0 /* Base PLL0, OCP 2 */
3518 +#define LTQ_CLK_CPU_600_DDR_200 1 /* Base PLL0, OCP 3 */
3519 +#define LTQ_CLK_CPU_500_DDR_250 2 /* Base PLL0, OCP 2 */
3520 +#define LTQ_CLK_CPU_500_DDR_200 3 /* Base PLL0, OCP 2.5 */
3521 +#define LTQ_CLK_CPU_333_DDR_167 4 /* Base PLL0, OCP 2 */
3522 +#define LTQ_CLK_CPU_167_DDR_167 5 /* Base PLL0, OCP 1 */
3523 +#define LTQ_CLK_CPU_125_DDR_125 6 /* Base PLL0, OCP 1 */
3524 +#define LTQ_CLK_CPU_393_DDR_197 7 /* Base PLL1, OCP 2 */
3525 +#define LTQ_CLK_CPU_197_DDR_197 8 /* Base PLL1, OCP 1 */
3526 +
3527 +/* CPU speed */
3528 +#define CONFIG_SYS_CLOCK_MODE LTQ_CLK_CPU_500_DDR_250
3529 +#define CONFIG_SYS_MIPS_TIMER_FREQ 250000000
3530 +#define CONFIG_SYS_HZ 1000
3531 +
3532 +/* RAM */
3533 +#define CONFIG_NR_DRAM_BANKS 1
3534 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
3535 +#define CONFIG_SYS_SDRAM_BASE_UC 0xa0000000
3536 +#define CONFIG_SYS_MEMTEST_START 0x81000000
3537 +#define CONFIG_SYS_MEMTEST_END 0x82000000
3538 +#define CONFIG_SYS_LOAD_ADDR 0x81000000
3539 +#define CONFIG_SYS_INIT_SP_OFFSET (32 * 1024)
3540 +
3541 +/* SRAM */
3542 +#define CONFIG_SYS_SRAM_BASE 0xBE220000
3543 +#define CONFIG_SYS_SRAM_SIZE 0x10000
3544 +
3545 +/* ASC/UART driver and console */
3546 +#define CONFIG_LANTIQ_SERIAL
3547 +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
3548 +
3549 +/* GPIO */
3550 +#define CONFIG_LANTIQ_GPIO
3551 +#define CONFIG_LTQ_GPIO_MAX_BANKS 3
3552 +#define CONFIG_LTQ_HAS_GPIO_BANK3
3553 +
3554 +/* FLASH driver */
3555 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
3556 +#ifndef CONFIG_SYS_MAX_FLASH_BANKS
3557 +#define CONFIG_SYS_MAX_FLASH_BANKS 1
3558 +#endif
3559 +#define CONFIG_SYS_MAX_FLASH_SECT 256
3560 +#define CONFIG_SYS_FLASH_BASE 0xB0000000
3561 +#define CONFIG_SYS_FLASH2_BASE 0xB4000000
3562 +#define CONFIG_FLASH_16BIT
3563 +#define CONFIG_SYS_FLASH_CFI
3564 +#define CONFIG_FLASH_CFI_DRIVER
3565 +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
3566 +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
3567 +#define CONFIG_FLASH_SHOW_PROGRESS 50
3568 +#define CONFIG_SYS_FLASH_PROTECTION
3569 +#define CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP
3570 +
3571 +#define CONFIG_CMD_FLASH
3572 +#else
3573 +#define CONFIG_SYS_NO_FLASH
3574 +#endif /* CONFIG_NOR_FLASH */
3575 +
3576 +#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)
3577 +#define CONFIG_LANTIQ_SPI
3578 +#define CONFIG_SPI_FLASH
3579 +
3580 +#define CONFIG_CMD_SF
3581 +#define CONFIG_CMD_SPI
3582 +#endif
3583 +
3584 +#if defined(CONFIG_LTQ_SUPPORT_NAND_FLASH)
3585 +#define CONFIG_NAND_LANTIQ
3586 +#define CONFIG_SYS_MAX_NAND_DEVICE 1
3587 +#define CONFIG_SYS_NAND_BASE 0xB4000000
3588 +
3589 +#define CONFIG_CMD_NAND
3590 +#endif
3591 +
3592 +#if defined(CONFIG_LTQ_SUPPORT_ETHERNET)
3593 +#define CONFIG_LANTIQ_DMA
3594 +#define CONFIG_LANTIQ_VRX200_SWITCH
3595 +#define CONFIG_PHY_LANTIQ
3596 +
3597 +#define CONFIG_SYS_RX_ETH_BUFFER 8
3598 +#define CONFIG_PHYLIB
3599 +#define CONFIG_MII
3600 +#define CONFIG_UDP_CHECKSUM
3601 +
3602 +#define CONFIG_CMD_MII
3603 +#define CONFIG_CMD_NET
3604 +#endif
3605 +
3606 +#define CONFIG_SPL_MAX_SIZE (32 * 1024)
3607 +#define CONFIG_SPL_BSS_MAX_SIZE (8 * 1024)
3608 +#define CONFIG_SPL_STACK_MAX_SIZE (8 * 1024)
3609 +#define CONFIG_SPL_MALLOC_MAX_SIZE (32 * 1024)
3610 +#define CONFIG_SPL_STACK_BSS_IN_SRAM
3611 +
3612 +#if defined(CONFIG_SPL_STACK_BSS_IN_SRAM)
3613 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SRAM_BASE + \
3614 + CONFIG_SPL_MAX_SIZE + \
3615 + CONFIG_SPL_STACK_MAX_SIZE - 1)
3616 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
3617 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SYS_SDRAM_BASE + \
3618 + CONFIG_SYS_INIT_SP_OFFSET)
3619 +#else
3620 +#define CONFIG_SPL_STACK_BASE (CONFIG_SYS_SDRAM_BASE + \
3621 + CONFIG_SYS_INIT_SP_OFFSET + \
3622 + CONFIG_SPL_STACK_MAX_SIZE - 1)
3623 +#define CONFIG_SPL_BSS_BASE (CONFIG_SPL_STACK_BASE + 1)
3624 +#define CONFIG_SPL_MALLOC_BASE (CONFIG_SPL_BSS_BASE + \
3625 + CONFIG_SPL_BSS_MAX_SIZE)
3626 +#endif
3627 +
3628 +#if defined(CONFIG_SYS_BOOT_RAM)
3629 +#define CONFIG_SYS_TEXT_BASE 0xA0100000
3630 +#define CONFIG_SKIP_LOWLEVEL_INIT
3631 +#define CONFIG_SYS_DISABLE_CACHE
3632 +#endif
3633 +
3634 +#if defined(CONFIG_SYS_BOOT_NOR)
3635 +#define CONFIG_SYS_TEXT_BASE 0xB0000000
3636 +#endif
3637 +
3638 +#if defined(CONFIG_SYS_BOOT_SFSPL)
3639 +#define CONFIG_SYS_TEXT_BASE 0x80100000
3640 +#define CONFIG_SPL_TEXT_BASE 0xBE220000
3641 +#endif
3642 +
3643 +#if defined(CONFIG_SYS_BOOT_NORSPL)
3644 +#define CONFIG_SYS_TEXT_BASE 0x80100000
3645 +#define CONFIG_SPL_TEXT_BASE 0xB0000000
3646 +#endif
3647 +
3648 +#if defined(CONFIG_SYS_BOOT_NOR) || defined(CONFIG_SYS_BOOT_NORSPL)
3649 +#define CONFIG_SYS_XWAY_EBU_BOOTCFG 0x688C688C
3650 +#define CONFIG_XWAY_SWAP_BYTES
3651 +#endif
3652 +
3653 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
3654 +
3655 +#endif /* __VRX200_CONFIG_H__ */
3656 --- /dev/null
3657 +++ b/arch/mips/include/asm/arch-vrx200/gphy.h
3658 @@ -0,0 +1,65 @@
3659 +/*
3660 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3661 + *
3662 + * SPDX-License-Identifier: GPL-2.0+
3663 + */
3664 +
3665 +#ifndef __VRX200_GPHY_H__
3666 +#define __VRX200_GPHY_H__
3667 +
3668 +enum ltq_gphy_clk {
3669 + /* XTAL 36 MHz input */
3670 + LTQ_GPHY_CLK_36MHZ_XTAL = 1,
3671 + /* 25 MHz from PLL0 with divider */
3672 + LTQ_GPHY_CLK_25MHZ_PLL0 = 2,
3673 + /* derived from PLL2 output (XTAL is 36 MHz) */
3674 + LTQ_GPHY_CLK_24MHZ_PLL2 = 3,
3675 + /* 25 MHz Clock from Pin GPIO3 */
3676 + LTQ_GPHY_CLK_25MHZ_GPIO3 = 4,
3677 +};
3678 +
3679 +/*
3680 + * Load PHY11G firmware for VRX200 v1.1 to given RAM address
3681 + *
3682 + * Address must be 16k aligned!
3683 + */
3684 +extern void ltq_gphy_phy11g_a1x_load(ulong addr);
3685 +
3686 +/*
3687 + * Load PHY11G firmware for VRX200 v1.2 to given RAM address
3688 + *
3689 + * Address must be 16k aligned!
3690 + */
3691 +extern void ltq_gphy_phy11g_a2x_load(ulong addr);
3692 +
3693 +/*
3694 + * Load PHY22F firmware for VRX200 v1.1 to given RAM address
3695 + *
3696 + * Address must be 16k aligned!
3697 + */
3698 +extern void ltq_gphy_phy22f_a1x_load(ulong addr);
3699 +
3700 +/*
3701 + * Load PHY22F firmware for VRX200 v1.2 to given RAM address
3702 + *
3703 + * Address must be 16k aligned!
3704 + */
3705 +extern void ltq_gphy_phy22f_a2x_load(ulong addr);
3706 +
3707 +/*
3708 + * Set clock source of internal GPHYs
3709 + *
3710 + * According registers resides in CGU address space. Thus this function
3711 + * is implemented by the CGU driver.
3712 + */
3713 +extern void ltq_cgu_gphy_clk_src(enum ltq_gphy_clk clk);
3714 +
3715 +/*
3716 + * Boot internal GPHY with id from given RAM address
3717 + *
3718 + * According registers resides in RCU address space. Thus this function
3719 + * is implemented by the RCU driver.
3720 + */
3721 +extern void ltq_rcu_gphy_boot(unsigned int id, ulong addr);
3722 +
3723 +#endif /* __VRX200_GPHY_H__ */
3724 --- /dev/null
3725 +++ b/arch/mips/include/asm/arch-vrx200/gpio.h
3726 @@ -0,0 +1,12 @@
3727 +/*
3728 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3729 + *
3730 + * SPDX-License-Identifier: GPL-2.0+
3731 + */
3732 +
3733 +#ifndef __VRX200_GPIO_H__
3734 +#define __VRX200_GPIO_H__
3735 +
3736 +#include <asm/lantiq/gpio.h>
3737 +
3738 +#endif /* __VRX200_GPIO_H__ */
3739 --- /dev/null
3740 +++ b/arch/mips/include/asm/arch-vrx200/nand.h
3741 @@ -0,0 +1,13 @@
3742 +/*
3743 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3744 + *
3745 + * SPDX-License-Identifier: GPL-2.0+
3746 + */
3747 +
3748 +#ifndef __VRX200_NAND_H__
3749 +#define __VRX200_NAND_H__
3750 +
3751 +struct nand_chip;
3752 +int ltq_nand_init(struct nand_chip *nand);
3753 +
3754 +#endif /* __VRX200_NAND_H__ */
3755 --- /dev/null
3756 +++ b/arch/mips/include/asm/arch-vrx200/soc.h
3757 @@ -0,0 +1,45 @@
3758 +/*
3759 + * Copyright (C) 2010 Lantiq Deutschland GmbH
3760 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3761 + *
3762 + * SPDX-License-Identifier: GPL-2.0+
3763 + */
3764 +
3765 +#ifndef __VRX200_SOC_H__
3766 +#define __VRX200_SOC_H__
3767 +
3768 +#define LTQ_ASC0_BASE 0x1E100400
3769 +#define LTQ_SPI_BASE 0x1E100800
3770 +#define LTQ_GPIO_BASE 0x1E100B00
3771 +#define LTQ_SSIO_BASE 0x1E100BB0
3772 +#define LTQ_ASC1_BASE 0x1E100C00
3773 +#define LTQ_DMA_BASE 0x1E104100
3774 +
3775 +#define LTQ_EBU_BASE 0x1E105300
3776 +#define LTQ_EBU_REGION0_BASE 0x10000000
3777 +#define LTQ_EBU_REGION1_BASE 0x14000000
3778 +#define LTQ_EBU_NAND_BASE (LTQ_EBU_BASE + 0xB0)
3779 +
3780 +#define LTQ_SWITCH_BASE 0x1E108000
3781 +#define LTQ_SWITCH_CORE_BASE LTQ_SWITCH_BASE
3782 +#define LTQ_SWITCH_TOP_PDI_BASE LTQ_SWITCH_CORE_BASE
3783 +#define LTQ_SWITCH_BM_PDI_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x40)
3784 +#define LTQ_SWITCH_MAC_PDI_0_BASE (LTQ_SWITCH_CORE_BASE + 4 * 0x900)
3785 +#define LTQ_SWITCH_MAC_PDI_X_BASE(x) (LTQ_SWITCH_MAC_PDI_0_BASE + x * 0x30)
3786 +#define LTQ_SWITCH_TOPLEVEL_BASE (LTQ_SWITCH_BASE + 4 * 0xC40)
3787 +#define LTQ_SWITCH_MDIO_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE)
3788 +#define LTQ_SWITCH_MII_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x36)
3789 +#define LTQ_SWITCH_PMAC_PDI_BASE (LTQ_SWITCH_TOPLEVEL_BASE + 4 * 0x82)
3790 +
3791 +#define LTQ_PMU_BASE 0x1F102000
3792 +#define LTQ_CGU_BASE 0x1F103000
3793 +#define LTQ_DCDC_BASE 0x1F106A00
3794 +#define LTQ_MPS_BASE 0x1F107000
3795 +#define LTQ_CHIPID_BASE (LTQ_MPS_BASE + 0x340)
3796 +#define LTQ_RCU_BASE 0x1F203000
3797 +
3798 +#define LTQ_MC_GLOBAL_BASE 0x1F400000
3799 +#define LTQ_MC_DDR_BASE 0x1F401000
3800 +#define LTQ_MC_DDR_CCR_OFFSET(x) (x * 0x10)
3801 +
3802 +#endif /* __VRX200_SOC_H__ */
3803 --- /dev/null
3804 +++ b/arch/mips/include/asm/arch-vrx200/switch.h
3805 @@ -0,0 +1,502 @@
3806 +/*
3807 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
3808 + *
3809 + * SPDX-License-Identifier: GPL-2.0+
3810 + */
3811 +
3812 +#ifndef __VRX200_SWITCH_H__
3813 +#define __VRX200_SWITCH_H__
3814 +
3815 +/* Switch core registers */
3816 +struct vr9_switch_core_regs {
3817 + __be32 swres;
3818 + /* TODO: implement registers */
3819 + __be32 rsvd0[0x3f];
3820 +};
3821 +
3822 +/* Switch buffer management registers */
3823 +struct vr9_switch_bm_regs {
3824 + struct bm_core {
3825 + __be32 ram_val3; /* RAM value 3 */
3826 + __be32 ram_val2; /* RAM value 2 */
3827 + __be32 ram_val1; /* RAM value 1 */
3828 + __be32 ram_val0; /* RAM value 0 */
3829 + __be32 ram_addr; /* RAM address */
3830 + __be32 ram_ctrl; /* RAM access control */
3831 + __be32 fsqm_gctrl; /* Free segment queue global control */
3832 + __be32 cons_sel; /* Number of consumed segments */
3833 + __be32 cons_pkt; /* Number of consumed packet pointers */
3834 + __be32 gctrl; /* Global control */
3835 + __be32 queue_gctrl; /* Queue manager global control */
3836 + /* TODO: implement registers */
3837 + __be32 rsvd0[0x35];
3838 + } core;
3839 +
3840 + struct bm_port {
3841 + __be32 pcfg; /* Port config */
3842 + __be32 rmon_ctrl; /* RMON control */
3843 + } port[13];
3844 +
3845 + __be32 rsvd0[0x66];
3846 +
3847 + struct bm_queue {
3848 + __be32 rsvd0;
3849 + __be32 pqm_rs; /* Packet queue manager rate shape assignment */
3850 + } queue[32];
3851 +
3852 + struct bm_shaper {
3853 + __be32 ctrl; /* Rate shaper control */
3854 + __be32 cbs; /* Rate shaper committed burst size */
3855 + __be32 ibs; /* Rate shaper instantaneous burst size */
3856 + __be32 cir_ext; /* Rate shaper rate exponent */
3857 + __be32 cir_mant; /* Rate shaper rate mantissa */
3858 + } shaper[16];
3859 +
3860 + __be32 rsvd1[0x2a8];
3861 +};
3862 +
3863 +/* Switch parser and classification engine registers */
3864 +struct vr9_switch_pce_regs {
3865 + struct pce_core {
3866 + __be32 tbl_key[16]; /* Table key data */
3867 + __be32 tbl_mask; /* Table mask */
3868 + __be32 tbl_val[5]; /* Table value */
3869 + __be32 tbl_addr; /* Table entry address */
3870 + __be32 tbl_ctrl; /* Table access control */
3871 + __be32 tbl_stat; /* Table general status */
3872 + __be32 age_0; /* Aging counter config 0 */
3873 + __be32 age_1; /* Aging counter config 1 */
3874 + __be32 pmap_1; /* Port map (monitoring) */
3875 + __be32 pmap_2; /* Port map (multicast) */
3876 + __be32 pmap_3; /* Port map (unknown unicast) */
3877 + __be32 gctrl_0; /* Global control 0 */
3878 + __be32 gctrl_1; /* Global control 1 */
3879 + __be32 tcm_gctrl; /* Three-color marker global control */
3880 + __be32 igmp_ctrl; /* IGMP control */
3881 + __be32 igmp_drpm; /* IGMP default router port map */
3882 + __be32 igmp_age_0; /* IGMP aging 0 */
3883 + __be32 igmp_age_1; /* IGMP aging 1 */
3884 + __be32 igmp_stat; /* IGMP status */
3885 + __be32 wol_gctrl; /* Wake-on-LAN control */
3886 + __be32 wol_da_0; /* Wake-on-LAN destination address 0 */
3887 + __be32 wol_da_1; /* Wake-on-LAN destination address 1 */
3888 + __be32 wol_da_2; /* Wake-on-LAN destination address 2 */
3889 + __be32 wol_pw_0; /* Wake-on-LAN password 0 */
3890 + __be32 wol_pw_1; /* Wake-on-LAN password 1 */
3891 + __be32 wol_pw_2; /* Wake-on-LAN password 2 */
3892 + __be32 ier_0; /* PCE global interrupt enable 0 */
3893 + __be32 ier_1; /* PCE global interrupt enable 1 */
3894 + __be32 isr_0; /* PCE global interrupt status 0 */
3895 + __be32 isr_1; /* PCE global interrupt status 1 */
3896 + __be32 parser_stat; /* Parser status */
3897 + __be32 rsvd0[0x6];
3898 + } core;
3899 +
3900 + __be32 rsvd0[0x10];
3901 +
3902 + struct pce_port {
3903 + __be32 pctrl_0; /* Port control 0 */
3904 + __be32 pctrl_1; /* Port control 1 */
3905 + __be32 pctrl_2; /* Port control 2 */
3906 + __be32 pctrl_3; /* Port control 3 */
3907 + __be32 wol_ctrl; /* Wake-on-LAN control */
3908 + __be32 vlan_ctrl; /* VLAN control */
3909 + __be32 def_pvid; /* Default port VID */
3910 + __be32 pstat; /* Port status */
3911 + __be32 pier; /* Interrupt enable */
3912 + __be32 pisr; /* Interrupt status */
3913 + } port[13];
3914 +
3915 + __be32 rsvd1[0x7e];
3916 +
3917 + struct pce_meter {
3918 + /* TODO: implement registers */
3919 + __be32 rsvd0[0x7];
3920 + } meter[8];
3921 +
3922 + __be32 rsvd2[0x308];
3923 +};
3924 +
3925 +static inline unsigned int to_pce_tbl_key_id(unsigned int id)
3926 +{
3927 + BUG_ON(id > 15);
3928 +
3929 + return 15 - id;
3930 +}
3931 +
3932 +static inline unsigned int to_pce_tbl_value_id(unsigned int id)
3933 +{
3934 + BUG_ON(id > 4);
3935 +
3936 + return 4 - id;
3937 +}
3938 +
3939 +/* Switch ethernet MAC registers */
3940 +struct vr9_switch_mac_regs {
3941 + struct mac_core {
3942 + __be32 test; /* MAC test */
3943 + __be32 pfad_cfg; /* Pause frame source address config */
3944 + __be32 pfsa_0; /* Pause frame source address 0 */
3945 + __be32 pfsa_1; /* Pause frame source address 1 */
3946 + __be32 pfsa_2; /* Pause frame source address 2 */
3947 + __be32 flen; /* Frame length */
3948 + __be32 vlan_etype_0; /* VLAN ethertype 0 */
3949 + __be32 vlan_etype_1; /* VLAN ethertype 1 */
3950 + __be32 ier; /* Interrupt enable */
3951 + __be32 isr; /* Interrupt status */
3952 + __be32 rsvd0[0x36];
3953 + } core;
3954 +
3955 + struct mac_port {
3956 + __be32 pstat; /* Port status */
3957 + __be32 pisr; /* Interrupt status */
3958 + __be32 pier; /* Interrupt enable */
3959 + __be32 ctrl_0; /* Control 0 */
3960 + __be32 ctrl_1; /* Control 1 */
3961 + __be32 ctrl_2; /* Control 2 */
3962 + __be32 ctrl_3; /* Control 3 */
3963 + __be32 ctrl_4; /* Control 4 */
3964 + __be32 ctrl_5; /* Control 5 */
3965 + __be32 rsvd0[0x2];
3966 + __be32 testen; /* Test enable */
3967 + } port[13];
3968 +
3969 + __be32 rsvd0[0xa4];
3970 +};
3971 +
3972 +/* Switch Fetch DMA registers */
3973 +struct vr9_switch_fdma_regs {
3974 + struct fdma_core {
3975 + __be32 ctrl; /* FDMA control */
3976 + __be32 stetype; /* Special tag ethertype control */
3977 + __be32 vtetype; /* VLAN tag ethertype control */
3978 + __be32 stat; /* FDMA status */
3979 + __be32 ier; /* FDMA interrupt enable */
3980 + __be32 isr; /* FDMA interrupt status */
3981 + } core;
3982 +
3983 + __be32 rsvd0[0x3a];
3984 +
3985 + struct fdma_port {
3986 + __be32 pctrl; /* Port control */
3987 + __be32 prio; /* Port priority */
3988 + __be32 pstat_0; /* Port status 0 */
3989 + __be32 pstat_1; /* Port status 1 */
3990 + __be32 tstamp_0; /* Egress time stamp 0 */
3991 + __be32 tstamp_1; /* Egress time stamp 1 */
3992 + } port[13];
3993 +
3994 + __be32 rsvd1[0x72];
3995 +};
3996 +
3997 +/* Switch Store DMA registers */
3998 +struct vr9_switch_sdma_regs {
3999 + struct sdma_core {
4000 + __be32 ctrl; /* SDMA Control */
4001 + __be32 fcthr_1; /* Flow control threshold 1 */
4002 + __be32 rsvd0;
4003 + __be32 fcthr_3; /* Flow control threshold 3 */
4004 + __be32 fcthr_4; /* Flow control threshold 4 */
4005 + __be32 fcthr_5; /* Flow control threshold 5 */
4006 + __be32 fcthr_6; /* Flow control threshold 6 */
4007 + __be32 fcthr_7; /* Flow control threshold 7 */
4008 + __be32 stat_0; /* SDMA status 0 */
4009 + __be32 stat_1; /* SDMA status 1 */
4010 + __be32 stat_2; /* SDMA status 2 */
4011 + __be32 ier; /* SDMA interrupt enable */
4012 + __be32 isr; /* SDMA interrupt status */
4013 + } core;
4014 +
4015 + __be32 rsvd0[0x73];
4016 +
4017 + struct sdma_port {
4018 + __be32 pctrl; /* Port control */
4019 + __be32 prio; /* Port priority */
4020 + __be32 pstat_0; /* Port status 0 */
4021 + __be32 pstat_1; /* Port status 1 */
4022 + __be32 tstamp_0; /* Ingress time stamp 0 */
4023 + __be32 tstamp_1; /* Ingress time stamp 1 */
4024 + } port[13];
4025 +
4026 + __be32 rsvd1[0x32];
4027 +};
4028 +
4029 +/* Switch MDIO control and status registers */
4030 +struct vr9_switch_mdio_regs {
4031 + __be32 glob_ctrl; /* Global control 0 */
4032 + __be32 rsvd0[7];
4033 + __be32 mdio_ctrl; /* MDIO control */
4034 + __be32 mdio_read; /* MDIO read data */
4035 + __be32 mdio_write; /* MDIO write data */
4036 + __be32 mdc_cfg_0; /* MDC clock configuration 0 */
4037 + __be32 mdc_cfg_1; /* MDC clock configuration 1 */
4038 + __be32 rsvd1[0x3];
4039 + __be32 phy_addr[6]; /* PHY address port 5..0 */
4040 + __be32 mdio_stat[6]; /* MDIO PHY polling status port 0..5 */
4041 + __be32 aneg_eee[6]; /* EEE auto-neg overrides port 0..5 */
4042 + __be32 rsvd2[0x14];
4043 +};
4044 +
4045 +static inline unsigned int to_mdio_phyaddr_id(unsigned int id)
4046 +{
4047 + BUG_ON(id > 5);
4048 +
4049 + return 5 - id;
4050 +}
4051 +
4052 +/* Switch xMII control registers */
4053 +struct vr9_switch_mii_regs {
4054 + __be32 mii_cfg0; /* xMII port 0 configuration */
4055 + __be32 pcdu0; /* Port 0 clock delay configuration */
4056 + __be32 mii_cfg1; /* xMII port 1 configuration */
4057 + __be32 pcdu1; /* Port 1 clock delay configuration */
4058 + __be32 rsvd0[0x6];
4059 + __be32 mii_cfg5; /* xMII port 5 configuration */
4060 + __be32 pcdu5; /* Port 5 clock delay configuration */
4061 + __be32 rsvd1[0x14];
4062 + __be32 rxb_ctl_0; /* Port 0 receive buffer control */
4063 + __be32 rxb_ctl_1; /* Port 1 receive buffer control */
4064 + __be32 rxb_ctl_5; /* Port 5 receive buffer control */
4065 + __be32 rsvd2[0x28];
4066 + __be32 dbg_ctl; /* Debug control */
4067 +};
4068 +
4069 +/* Switch Pseudo-MAC registers */
4070 +struct vr9_switch_pmac_regs {
4071 + __be32 hd_ctl; /* PMAC header control */
4072 + __be32 tl; /* PMAC type/length */
4073 + __be32 sa1; /* PMAC source address 1 */
4074 + __be32 sa2; /* PMAC source address 2 */
4075 + __be32 sa3; /* PMAC source address 3 */
4076 + __be32 da1; /* PMAC destination address 1 */
4077 + __be32 da2; /* PMAC destination address 2 */
4078 + __be32 da3; /* PMAC destination address 3 */
4079 + __be32 vlan; /* PMAC VLAN */
4080 + __be32 rx_ipg; /* PMAC interpacket gap in RX direction */
4081 + __be32 st_etype; /* PMAC special tag ethertype */
4082 + __be32 ewan; /* PMAC ethernet WAN group */
4083 + __be32 ctl; /* PMAC control */
4084 + __be32 rsvd0[0x2];
4085 +};
4086 +
4087 +struct vr9_switch_regs {
4088 + struct vr9_switch_core_regs core;
4089 + struct vr9_switch_bm_regs bm;
4090 + struct vr9_switch_pce_regs pce;
4091 + struct vr9_switch_mac_regs mac;
4092 + struct vr9_switch_fdma_regs fdma;
4093 + struct vr9_switch_sdma_regs sdma;
4094 + struct vr9_switch_mdio_regs mdio;
4095 + struct vr9_switch_mii_regs mii;
4096 + struct vr9_switch_pmac_regs pmac;
4097 +};
4098 +
4099 +static inline void *to_pce_tbl_key(struct vr9_switch_regs *regs,
4100 + unsigned int id)
4101 +{
4102 + return &regs->pce.core.tbl_key[to_pce_tbl_key_id(id)];
4103 +}
4104 +
4105 +static inline void *to_pce_tbl_value(struct vr9_switch_regs *regs,
4106 + unsigned int id)
4107 +{
4108 + return &regs->pce.core.tbl_val[to_pce_tbl_value_id(id)];
4109 +}
4110 +
4111 +static inline void *to_mac_ctrl(struct vr9_switch_regs *regs,
4112 + unsigned int id, unsigned int ctrl)
4113 +{
4114 + struct mac_port *mac = &regs->mac.port[id];
4115 +
4116 + switch (ctrl) {
4117 + case 0:
4118 + return &mac->ctrl_0;
4119 + case 1:
4120 + return &mac->ctrl_1;
4121 + case 2:
4122 + return &mac->ctrl_2;
4123 + case 3:
4124 + return &mac->ctrl_3;
4125 + case 4:
4126 + return &mac->ctrl_4;
4127 + case 5:
4128 + return &mac->ctrl_5;
4129 + default:
4130 + return NULL;
4131 + }
4132 +}
4133 +
4134 +static inline void *to_mdio_phyaddr(struct vr9_switch_regs *regs,
4135 + unsigned int id)
4136 +{
4137 + return &regs->mdio.phy_addr[to_mdio_phyaddr_id(id)];
4138 +}
4139 +
4140 +static inline void *to_mii_miicfg(struct vr9_switch_regs *regs,
4141 + unsigned int id)
4142 +{
4143 + switch (id) {
4144 + case 0:
4145 + return &regs->mii.mii_cfg0;
4146 + case 1:
4147 + return &regs->mii.mii_cfg1;
4148 + case 5:
4149 + return &regs->mii.mii_cfg5;
4150 + default:
4151 + return NULL;
4152 + }
4153 +}
4154 +
4155 +static inline void *to_mii_pcdu(struct vr9_switch_regs *regs,
4156 + unsigned int id)
4157 +{
4158 + switch (id) {
4159 + case 0:
4160 + return &regs->mii.pcdu0;
4161 + case 1:
4162 + return &regs->mii.pcdu1;
4163 + case 5:
4164 + return &regs->mii.pcdu5;
4165 + default:
4166 + return NULL;
4167 + }
4168 +}
4169 +
4170 +#define VR9_SWITCH_REG_OFFSET(reg) (4 * (reg))
4171 +
4172 +#define BUILD_CHECK_VR9_REG(name, offset) \
4173 + BUILD_BUG_ON(offsetof(struct vr9_switch_regs, name) != (4 * offset))
4174 +
4175 +static inline void build_check_vr9_registers(void)
4176 +{
4177 + BUILD_CHECK_VR9_REG(core, 0x0);
4178 + BUILD_CHECK_VR9_REG(bm.core, 0x40);
4179 + BUILD_CHECK_VR9_REG(bm.core.queue_gctrl, 0x4a);
4180 + BUILD_CHECK_VR9_REG(bm.port[0], 0x80);
4181 + BUILD_CHECK_VR9_REG(bm.queue, 0x100);
4182 + BUILD_CHECK_VR9_REG(bm.shaper, 0x140);
4183 + BUILD_CHECK_VR9_REG(pce.core, 0x438);
4184 + BUILD_CHECK_VR9_REG(pce.core.tbl_ctrl, 0x44f);
4185 + BUILD_CHECK_VR9_REG(pce.core.parser_stat, 0x469);
4186 + BUILD_CHECK_VR9_REG(pce.port[0], 0x480);
4187 + BUILD_CHECK_VR9_REG(pce.meter[0], 0x580);
4188 + BUILD_CHECK_VR9_REG(mac.core, 0x8c0);
4189 + BUILD_CHECK_VR9_REG(mac.port[0].pstat, 0x900);
4190 + BUILD_CHECK_VR9_REG(mac.port[0].ctrl_0, 0x903);
4191 + BUILD_CHECK_VR9_REG(mac.port[1].pstat, 0x90c);
4192 + BUILD_CHECK_VR9_REG(mac.port[1].ctrl_0, 0x90f);
4193 + BUILD_CHECK_VR9_REG(mac.port[2].pstat, 0x918);
4194 + BUILD_CHECK_VR9_REG(mac.port[2].ctrl_0, 0x91b);
4195 + BUILD_CHECK_VR9_REG(fdma.core, 0xa40);
4196 + BUILD_CHECK_VR9_REG(fdma.port[0], 0xa80);
4197 + BUILD_CHECK_VR9_REG(sdma.core, 0xb40);
4198 + BUILD_CHECK_VR9_REG(sdma.port[0], 0xbc0);
4199 + BUILD_CHECK_VR9_REG(mdio, 0xc40);
4200 + BUILD_CHECK_VR9_REG(mii, (0xc40 + 0x36));
4201 + BUILD_CHECK_VR9_REG(pmac, (0xc40 + 0x82));
4202 +}
4203 +
4204 +#define BM_GCTRL_F_SRES 1
4205 +
4206 +#define MAC_CTRL0_BM (1 << 12)
4207 +#define MAC_CTRL0_APADEN (1 << 11)
4208 +#define MAC_CTRL0_VPAD2EN (1 << 10)
4209 +#define MAC_CTRL0_VPADEN (1 << 9)
4210 +#define MAC_CTRL0_PADEN (1 << 8)
4211 +#define MAC_CTRL0_FCS (1 << 7)
4212 +#define MAC_CTRL0_FCON_SHIFT 4
4213 +#define MAC_CTRL0_FCON_AUTO (0x0 << MAC_CTRL0_FCON_SHIFT)
4214 +#define MAC_CTRL0_FCON_RX (0x1 << MAC_CTRL0_FCON_SHIFT)
4215 +#define MAC_CTRL0_FCON_TX (0x2 << MAC_CTRL0_FCON_SHIFT)
4216 +#define MAC_CTRL0_FCON_RXTX (0x3 << MAC_CTRL0_FCON_SHIFT)
4217 +#define MAC_CTRL0_FCON_NONE (0x4 << MAC_CTRL0_FCON_SHIFT)
4218 +#define MAC_CTRL0_FDUP_SHIFT 2
4219 +#define MAC_CTRL0_FDUP_AUTO (0x0 << MAC_CTRL0_FDUP_SHIFT)
4220 +#define MAC_CTRL0_FDUP_EN (0x1 << MAC_CTRL0_FDUP_SHIFT)
4221 +#define MAC_CTRL0_FDUP_DIS (0x3 << MAC_CTRL0_FDUP_SHIFT)
4222 +#define MAC_CTRL0_GMII_AUTO 0x0
4223 +#define MAC_CTRL0_GMII_MII 0x1
4224 +#define MAC_CTRL0_GMII_GMII 0x2
4225 +#define MAC_CTRL0_GMII_GMII_2G 0x3
4226 +
4227 +#define MAC_CTRL1_DEFERMODE (1 << 15)
4228 +#define MAC_CTRL1_SHORTPRE (1 << 8)
4229 +
4230 +#define MAC_CTRL2_MLEN (1 << 3)
4231 +#define MAC_CTRL2_LCHKL (1 << 2)
4232 +#define MAC_CTRL2_LCHKS_DIS 0x0
4233 +#define MAC_CTRL2_LCHKS_UNTAG 0x1
4234 +#define MAC_CTRL2_LCHKS_TAG 0x2
4235 +
4236 +#define PHY_ADDR_LNKST_SHIFT 13
4237 +#define PHY_ADDR_LNKST_AUTO (0x0 << PHY_ADDR_LNKST_SHIFT)
4238 +#define PHY_ADDR_LNKST_UP (0x1 << PHY_ADDR_LNKST_SHIFT)
4239 +#define PHY_ADDR_LNKST_DOWN (0x2 << PHY_ADDR_LNKST_SHIFT)
4240 +#define PHY_ADDR_SPEED_SHIFT 11
4241 +#define PHY_ADDR_SPEED_M10 (0x0 << PHY_ADDR_SPEED_SHIFT)
4242 +#define PHY_ADDR_SPEED_M100 (0x1 << PHY_ADDR_SPEED_SHIFT)
4243 +#define PHY_ADDR_SPEED_G1 (0x2 << PHY_ADDR_SPEED_SHIFT)
4244 +#define PHY_ADDR_SPEED_AUTO (0x3 << PHY_ADDR_SPEED_SHIFT)
4245 +#define PHY_ADDR_FDUP_SHIFT 9
4246 +#define PHY_ADDR_FDUP_AUTO (0x0 << PHY_ADDR_FDUP_SHIFT)
4247 +#define PHY_ADDR_FDUP_EN (0x1 << PHY_ADDR_FDUP_SHIFT)
4248 +#define PHY_ADDR_FDUP_DIS (0x3 << PHY_ADDR_FDUP_SHIFT)
4249 +#define PHY_ADDR_FCONTX_SHIFT 7
4250 +#define PHY_ADDR_FCONTX_AUTO (0x0 << PHY_ADDR_FCONTX_SHIFT)
4251 +#define PHY_ADDR_FCONTX_EN (0x1 << PHY_ADDR_FCONTX_SHIFT)
4252 +#define PHY_ADDR_FCONTX_DIS (0x3 << PHY_ADDR_FCONTX_SHIFT)
4253 +#define PHY_ADDR_FCONRX_SHIFT 5
4254 +#define PHY_ADDR_FCONRX_AUTO (0x0 << PHY_ADDR_FCONRX_SHIFT)
4255 +#define PHY_ADDR_FCONRX_EN (0x1 << PHY_ADDR_FCONRX_SHIFT)
4256 +#define PHY_ADDR_FCONRX_DIS (0x3 << PHY_ADDR_FCONRX_SHIFT)
4257 +
4258 +#define MII_CFG_RES (1 << 15)
4259 +#define MII_CFG_EN (1 << 14)
4260 +#define MII_CFG_LDCLKDIS (1 << 12)
4261 +#define MII_CFG_MIIRATE_SHIFT 4
4262 +#define MII_CFG_MIIRATE_MASK (0x7 << MII_CFG_MIIRATE_SHIFT)
4263 +#define MII_CFG_MIIRATE_M2P5 (0x0 << MII_CFG_MIIRATE_SHIFT)
4264 +#define MII_CFG_MIIRATE_M25 (0x1 << MII_CFG_MIIRATE_SHIFT)
4265 +#define MII_CFG_MIIRATE_M125 (0x2 << MII_CFG_MIIRATE_SHIFT)
4266 +#define MII_CFG_MIIRATE_M50 (0x3 << MII_CFG_MIIRATE_SHIFT)
4267 +#define MII_CFG_MIIRATE_AUTO (0x4 << MII_CFG_MIIRATE_SHIFT)
4268 +#define MII_CFG_MIIMODE_MASK 0xf
4269 +#define MII_CFG_MIIMODE_MIIP 0x0
4270 +#define MII_CFG_MIIMODE_MIIM 0x1
4271 +#define MII_CFG_MIIMODE_RMIIP 0x2
4272 +#define MII_CFG_MIIMODE_RMIIM 0x3
4273 +#define MII_CFG_MIIMODE_RGMII 0x4
4274 +
4275 +#define PCDU_RXDLY_SHIFT 7
4276 +#define PCDU_RXDLY_MASK (0x7 << PCDU_RXDLY_SHIFT)
4277 +#define PCDU_TXDLY_MASK 0x7
4278 +
4279 +#define PMAC_HD_CTL_FC (1 << 10)
4280 +#define PMAC_HD_CTL_CCRC (1 << 9)
4281 +#define PMAC_HD_CTL_RST (1 << 8)
4282 +#define PMAC_HD_CTL_AST (1 << 7)
4283 +#define PMAC_HD_CTL_RXSH (1 << 6)
4284 +#define PMAC_HD_CTL_RC (1 << 4)
4285 +#define PMAC_HD_CTL_AS (1 << 3)
4286 +#define PMAC_HD_CTL_AC (1 << 2)
4287 +
4288 +#define PCE_PCTRL_0_IGSTEN (1 << 11)
4289 +
4290 +#define FDMA_PCTRL_STEN (1 << 1)
4291 +#define FDMA_PCTRL_EN (1 << 0)
4292 +
4293 +#define SDMA_PCTRL_EN (1 << 0)
4294 +
4295 +#define MDIO_GLOB_CTRL_SE (1 << 15)
4296 +
4297 +#define MDIO_MDC_CFG1_RES (1 << 15)
4298 +#define MDIO_MDC_CFG1_MCEN (1 << 8)
4299 +
4300 +#define MDIO_CTRL_MBUSY (1 << 12)
4301 +#define MDIO_CTRL_OP_READ (1 << 11)
4302 +#define MDIO_CTRL_OP_WRITE (1 << 10)
4303 +#define MDIO_CTRL_PHYAD_SHIFT 5
4304 +#define MDIO_CTRL_PHYAD_MASK (0x1f << MDIO_CTRL_PHYAD_SHIFT)
4305 +#define MDIO_CTRL_REGAD_MASK 0x1f
4306 +
4307 +#endif /* __VRX200_SWITCH_H__ */
4308 --- a/arch/mips/include/asm/asm.h
4309 +++ b/arch/mips/include/asm/asm.h
4310 @@ -53,6 +53,7 @@
4311 .align 2; \
4312 .type symbol, @function; \
4313 .ent symbol, 0; \
4314 + .section .text.symbol,"x"; \
4315 symbol: .frame sp, 0, ra
4316
4317 /*
4318 @@ -62,7 +63,8 @@ symbol: .frame sp, 0, ra
4319 .globl symbol; \
4320 .align 2; \
4321 .type symbol, @function; \
4322 - .ent symbol, 0; \
4323 + .ent symbol, 0; \
4324 + .section .text.symbol,"x"; \
4325 symbol: .frame sp, framesize, rpc
4326
4327 /*
4328 --- /dev/null
4329 +++ b/arch/mips/include/asm/gpio.h
4330 @@ -0,0 +1,6 @@
4331 +/*
4332 + * SPDX-License-Identifier: GPL-2.0+
4333 + */
4334 +
4335 +#include <asm/arch/gpio.h>
4336 +#include <asm-generic/gpio.h>
4337 --- /dev/null
4338 +++ b/arch/mips/include/asm/lantiq/chipid.h
4339 @@ -0,0 +1,73 @@
4340 +/*
4341 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4342 + *
4343 + * SPDX-License-Identifier: GPL-2.0+
4344 + */
4345 +
4346 +#ifndef __LANTIQ_CHIPID_H__
4347 +#define __LANTIQ_CHIPID_H__
4348 +
4349 +enum ltq_chip_partnum {
4350 + LTQ_SOC_UNKNOWN = 0,
4351 + LTQ_SOC_VRX288_2 = 0x000B, /* VRX288 v1.2 */
4352 + LTQ_SOC_VRX268_2 = 0x000C, /* VRX268 v1.2 */
4353 + LTQ_SOC_GRX288_2 = 0x000D, /* GRX288 v1.2 */
4354 + LTQ_SOC_DANUBE = 0x0129,
4355 + LTQ_SOC_DANUBE_S = 0x012B,
4356 + LTQ_SOC_TWINPASS = 0x012D,
4357 + LTQ_SOC_VRX288 = 0x01C0, /* VRX288 v1.1 */
4358 + LTQ_SOC_VRX268 = 0x01C2, /* VRX268 v1.1 */
4359 + LTQ_SOC_GRX288 = 0x01C9, /* GRX288 v1.1 */
4360 +};
4361 +
4362 +extern unsigned int ltq_chip_version_get(void);
4363 +extern unsigned int ltq_chip_partnum_get(void);
4364 +extern const char *ltq_chip_partnum_str(void);
4365 +
4366 +extern void ltq_chip_print_info(void);
4367 +
4368 +#ifdef CONFIG_SOC_XWAY_DANUBE
4369 +static inline int ltq_soc_is_danube(void)
4370 +{
4371 + return 1;
4372 +}
4373 +#else
4374 +static inline int ltq_soc_is_danube(void)
4375 +{
4376 + return 0;
4377 +}
4378 +#endif
4379 +
4380 +#ifdef CONFIG_SOC_XWAY_VRX200
4381 +static inline int ltq_soc_is_vrx200(void)
4382 +{
4383 + return 1;
4384 +}
4385 +
4386 +static inline int ltq_soc_is_vrx200_v1(void)
4387 +{
4388 + return ltq_chip_version_get() == 1;
4389 +}
4390 +
4391 +static inline int ltq_soc_is_vrx200_v2(void)
4392 +{
4393 + return ltq_chip_version_get() == 2;
4394 +}
4395 +#else
4396 +static inline int ltq_soc_is_vrx200(void)
4397 +{
4398 + return 0;
4399 +}
4400 +
4401 +static inline int ltq_soc_is_vrx200_v1(void)
4402 +{
4403 + return 0;
4404 +}
4405 +
4406 +static inline int ltq_soc_is_vrx200_v2(void)
4407 +{
4408 + return 0;
4409 +}
4410 +#endif
4411 +
4412 +#endif /* __LANTIQ_CHIPID_H__ */
4413 --- /dev/null
4414 +++ b/arch/mips/include/asm/lantiq/clk.h
4415 @@ -0,0 +1,30 @@
4416 +/*
4417 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
4418 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4419 + * *
4420 + * SPDX-License-Identifier: GPL-2.0+
4421 + */
4422 +
4423 +#ifndef __LANTIQ_CLK_H__
4424 +#define __LANTIQ_CLK_H__
4425 +
4426 +/* Symbolic clock speeds */
4427 +enum ltq_clk {
4428 + CLOCK_83_MHZ = 83333333,
4429 + CLOCK_111_MHZ = 111111111,
4430 + CLOCK_125_MHZ = 125000000,
4431 + CLOCK_133_MHZ = 133333333,
4432 + CLOCK_166_MHZ = 166666667,
4433 + CLOCK_197_MHZ = 197000000,
4434 + CLOCK_333_MHZ = 333333333,
4435 + CLOCK_393_MHZ = 393219000,
4436 + CLOCK_500_MHZ = 500000000,
4437 + CLOCK_600_MHZ = 600000000,
4438 + CLOCK_1000_MHZ = 1000000000,
4439 +};
4440 +
4441 +extern unsigned long ltq_get_cpu_clock(void);
4442 +extern unsigned long ltq_get_bus_clock(void);
4443 +extern unsigned long ltq_get_io_region_clock(void);
4444 +
4445 +#endif /* __LANTIQ_CLK_H__ */
4446 --- /dev/null
4447 +++ b/arch/mips/include/asm/lantiq/config.h
4448 @@ -0,0 +1,164 @@
4449 +/*
4450 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
4451 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4452 + *
4453 + * SPDX-License-Identifier: GPL-2.0+
4454 + */
4455 +
4456 +#ifndef __LANTIQ_CONFIG_H__
4457 +#define __LANTIQ_CONFIG_H__
4458 +
4459 +/* Memory usage */
4460 +#define CONFIG_SYS_MAXARGS 24
4461 +#define CONFIG_SYS_MALLOC_LEN 1024*1024
4462 +#define CONFIG_SYS_BOOTPARAMS_LEN 128*1024
4463 +
4464 +/* Command line */
4465 +#define CONFIG_SYS_PROMPT CONFIG_MACH_TYPE " # "
4466 +#define CONFIG_SYS_CBSIZE 512
4467 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
4468 + sizeof(CONFIG_SYS_PROMPT)+16)
4469 +
4470 +#define CONFIG_SYS_HUSH_PARSER
4471 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
4472 +
4473 +/*
4474 + * Enable advanced console features on demand to reduce
4475 + * flash and RAM footprint
4476 + */
4477 +#if defined(CONFIG_LTQ_ADVANCED_CONSOLE)
4478 +#define CONFIG_SYS_LONGHELP
4479 +#define CONFIG_AUTO_COMPLETE
4480 +#define CONFIG_CMDLINE_EDITING
4481 +#endif
4482 +
4483 +/* SPI flash SPL */
4484 +#if defined(CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH) && defined(CONFIG_SYS_BOOT_SFSPL)
4485 +#define CONFIG_SPL
4486 +#define CONFIG_SPL_SPI_SUPPORT
4487 +#define CONFIG_SPL_SPI_FLASH_SUPPORT
4488 +#define CONFIG_SPI_SPL_SIMPLE
4489 +#endif
4490 +
4491 +#if defined(CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH) && defined(CONFIG_SYS_BOOT_NORSPL)
4492 +#define CONFIG_SPL
4493 +#endif
4494 +
4495 +/* Common SPL */
4496 +#if defined(CONFIG_SPL)
4497 +#define CONFIG_SKIP_LOWLEVEL_INIT
4498 +#define CONFIG_SPL_LIBGENERIC_SUPPORT
4499 +#define CONFIG_SPL_GPIO_SUPPORT
4500 +#define CONFIG_SPL_START_S_PATH \
4501 + "arch/mips/cpu/mips32/lantiq-common"
4502 +#define CONFIG_SPL_LDSCRIPT \
4503 + "arch/mips/cpu/mips32/lantiq-common/u-boot-spl.lds"
4504 +#endif
4505 +
4506 +#if defined(CONFIG_LTQ_SPL_CONSOLE)
4507 +#define CONFIG_SPL_SERIAL_SUPPORT
4508 +#define CONFIG_SPL_LIBCOMMON_SUPPORT
4509 +#endif
4510 +
4511 +#if defined(CONFIG_LTQ_SPL_COMP_LZMA)
4512 +#define CONFIG_LZMA
4513 +#define CONFIG_SPL_LZMA_SUPPORT
4514 +#endif
4515 +
4516 +#if defined(CONFIG_LTQ_SPL_COMP_LZO)
4517 +#define CONFIG_LZO
4518 +#define CONFIG_SPL_LZO_SUPPORT
4519 +#endif
4520 +
4521 +/* Basic commands */
4522 +#define CONFIG_CMD_BDI
4523 +#define CONFIG_CMD_EDITENV
4524 +#define CONFIG_CMD_IMI
4525 +#define CONFIG_CMD_MEMORY
4526 +#define CONFIG_CMD_RUN
4527 +#define CONFIG_CMD_SAVEENV
4528 +#define CONFIG_CMD_LOADB
4529 +
4530 +/* Other U-Boot settings */
4531 +#define CONFIG_TIMESTAMP
4532 +
4533 +/* Default environment */
4534 +#define CONFIG_ENV_CONSOLEDEV \
4535 + "consoledev=" CONFIG_CONSOLE_DEV "\0"
4536 +
4537 +#define CONFIG_ENV_ADDCONSOLE \
4538 + "addconsole=setenv bootargs $bootargs" \
4539 + " console=$consoledev,$baudrate\0"
4540 +
4541 +#if defined(CONFIG_NET_DEV)
4542 +#define CONFIG_ENV_NETDEV \
4543 + "netdev=" CONFIG_NET_DEV "\0"
4544 +#else
4545 +#define CONFIG_ENV_NETDEV \
4546 + "netdev=eth0\0"
4547 +#endif
4548 +
4549 +#define CONFIG_ENV_ADDIP \
4550 + "addip=setenv bootargs $bootargs" \
4551 + " ip=$ipaddr:$serverip::::$netdev:off\0"
4552 +
4553 +#define CONFIG_ENV_ADDETH \
4554 + "addeth=setenv bootargs $bootargs" \
4555 + " ethaddr=$ethaddr\0"
4556 +
4557 +#define CONFIG_ENV_ADDMACHTYPE \
4558 + "addmachtype=setenv bootargs $bootargs" \
4559 + " machtype=" CONFIG_MACH_TYPE "\0"
4560 +
4561 +#if defined(CONFIG_LTQ_SUPPORT_NOR_FLASH)
4562 +#define CONFIG_ENV_WRITE_UBOOT_NOR \
4563 + "write-uboot-nor=" \
4564 + "protect off " __stringify(CONFIG_SYS_FLASH_BASE) " +$filesize && " \
4565 + "erase " __stringify(CONFIG_SYS_FLASH_BASE) " +$filesize && " \
4566 + "cp.b $fileaddr " __stringify(CONFIG_SYS_FLASH_BASE) " $filesize\0"
4567 +
4568 +#define CONFIG_ENV_LOAD_UBOOT_NOR \
4569 + "load-uboot-nor=tftpboot u-boot.bin\0" \
4570 + "load-uboot-norspl=tftpboot u-boot.ltq.norspl\0" \
4571 + "load-uboot-norspl-lzo=tftpboot u-boot.ltq.lzo.norspl\0" \
4572 + "load-uboot-norspl-lzma=tftpboot u-boot.ltq.lzma.norspl\0"
4573 +#else
4574 +#define CONFIG_ENV_WRITE_UBOOT_NOR
4575 +#define CONFIG_ENV_LOAD_UBOOT_NOR
4576 +#endif
4577 +
4578 +#if defined(CONFIG_LTQ_SUPPORT_SPI_FLASH)
4579 +#define CONFIG_ENV_SF_PROBE \
4580 + "sf-probe=sf probe " __stringify(CONFIG_ENV_SPI_CS) " " \
4581 + __stringify(CONFIG_ENV_SPI_MAX_HZ) " " \
4582 + __stringify(CONFIG_ENV_SPI_MODE) " \0"
4583 +
4584 +#define CONFIG_ENV_WRITE_UBOOT_SF \
4585 + "write-uboot-sf=" \
4586 + "run sf-probe && sf erase 0 +$filesize && " \
4587 + "sf write $fileaddr 0 $filesize\0"
4588 +
4589 +#define CONFIG_ENV_LOAD_UBOOT_SF \
4590 + "load-uboot-sfspl=tftpboot u-boot.ltq.sfspl\0" \
4591 + "load-uboot-sfspl-lzo=tftpboot u-boot.ltq.lzo.sfspl\0" \
4592 + "load-uboot-sfspl-lzma=tftpboot u-boot.ltq.lzma.sfspl\0"
4593 +#else
4594 +#define CONFIG_ENV_SF_PROBE
4595 +#define CONFIG_ENV_WRITE_UBOOT_SF
4596 +#define CONFIG_ENV_LOAD_UBOOT_SF
4597 +#endif
4598 +
4599 +#define CONFIG_ENV_LANTIQ_DEFAULTS \
4600 + CONFIG_ENV_CONSOLEDEV \
4601 + CONFIG_ENV_ADDCONSOLE \
4602 + CONFIG_ENV_NETDEV \
4603 + CONFIG_ENV_ADDIP \
4604 + CONFIG_ENV_ADDETH \
4605 + CONFIG_ENV_ADDMACHTYPE \
4606 + CONFIG_ENV_WRITE_UBOOT_NOR \
4607 + CONFIG_ENV_LOAD_UBOOT_NOR \
4608 + CONFIG_ENV_SF_PROBE \
4609 + CONFIG_ENV_WRITE_UBOOT_SF \
4610 + CONFIG_ENV_LOAD_UBOOT_SF
4611 +
4612 +#endif /* __LANTIQ_CONFIG_H__ */
4613 --- /dev/null
4614 +++ b/arch/mips/include/asm/lantiq/cpu.h
4615 @@ -0,0 +1,34 @@
4616 +/*
4617 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4618 + *
4619 + * SPDX-License-Identifier: GPL-2.0+
4620 + */
4621 +
4622 +#ifndef __LANTIQ_CPU_H__
4623 +#define __LANTIQ_CPU_H__
4624 +
4625 +enum ltq_boot_select {
4626 + BOOT_NOR,
4627 + BOOT_NOR_NO_BOOTROM,
4628 + BOOT_UART,
4629 + BOOT_UART_NO_EEPROM,
4630 + BOOT_SPI,
4631 + BOOT_NAND,
4632 + BOOT_PCI,
4633 + BOOT_MII0,
4634 + BOOT_RMII0,
4635 + BOOT_RGMII1,
4636 + BOOT_UNKNOWN,
4637 +};
4638 +
4639 +enum ltq_boot_select ltq_boot_select(void);
4640 +const char *ltq_boot_select_str(void);
4641 +
4642 +void ltq_pmu_init(void);
4643 +void ltq_ebu_init(void);
4644 +void ltq_gpio_init(void);
4645 +
4646 +void ltq_pll_init(void);
4647 +void ltq_dcdc_init(unsigned int dig_ref);
4648 +
4649 +#endif /* __LANTIQ_CPU_H__ */
4650 --- /dev/null
4651 +++ b/arch/mips/include/asm/lantiq/dma.h
4652 @@ -0,0 +1,94 @@
4653 +/*
4654 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4655 + *
4656 + * SPDX-License-Identifier: GPL-2.0+
4657 + */
4658 +
4659 +#ifndef __LANTIQ_DMA_H__
4660 +#define __LANTIQ_DMA_H__
4661 +
4662 +enum ltq_dma_endianess {
4663 + LTQ_DMA_ENDIANESS_B0_B1_B2_B3, /* No byte swapping */
4664 + LTQ_DMA_ENDIANESS_B1_B0_B3_B2, /* B0B1B2B3 => B1B0B3B2 */
4665 + LTQ_DMA_ENDIANESS_B2_B3_B0_B1, /* B0B1B2B3 => B2B3B0B1 */
4666 + LTQ_DMA_ENDIANESS_B3_B2_B1_B0, /* B0B1B2B3 => B3B2B1B0 */
4667 +};
4668 +
4669 +enum ltq_dma_burst_len {
4670 + LTQ_DMA_BURST_2WORDS = 1,
4671 + LTQ_DMA_BURST_4WORDS = 2,
4672 + LTQ_DMA_BURST_8WORDS = 3,
4673 +};
4674 +
4675 +struct ltq_dma_desc {
4676 + u32 ctl;
4677 + u32 addr;
4678 +};
4679 +
4680 +struct ltq_dma_channel {
4681 + struct ltq_dma_device *dev;
4682 + u8 chan_no;
4683 + u8 class;
4684 + u16 num_desc;
4685 + struct ltq_dma_desc *desc_base;
4686 + void *mem_base;
4687 + u32 dma_addr;
4688 +};
4689 +
4690 +struct ltq_dma_device {
4691 + enum ltq_dma_endianess rx_endian_swap;
4692 + enum ltq_dma_endianess tx_endian_swap;
4693 + enum ltq_dma_burst_len rx_burst_len;
4694 + enum ltq_dma_burst_len tx_burst_len;
4695 + struct ltq_dma_channel rx_chan;
4696 + struct ltq_dma_channel tx_chan;
4697 + u8 port;
4698 +};
4699 +
4700 +/**
4701 + * Initialize DMA hardware and driver
4702 + */
4703 +void ltq_dma_init(void);
4704 +
4705 +/**
4706 + * Register given DMA client context
4707 + *
4708 + * @returns 0 on success, negative value otherwise
4709 + */
4710 +int ltq_dma_register(struct ltq_dma_device *dev);
4711 +
4712 +/**
4713 + * Reset and halt all channels related to given DMA client
4714 + */
4715 +void ltq_dma_reset(struct ltq_dma_device *dev);
4716 +void ltq_dma_enable(struct ltq_dma_device *dev);
4717 +void ltq_dma_disable(struct ltq_dma_device *dev);
4718 +
4719 +/**
4720 + * Map RX DMA descriptor to memory region
4721 + *
4722 + * @returns 0 on success, negative value otherwise
4723 + */
4724 +int ltq_dma_rx_map(struct ltq_dma_device *dev, int index, void *data, int len);
4725 +
4726 +/**
4727 + * Check if new data is available.
4728 + *
4729 + * @returns length of received data, 0 otherwise
4730 + */
4731 +int ltq_dma_rx_poll(struct ltq_dma_device *dev, int index);
4732 +
4733 +int ltq_dma_rx_length(struct ltq_dma_device *dev, int index);
4734 +
4735 +/**
4736 + * Map TX DMA descriptor to memory region
4737 + *
4738 + * @returns 0 on success, negative value otherwise
4739 + */
4740 +int ltq_dma_tx_map(struct ltq_dma_device *dev, int index, void *data, int len,
4741 + unsigned long timeout);
4742 +
4743 +int ltq_dma_tx_wait(struct ltq_dma_device *dev, int index,
4744 + unsigned long timeout);
4745 +
4746 +#endif /* __LANTIQ_DMA_H__ */
4747 --- /dev/null
4748 +++ b/arch/mips/include/asm/lantiq/eth.h
4749 @@ -0,0 +1,35 @@
4750 +/*
4751 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4752 + *
4753 + * SPDX-License-Identifier: GPL-2.0+
4754 + */
4755 +
4756 +#ifndef __LANTIQ_ETH_H__
4757 +#define __LANTIQ_ETH_H__
4758 +
4759 +#include <phy.h>
4760 +
4761 +enum LTQ_ETH_PORT_FLAGS {
4762 + LTQ_ETH_PORT_NONE = 0,
4763 + LTQ_ETH_PORT_PHY = 1,
4764 + LTQ_ETH_PORT_SWITCH = (1 << 1),
4765 + LTQ_ETH_PORT_MAC = (1 << 2),
4766 +};
4767 +
4768 +struct ltq_eth_port_config {
4769 + u8 num;
4770 + u8 phy_addr;
4771 + u16 flags;
4772 + phy_interface_t phy_if;
4773 + u8 rgmii_rx_delay;
4774 + u8 rgmii_tx_delay;
4775 +};
4776 +
4777 +struct ltq_eth_board_config {
4778 + const struct ltq_eth_port_config *ports;
4779 + int num_ports;
4780 +};
4781 +
4782 +extern int ltq_eth_initialize(const struct ltq_eth_board_config *board_config);
4783 +
4784 +#endif /* __LANTIQ_ETH_H__ */
4785 --- /dev/null
4786 +++ b/arch/mips/include/asm/lantiq/gpio.h
4787 @@ -0,0 +1,50 @@
4788 +/*
4789 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4790 + *
4791 + * SPDX-License-Identifier: GPL-2.0+
4792 + */
4793 +
4794 +#ifndef __LANTIQ_GPIO_H__
4795 +#define __LANTIQ_GPIO_H__
4796 +
4797 +enum ltq_gpio_dir {
4798 + GPIO_DIR_IN = 0,
4799 + GPIO_DIR_OUT
4800 +};
4801 +
4802 +enum ltq_gpio_od {
4803 + GPIO_OD_ACTIVE = 0,
4804 + GPIO_OD_NORMAL
4805 +};
4806 +
4807 +enum ltq_gpio_altsel {
4808 + GPIO_ALTSEL_CLR = 0,
4809 + GPIO_ALTSEL_SET
4810 +};
4811 +
4812 +extern int gpio_set_altfunc(unsigned gpio, int altsel0, int altsel1, int dir);
4813 +extern int gpio_set_opendrain(unsigned gpio, int od);
4814 +
4815 +static inline int gpio_to_port(unsigned gpio)
4816 +{
4817 + return gpio >> 4;
4818 +}
4819 +
4820 +static inline int gpio_to_pin(unsigned gpio)
4821 +{
4822 + return gpio & 0xF;
4823 +}
4824 +
4825 +static inline int gpio_to_bit(unsigned gpio)
4826 +{
4827 + return 1 << gpio_to_pin(gpio);
4828 +}
4829 +
4830 +static inline int gpio_to_gpio(unsigned port, unsigned pin)
4831 +{
4832 + return (port << 4) | (pin & 0xF);
4833 +}
4834 +
4835 +#include <asm-generic/gpio.h>
4836 +
4837 +#endif /* __LANTIQ_GPIO_H__ */
4838 --- /dev/null
4839 +++ b/arch/mips/include/asm/lantiq/io.h
4840 @@ -0,0 +1,37 @@
4841 +/*
4842 + * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
4843 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4844 + *
4845 + * SPDX-License-Identifier: GPL-2.0+
4846 + */
4847 +
4848 +#ifndef __LANTIQ_IO_H__
4849 +#define __LANTIQ_IO_H__
4850 +
4851 +#include <asm/io.h>
4852 +
4853 +#define ltq_readb(a) __raw_readb(a)
4854 +#define ltq_writeb(a, v) __raw_writeb(v, a)
4855 +
4856 +#define ltq_readl(a) __raw_readl(a)
4857 +#define ltq_writel(a, v) __raw_writel(v, a)
4858 +
4859 +#define ltq_clrbits(a, clear) \
4860 + ltq_writel(a, ltq_readl(a) & ~(clear))
4861 +
4862 +#define ltq_setbits(a, set) \
4863 + ltq_writel(a, ltq_readl(a) | (set))
4864 +
4865 +#define ltq_clrsetbits(a, clear, set) \
4866 + ltq_writel(a, (ltq_readl(a) & ~(clear)) | (set))
4867 +
4868 +static inline void ltq_reg_dump(const void *addr, const char *desc)
4869 +{
4870 + u32 data;
4871 +
4872 + data = ltq_readl(addr);
4873 + printf("ltq_reg_dump: %s 0x%p = 0x%08x\n",
4874 + desc, addr, data);
4875 +}
4876 +
4877 +#endif /* __LANTIQ_IO_H__ */
4878 --- /dev/null
4879 +++ b/arch/mips/include/asm/lantiq/pm.h
4880 @@ -0,0 +1,21 @@
4881 +/*
4882 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4883 + *
4884 + * SPDX-License-Identifier: GPL-2.0+
4885 + */
4886 +
4887 +#ifndef __LANTIQ_PM_H__
4888 +#define __LANTIQ_PM_H__
4889 +
4890 +enum ltq_pm_modules {
4891 + LTQ_PM_CORE,
4892 + LTQ_PM_DMA,
4893 + LTQ_PM_ETH,
4894 + LTQ_PM_SPI,
4895 +};
4896 +
4897 +u32 ltq_pm_map(enum ltq_pm_modules module);
4898 +int ltq_pm_enable(enum ltq_pm_modules module);
4899 +int ltq_pm_disable(enum ltq_pm_modules module);
4900 +
4901 +#endif /* __LANTIQ_PM_H__ */
4902 --- /dev/null
4903 +++ b/arch/mips/include/asm/lantiq/reset.h
4904 @@ -0,0 +1,37 @@
4905 +/*
4906 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
4907 + *
4908 + * SPDX-License-Identifier: GPL-2.0+
4909 + */
4910 +
4911 +#ifndef __LANTIQ_RESET_H__
4912 +#define __LANTIQ_RESET_H__
4913 +
4914 +enum ltq_reset_modules {
4915 + LTQ_RESET_CORE,
4916 + LTQ_RESET_DMA,
4917 + LTQ_RESET_ETH,
4918 + LTQ_RESET_PHY,
4919 + LTQ_RESET_HARD,
4920 + LTQ_RESET_SOFT,
4921 +};
4922 +
4923 +extern u32 ltq_reset_map(enum ltq_reset_modules module);
4924 +extern int ltq_reset_activate(enum ltq_reset_modules module);
4925 +extern int ltq_reset_deactivate(enum ltq_reset_modules module);
4926 +
4927 +static inline int ltq_reset_once(enum ltq_reset_modules module, ulong usec)
4928 +{
4929 + int ret;
4930 +
4931 + ret = ltq_reset_activate(module);
4932 + if (ret)
4933 + return ret;
4934 +
4935 + __udelay(usec);
4936 + ret = ltq_reset_deactivate(module);
4937 +
4938 + return ret;
4939 +}
4940 +
4941 +#endif /* __LANTIQ_RESET_H__ */
4942 --- a/arch/mips/include/asm/mipsregs.h
4943 +++ b/arch/mips/include/asm/mipsregs.h
4944 @@ -46,7 +46,10 @@
4945 #define CP0_ENTRYLO1 $3
4946 #define CP0_CONF $3
4947 #define CP0_CONTEXT $4
4948 +#define CP0_CONTEXTCONFIG $4,1
4949 +#define CP0_USERLOCAL $4,1
4950 #define CP0_PAGEMASK $5
4951 +#define CP0_PAGEGRAIN $5,1
4952 #define CP0_WIRED $6
4953 #define CP0_INFO $7
4954 #define CP0_BADVADDR $8
4955 @@ -54,10 +57,19 @@
4956 #define CP0_ENTRYHI $10
4957 #define CP0_COMPARE $11
4958 #define CP0_STATUS $12
4959 +#define CP0_INTCTL $12,1
4960 +#define CP0_SRSCTL $12,2
4961 +#define CP0_SRSMAP $12,3
4962 +#define CP0_SRSHIGH $12,4
4963 #define CP0_CAUSE $13
4964 #define CP0_EPC $14
4965 #define CP0_PRID $15
4966 +#define CP0_EBASE $15,1
4967 #define CP0_CONFIG $16
4968 +#define CP0_CONFIG1 $16,1
4969 +#define CP0_CONFIG2 $16,2
4970 +#define CP0_CONFIG3 $16,3
4971 +#define CP0_CONFIG7 $16,7
4972 #define CP0_LLADDR $17
4973 #define CP0_WATCHLO $18
4974 #define CP0_WATCHHI $19
4975 @@ -70,7 +82,17 @@
4976 #define CP0_ECC $26
4977 #define CP0_CACHEERR $27
4978 #define CP0_TAGLO $28
4979 +#define CP0_ITAGLO $28
4980 +#define CP0_IDATALO $28,1
4981 +#define CP0_DTAGLO $28,2
4982 +#define CP0_DDATALO $28,3
4983 +#define CP0_L23TAGLO $28,4
4984 +#define CP0_L23DATALO $28,5
4985 #define CP0_TAGHI $29
4986 +#define CP0_IDATAHI $29,1
4987 +#define CP0_DTAGHI $29,2
4988 +#define CP0_L23TAGHI $29,4
4989 +#define CP0_L23DATAHI $29,5
4990 #define CP0_ERROREPC $30
4991 #define CP0_DESAVE $31
4992
4993 @@ -395,6 +417,12 @@
4994 #define CAUSEF_BD (_ULCAST_(1) << 31)
4995
4996 /*
4997 + * Bits in the coprocessor 0 EBase register.
4998 + */
4999 +#define EBASEB_CPUNUM 0
5000 +#define EBASEF_CPUNUM (_ULCAST_(1023))
5001 +
5002 +/*
5003 * Bits in the coprocessor 0 config register.
5004 */
5005 /* Generic bits. */
5006 --- a/arch/mips/include/asm/u-boot-mips.h
5007 +++ b/arch/mips/include/asm/u-boot-mips.h
5008 @@ -23,3 +23,4 @@ static inline unsigned long image_copy_e
5009 }
5010
5011 extern int incaip_set_cpuclk(void);
5012 +extern int arch_cpu_init(void);
5013 --- a/arch/mips/lib/board.c
5014 +++ b/arch/mips/lib/board.c
5015 @@ -33,6 +33,16 @@ static char *failed = "*** failed ***\n"
5016 */
5017 const unsigned long mips_io_port_base = -1;
5018
5019 +int __arch_cpu_init(void)
5020 +{
5021 + /*
5022 + * Nothing to do in this dummy implementation
5023 + */
5024 + return 0;
5025 +}
5026 +int arch_cpu_init(void)
5027 + __attribute__((weak, alias("__arch_cpu_init")));
5028 +
5029 int __board_early_init_f(void)
5030 {
5031 /*
5032 @@ -106,6 +116,7 @@ static int init_baudrate(void)
5033 typedef int (init_fnc_t)(void);
5034
5035 init_fnc_t *init_sequence[] = {
5036 + arch_cpu_init,
5037 board_early_init_f,
5038 timer_init,
5039 env_init, /* initialize environment */
5040 --- a/drivers/dma/Makefile
5041 +++ b/drivers/dma/Makefile
5042 @@ -12,6 +12,7 @@ LIB := $(obj)libdma.o
5043 COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o
5044 COBJS-$(CONFIG_APBH_DMA) += apbh_dma.o
5045 COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o
5046 +COBJS-$(CONFIG_LANTIQ_DMA) += lantiq_dma.o
5047 COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o
5048
5049 COBJS := $(COBJS-y)
5050 --- /dev/null
5051 +++ b/drivers/dma/lantiq_dma.c
5052 @@ -0,0 +1,387 @@
5053 +/*
5054 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
5055 + *
5056 + * SPDX-License-Identifier: GPL-2.0+
5057 + */
5058 +
5059 +#include <common.h>
5060 +#include <malloc.h>
5061 +#include <watchdog.h>
5062 +#include <linux/compiler.h>
5063 +#include <asm/lantiq/io.h>
5064 +#include <asm/lantiq/dma.h>
5065 +#include <asm/lantiq/pm.h>
5066 +#include <asm/lantiq/reset.h>
5067 +#include <asm/arch/soc.h>
5068 +#include <asm/processor.h>
5069 +
5070 +#define DMA_CTRL_PKTARB (1 << 31)
5071 +#define DMA_CTRL_MBRSTARB (1 << 30)
5072 +#define DMA_CTRL_MBRSTCNT_SHIFT 16
5073 +#define DMA_CTRL_MBRSTCNT_MASK (0x3ff << DMA_CTRL_MBRSTCNT_SHIFT)
5074 +#define DMA_CTRL_DRB (1 << 8)
5075 +#define DMA_CTRL_RESET (1 << 0)
5076 +
5077 +#define DMA_CPOLL_EN (1 << 31)
5078 +#define DMA_CPOLL_CNT_SHIFT 4
5079 +#define DMA_CPOLL_CNT_MASK (0xFFF << DMA_CPOLL_CNT_SHIFT)
5080 +
5081 +#define DMA_CCTRL_TXWGT_SHIFT 16
5082 +#define DMA_CCTRL_TXWGT_MASK (0x3 << DMA_CCTRL_TXWGT_SHIFT)
5083 +#define DMA_CCTRL_CLASS_SHIFT 9
5084 +#define DMA_CCTRL_CLASS_MASK (0x3 << DMA_CCTRL_CLASS_SHIFT)
5085 +#define DMA_CCTRL_RST (1 << 1)
5086 +#define DMA_CCTRL_ONOFF (1 << 0)
5087 +
5088 +#define DMA_PCTRL_TXBL_SHIFT 4
5089 +#define DMA_PCTRL_TXBL_2WORDS (1 << DMA_PCTRL_TXBL_SHIFT)
5090 +#define DMA_PCTRL_TXBL_4WORDS (2 << DMA_PCTRL_TXBL_SHIFT)
5091 +#define DMA_PCTRL_TXBL_8WORDS (3 << DMA_PCTRL_TXBL_SHIFT)
5092 +#define DMA_PCTRL_RXBL_SHIFT 2
5093 +#define DMA_PCTRL_RXBL_2WORDS (1 << DMA_PCTRL_RXBL_SHIFT)
5094 +#define DMA_PCTRL_RXBL_4WORDS (2 << DMA_PCTRL_RXBL_SHIFT)
5095 +#define DMA_PCTRL_RXBL_8WORDS (3 << DMA_PCTRL_RXBL_SHIFT)
5096 +#define DMA_PCTRL_TXENDI_SHIFT 10
5097 +#define DMA_PCTRL_TXENDI_MASK (0x3 << DMA_PCTRL_TXENDI_SHIFT)
5098 +#define DMA_PCTRL_RXENDI_SHIFT 8
5099 +#define DMA_PCTRL_RXENDI_MASK (0x3 << DMA_PCTRL_RXENDI_SHIFT)
5100 +
5101 +#define DMA_DESC_OWN (1 << 31)
5102 +#define DMA_DESC_C (1 << 30)
5103 +#define DMA_DESC_SOP (1 << 29)
5104 +#define DMA_DESC_EOP (1 << 28)
5105 +#define DMA_DESC_TX_OFFSET(x) ((x & 0x1f) << 23)
5106 +#define DMA_DESC_RX_OFFSET(x) ((x & 0x3) << 23)
5107 +#define DMA_DESC_LENGTH(x) (x & 0xffff)
5108 +
5109 +#define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a)))
5110 +
5111 +struct ltq_dma_regs {
5112 + u32 clc; /* Clock control */
5113 + u32 rsvd0;
5114 + u32 id; /* Identification */
5115 + u32 rsvd1;
5116 + u32 ctrl; /* Control */
5117 + u32 cpoll; /* Channel polling */
5118 + u32 cs; /* Channel select */
5119 + u32 cctrl; /* Channel control */
5120 + u32 cdba; /* Channel descriptor base address */
5121 + u32 cdlen; /* Channel descriptor length */
5122 + u32 cis; /* Channel interrupt status */
5123 + u32 cie; /* Channel interrupt enable */
5124 + u32 cgbl; /* Channel global buffer length */
5125 + u32 cdptnrd; /* Current descriptor pointer */
5126 + u32 rsvd2[2];
5127 + u32 ps; /* Port select */
5128 + u32 pctrl; /* Port control */
5129 + u32 rsvd3[43];
5130 + u32 irnen; /* Interrupt node enable */
5131 + u32 irncr; /* Interrupt node control */
5132 + u32 irnicr; /* Interrupt capture */
5133 +};
5134 +
5135 +static struct ltq_dma_regs *ltq_dma_regs =
5136 + (struct ltq_dma_regs *) CKSEG1ADDR(LTQ_DMA_BASE);
5137 +
5138 +static inline unsigned long ltq_dma_addr_to_virt(u32 dma_addr)
5139 +{
5140 + return KSEG0ADDR(dma_addr);
5141 +}
5142 +
5143 +static inline u32 ltq_virt_to_dma_addr(void *addr)
5144 +{
5145 + return CPHYSADDR(addr);
5146 +}
5147 +
5148 +static inline int ltq_dma_burst_align(enum ltq_dma_burst_len burst_len)
5149 +{
5150 + switch (burst_len) {
5151 + case LTQ_DMA_BURST_2WORDS:
5152 + return 2 * 4;
5153 + case LTQ_DMA_BURST_4WORDS:
5154 + return 4 * 4;
5155 + case LTQ_DMA_BURST_8WORDS:
5156 + return 8 * 4;
5157 + }
5158 +
5159 + return 0;
5160 +}
5161 +
5162 +static inline void ltq_dma_sync(void)
5163 +{
5164 + __asm__ __volatile__("sync");
5165 +}
5166 +
5167 +static inline void ltq_dma_dcache_wb_inv(const void *ptr, size_t size)
5168 +{
5169 + unsigned long addr = (unsigned long) ptr;
5170 +
5171 + flush_dcache_range(addr, addr + size);
5172 + ltq_dma_sync();
5173 +}
5174 +
5175 +static inline void ltq_dma_dcache_inv(const void *ptr, size_t size)
5176 +{
5177 + unsigned long addr = (unsigned long) ptr;
5178 +
5179 + invalidate_dcache_range(addr, addr + size);
5180 +}
5181 +
5182 +void ltq_dma_init(void)
5183 +{
5184 + /* Power up DMA */
5185 + ltq_pm_enable(LTQ_PM_DMA);
5186 +
5187 + /* Reset DMA */
5188 + ltq_setbits(&ltq_dma_regs->ctrl, DMA_CTRL_RESET);
5189 +
5190 + /* Disable and clear all interrupts */
5191 + ltq_writel(&ltq_dma_regs->irnen, 0);
5192 + ltq_writel(&ltq_dma_regs->irncr, 0xFFFFF);
5193 +
5194 +#if 0
5195 + /* Enable packet arbitration */
5196 + ltq_setbits(&ltq_dma_regs->ctrl, DMA_CTRL_PKTARB);
5197 +#endif
5198 +
5199 +#if 0
5200 + /* Enable descriptor read back */
5201 + ltq_setbits(&ltq_dma_regs->ctrl, DMA_CTRL_DRB);
5202 +#endif
5203 +
5204 + /* Enable polling for descriptor fetching for all channels */
5205 + ltq_writel(&ltq_dma_regs->cpoll, DMA_CPOLL_EN |
5206 + (4 << DMA_CPOLL_CNT_SHIFT));
5207 +}
5208 +
5209 +static void ltq_dma_channel_reset(struct ltq_dma_channel *chan)
5210 +{
5211 + ltq_writel(&ltq_dma_regs->cs, chan->chan_no);
5212 + ltq_setbits(&ltq_dma_regs->cctrl, DMA_CCTRL_RST);
5213 +}
5214 +
5215 +static void ltq_dma_channel_enable(struct ltq_dma_channel *chan)
5216 +{
5217 + ltq_writel(&ltq_dma_regs->cs, chan->chan_no);
5218 + ltq_setbits(&ltq_dma_regs->cctrl, DMA_CCTRL_ONOFF);
5219 +}
5220 +
5221 +static void ltq_dma_channel_disable(struct ltq_dma_channel *chan)
5222 +{
5223 + ltq_writel(&ltq_dma_regs->cs, chan->chan_no);
5224 + ltq_clrbits(&ltq_dma_regs->cctrl, DMA_CCTRL_ONOFF);
5225 +}
5226 +
5227 +static void ltq_dma_port_init(struct ltq_dma_device *dev)
5228 +{
5229 + u32 pctrl;
5230 +
5231 + pctrl = dev->tx_endian_swap << DMA_PCTRL_TXENDI_SHIFT;
5232 + pctrl |= dev->rx_endian_swap << DMA_PCTRL_RXENDI_SHIFT;
5233 + pctrl |= dev->tx_burst_len << DMA_PCTRL_TXBL_SHIFT;
5234 + pctrl |= dev->rx_burst_len << DMA_PCTRL_RXBL_SHIFT;
5235 +
5236 + ltq_writel(&ltq_dma_regs->ps, dev->port);
5237 + ltq_writel(&ltq_dma_regs->pctrl, pctrl);
5238 +}
5239 +
5240 +static int ltq_dma_alloc_descriptors(struct ltq_dma_device *dev,
5241 + struct ltq_dma_channel *chan)
5242 +{
5243 + size_t size;
5244 + void *desc_base;
5245 +
5246 + size = ALIGN(sizeof(struct ltq_dma_desc) * chan->num_desc +
5247 + ARCH_DMA_MINALIGN, ARCH_DMA_MINALIGN);
5248 +
5249 + chan->mem_base = malloc(size);
5250 + if (!chan->mem_base)
5251 + return 1;
5252 +
5253 + memset(chan->mem_base, 0, size);
5254 + ltq_dma_dcache_wb_inv(chan->mem_base, size);
5255 +
5256 + desc_base = PTR_ALIGN(chan->mem_base, ARCH_DMA_MINALIGN);
5257 +
5258 + debug("DMA: mem %p, desc %p\n", chan->mem_base, desc_base);
5259 +
5260 + /* Align descriptor base to 8 bytes */
5261 + chan->desc_base = (void *) CKSEG1ADDR(desc_base);
5262 + chan->dma_addr = CPHYSADDR(desc_base);
5263 + chan->dev = dev;
5264 +
5265 + debug("DMA: desc_base %p, size %u\n", chan->desc_base, size);
5266 +
5267 + /* Configure hardware with location of descriptor list */
5268 + ltq_writel(&ltq_dma_regs->cs, chan->chan_no);
5269 + ltq_writel(&ltq_dma_regs->cdba, chan->dma_addr);
5270 + ltq_writel(&ltq_dma_regs->cdlen, chan->num_desc);
5271 + ltq_writel(&ltq_dma_regs->cctrl, (3 << DMA_CCTRL_TXWGT_SHIFT) |
5272 + (chan->class << DMA_CCTRL_CLASS_SHIFT));
5273 + ltq_writel(&ltq_dma_regs->cctrl, DMA_CCTRL_RST);
5274 +
5275 + return 0;
5276 +}
5277 +
5278 +static void ltq_dma_free_descriptors(struct ltq_dma_channel *chan)
5279 +{
5280 + ltq_writel(&ltq_dma_regs->cs, chan->chan_no);
5281 + ltq_writel(&ltq_dma_regs->cdba, 0);
5282 + ltq_writel(&ltq_dma_regs->cdlen, 0);
5283 +
5284 + ltq_dma_channel_reset(chan);
5285 +
5286 + free(chan->mem_base);
5287 +}
5288 +
5289 +int ltq_dma_register(struct ltq_dma_device *dev)
5290 +{
5291 + int ret;
5292 +
5293 + ltq_dma_port_init(dev);
5294 +
5295 + ret = ltq_dma_alloc_descriptors(dev, &dev->rx_chan);
5296 + if (ret)
5297 + return ret;
5298 +
5299 + ret = ltq_dma_alloc_descriptors(dev, &dev->tx_chan);
5300 + if (ret) {
5301 + ltq_dma_free_descriptors(&dev->rx_chan);
5302 + return ret;
5303 + }
5304 +
5305 + return 0;
5306 +}
5307 +
5308 +void ltq_dma_reset(struct ltq_dma_device *dev)
5309 +{
5310 + ltq_dma_channel_reset(&dev->rx_chan);
5311 + ltq_dma_channel_reset(&dev->tx_chan);
5312 +}
5313 +
5314 +void ltq_dma_enable(struct ltq_dma_device *dev)
5315 +{
5316 + ltq_dma_channel_enable(&dev->rx_chan);
5317 + ltq_dma_channel_enable(&dev->tx_chan);
5318 +}
5319 +
5320 +void ltq_dma_disable(struct ltq_dma_device *dev)
5321 +{
5322 + ltq_dma_channel_disable(&dev->rx_chan);
5323 + ltq_dma_channel_disable(&dev->tx_chan);
5324 +}
5325 +
5326 +int ltq_dma_rx_map(struct ltq_dma_device *dev, int index, void *data, int len)
5327 +{
5328 + struct ltq_dma_channel *chan = &dev->rx_chan;
5329 + struct ltq_dma_desc *desc = &chan->desc_base[index];
5330 + u32 dma_addr = ltq_virt_to_dma_addr(data);
5331 + unsigned int offset;
5332 +
5333 + offset = dma_addr % ltq_dma_burst_align(dev->rx_burst_len);
5334 +
5335 + ltq_dma_dcache_inv(data, len);
5336 +
5337 +#if 0
5338 + printf("%s: index %d, data %p, dma_addr %08x, offset %u, len %d\n",
5339 + __func__, index, data, dma_addr, offset, len);
5340 +#endif
5341 +
5342 +
5343 + desc->addr = dma_addr - offset;
5344 + desc->ctl = DMA_DESC_OWN | DMA_DESC_RX_OFFSET(offset) |
5345 + DMA_DESC_LENGTH(len);
5346 +
5347 +#if 0
5348 + printf("%s: index %d, desc %p, desc->ctl %08x\n",
5349 + __func__, index, desc, desc->ctl);
5350 +#endif
5351 +
5352 + return 0;
5353 +}
5354 +
5355 +int ltq_dma_rx_poll(struct ltq_dma_device *dev, int index)
5356 +{
5357 + struct ltq_dma_channel *chan = &dev->rx_chan;
5358 + struct ltq_dma_desc *desc = &chan->desc_base[index];
5359 +
5360 +#if 0
5361 + printf("%s: index %d, desc %p, desc->ctl %08x\n",
5362 + __func__, index, desc, desc->ctl);
5363 +#endif
5364 +
5365 + if (desc->ctl & DMA_DESC_OWN)
5366 + return 0;
5367 +
5368 + if (desc->ctl & DMA_DESC_C)
5369 + return 1;
5370 +
5371 + return 0;
5372 +}
5373 +
5374 +int ltq_dma_rx_length(struct ltq_dma_device *dev, int index)
5375 +{
5376 + struct ltq_dma_channel *chan = &dev->rx_chan;
5377 + struct ltq_dma_desc *desc = &chan->desc_base[index];
5378 +
5379 + return DMA_DESC_LENGTH(desc->ctl);
5380 +}
5381 +
5382 +int ltq_dma_tx_map(struct ltq_dma_device *dev, int index, void *data, int len,
5383 + unsigned long timeout)
5384 +{
5385 + struct ltq_dma_channel *chan = &dev->tx_chan;
5386 + struct ltq_dma_desc *desc = &chan->desc_base[index];
5387 + unsigned int offset;
5388 + unsigned long timebase = get_timer(0);
5389 + u32 dma_addr = ltq_virt_to_dma_addr(data);
5390 +
5391 + while (desc->ctl & DMA_DESC_OWN) {
5392 + WATCHDOG_RESET();
5393 +
5394 + if (get_timer(timebase) >= timeout) {
5395 +#if 0
5396 + printf("%s: timeout: index %d, desc %p, desc->ctl %08x\n",
5397 + __func__, index, desc, desc->ctl);
5398 +#endif
5399 + return -1;
5400 + }
5401 + }
5402 +
5403 + offset = dma_addr % ltq_dma_burst_align(dev->rx_burst_len);
5404 +
5405 +#if 0
5406 + printf("%s: index %d, desc %p, data %p, dma_addr %08x, offset %u, len %d\n",
5407 + __func__, index, desc, data, dma_addr, offset, len);
5408 +#endif
5409 +
5410 + ltq_dma_dcache_wb_inv(data, len);
5411 +
5412 + desc->addr = dma_addr - offset;
5413 + desc->ctl = DMA_DESC_OWN | DMA_DESC_SOP | DMA_DESC_EOP |
5414 + DMA_DESC_TX_OFFSET(offset) | DMA_DESC_LENGTH(len);
5415 +
5416 +#if 0
5417 + printf("%s: index %d, desc %p, desc->ctl %08x\n",
5418 + __func__, index, desc, desc->ctl);
5419 +#endif
5420 +
5421 + return 0;
5422 +}
5423 +
5424 +int ltq_dma_tx_wait(struct ltq_dma_device *dev, int index,
5425 + unsigned long timeout)
5426 +{
5427 + struct ltq_dma_channel *chan = &dev->tx_chan;
5428 + struct ltq_dma_desc *desc = &chan->desc_base[index];
5429 + unsigned long timebase = get_timer(0);
5430 +
5431 + while ((desc->ctl & (DMA_DESC_OWN | DMA_DESC_C)) != DMA_DESC_C) {
5432 + WATCHDOG_RESET();
5433 +
5434 + if (get_timer(timebase) >= timeout)
5435 + return -1;
5436 + }
5437 +
5438 + return 0;
5439 +}
5440 --- a/drivers/gpio/Makefile
5441 +++ b/drivers/gpio/Makefile
5442 @@ -12,6 +12,7 @@ LIB := $(obj)libgpio.o
5443 COBJS-$(CONFIG_AT91_GPIO) += at91_gpio.o
5444 COBJS-$(CONFIG_INTEL_ICH6_GPIO) += intel_ich6_gpio.o
5445 COBJS-$(CONFIG_KIRKWOOD_GPIO) += kw_gpio.o
5446 +COBJS-$(CONFIG_LANTIQ_GPIO) += lantiq_gpio.o
5447 COBJS-$(CONFIG_MARVELL_GPIO) += mvgpio.o
5448 COBJS-$(CONFIG_MARVELL_MFP) += mvmfp.o
5449 COBJS-$(CONFIG_MXC_GPIO) += mxc_gpio.o
5450 --- /dev/null
5451 +++ b/drivers/gpio/lantiq_gpio.c
5452 @@ -0,0 +1,329 @@
5453 +/*
5454 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
5455 + *
5456 + * SPDX-License-Identifier: GPL-2.0+
5457 + */
5458 +
5459 +#include <common.h>
5460 +#include <asm/arch/soc.h>
5461 +#include <asm/arch/gpio.h>
5462 +#include <asm/lantiq/io.h>
5463 +
5464 +#define SSIO_GPIO_BASE 64
5465 +
5466 +#define SSIO_CON0_SWU (1 << 31)
5467 +#define SSIO_CON0_RZFL (1 << 26)
5468 +#define SSIO_CON0_GPHY1_SHIFT 27
5469 +#define SSIO_CON0_GPHY1_CONFIG ((CONFIG_LTQ_SSIO_GPHY1_MODE & 0x7) << 27)
5470 +
5471 +#define SSIO_CON1_US_FPI (2 << 30)
5472 +#define SSIO_CON1_FPID_2HZ (0 << 23)
5473 +#define SSIO_CON1_FPID_4HZ (1 << 23)
5474 +#define SSIO_CON1_FPID_8HZ (2 << 23)
5475 +#define SSIO_CON1_FPID_10HZ (3 << 23)
5476 +#define SSIO_CON1_FPIS_1_2 (1 << 20)
5477 +#define SSIO_CON1_FPIS_1_32 (2 << 20)
5478 +#define SSIO_CON1_FPIS_1_64 (3 << 20)
5479 +
5480 +#define SSIO_CON1_GPHY2_SHIFT 15
5481 +#define SSIO_CON1_GPHY2_CONFIG ((CONFIG_LTQ_SSIO_GPHY2_MODE & 0x7) << 15)
5482 +
5483 +#define SSIO_CON1_GROUP2 (1 << 2)
5484 +#define SSIO_CON1_GROUP1 (1 << 1)
5485 +#define SSIO_CON1_GROUP0 (1 << 0)
5486 +#define SSIO_CON1_GROUP_CONFIG (0x3)
5487 +
5488 +#ifdef CONFIG_LTQ_SSIO_SHIFT_REGS
5489 +#define enable_ssio 1
5490 +#else
5491 +#define enable_ssio 0
5492 +
5493 +#define CONFIG_LTQ_SSIO_GPHY1_MODE 0
5494 +#define CONFIG_LTQ_SSIO_GPHY2_MODE 0
5495 +#define CONFIG_LTQ_SSIO_INIT_VALUE 0
5496 +#endif
5497 +
5498 +#ifdef CONFIG_LTQ_SSIO_EDGE_FALLING
5499 +#define SSIO_RZFL_CONFIG SSIO_CON0_RZFL
5500 +#else
5501 +#define SSIO_RZFL_CONFIG 0
5502 +#endif
5503 +
5504 +struct ltq_gpio_port_regs {
5505 + __be32 out;
5506 + __be32 in;
5507 + __be32 dir;
5508 + __be32 altsel0;
5509 + __be32 altsel1;
5510 + __be32 od;
5511 + __be32 stoff;
5512 + __be32 pudsel;
5513 + __be32 puden;
5514 + __be32 rsvd1[3];
5515 +};
5516 +
5517 +struct ltq_gpio_regs {
5518 + u32 rsvd[4];
5519 + struct ltq_gpio_port_regs ports[CONFIG_LTQ_GPIO_MAX_BANKS];
5520 +};
5521 +
5522 +struct ltq_gpio3_regs {
5523 + u32 rsvd0[13];
5524 + __be32 od;
5525 + __be32 pudsel;
5526 + __be32 puden;
5527 + u32 rsvd1[9];
5528 + __be32 altsel1;
5529 + u32 rsvd2[14];
5530 + __be32 out;
5531 + __be32 in;
5532 + __be32 dir;
5533 + __be32 altsel0;
5534 +};
5535 +
5536 +struct ltq_ssio_regs {
5537 + __be32 con0;
5538 + __be32 con1;
5539 + __be32 cpu0;
5540 + __be32 cpu1;
5541 + __be32 ar;
5542 +};
5543 +
5544 +static struct ltq_gpio_regs *ltq_gpio_regs =
5545 + (struct ltq_gpio_regs *) CKSEG1ADDR(LTQ_GPIO_BASE);
5546 +
5547 +static struct ltq_gpio3_regs *ltq_gpio3_regs =
5548 + (struct ltq_gpio3_regs *) CKSEG1ADDR(LTQ_GPIO_BASE);
5549 +
5550 +static struct ltq_ssio_regs *ltq_ssio_regs =
5551 + (struct ltq_ssio_regs *) CKSEG1ADDR(LTQ_SSIO_BASE);
5552 +
5553 +static int is_gpio_bank3(unsigned int port)
5554 +{
5555 +#ifdef CONFIG_LTQ_HAS_GPIO_BANK3
5556 + return port == 3;
5557 +#else
5558 + return 0;
5559 +#endif
5560 +}
5561 +
5562 +static int is_gpio_ssio(unsigned int gpio)
5563 +{
5564 +#ifdef CONFIG_LTQ_SSIO_SHIFT_REGS
5565 + return gpio >= SSIO_GPIO_BASE;
5566 +#else
5567 + return 0;
5568 +#endif
5569 +}
5570 +
5571 +static inline int ssio_gpio_to_bit(unsigned gpio)
5572 +{
5573 + return 1 << (gpio - SSIO_GPIO_BASE);
5574 +}
5575 +
5576 +int ltq_gpio_init(void)
5577 +{
5578 + ltq_writel(&ltq_ssio_regs->ar, 0);
5579 + ltq_writel(&ltq_ssio_regs->cpu0, CONFIG_LTQ_SSIO_INIT_VALUE);
5580 + ltq_writel(&ltq_ssio_regs->cpu1, 0);
5581 + ltq_writel(&ltq_ssio_regs->con0, SSIO_CON0_SWU);
5582 +
5583 + if (enable_ssio) {
5584 + ltq_writel(&ltq_ssio_regs->con0, SSIO_CON0_GPHY1_CONFIG |
5585 + SSIO_RZFL_CONFIG);
5586 + ltq_writel(&ltq_ssio_regs->con1, SSIO_CON1_US_FPI |
5587 + SSIO_CON1_FPID_8HZ | SSIO_CON1_GPHY2_CONFIG |
5588 + SSIO_CON1_GROUP_CONFIG);
5589 + }
5590 +
5591 + return 0;
5592 +}
5593 +
5594 +int gpio_request(unsigned gpio, const char *label)
5595 +{
5596 + return 0;
5597 +}
5598 +
5599 +int gpio_free(unsigned gpio)
5600 +{
5601 + return 0;
5602 +}
5603 +
5604 +int gpio_direction_input(unsigned gpio)
5605 +{
5606 + unsigned port = gpio_to_port(gpio);
5607 + const void *gpio_od = &ltq_gpio_regs->ports[port].od;
5608 + const void *gpio_altsel0 = &ltq_gpio_regs->ports[port].altsel0;
5609 + const void *gpio_altsel1 = &ltq_gpio_regs->ports[port].altsel1;
5610 + const void *gpio_dir = &ltq_gpio_regs->ports[port].dir;
5611 +
5612 + if (is_gpio_ssio(gpio))
5613 + return 0;
5614 +
5615 + if (is_gpio_bank3(port)) {
5616 + gpio_od = &ltq_gpio3_regs->od;
5617 + gpio_altsel0 = &ltq_gpio3_regs->altsel0;
5618 + gpio_altsel1 = &ltq_gpio3_regs->altsel1;
5619 + gpio_dir = &ltq_gpio3_regs->dir;
5620 + }
5621 +
5622 + /*
5623 + * Reset open drain and altsel configs to workaround improper
5624 + * reset values or unwanted modifications by BootROM
5625 + */
5626 + ltq_clrbits(gpio_od, gpio_to_bit(gpio));
5627 + ltq_clrbits(gpio_altsel0, gpio_to_bit(gpio));
5628 + ltq_clrbits(gpio_altsel1, gpio_to_bit(gpio));
5629 +
5630 + /* Switch to input */
5631 + ltq_clrbits(gpio_dir, gpio_to_bit(gpio));
5632 +
5633 + return 0;
5634 +}
5635 +
5636 +int gpio_direction_output(unsigned gpio, int value)
5637 +{
5638 + unsigned port = gpio_to_port(gpio);
5639 + const void *gpio_od = &ltq_gpio_regs->ports[port].od;
5640 + const void *gpio_altsel0 = &ltq_gpio_regs->ports[port].altsel0;
5641 + const void *gpio_altsel1 = &ltq_gpio_regs->ports[port].altsel1;
5642 + const void *gpio_dir = &ltq_gpio_regs->ports[port].dir;
5643 + const void *gpio_out = &ltq_gpio_regs->ports[port].out;
5644 + u32 data = gpio_to_bit(gpio);
5645 +
5646 + if (is_gpio_ssio(gpio)) {
5647 + data = ssio_gpio_to_bit(gpio);
5648 + if (value)
5649 + ltq_setbits(&ltq_ssio_regs->cpu0, data);
5650 + else
5651 + ltq_clrbits(&ltq_ssio_regs->cpu0, data);
5652 +
5653 + return 0;
5654 + }
5655 +
5656 + if (is_gpio_bank3(port)) {
5657 + gpio_od = &ltq_gpio3_regs->od;
5658 + gpio_altsel0 = &ltq_gpio3_regs->altsel0;
5659 + gpio_altsel1 = &ltq_gpio3_regs->altsel1;
5660 + gpio_dir = &ltq_gpio3_regs->dir;
5661 + gpio_out = &ltq_gpio3_regs->out;
5662 + }
5663 +
5664 + /*
5665 + * Reset open drain and altsel configs to workaround improper
5666 + * reset values or unwanted modifications by BootROM
5667 + */
5668 + ltq_setbits(gpio_od, data);
5669 + ltq_clrbits(gpio_altsel0, data);
5670 + ltq_clrbits(gpio_altsel1, data);
5671 +
5672 + if (value)
5673 + ltq_setbits(gpio_out, data);
5674 + else
5675 + ltq_clrbits(gpio_out, data);
5676 +
5677 + /* Switch to output */
5678 + ltq_setbits(gpio_dir, data);
5679 +
5680 + return 0;
5681 +}
5682 +
5683 +int gpio_get_value(unsigned gpio)
5684 +{
5685 + unsigned port = gpio_to_port(gpio);
5686 + const void *gpio_in = &ltq_gpio_regs->ports[port].in;
5687 + u32 data = gpio_to_bit(gpio);
5688 + u32 val;
5689 +
5690 + if (is_gpio_ssio(gpio)) {
5691 + gpio_in = &ltq_ssio_regs->cpu0;
5692 + data = ssio_gpio_to_bit(gpio);
5693 + }
5694 +
5695 + if (is_gpio_bank3(port))
5696 + gpio_in = &ltq_gpio3_regs->in;
5697 +
5698 + val = ltq_readl(gpio_in);
5699 +
5700 + return !!(val & data);
5701 +}
5702 +
5703 +int gpio_set_value(unsigned gpio, int value)
5704 +{
5705 + unsigned port = gpio_to_port(gpio);
5706 + const void *gpio_out = &ltq_gpio_regs->ports[port].out;
5707 + u32 data = gpio_to_bit(gpio);
5708 +
5709 + if (is_gpio_ssio(gpio)) {
5710 + gpio_out = &ltq_ssio_regs->cpu0;
5711 + data = ssio_gpio_to_bit(gpio);
5712 + }
5713 +
5714 + if (is_gpio_bank3(port))
5715 + gpio_out = &ltq_gpio3_regs->out;
5716 +
5717 + if (value)
5718 + ltq_setbits(gpio_out, data);
5719 + else
5720 + ltq_clrbits(gpio_out, data);
5721 +
5722 + return 0;
5723 +}
5724 +
5725 +int gpio_set_altfunc(unsigned gpio, int altsel0, int altsel1, int dir)
5726 +{
5727 + unsigned port = gpio_to_port(gpio);
5728 + const void *gpio_od = &ltq_gpio_regs->ports[port].od;
5729 + const void *gpio_altsel0 = &ltq_gpio_regs->ports[port].altsel0;
5730 + const void *gpio_altsel1 = &ltq_gpio_regs->ports[port].altsel1;
5731 + const void *gpio_dir = &ltq_gpio_regs->ports[port].dir;
5732 +
5733 + if (is_gpio_ssio(gpio))
5734 + return 0;
5735 +
5736 + if (is_gpio_bank3(port)) {
5737 + gpio_od = &ltq_gpio3_regs->od;
5738 + gpio_altsel0 = &ltq_gpio3_regs->altsel0;
5739 + gpio_altsel1 = &ltq_gpio3_regs->altsel1;
5740 + gpio_dir = &ltq_gpio3_regs->dir;
5741 + }
5742 +
5743 + if (altsel0)
5744 + ltq_setbits(gpio_altsel0, gpio_to_bit(gpio));
5745 + else
5746 + ltq_clrbits(gpio_altsel0, gpio_to_bit(gpio));
5747 +
5748 + if (altsel1)
5749 + ltq_setbits(gpio_altsel1, gpio_to_bit(gpio));
5750 + else
5751 + ltq_clrbits(gpio_altsel1, gpio_to_bit(gpio));
5752 +
5753 + if (dir) {
5754 + ltq_setbits(gpio_od, gpio_to_bit(gpio));
5755 + ltq_setbits(gpio_dir, gpio_to_bit(gpio));
5756 + } else {
5757 + ltq_clrbits(gpio_od, gpio_to_bit(gpio));
5758 + ltq_clrbits(gpio_dir, gpio_to_bit(gpio));
5759 + }
5760 +
5761 + return 0;
5762 +}
5763 +
5764 +int gpio_set_opendrain(unsigned gpio, int od)
5765 +{
5766 + unsigned port = gpio_to_port(gpio);
5767 + const void *gpio_od = &ltq_gpio_regs->ports[port].od;
5768 +
5769 + if (is_gpio_ssio(gpio))
5770 + return 0;
5771 +
5772 + if (is_gpio_bank3(port))
5773 + gpio_od = &ltq_gpio3_regs->od;
5774 +
5775 + if (od)
5776 + ltq_setbits(gpio_od, gpio_to_bit(gpio));
5777 + else
5778 + ltq_clrbits(gpio_od, gpio_to_bit(gpio));
5779 +
5780 + return 0;
5781 +}
5782 --- a/drivers/mtd/cfi_flash.c
5783 +++ b/drivers/mtd/cfi_flash.c
5784 @@ -161,6 +161,18 @@ u64 flash_read64(void *addr)__attribute_
5785 #define flash_read64 __flash_read64
5786 #endif
5787
5788 +static inline void *__flash_swap_addr(unsigned long addr)
5789 +{
5790 + return (void *) addr;
5791 +}
5792 +
5793 +#ifdef CONFIG_CFI_FLASH_USE_WEAK_ADDR_SWAP
5794 +void *flash_swap_addr(unsigned long addr)
5795 + __attribute__((weak, alias("__flash_swap_addr")));
5796 +#else
5797 +#define flash_swap_addr __flash_swap_addr
5798 +#endif
5799 +
5800 /*-----------------------------------------------------------------------
5801 */
5802 #if defined(CONFIG_ENV_IS_IN_FLASH) || defined(CONFIG_ENV_ADDR_REDUND) || (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
5803 @@ -196,7 +208,7 @@ flash_map (flash_info_t * info, flash_se
5804 {
5805 unsigned int byte_offset = offset * info->portwidth;
5806
5807 - return (void *)(info->start[sect] + byte_offset);
5808 + return flash_swap_addr(info->start[sect] + byte_offset);
5809 }
5810
5811 static inline void flash_unmap(flash_info_t *info, flash_sect_t sect,
5812 --- a/drivers/mtd/nand/Makefile
5813 +++ b/drivers/mtd/nand/Makefile
5814 @@ -53,6 +53,7 @@ COBJS-$(CONFIG_NAND_JZ4740) += jz4740_na
5815 COBJS-$(CONFIG_NAND_KB9202) += kb9202_nand.o
5816 COBJS-$(CONFIG_NAND_KIRKWOOD) += kirkwood_nand.o
5817 COBJS-$(CONFIG_NAND_KMETER1) += kmeter1_nand.o
5818 +COBJS-$(CONFIG_NAND_LANTIQ) += lantiq_nand.o
5819 COBJS-$(CONFIG_NAND_MPC5121_NFC) += mpc5121_nfc.o
5820 COBJS-$(CONFIG_NAND_MXC) += mxc_nand.o
5821 COBJS-$(CONFIG_NAND_MXS) += mxs_nand.o
5822 --- /dev/null
5823 +++ b/drivers/mtd/nand/lantiq_nand.c
5824 @@ -0,0 +1,126 @@
5825 +/*
5826 + * Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
5827 + *
5828 + * SPDX-License-Identifier: GPL-2.0+
5829 + */
5830 +
5831 +#include <common.h>
5832 +#include <linux/mtd/nand.h>
5833 +#include <linux/compiler.h>
5834 +#include <asm/arch/soc.h>
5835 +#include <asm/arch/nand.h>
5836 +#include <asm/lantiq/io.h>
5837 +
5838 +#define NAND_CON_ECC_ON (1 << 31)
5839 +#define NAND_CON_LATCH_PRE (1 << 23)
5840 +#define NAND_CON_LATCH_WP (1 << 22)
5841 +#define NAND_CON_LATCH_SE (1 << 21)
5842 +#define NAND_CON_LATCH_CS (1 << 20)
5843 +#define NAND_CON_LATCH_CLE (1 << 19)
5844 +#define NAND_CON_LATCH_ALE (1 << 18)
5845 +#define NAND_CON_OUT_CS1 (1 << 10)
5846 +#define NAND_CON_IN_CS1 (1 << 8)
5847 +#define NAND_CON_PRE_P (1 << 7)
5848 +#define NAND_CON_WP_P (1 << 6)
5849 +#define NAND_CON_SE_P (1 << 5)
5850 +#define NAND_CON_CS_P (1 << 4)
5851 +#define NAND_CON_CLE_P (1 << 3)
5852 +#define NAND_CON_ALE_P (1 << 2)
5853 +#define NAND_CON_CSMUX (1 << 1)
5854 +#define NAND_CON_NANDM (1 << 0)
5855 +
5856 +#define NAND_WAIT_WR_C (1 << 3)
5857 +#define NAND_WAIT_RDBY (1 << 0)
5858 +
5859 +#define NAND_CMD_ALE (1 << 2)
5860 +#define NAND_CMD_CLE (1 << 3)
5861 +#define NAND_CMD_CS (1 << 4)
5862 +#define NAND_CMD_SE (1 << 5)
5863 +#define NAND_CMD_WP (1 << 6)
5864 +#define NAND_CMD_PRE (1 << 7)
5865 +
5866 +struct ltq_nand_regs {
5867 + __be32 con; /* NAND controller control */
5868 + __be32 wait; /* NAND Flash Device RD/BY State */
5869 + __be32 ecc0; /* NAND Flash ECC Register 0 */
5870 + __be32 ecc_ac; /* NAND Flash ECC Register address counter */
5871 + __be32 ecc_cr; /* NAND Flash ECC Comparison */
5872 +};
5873 +
5874 +static struct ltq_nand_regs *ltq_nand_regs =
5875 + (struct ltq_nand_regs *) CKSEG1ADDR(LTQ_EBU_NAND_BASE);
5876 +
5877 +static void ltq_nand_wait_ready(void)
5878 +{
5879 + while ((ltq_readl(&ltq_nand_regs->wait) & NAND_WAIT_WR_C) == 0)
5880 + ;
5881 +}
5882 +
5883 +static int ltq_nand_dev_ready(struct mtd_info *mtd)
5884 +{
5885 + u32 data = ltq_readl(&ltq_nand_regs->wait);
5886 + return data & NAND_WAIT_RDBY;
5887 +}
5888 +
5889 +static void ltq_nand_select_chip(struct mtd_info *mtd, int chip)
5890 +{
5891 + if (chip == 0) {
5892 + ltq_setbits(&ltq_nand_regs->con, NAND_CON_NANDM);
5893 + ltq_setbits(&ltq_nand_regs->con, NAND_CON_LATCH_CS);
5894 + } else {
5895 + ltq_clrbits(&ltq_nand_regs->con, NAND_CON_LATCH_CS);
5896 + ltq_clrbits(&ltq_nand_regs->con, NAND_CON_NANDM);
5897 + }
5898 +}
5899 +
5900 +static void ltq_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
5901 +{
5902 + struct nand_chip *chip = mtd->priv;
5903 + unsigned long addr = (unsigned long) chip->IO_ADDR_W;
5904 +
5905 + if (ctrl & NAND_CTRL_CHANGE) {
5906 + if (ctrl & NAND_ALE)
5907 + addr |= NAND_CMD_ALE;
5908 + else
5909 + addr &= ~NAND_CMD_ALE;
5910 +
5911 + if (ctrl & NAND_CLE)
5912 + addr |= NAND_CMD_CLE;
5913 + else
5914 + addr &= ~NAND_CMD_CLE;
5915 +
5916 + chip->IO_ADDR_W = (void __iomem *) addr;
5917 + }
5918 +
5919 + if (cmd != NAND_CMD_NONE) {
5920 + writeb(cmd, chip->IO_ADDR_W);
5921 + ltq_nand_wait_ready();
5922 + }
5923 +}
5924 +
5925 +int ltq_nand_init(struct nand_chip *nand)
5926 +{
5927 + /* Enable NAND, set NAND CS to EBU CS1, enable EBU CS mux */
5928 + ltq_writel(&ltq_nand_regs->con, NAND_CON_OUT_CS1 | NAND_CON_IN_CS1 |
5929 + NAND_CON_PRE_P | NAND_CON_WP_P | NAND_CON_SE_P |
5930 + NAND_CON_CS_P | NAND_CON_CSMUX);
5931 +
5932 + nand->dev_ready = ltq_nand_dev_ready;
5933 + nand->select_chip = ltq_nand_select_chip;
5934 + nand->cmd_ctrl = ltq_nand_cmd_ctrl;
5935 +
5936 + nand->chip_delay = 30;
5937 + nand->options = 0;
5938 + nand->ecc.mode = NAND_ECC_SOFT;
5939 +
5940 + /* Enable CS bit in address offset */
5941 + nand->IO_ADDR_R = nand->IO_ADDR_R + NAND_CMD_CS;
5942 + nand->IO_ADDR_W = nand->IO_ADDR_W + NAND_CMD_CS;
5943 +
5944 + return 0;
5945 +}
5946 +
5947 +__weak int board_nand_init(struct nand_chip *chip)
5948 +{
5949 + return ltq_nand_init(chip);
5950 +}
5951 --- a/drivers/net/Makefile
5952 +++ b/drivers/net/Makefile
5953 @@ -37,6 +37,8 @@ COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-i
5954 COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o
5955 COBJS-$(CONFIG_KS8851_MLL) += ks8851_mll.o
5956 COBJS-$(CONFIG_LAN91C96) += lan91c96.o
5957 +COBJS-$(CONFIG_LANTIQ_DANUBE_ETOP) += lantiq_danube_etop.o
5958 +COBJS-$(CONFIG_LANTIQ_VRX200_SWITCH) += lantiq_vrx200_switch.o
5959 COBJS-$(CONFIG_MACB) += macb.o
5960 COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o
5961 COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o
5962 --- /dev/null
5963 +++ b/drivers/net/lantiq_danube_etop.c
5964 @@ -0,0 +1,410 @@
5965 +/*
5966 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
5967 + *
5968 + * SPDX-License-Identifier: GPL-2.0+
5969 + */
5970 +
5971 +#include <common.h>
5972 +#include <malloc.h>
5973 +#include <netdev.h>
5974 +#include <miiphy.h>
5975 +#include <switch.h>
5976 +#include <asm/lantiq/io.h>
5977 +#include <asm/lantiq/eth.h>
5978 +#include <asm/lantiq/pm.h>
5979 +#include <asm/lantiq/reset.h>
5980 +#include <asm/lantiq/dma.h>
5981 +#include <asm/arch/soc.h>
5982 +
5983 +#define LTQ_PPE_ETOP_MDIO_ACC_RA (1 << 31)
5984 +#define LTQ_PPE_ETOP_MDIO_CFG_UMM1 (1 << 2)
5985 +#define LTQ_PPE_ETOP_MDIO_CFG_UMM0 (1 << 1)
5986 +
5987 +#define LTQ_PPE_ETOP_CFG_TCKINV1 (1 << 11)
5988 +#define LTQ_PPE_ETOP_CFG_TCKINV0 (1 << 10)
5989 +#define LTQ_PPE_ETOP_CFG_FEN1 (1 << 9)
5990 +#define LTQ_PPE_ETOP_CFG_FEN0 (1 << 8)
5991 +#define LTQ_PPE_ETOP_CFG_SEN1 (1 << 7)
5992 +#define LTQ_PPE_ETOP_CFG_SEN0 (1 << 6)
5993 +#define LTQ_PPE_ETOP_CFG_TURBO1 (1 << 5)
5994 +#define LTQ_PPE_ETOP_CFG_REMII1 (1 << 4)
5995 +#define LTQ_PPE_ETOP_CFG_OFF1 (1 << 3)
5996 +#define LTQ_PPE_ETOP_CFG_TURBO0 (1 << 2)
5997 +#define LTQ_PPE_ETOP_CFG_REMII0 (1 << 1)
5998 +#define LTQ_PPE_ETOP_CFG_OFF0 (1 << 0)
5999 +
6000 +#define LTQ_PPE_ENET0_MAC_CFG_CGEN (1 << 11)
6001 +#define LTQ_PPE_ENET0_MAC_CFG_DUPLEX (1 << 2)
6002 +#define LTQ_PPE_ENET0_MAC_CFG_SPEED (1 << 1)
6003 +#define LTQ_PPE_ENET0_MAC_CFG_LINK (1 << 0)
6004 +
6005 +#define LTQ_PPE_ENETS0_CFG_FTUC (1 << 28)
6006 +
6007 +#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX
6008 +#define LTQ_ETH_TX_BUFFER_CNT 8
6009 +#define LTQ_ETH_RX_DATA_SIZE PKTSIZE_ALIGN
6010 +#define LTQ_ETH_IP_ALIGN 2
6011 +
6012 +#define LTQ_MDIO_DRV_NAME "ltq-mdio"
6013 +#define LTQ_ETH_DRV_NAME "ltq-eth"
6014 +
6015 +struct ltq_ppe_etop_regs {
6016 + u32 mdio_cfg; /* MDIO configuration */
6017 + u32 mdio_acc; /* MDIO access */
6018 + u32 cfg; /* ETOP configuration */
6019 + u32 ig_vlan_cos; /* IG VLAN priority CoS mapping */
6020 + u32 ig_dscp_cos3; /* IG DSCP CoS mapping 3 */
6021 + u32 ig_dscp_cos2; /* IG DSCP CoS mapping 2 */
6022 + u32 ig_dscp_cos1; /* IG DSCP CoS mapping 1 */
6023 + u32 ig_dscp_cos0; /* IG DSCP CoS mapping 0 */
6024 + u32 ig_plen_ctrl; /* IG frame length control */
6025 + u32 rsvd0[3];
6026 + u32 vpid; /* VLAN protocol ID */
6027 +};
6028 +
6029 +struct ltq_ppe_enet_regs {
6030 + u32 mac_cfg; /* MAC configuration */
6031 + u32 rsvd0[3];
6032 + u32 ig_cfg; /* Ingress configuration */
6033 + u32 ig_pgcnt; /* Ingress buffer used page count */
6034 + u32 rsvd1;
6035 + u32 ig_buf_ctrl; /* Ingress buffer backpressure ctrl */
6036 + u32 cos_cfg; /* Classification configuration */
6037 + u32 ig_drop; /* Total ingress drop frames */
6038 + u32 ig_err; /* Total ingress error frames */
6039 + u32 mac_da0; /* Ingress MAC address 0 */
6040 + u32 mac_da1; /* Ingress MAC address 1 */
6041 + u32 rsvd2[22];
6042 + u32 pgcnt; /* Page counter */
6043 + u32 rsvd3;
6044 + u32 hf_ctrl; /* Half duplex control */
6045 + u32 tx_ctrl; /* Transmit control */
6046 + u32 rsvd4;
6047 + u32 vlcos0; /* VLAN insertion config CoS 0 */
6048 + u32 vlcos1; /* VLAN insertion config CoS 1 */
6049 + u32 vlcos2; /* VLAN insertion config CoS 2 */
6050 + u32 vlcos3; /* VLAN insertion config CoS 3 */
6051 + u32 eg_col; /* Total egress collision frames */
6052 + u32 eg_drop; /* Total egress drop frames */
6053 +};
6054 +
6055 +struct ltq_eth_priv {
6056 + struct ltq_dma_device dma_dev;
6057 + struct mii_dev *bus;
6058 + struct eth_device *dev;
6059 + int rx_num;
6060 + int tx_num;
6061 +};
6062 +
6063 +struct ltq_mdio_access {
6064 + union {
6065 + struct {
6066 + unsigned ra:1;
6067 + unsigned rw:1;
6068 + unsigned rsvd:4;
6069 + unsigned phya:5;
6070 + unsigned rega:5;
6071 + unsigned phyd:16;
6072 + } reg;
6073 + u32 val;
6074 + };
6075 +};
6076 +
6077 +static struct ltq_ppe_etop_regs *ltq_ppe_etop_regs =
6078 + (struct ltq_ppe_etop_regs *) CKSEG1ADDR(LTQ_PPE_ETOP_BASE);
6079 +
6080 +static struct ltq_ppe_enet_regs *ltq_ppe_enet0_regs =
6081 + (struct ltq_ppe_enet_regs *) CKSEG1ADDR(LTQ_PPE_ENET0_BASE);
6082 +
6083 +static inline int ltq_mdio_poll(void)
6084 +{
6085 + struct ltq_mdio_access acc;
6086 + unsigned cnt = 10000;
6087 +
6088 + while (likely(cnt--)) {
6089 + acc.val = ltq_readl(&ltq_ppe_etop_regs->mdio_acc);
6090 + if (!acc.reg.ra)
6091 + return 0;
6092 + }
6093 +
6094 + return 1;
6095 +}
6096 +
6097 +static int ltq_mdio_read(struct mii_dev *bus, int addr, int dev_addr,
6098 + int regnum)
6099 +{
6100 + struct ltq_mdio_access acc;
6101 + int ret;
6102 +
6103 + acc.val = 0;
6104 + acc.reg.ra = 1;
6105 + acc.reg.rw = 1;
6106 + acc.reg.phya = addr;
6107 + acc.reg.rega = regnum;
6108 +
6109 + ret = ltq_mdio_poll();
6110 + if (ret)
6111 + return ret;
6112 +
6113 + ltq_writel(&ltq_ppe_etop_regs->mdio_acc, acc.val);
6114 +
6115 + ret = ltq_mdio_poll();
6116 + if (ret)
6117 + return ret;
6118 +
6119 + acc.val = ltq_readl(&ltq_ppe_etop_regs->mdio_acc);
6120 +
6121 + return acc.reg.phyd;
6122 +}
6123 +
6124 +static int ltq_mdio_write(struct mii_dev *bus, int addr, int dev_addr,
6125 + int regnum, u16 val)
6126 +{
6127 + struct ltq_mdio_access acc;
6128 + int ret;
6129 +
6130 + acc.val = 0;
6131 + acc.reg.ra = 1;
6132 + acc.reg.rw = 0;
6133 + acc.reg.phya = addr;
6134 + acc.reg.rega = regnum;
6135 + acc.reg.phyd = val;
6136 +
6137 + ret = ltq_mdio_poll();
6138 + if (ret)
6139 + return ret;
6140 +
6141 + ltq_writel(&ltq_ppe_etop_regs->mdio_acc, acc.val);
6142 +
6143 + return 0;
6144 +}
6145 +
6146 +static inline void ltq_eth_write_hwaddr(const struct eth_device *dev)
6147 +{
6148 + u32 da0, da1;
6149 +
6150 + da0 = (dev->enetaddr[0] << 24) + (dev->enetaddr[1] << 16) +
6151 + (dev->enetaddr[2] << 8) + dev->enetaddr[3];
6152 + da1 = (dev->enetaddr[4] << 24) + (dev->enetaddr[5] << 16);
6153 +
6154 + ltq_writel(&ltq_ppe_enet0_regs->mac_da0, da0);
6155 + ltq_writel(&ltq_ppe_enet0_regs->mac_da1, da1);
6156 +}
6157 +
6158 +static inline u8 *ltq_eth_rx_packet_align(int rx_num)
6159 +{
6160 + u8 *packet = (u8 *) NetRxPackets[rx_num];
6161 +
6162 + /*
6163 + * IP header needs
6164 + */
6165 + return packet + LTQ_ETH_IP_ALIGN;
6166 +}
6167 +
6168 +static int ltq_eth_init(struct eth_device *dev, bd_t *bis)
6169 +{
6170 + struct ltq_eth_priv *priv = dev->priv;
6171 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6172 + int i;
6173 +
6174 + ltq_eth_write_hwaddr(dev);
6175 +
6176 + for (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)
6177 + ltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),
6178 + LTQ_ETH_RX_DATA_SIZE);
6179 +
6180 + ltq_dma_enable(dma_dev);
6181 +
6182 + priv->rx_num = 0;
6183 + priv->tx_num = 0;
6184 +
6185 + return 0;
6186 +}
6187 +
6188 +static void ltq_eth_halt(struct eth_device *dev)
6189 +{
6190 + struct ltq_eth_priv *priv = dev->priv;
6191 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6192 +
6193 + ltq_dma_reset(dma_dev);
6194 +}
6195 +
6196 +static int ltq_eth_send(struct eth_device *dev, void *packet, int length)
6197 +{
6198 + struct ltq_eth_priv *priv = dev->priv;
6199 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6200 + int err;
6201 +
6202 + /* Minimum payload length w/ CRC is 60 bytes */
6203 + if (length < 60)
6204 + length = 60;
6205 +
6206 + err = ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);
6207 + if (err) {
6208 + puts("NET: timeout on waiting for TX descriptor\n");
6209 + return -1;
6210 + }
6211 +
6212 + priv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;
6213 +
6214 + return err;
6215 +}
6216 +
6217 +static int ltq_eth_recv(struct eth_device *dev)
6218 +{
6219 + struct ltq_eth_priv *priv = dev->priv;
6220 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6221 + u8 *packet;
6222 + int len;
6223 +
6224 + if (!ltq_dma_rx_poll(dma_dev, priv->rx_num))
6225 + return 0;
6226 +
6227 +#if 0
6228 + printf("%s: rx_num %d\n", __func__, priv->rx_num);
6229 +#endif
6230 +
6231 + len = ltq_dma_rx_length(dma_dev, priv->rx_num);
6232 + packet = ltq_eth_rx_packet_align(priv->rx_num);
6233 +
6234 +#if 0
6235 + printf("%s: received: packet %p, len %u, rx_num %d\n",
6236 + __func__, packet, len, priv->rx_num);
6237 +#endif
6238 +
6239 + if (len)
6240 + NetReceive(packet, len);
6241 +
6242 + ltq_dma_rx_map(dma_dev, priv->rx_num, packet,
6243 + LTQ_ETH_RX_DATA_SIZE);
6244 +
6245 + priv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;
6246 +
6247 + return 0;
6248 +}
6249 +
6250 +static void ltq_eth_hw_init(const struct ltq_eth_port_config *port)
6251 +{
6252 + u32 data;
6253 +
6254 + /* Power up ethernet subsystems */
6255 + ltq_pm_enable(LTQ_PM_ETH);
6256 +
6257 + /* Reset ethernet subsystems */
6258 + ltq_reset_once(LTQ_RESET_ETH, 1);
6259 +
6260 + /* Disable MDIO auto-detection */
6261 + ltq_clrbits(&ltq_ppe_etop_regs->mdio_cfg, LTQ_PPE_ETOP_MDIO_CFG_UMM1 |
6262 + LTQ_PPE_ETOP_MDIO_CFG_UMM0);
6263 +
6264 + /* Enable CRC generation, Full Duplex, 100Mbps, Link up */
6265 + ltq_writel(&ltq_ppe_enet0_regs->mac_cfg, LTQ_PPE_ENET0_MAC_CFG_CGEN |
6266 + LTQ_PPE_ENET0_MAC_CFG_DUPLEX |
6267 + LTQ_PPE_ENET0_MAC_CFG_SPEED |
6268 + LTQ_PPE_ENET0_MAC_CFG_LINK);
6269 +
6270 + /* Reset ETOP cfg and disable all */
6271 + data = LTQ_PPE_ETOP_CFG_OFF0 | LTQ_PPE_ETOP_CFG_OFF1;
6272 +
6273 + /* Enable ENET0, enable store and fetch */
6274 + data &= ~LTQ_PPE_ETOP_CFG_OFF0;
6275 + data |= LTQ_PPE_ETOP_CFG_SEN0 | LTQ_PPE_ETOP_CFG_FEN0;
6276 +
6277 + if (port->phy_if == PHY_INTERFACE_MODE_RMII)
6278 + data |= LTQ_PPE_ETOP_CFG_REMII0;
6279 + else
6280 + data &= ~LTQ_PPE_ETOP_CFG_REMII0;
6281 +
6282 + ltq_writel(&ltq_ppe_etop_regs->cfg, data);
6283 +
6284 + /* Set allowed packet length from 64 bytes to 1518 bytes */
6285 + ltq_writel(&ltq_ppe_etop_regs->ig_plen_ctrl, (64 << 16) | 1518);
6286 +
6287 + /* Enable filter for unicast packets */
6288 + ltq_setbits(&ltq_ppe_enet0_regs->ig_cfg, LTQ_PPE_ENETS0_CFG_FTUC);
6289 +}
6290 +
6291 +int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)
6292 +{
6293 + struct eth_device *dev;
6294 + struct mii_dev *bus;
6295 + struct ltq_eth_priv *priv;
6296 + struct ltq_dma_device *dma_dev;
6297 + const struct ltq_eth_port_config *port = &board_config->ports[0];
6298 + struct phy_device *phy;
6299 + struct switch_device *sw;
6300 + int ret;
6301 +
6302 + ltq_dma_init();
6303 + ltq_eth_hw_init(port);
6304 +
6305 + dev = calloc(1, sizeof(*dev));
6306 + if (!dev)
6307 + return -1;
6308 +
6309 + priv = calloc(1, sizeof(*priv));
6310 + if (!priv)
6311 + return -1;
6312 +
6313 + bus = mdio_alloc();
6314 + if (!bus)
6315 + return -1;
6316 +
6317 + sprintf(dev->name, LTQ_ETH_DRV_NAME);
6318 + dev->priv = priv;
6319 + dev->init = ltq_eth_init;
6320 + dev->halt = ltq_eth_halt;
6321 + dev->recv = ltq_eth_recv;
6322 + dev->send = ltq_eth_send;
6323 +
6324 + sprintf(bus->name, LTQ_MDIO_DRV_NAME);
6325 + bus->read = ltq_mdio_read;
6326 + bus->write = ltq_mdio_write;
6327 + bus->priv = priv;
6328 +
6329 + dma_dev = &priv->dma_dev;
6330 + dma_dev->port = 0;
6331 + dma_dev->rx_chan.chan_no = 6;
6332 + dma_dev->rx_chan.class = 3;
6333 + dma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;
6334 + dma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
6335 + dma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;
6336 + dma_dev->tx_chan.chan_no = 7;
6337 + dma_dev->tx_chan.class = 3;
6338 + dma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;
6339 + dma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
6340 + dma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;
6341 +
6342 + priv->bus = bus;
6343 + priv->dev = dev;
6344 +
6345 + ret = ltq_dma_register(dma_dev);
6346 + if (ret)
6347 + return ret;
6348 +
6349 + ret = mdio_register(bus);
6350 + if (ret)
6351 + return ret;
6352 +
6353 + ret = eth_register(dev);
6354 + if (ret)
6355 + return ret;
6356 +
6357 + if (port->flags & LTQ_ETH_PORT_SWITCH) {
6358 + sw = switch_connect(bus);
6359 + if (!sw)
6360 + return -1;
6361 +
6362 + switch_setup(sw);
6363 + }
6364 +
6365 + if (port->flags & LTQ_ETH_PORT_PHY) {
6366 + phy = phy_connect(bus, port->phy_addr, dev, port->phy_if);
6367 + if (!phy)
6368 + return -1;
6369 +
6370 + phy_config(phy);
6371 + }
6372 +
6373 + return 0;
6374 +}
6375 --- /dev/null
6376 +++ b/drivers/net/lantiq_vrx200_switch.c
6377 @@ -0,0 +1,675 @@
6378 +/*
6379 + * Copyright (C) 2010-2011 Lantiq Deutschland GmbH
6380 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
6381 + *
6382 + * SPDX-License-Identifier: GPL-2.0+
6383 + */
6384 +
6385 +#define DEBUG
6386 +
6387 +#include <common.h>
6388 +#include <malloc.h>
6389 +#include <netdev.h>
6390 +#include <miiphy.h>
6391 +#include <linux/compiler.h>
6392 +#include <asm/gpio.h>
6393 +#include <asm/processor.h>
6394 +#include <asm/lantiq/io.h>
6395 +#include <asm/lantiq/eth.h>
6396 +#include <asm/lantiq/pm.h>
6397 +#include <asm/lantiq/reset.h>
6398 +#include <asm/lantiq/dma.h>
6399 +#include <asm/arch/soc.h>
6400 +#include <asm/arch/switch.h>
6401 +
6402 +#define LTQ_ETH_RX_BUFFER_CNT PKTBUFSRX
6403 +#define LTQ_ETH_TX_BUFFER_CNT 8
6404 +#define LTQ_ETH_RX_DATA_SIZE PKTSIZE_ALIGN
6405 +#define LTQ_ETH_IP_ALIGN 2
6406 +
6407 +#define LTQ_MDIO_DRV_NAME "ltq-mdio"
6408 +#define LTQ_ETH_DRV_NAME "ltq-eth"
6409 +
6410 +#define LTQ_ETHSW_MAX_GMAC 6
6411 +#define LTQ_ETHSW_PMAC 6
6412 +
6413 +struct ltq_mdio_phy_addr_reg {
6414 + union {
6415 + struct {
6416 + unsigned rsvd:1;
6417 + unsigned lnkst:2; /* Link status control */
6418 + unsigned speed:2; /* Speed control */
6419 + unsigned fdup:2; /* Full duplex control */
6420 + unsigned fcontx:2; /* Flow control mode TX */
6421 + unsigned fconrx:2; /* Flow control mode RX */
6422 + unsigned addr:5; /* PHY address */
6423 + } bits;
6424 + u16 val;
6425 + };
6426 +};
6427 +
6428 +enum ltq_mdio_phy_addr_lnkst {
6429 + LTQ_MDIO_PHY_ADDR_LNKST_AUTO = 0,
6430 + LTQ_MDIO_PHY_ADDR_LNKST_UP = 1,
6431 + LTQ_MDIO_PHY_ADDR_LNKST_DOWN = 2,
6432 +};
6433 +
6434 +enum ltq_mdio_phy_addr_speed {
6435 + LTQ_MDIO_PHY_ADDR_SPEED_M10 = 0,
6436 + LTQ_MDIO_PHY_ADDR_SPEED_M100 = 1,
6437 + LTQ_MDIO_PHY_ADDR_SPEED_G1 = 2,
6438 + LTQ_MDIO_PHY_ADDR_SPEED_AUTO = 3,
6439 +};
6440 +
6441 +enum ltq_mdio_phy_addr_fdup {
6442 + LTQ_MDIO_PHY_ADDR_FDUP_AUTO = 0,
6443 + LTQ_MDIO_PHY_ADDR_FDUP_ENABLE = 1,
6444 + LTQ_MDIO_PHY_ADDR_FDUP_DISABLE = 3,
6445 +};
6446 +
6447 +enum ltq_mdio_phy_addr_fcon {
6448 + LTQ_MDIO_PHY_ADDR_FCON_AUTO = 0,
6449 + LTQ_MDIO_PHY_ADDR_FCON_ENABLE = 1,
6450 + LTQ_MDIO_PHY_ADDR_FCON_DISABLE = 3,
6451 +};
6452 +
6453 +struct ltq_mii_mii_cfg_reg {
6454 + union {
6455 + struct {
6456 + unsigned res:1; /* Hardware reset */
6457 + unsigned en:1; /* xMII interface enable */
6458 + unsigned isol:1; /* xMII interface isolate */
6459 + unsigned ldclkdis:1; /* Link down clock disable */
6460 + unsigned rsvd:1;
6461 + unsigned crs:2; /* CRS sensitivity config */
6462 + unsigned rgmii_ibs:1; /* RGMII In Band status */
6463 + unsigned rmii:1; /* RMII ref clock direction */
6464 + unsigned miirate:3; /* xMII interface clock rate */
6465 + unsigned miimode:4; /* xMII interface mode */
6466 + } bits;
6467 + u16 val;
6468 + };
6469 +};
6470 +
6471 +enum ltq_mii_mii_cfg_miirate {
6472 + LTQ_MII_MII_CFG_MIIRATE_M2P5 = 0,
6473 + LTQ_MII_MII_CFG_MIIRATE_M25 = 1,
6474 + LTQ_MII_MII_CFG_MIIRATE_M125 = 2,
6475 + LTQ_MII_MII_CFG_MIIRATE_M50 = 3,
6476 + LTQ_MII_MII_CFG_MIIRATE_AUTO = 4,
6477 +};
6478 +
6479 +enum ltq_mii_mii_cfg_miimode {
6480 + LTQ_MII_MII_CFG_MIIMODE_MIIP = 0,
6481 + LTQ_MII_MII_CFG_MIIMODE_MIIM = 1,
6482 + LTQ_MII_MII_CFG_MIIMODE_RMIIP = 2,
6483 + LTQ_MII_MII_CFG_MIIMODE_RMIIM = 3,
6484 + LTQ_MII_MII_CFG_MIIMODE_RGMII = 4,
6485 +};
6486 +
6487 +struct ltq_eth_priv {
6488 + struct ltq_dma_device dma_dev;
6489 + struct mii_dev *bus;
6490 + struct eth_device *dev;
6491 + struct phy_device *phymap[LTQ_ETHSW_MAX_GMAC];
6492 + int rx_num;
6493 + int tx_num;
6494 +};
6495 +
6496 +static struct vr9_switch_regs *switch_regs =
6497 + (struct vr9_switch_regs *) CKSEG1ADDR(LTQ_SWITCH_BASE);
6498 +
6499 +static inline void vr9_switch_sync(void)
6500 +{
6501 + __asm__("sync");
6502 +}
6503 +
6504 +static inline int vr9_switch_mdio_is_busy(void)
6505 +{
6506 + u32 mdio_ctrl = ltq_readl(&switch_regs->mdio.mdio_ctrl);
6507 +
6508 + return mdio_ctrl & MDIO_CTRL_MBUSY;
6509 +}
6510 +
6511 +static inline void vr9_switch_mdio_poll(void)
6512 +{
6513 + while (vr9_switch_mdio_is_busy())
6514 + cpu_relax();
6515 +}
6516 +
6517 +static int vr9_switch_mdio_read(struct mii_dev *bus, int phyad, int devad,
6518 + int regad)
6519 +{
6520 + u32 mdio_ctrl;
6521 + int retval;
6522 +
6523 + mdio_ctrl = MDIO_CTRL_OP_READ |
6524 + ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
6525 + (regad & MDIO_CTRL_REGAD_MASK);
6526 +
6527 + vr9_switch_mdio_poll();
6528 + ltq_writel(&switch_regs->mdio.mdio_ctrl, mdio_ctrl);
6529 + vr9_switch_mdio_poll();
6530 + retval = ltq_readl(&switch_regs->mdio.mdio_read);
6531 +
6532 + return retval;
6533 +}
6534 +
6535 +static int vr9_switch_mdio_write(struct mii_dev *bus, int phyad, int devad,
6536 + int regad, u16 val)
6537 +{
6538 + u32 mdio_ctrl;
6539 +
6540 + mdio_ctrl = MDIO_CTRL_OP_WRITE |
6541 + ((phyad << MDIO_CTRL_PHYAD_SHIFT) & MDIO_CTRL_PHYAD_MASK) |
6542 + (regad & MDIO_CTRL_REGAD_MASK);
6543 +
6544 + vr9_switch_mdio_poll();
6545 + ltq_writel(&switch_regs->mdio.mdio_write, val);
6546 + ltq_writel(&switch_regs->mdio.mdio_ctrl, mdio_ctrl);
6547 +
6548 + return 0;
6549 +}
6550 +
6551 +static void ltq_eth_gmac_update(struct phy_device *phydev, int num)
6552 +{
6553 + struct ltq_mdio_phy_addr_reg phy_addr_reg;
6554 + struct ltq_mii_mii_cfg_reg mii_cfg_reg;
6555 +
6556 + phy_addr_reg.val = ltq_readl(to_mdio_phyaddr(switch_regs, num));
6557 +
6558 + switch (num) {
6559 + case 0:
6560 + case 1:
6561 + case 5:
6562 + mii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs, num));
6563 + break;
6564 + default:
6565 + mii_cfg_reg.val = 0;
6566 + break;
6567 + }
6568 +
6569 + phy_addr_reg.bits.addr = phydev->addr;
6570 +
6571 + if (phydev->link)
6572 + phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_UP;
6573 + else
6574 + phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;
6575 +
6576 + switch (phydev->speed) {
6577 + case SPEED_1000:
6578 + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_G1;
6579 + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M125;
6580 + break;
6581 + case SPEED_100:
6582 + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M100;
6583 + switch (mii_cfg_reg.bits.miimode) {
6584 + case LTQ_MII_MII_CFG_MIIMODE_RMIIM:
6585 + case LTQ_MII_MII_CFG_MIIMODE_RMIIP:
6586 + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M50;
6587 + break;
6588 + default:
6589 + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M25;
6590 + break;
6591 + }
6592 + break;
6593 + default:
6594 + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;
6595 + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;
6596 + break;
6597 + }
6598 +
6599 + if (phydev->duplex == DUPLEX_FULL)
6600 + phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_ENABLE;
6601 + else
6602 + phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;
6603 +
6604 + ltq_writel(to_mdio_phyaddr(switch_regs, num), phy_addr_reg.val);
6605 +
6606 + switch (num) {
6607 + case 0:
6608 + case 1:
6609 + case 5:
6610 + ltq_writel(to_mii_miicfg(switch_regs, num), mii_cfg_reg.val);
6611 + break;
6612 + default:
6613 + break;
6614 + }
6615 +}
6616 +
6617 +static inline u8 *ltq_eth_rx_packet_align(int rx_num)
6618 +{
6619 + u8 *packet = (u8 *) NetRxPackets[rx_num];
6620 +
6621 + /*
6622 + * IP header needs
6623 + */
6624 + return packet + LTQ_ETH_IP_ALIGN;
6625 +}
6626 +
6627 +static int ltq_eth_init(struct eth_device *dev, bd_t *bis)
6628 +{
6629 + struct ltq_eth_priv *priv = dev->priv;
6630 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6631 + struct phy_device *phydev;
6632 + int i;
6633 +
6634 + for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
6635 + phydev = priv->phymap[i];
6636 + if (!phydev)
6637 + continue;
6638 +
6639 + phy_startup(phydev);
6640 + ltq_eth_gmac_update(phydev, i);
6641 + }
6642 +
6643 + for (i = 0; i < LTQ_ETH_RX_BUFFER_CNT; i++)
6644 + ltq_dma_rx_map(dma_dev, i, ltq_eth_rx_packet_align(i),
6645 + LTQ_ETH_RX_DATA_SIZE);
6646 +
6647 + ltq_dma_enable(dma_dev);
6648 +
6649 + priv->rx_num = 0;
6650 + priv->tx_num = 0;
6651 +
6652 + return 0;
6653 +}
6654 +
6655 +static void ltq_eth_halt(struct eth_device *dev)
6656 +{
6657 + struct ltq_eth_priv *priv = dev->priv;
6658 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6659 + struct phy_device *phydev;
6660 + int i;
6661 +
6662 + ltq_dma_reset(dma_dev);
6663 +
6664 + for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++) {
6665 + phydev = priv->phymap[i];
6666 + if (!phydev)
6667 + continue;
6668 +
6669 + phy_shutdown(phydev);
6670 + phydev->link = 0;
6671 + ltq_eth_gmac_update(phydev, i);
6672 + }
6673 +}
6674 +
6675 +static int ltq_eth_send(struct eth_device *dev, void *packet, int length)
6676 +{
6677 + struct ltq_eth_priv *priv = dev->priv;
6678 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6679 +
6680 +#if 0
6681 + printf("%s: packet %p, len %d\n", __func__, packet, length);
6682 +#endif
6683 +
6684 + ltq_dma_tx_map(dma_dev, priv->tx_num, packet, length, 10);
6685 + priv->tx_num = (priv->tx_num + 1) % LTQ_ETH_TX_BUFFER_CNT;
6686 +
6687 + return 0;
6688 +}
6689 +
6690 +static int ltq_eth_recv(struct eth_device *dev)
6691 +{
6692 + struct ltq_eth_priv *priv = dev->priv;
6693 + struct ltq_dma_device *dma_dev = &priv->dma_dev;
6694 + u8 *packet;
6695 + int len;
6696 +
6697 + if (!ltq_dma_rx_poll(dma_dev, priv->rx_num))
6698 + return 0;
6699 +
6700 +#if 0
6701 + printf("%s: rx_num %d\n", __func__, priv->rx_num);
6702 +#endif
6703 +
6704 + len = ltq_dma_rx_length(dma_dev, priv->rx_num);
6705 + packet = ltq_eth_rx_packet_align(priv->rx_num);
6706 +
6707 +#if 0
6708 + printf("%s: received: packet %p, len %u, rx_num %d\n",
6709 + __func__, packet, len, priv->rx_num);
6710 +#endif
6711 +
6712 + if (len)
6713 + NetReceive(packet, len);
6714 +
6715 + ltq_dma_rx_map(dma_dev, priv->rx_num, packet,
6716 + LTQ_ETH_RX_DATA_SIZE);
6717 +
6718 + priv->rx_num = (priv->rx_num + 1) % LTQ_ETH_RX_BUFFER_CNT;
6719 +
6720 + return 0;
6721 +}
6722 +
6723 +static void ltq_eth_gmac_init(int num)
6724 +{
6725 + struct ltq_mdio_phy_addr_reg phy_addr_reg;
6726 + struct ltq_mii_mii_cfg_reg mii_cfg_reg;
6727 +
6728 + /* Reset PHY status to link down */
6729 + phy_addr_reg.val = ltq_readl(to_mdio_phyaddr(switch_regs, num));
6730 + phy_addr_reg.bits.addr = num;
6731 + phy_addr_reg.bits.lnkst = LTQ_MDIO_PHY_ADDR_LNKST_DOWN;
6732 + phy_addr_reg.bits.speed = LTQ_MDIO_PHY_ADDR_SPEED_M10;
6733 + phy_addr_reg.bits.fdup = LTQ_MDIO_PHY_ADDR_FDUP_DISABLE;
6734 + ltq_writel(to_mdio_phyaddr(switch_regs, num), phy_addr_reg.val);
6735 +
6736 + /* Reset and disable MII interface */
6737 + switch (num) {
6738 + case 0:
6739 + case 1:
6740 + case 5:
6741 + mii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs, num));
6742 + mii_cfg_reg.bits.en = 0;
6743 + mii_cfg_reg.bits.res = 1;
6744 + mii_cfg_reg.bits.miirate = LTQ_MII_MII_CFG_MIIRATE_M2P5;
6745 + ltq_writel(to_mii_miicfg(switch_regs, num), mii_cfg_reg.val);
6746 + break;
6747 + default:
6748 + break;
6749 + }
6750 +
6751 + /*
6752 + * - enable frame checksum generation
6753 + * - enable padding of short frames
6754 + * - disable flow control
6755 + */
6756 + ltq_writel(to_mac_ctrl(switch_regs, num, 0),
6757 + MAC_CTRL0_PADEN | MAC_CTRL0_FCS | MAC_CTRL0_FCON_NONE);
6758 +
6759 + vr9_switch_sync();
6760 +}
6761 +
6762 +static void ltq_eth_pmac_init(void)
6763 +{
6764 + /*
6765 + * WAR: buffer congestion:
6766 + * - shorten preambel to 1 byte
6767 + * - set TX IPG to 7 bytes
6768 + */
6769 +#if 1
6770 + ltq_writel(to_mac_ctrl(switch_regs, LTQ_ETHSW_PMAC, 1),
6771 + MAC_CTRL1_SHORTPRE | 7);
6772 +#endif
6773 +
6774 + /*
6775 + * WAR: systematical concept weakness ACM bug
6776 + * - set maximum number of used buffer segments to 254
6777 + * - soft-reset BM FSQM
6778 + */
6779 +#if 1
6780 + ltq_writel(&switch_regs->bm.core.fsqm_gctrl, 253);
6781 + ltq_setbits(&switch_regs->bm.core.gctrl, BM_GCTRL_F_SRES);
6782 + ltq_clrbits(&switch_regs->bm.core.gctrl, BM_GCTRL_F_SRES);
6783 +#endif
6784 +
6785 + /*
6786 + * WAR: switch MAC drop bug
6787 + */
6788 +#if 1
6789 + ltq_writel(to_pce_tbl_key(switch_regs, 0), 0xf);
6790 + ltq_writel(to_pce_tbl_value(switch_regs, 0), 0x40);
6791 + ltq_writel(&switch_regs->pce.core.tbl_addr, 0x3);
6792 + ltq_writel(&switch_regs->pce.core.tbl_ctrl, 0x902f);
6793 +#endif
6794 +
6795 + /*
6796 + * Configure frame header control:
6797 + * - enable flow control
6798 + * - enable CRC check for packets from DMA to PMAC
6799 + * - remove special tag from packets from PMAC to DMA
6800 + * - add CRC for packets from DMA to PMAC
6801 + */
6802 + ltq_writel(&switch_regs->pmac.hd_ctl, /*PMAC_HD_CTL_FC |*/
6803 + PMAC_HD_CTL_CCRC | PMAC_HD_CTL_RST | PMAC_HD_CTL_AC |
6804 + PMAC_HD_CTL_RC);
6805 +
6806 +#if 1
6807 + ltq_writel(&switch_regs->pmac.rx_ipg, 0x8b);
6808 +#endif
6809 +
6810 + /*
6811 + * - enable frame checksum generation
6812 + * - enable padding of short frames
6813 + * - disable flow control
6814 + */
6815 + ltq_writel(to_mac_ctrl(switch_regs, LTQ_ETHSW_PMAC, 0),
6816 + MAC_CTRL0_PADEN | MAC_CTRL0_FCS | MAC_CTRL0_FCON_NONE);
6817 +
6818 + vr9_switch_sync();
6819 +}
6820 +
6821 +static void ltq_eth_hw_init(void)
6822 +{
6823 + int i;
6824 +
6825 + /* Power up ethernet and switch subsystems */
6826 + ltq_pm_enable(LTQ_PM_ETH);
6827 +
6828 + /* Reset ethernet and switch subsystems */
6829 +#if 0
6830 + ltq_reset_once(LTQ_RESET_ETH, 10);
6831 +#endif
6832 +
6833 + /* Enable switch macro */
6834 + ltq_setbits(&switch_regs->mdio.glob_ctrl, MDIO_GLOB_CTRL_SE);
6835 +
6836 + /* Disable MDIO auto-polling for all ports */
6837 + ltq_writel(&switch_regs->mdio.mdc_cfg_0, 0);
6838 +
6839 + /*
6840 + * Enable and set MDIO management clock to 2.5 MHz. This is the
6841 + * maximum clock for FE PHYs.
6842 + * Formula for clock is:
6843 + *
6844 + * 50 MHz
6845 + * x = ----------- - 1
6846 + * 2 * f_MDC
6847 + */
6848 + ltq_writel(&switch_regs->mdio.mdc_cfg_1, MDIO_MDC_CFG1_RES |
6849 + MDIO_MDC_CFG1_MCEN | 5);
6850 +
6851 + vr9_switch_sync();
6852 +
6853 + /* Init MAC connected to CPU */
6854 + ltq_eth_pmac_init();
6855 +
6856 + /* Init MACs connected to external MII interfaces */
6857 + for (i = 0; i < LTQ_ETHSW_MAX_GMAC; i++)
6858 + ltq_eth_gmac_init(i);
6859 +}
6860 +
6861 +static void ltq_eth_port_config(struct ltq_eth_priv *priv,
6862 + const struct ltq_eth_port_config *port)
6863 +{
6864 + struct ltq_mii_mii_cfg_reg mii_cfg_reg;
6865 + struct phy_device *phydev;
6866 + int setup_gpio = 0;
6867 +
6868 + switch (port->num) {
6869 + case 0: /* xMII0 */
6870 + case 1: /* xMII1 */
6871 + mii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs,
6872 + port->num));
6873 + mii_cfg_reg.bits.en = port->flags ? 1 : 0;
6874 +
6875 + switch (port->phy_if) {
6876 + case PHY_INTERFACE_MODE_MII:
6877 + if (port->flags & LTQ_ETH_PORT_PHY)
6878 + /* MII MAC mode, connected to external PHY */
6879 + mii_cfg_reg.bits.miimode =
6880 + LTQ_MII_MII_CFG_MIIMODE_MIIM;
6881 + else
6882 + /* MII PHY mode, connected to external MAC */
6883 + mii_cfg_reg.bits.miimode =
6884 + LTQ_MII_MII_CFG_MIIMODE_MIIP;
6885 + setup_gpio = 1;
6886 + break;
6887 + case PHY_INTERFACE_MODE_RMII:
6888 + if (port->flags & LTQ_ETH_PORT_PHY)
6889 + /* RMII MAC mode, connected to external PHY */
6890 + mii_cfg_reg.bits.miimode =
6891 + LTQ_MII_MII_CFG_MIIMODE_RMIIM;
6892 + else
6893 + /* RMII PHY mode, connected to external MAC */
6894 + mii_cfg_reg.bits.miimode =
6895 + LTQ_MII_MII_CFG_MIIMODE_RMIIP;
6896 + setup_gpio = 1;
6897 + break;
6898 + case PHY_INTERFACE_MODE_RGMII:
6899 + /* RGMII MAC mode, connected to external PHY */
6900 + mii_cfg_reg.bits.miimode =
6901 + LTQ_MII_MII_CFG_MIIMODE_RGMII;
6902 + setup_gpio = 1;
6903 +
6904 + /* RGMII clock delays */
6905 + ltq_writel(to_mii_pcdu(switch_regs, port->num),
6906 + port->rgmii_rx_delay << PCDU_RXDLY_SHIFT |
6907 + port->rgmii_tx_delay);
6908 + break;
6909 + default:
6910 + break;
6911 + }
6912 +
6913 + ltq_writel(to_mii_miicfg(switch_regs, port->num),
6914 + mii_cfg_reg.val);
6915 + break;
6916 + case 2: /* internal GPHY0 */
6917 + case 3: /* internal GPHY0 */
6918 + case 4: /* internal GPHY1 */
6919 + switch (port->phy_if) {
6920 + case PHY_INTERFACE_MODE_MII:
6921 + case PHY_INTERFACE_MODE_GMII:
6922 + setup_gpio = 1;
6923 + break;
6924 + default:
6925 + break;
6926 + }
6927 + break;
6928 + case 5: /* internal GPHY1 or xMII2 */
6929 + mii_cfg_reg.val = ltq_readl(to_mii_miicfg(switch_regs,
6930 + port->num));
6931 + mii_cfg_reg.bits.en = port->flags ? 1 : 0;
6932 +
6933 + switch (port->phy_if) {
6934 + case PHY_INTERFACE_MODE_MII:
6935 + /* MII MAC mode, connected to internal GPHY */
6936 + mii_cfg_reg.bits.miimode =
6937 + LTQ_MII_MII_CFG_MIIMODE_MIIM;
6938 + setup_gpio = 1;
6939 + break;
6940 + case PHY_INTERFACE_MODE_RGMII:
6941 + /* RGMII MAC mode, connected to external PHY */
6942 + mii_cfg_reg.bits.miimode =
6943 + LTQ_MII_MII_CFG_MIIMODE_RGMII;
6944 + setup_gpio = 1;
6945 +
6946 + /* RGMII clock delays */
6947 + ltq_writel(to_mii_pcdu(switch_regs, port->num),
6948 + port->rgmii_rx_delay << PCDU_RXDLY_SHIFT |
6949 + port->rgmii_tx_delay);
6950 + break;
6951 + default:
6952 + break;
6953 + }
6954 +
6955 + ltq_writel(to_mii_miicfg(switch_regs, port->num),
6956 + mii_cfg_reg.val);
6957 + break;
6958 + default:
6959 + break;
6960 + }
6961 +
6962 + /* Setup GPIOs for MII with external PHYs/MACs */
6963 + if (setup_gpio) {
6964 + /* MII/MDIO */
6965 + gpio_set_altfunc(42, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR,
6966 + GPIO_DIR_OUT);
6967 + /* MII/MDC */
6968 + gpio_set_altfunc(43, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR,
6969 + GPIO_DIR_OUT);
6970 + }
6971 +
6972 + /* Connect to internal/external PHYs */
6973 + if (port->flags & LTQ_ETH_PORT_PHY) {
6974 + phydev = phy_connect(priv->bus, port->phy_addr, priv->dev,
6975 + port->phy_if);
6976 + if (phydev)
6977 + phy_config(phydev);
6978 +
6979 + priv->phymap[port->num] = phydev;
6980 + }
6981 +}
6982 +
6983 +int ltq_eth_initialize(const struct ltq_eth_board_config *board_config)
6984 +{
6985 + struct eth_device *dev;
6986 + struct mii_dev *bus;
6987 + struct ltq_eth_priv *priv;
6988 + struct ltq_dma_device *dma_dev;
6989 + int i, ret;
6990 +
6991 + build_check_vr9_registers();
6992 +
6993 + ltq_dma_init();
6994 + ltq_eth_hw_init();
6995 +
6996 + dev = calloc(1, sizeof(struct eth_device));
6997 + if (!dev)
6998 + return -1;
6999 +
7000 + priv = calloc(1, sizeof(struct ltq_eth_priv));
7001 + if (!priv)
7002 + return -1;
7003 +
7004 + bus = mdio_alloc();
7005 + if (!bus)
7006 + return -1;
7007 +
7008 + sprintf(dev->name, LTQ_ETH_DRV_NAME);
7009 + dev->priv = priv;
7010 + dev->init = ltq_eth_init;
7011 + dev->halt = ltq_eth_halt;
7012 + dev->recv = ltq_eth_recv;
7013 + dev->send = ltq_eth_send;
7014 +
7015 + sprintf(bus->name, LTQ_MDIO_DRV_NAME);
7016 + bus->read = vr9_switch_mdio_read;
7017 + bus->write = vr9_switch_mdio_write;
7018 + bus->priv = priv;
7019 +
7020 + dma_dev = &priv->dma_dev;
7021 + dma_dev->port = 0;
7022 + dma_dev->rx_chan.chan_no = 0;
7023 + dma_dev->rx_chan.class = 0;
7024 + dma_dev->rx_chan.num_desc = LTQ_ETH_RX_BUFFER_CNT;
7025 + dma_dev->rx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
7026 + dma_dev->rx_burst_len = LTQ_DMA_BURST_2WORDS;
7027 + dma_dev->tx_chan.chan_no = 1;
7028 + dma_dev->tx_chan.class = 0;
7029 + dma_dev->tx_chan.num_desc = LTQ_ETH_TX_BUFFER_CNT;
7030 + dma_dev->tx_endian_swap = LTQ_DMA_ENDIANESS_B3_B2_B1_B0;
7031 + dma_dev->tx_burst_len = LTQ_DMA_BURST_2WORDS;
7032 +
7033 + priv->bus = bus;
7034 + priv->dev = dev;
7035 +
7036 + ret = ltq_dma_register(dma_dev);
7037 + if (ret)
7038 + return -1;
7039 +
7040 + ret = mdio_register(bus);
7041 + if (ret)
7042 + return -1;
7043 +
7044 + ret = eth_register(dev);
7045 + if (ret)
7046 + return -1;
7047 +
7048 + for (i = 0; i < board_config->num_ports; i++)
7049 + ltq_eth_port_config(priv, &board_config->ports[i]);
7050 +
7051 + return 0;
7052 +}
7053 --- a/drivers/net/phy/Makefile
7054 +++ b/drivers/net/phy/Makefile
7055 @@ -20,6 +20,7 @@ COBJS-$(CONFIG_PHY_BROADCOM) += broadcom
7056 COBJS-$(CONFIG_PHY_DAVICOM) += davicom.o
7057 COBJS-$(CONFIG_PHY_ET1011C) += et1011c.o
7058 COBJS-$(CONFIG_PHY_ICPLUS) += icplus.o
7059 +COBJS-$(CONFIG_PHY_LANTIQ) += lantiq.o
7060 COBJS-$(CONFIG_PHY_LXT) += lxt.o
7061 COBJS-$(CONFIG_PHY_MARVELL) += marvell.o
7062 COBJS-$(CONFIG_PHY_MICREL) += micrel.o
7063 --- /dev/null
7064 +++ b/drivers/net/phy/lantiq.c
7065 @@ -0,0 +1,238 @@
7066 +/*
7067 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
7068 + *
7069 + * SPDX-License-Identifier: GPL-2.0+
7070 + */
7071 +
7072 +#define DEBUG
7073 +
7074 +#include <common.h>
7075 +#include <miiphy.h>
7076 +
7077 +#define ADVERTIZE_MPD (1 << 10)
7078 +
7079 +DECLARE_GLOBAL_DATA_PTR;
7080 +
7081 +/*
7082 + * Update link status.
7083 + *
7084 + * Based on genphy_update_link in phylib.c
7085 + */
7086 +static int ltq_phy_update_link(struct phy_device *phydev)
7087 +{
7088 + unsigned int mii_reg;
7089 +
7090 + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
7091 +
7092 + /*
7093 + * If we already saw the link up, and it hasn't gone down, then
7094 + * we don't need to wait for autoneg again
7095 + */
7096 + if (phydev->link && mii_reg & BMSR_LSTATUS)
7097 + return 0;
7098 +
7099 + if ((mii_reg & BMSR_ANEGCAPABLE) && !(mii_reg & BMSR_ANEGCOMPLETE)) {
7100 + phydev->link = 0;
7101 + return 0;
7102 + } else {
7103 + /* Read the link a second time to clear the latched state */
7104 + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
7105 +
7106 + if (mii_reg & BMSR_LSTATUS)
7107 + phydev->link = 1;
7108 + else
7109 + phydev->link = 0;
7110 + }
7111 +
7112 + return 0;
7113 +}
7114 +
7115 +/*
7116 + * Update speed and duplex.
7117 + *
7118 + * Based on genphy_parse_link in phylib.c
7119 + */
7120 +static int ltq_phy_parse_link(struct phy_device *phydev)
7121 +{
7122 + unsigned int mii_reg;
7123 +
7124 + mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMSR);
7125 +
7126 + /* We're using autonegotiation */
7127 + if (mii_reg & BMSR_ANEGCAPABLE) {
7128 + u32 lpa = 0;
7129 + u32 gblpa = 0;
7130 +
7131 + /* Check for gigabit capability */
7132 + if (mii_reg & BMSR_ERCAP) {
7133 + /* We want a list of states supported by
7134 + * both PHYs in the link
7135 + */
7136 + gblpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_STAT1000);
7137 + gblpa &= phy_read(phydev,
7138 + MDIO_DEVAD_NONE, MII_CTRL1000) << 2;
7139 + }
7140 +
7141 + /* Set the baseline so we only have to set them
7142 + * if they're different
7143 + */
7144 + phydev->speed = SPEED_10;
7145 + phydev->duplex = DUPLEX_HALF;
7146 +
7147 + /* Check the gigabit fields */
7148 + if (gblpa & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
7149 + phydev->speed = SPEED_1000;
7150 +
7151 + if (gblpa & PHY_1000BTSR_1000FD)
7152 + phydev->duplex = DUPLEX_FULL;
7153 +
7154 + /* We're done! */
7155 + return 0;
7156 + }
7157 +
7158 + lpa = phy_read(phydev, MDIO_DEVAD_NONE, MII_ADVERTISE);
7159 + lpa &= phy_read(phydev, MDIO_DEVAD_NONE, MII_LPA);
7160 +
7161 + if (lpa & (LPA_100FULL | LPA_100HALF)) {
7162 + phydev->speed = SPEED_100;
7163 +
7164 + if (lpa & LPA_100FULL)
7165 + phydev->duplex = DUPLEX_FULL;
7166 +
7167 + } else if (lpa & LPA_10FULL)
7168 + phydev->duplex = DUPLEX_FULL;
7169 + } else {
7170 + u32 bmcr = phy_read(phydev, MDIO_DEVAD_NONE, MII_BMCR);
7171 +
7172 + phydev->speed = SPEED_10;
7173 + phydev->duplex = DUPLEX_HALF;
7174 +
7175 + if (bmcr & BMCR_FULLDPLX)
7176 + phydev->duplex = DUPLEX_FULL;
7177 +
7178 + if (bmcr & BMCR_SPEED1000)
7179 + phydev->speed = SPEED_1000;
7180 + else if (bmcr & BMCR_SPEED100)
7181 + phydev->speed = SPEED_100;
7182 + }
7183 +
7184 + return 0;
7185 +}
7186 +
7187 +static int ltq_phy_config(struct phy_device *phydev)
7188 +{
7189 + u16 val;
7190 +
7191 + /* Advertise as Multi-port device */
7192 + val = phy_read(phydev, MDIO_DEVAD_NONE, MII_CTRL1000);
7193 + val |= ADVERTIZE_MPD;
7194 + phy_write(phydev, MDIO_DEVAD_NONE, MII_CTRL1000, val);
7195 +
7196 + genphy_config_aneg(phydev);
7197 +
7198 + return 0;
7199 +}
7200 +
7201 +static int ltq_phy_startup(struct phy_device *phydev)
7202 +{
7203 + /*
7204 + * Update PHY status immediately without any delays as genphy_startup
7205 + * does because VRX200 switch needs to be configured dependent
7206 + * on this information.
7207 + */
7208 + ltq_phy_update_link(phydev);
7209 + ltq_phy_parse_link(phydev);
7210 +
7211 + debug("ltq_phy: addr %d, link %d, speed %d, duplex %d\n",
7212 + phydev->addr, phydev->link, phydev->speed, phydev->duplex);
7213 +
7214 + return 0;
7215 +}
7216 +
7217 +static struct phy_driver xrx_11g_13_driver = {
7218 + .name = "Lantiq XWAY XRX PHY11G v1.3 and earlier",
7219 + .uid = 0x030260D0,
7220 + .mask = 0xFFFFFFF0,
7221 + .features = PHY_GBIT_FEATURES,
7222 + .config = ltq_phy_config,
7223 + .startup = ltq_phy_startup,
7224 + .shutdown = genphy_shutdown,
7225 +};
7226 +
7227 +static struct phy_driver xrx_11g_14_driver = {
7228 + .name = "Lantiq XWAY XRX PHY11G v1.4 and later",
7229 + .uid = 0xd565a408,
7230 + .mask = 0xFFFFFFF8,
7231 + .features = PHY_GBIT_FEATURES,
7232 + .config = ltq_phy_config,
7233 + .startup = ltq_phy_startup,
7234 + .shutdown = genphy_shutdown,
7235 +};
7236 +
7237 +static struct phy_driver xrx_22f_14_driver = {
7238 + .name = "Lantiq XWAY XRX PHY22F v1.4 and later",
7239 + .uid = 0xd565a418,
7240 + .mask = 0xFFFFFFF8,
7241 + .features = PHY_BASIC_FEATURES,
7242 + .config = ltq_phy_config,
7243 + .startup = ltq_phy_startup,
7244 + .shutdown = genphy_shutdown,
7245 +};
7246 +
7247 +static struct phy_driver pef7071_driver = {
7248 + .name = "Lantiq XWAY PEF7071",
7249 + .uid = 0xd565a400,
7250 + .mask = 0xFFFFFFFF,
7251 + .features = PHY_GBIT_FEATURES,
7252 + .config = ltq_phy_config,
7253 + .startup = ltq_phy_startup,
7254 + .shutdown = genphy_shutdown,
7255 +};
7256 +
7257 +static struct phy_driver xrx_genphy_driver = {
7258 + .name = "Generic PHY at Lantiq XWAY XRX switch",
7259 + .uid = 0,
7260 + .mask = 0,
7261 + .features = 0,
7262 + .config = genphy_config,
7263 + .startup = ltq_phy_startup,
7264 + .shutdown = genphy_shutdown,
7265 +};
7266 +
7267 +int phy_lantiq_init(void)
7268 +{
7269 +#ifdef CONFIG_NEEDS_MANUAL_RELOC
7270 + xrx_11g_13_driver.config = ltq_phy_config;
7271 + xrx_11g_13_driver.startup = ltq_phy_startup;
7272 + xrx_11g_13_driver.shutdown = genphy_shutdown;
7273 + xrx_11g_13_driver.name += gd->reloc_off;
7274 +
7275 + xrx_11g_14_driver.config = ltq_phy_config;
7276 + xrx_11g_14_driver.startup = ltq_phy_startup;
7277 + xrx_11g_14_driver.shutdown = genphy_shutdown;
7278 + xrx_11g_14_driver.name += gd->reloc_off;
7279 +
7280 + xrx_22f_14_driver.config = ltq_phy_config;
7281 + xrx_22f_14_driver.startup = ltq_phy_startup;
7282 + xrx_22f_14_driver.shutdown = genphy_shutdown;
7283 + xrx_22f_14_driver.name += gd->reloc_off;
7284 +
7285 + pef7071_driver.config = ltq_phy_config;
7286 + pef7071_driver.startup = ltq_phy_startup;
7287 + pef7071_driver.shutdown = genphy_shutdown;
7288 + pef7071_driver.name += gd->reloc_off;
7289 +
7290 + xrx_genphy_driver.config = genphy_config;
7291 + xrx_genphy_driver.startup = ltq_phy_startup;
7292 + xrx_genphy_driver.shutdown = genphy_shutdown;
7293 + xrx_genphy_driver.name += gd->reloc_off;
7294 +#endif
7295 +
7296 + phy_register(&xrx_11g_13_driver);
7297 + phy_register(&xrx_11g_14_driver);
7298 + phy_register(&xrx_22f_14_driver);
7299 + phy_register(&pef7071_driver);
7300 + phy_register(&xrx_genphy_driver);
7301 +
7302 + return 0;
7303 +}
7304 --- a/drivers/net/phy/phy.c
7305 +++ b/drivers/net/phy/phy.c
7306 @@ -16,9 +16,10 @@
7307 #include <command.h>
7308 #include <miiphy.h>
7309 #include <phy.h>
7310 -#include <errno.h>
7311 #include <linux/err.h>
7312
7313 +DECLARE_GLOBAL_DATA_PTR;
7314 +
7315 /* Generic PHY support and helper functions */
7316
7317 /**
7318 @@ -440,6 +441,16 @@ static LIST_HEAD(phy_drivers);
7319
7320 int phy_init(void)
7321 {
7322 +#ifdef CONFIG_NEEDS_MANUAL_RELOC
7323 + INIT_LIST_HEAD(&phy_drivers);
7324 +
7325 + genphy_driver.config = genphy_config;
7326 + genphy_driver.startup = genphy_startup;
7327 + genphy_driver.shutdown = genphy_shutdown;
7328 +
7329 + genphy_driver.name += gd->reloc_off;
7330 +#endif
7331 +
7332 #ifdef CONFIG_PHY_ATHEROS
7333 phy_atheros_init();
7334 #endif
7335 @@ -455,6 +466,9 @@ int phy_init(void)
7336 #ifdef CONFIG_PHY_ICPLUS
7337 phy_icplus_init();
7338 #endif
7339 +#ifdef CONFIG_PHY_LANTIQ
7340 + phy_lantiq_init();
7341 +#endif
7342 #ifdef CONFIG_PHY_LXT
7343 phy_lxt_init();
7344 #endif
7345 --- a/drivers/serial/Makefile
7346 +++ b/drivers/serial/Makefile
7347 @@ -24,6 +24,7 @@ COBJS-$(CONFIG_SYS_NS16550_SERIAL) += se
7348 COBJS-$(CONFIG_IMX_SERIAL) += serial_imx.o
7349 COBJS-$(CONFIG_IXP_SERIAL) += serial_ixp.o
7350 COBJS-$(CONFIG_KS8695_SERIAL) += serial_ks8695.o
7351 +COBJS-$(CONFIG_LANTIQ_SERIAL) += serial_lantiq.o
7352 COBJS-$(CONFIG_MAX3100_SERIAL) += serial_max3100.o
7353 COBJS-$(CONFIG_MXC_UART) += serial_mxc.o
7354 COBJS-$(CONFIG_PL010_SERIAL) += serial_pl01x.o
7355 --- a/drivers/serial/serial.c
7356 +++ b/drivers/serial/serial.c
7357 @@ -160,6 +160,7 @@ serial_initfunc(sa1100_serial_initialize
7358 serial_initfunc(sh_serial_initialize);
7359 serial_initfunc(arm_dcc_initialize);
7360 serial_initfunc(mxs_auart_initialize);
7361 +serial_initfunc(ltq_serial_initialize);
7362
7363 /**
7364 * serial_register() - Register serial driver with serial driver core
7365 @@ -253,6 +254,7 @@ void serial_initialize(void)
7366 sh_serial_initialize();
7367 arm_dcc_initialize();
7368 mxs_auart_initialize();
7369 + ltq_serial_initialize();
7370
7371 serial_assign(default_serial_console()->name);
7372 }
7373 --- /dev/null
7374 +++ b/drivers/serial/serial_lantiq.c
7375 @@ -0,0 +1,263 @@
7376 +/*
7377 + * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com>
7378 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
7379 + *
7380 + * SPDX-License-Identifier: GPL-2.0+
7381 + */
7382 +
7383 +#include <common.h>
7384 +#include <serial.h>
7385 +#include <asm/errno.h>
7386 +#include <asm/arch/soc.h>
7387 +#include <asm/lantiq/clk.h>
7388 +#include <asm/lantiq/io.h>
7389 +
7390 +#if CONFIG_CONSOLE_ASC == 0
7391 +#define LTQ_ASC_BASE LTQ_ASC0_BASE
7392 +#else
7393 +#define LTQ_ASC_BASE LTQ_ASC1_BASE
7394 +#endif
7395 +
7396 +#define LTQ_ASC_ID_TXFS_SHIFT 24
7397 +#define LTQ_ASC_ID_TXFS_MASK (0x3F << LTQ_ASC_ID_TXFS_SHIFT)
7398 +#define LTQ_ASC_ID_RXFS_SHIFT 16
7399 +#define LTQ_ASC_ID_RXFS_MASK (0x3F << LTQ_ASC_ID_RXFS_SHIFT)
7400 +
7401 +#define LTQ_ASC_MCON_R (1 << 15)
7402 +#define LTQ_ASC_MCON_FDE (1 << 9)
7403 +
7404 +#define LTQ_ASC_WHBSTATE_SETREN (1 << 1)
7405 +#define LTQ_ASC_WHBSTATE_CLRREN (1 << 0)
7406 +
7407 +#define LTQ_ASC_RXFCON_RXFITL_SHIFT 8
7408 +#define LTQ_ASC_RXFCON_RXFITL_MASK (0x3F << LTQ_ASC_RXFCON_RXFITL_SHIFT)
7409 +#define LTQ_ASC_RXFCON_RXFITL_RXFFLU (1 << 1)
7410 +#define LTQ_ASC_RXFCON_RXFITL_RXFEN (1 << 0)
7411 +
7412 +#define LTQ_ASC_TXFCON_TXFITL_SHIFT 8
7413 +#define LTQ_ASC_TXFCON_TXFITL_MASK (0x3F << LTQ_ASC_TXFCON_TXFITL_SHIFT)
7414 +#define LTQ_ASC_TXFCON_TXFITL_TXFFLU (1 << 1)
7415 +#define LTQ_ASC_TXFCON_TXFITL_TXFEN (1 << 0)
7416 +
7417 +#define LTQ_ASC_FSTAT_TXFREE_SHIFT 24
7418 +#define LTQ_ASC_FSTAT_TXFREE_MASK (0x3F << LTQ_ASC_FSTAT_TXFREE_SHIFT)
7419 +#define LTQ_ASC_FSTAT_RXFREE_SHIFT 16
7420 +#define LTQ_ASC_FSTAT_RXFREE_MASK (0x3F << LTQ_ASC_FSTAT_RXFREE_SHIFT)
7421 +#define LTQ_ASC_FSTAT_TXFFL_SHIFT 8
7422 +#define LTQ_ASC_FSTAT_TXFFL_MASK (0x3F << LTQ_ASC_FSTAT_TXFFL_SHIFT)
7423 +#define LTQ_ASC_FSTAT_RXFFL_MASK 0x3F
7424 +
7425 +#ifdef __BIG_ENDIAN
7426 +#define LTQ_ASC_RBUF_OFFSET 3
7427 +#define LTQ_ASC_TBUF_OFFSET 3
7428 +#else
7429 +#define LTQ_ASC_RBUF_OFFSET 0
7430 +#define LTQ_ASC_TBUF_OFFSET 0
7431 +#endif
7432 +
7433 +struct ltq_asc_regs {
7434 + u32 clc;
7435 + u32 pisel;
7436 + u32 id;
7437 + u32 rsvd0;
7438 + u32 mcon;
7439 + u32 state;
7440 + u32 whbstate;
7441 + u32 rsvd1;
7442 + u8 tbuf[4];
7443 + u8 rbuf[4];
7444 + u32 rsvd2[2];
7445 + u32 abcon;
7446 + u32 abstat;
7447 + u32 whbabcon;
7448 + u32 whbabstat;
7449 + u32 rxfcon;
7450 + u32 txfcon;
7451 + u32 fstat;
7452 + u32 rsvd3;
7453 + u32 bg;
7454 + u32 bg_timer;
7455 + u32 fdv;
7456 + u32 pmw;
7457 + u32 modcon;
7458 + u32 modstat;
7459 +};
7460 +
7461 +DECLARE_GLOBAL_DATA_PTR;
7462 +
7463 +static struct ltq_asc_regs *ltq_asc_regs =
7464 + (struct ltq_asc_regs *) CKSEG1ADDR(LTQ_ASC_BASE);
7465 +
7466 +static int ltq_serial_init(void)
7467 +{
7468 + /* Set clock divider for normal run mode to 1 and enable module */
7469 + ltq_writel(&ltq_asc_regs->clc, 0x100);
7470 +
7471 + /* Reset MCON register */
7472 + ltq_writel(&ltq_asc_regs->mcon, 0);
7473 +
7474 + /* Use Port A as receiver input */
7475 + ltq_writel(&ltq_asc_regs->pisel, 0);
7476 +
7477 + /* Enable and flush RX/TX FIFOs */
7478 + ltq_setbits(&ltq_asc_regs->rxfcon,
7479 + LTQ_ASC_RXFCON_RXFITL_RXFFLU | LTQ_ASC_RXFCON_RXFITL_RXFEN);
7480 + ltq_setbits(&ltq_asc_regs->txfcon,
7481 + LTQ_ASC_TXFCON_TXFITL_TXFFLU | LTQ_ASC_TXFCON_TXFITL_TXFEN);
7482 +
7483 + serial_setbrg();
7484 +
7485 + /* Disable error flags, enable receiver */
7486 + ltq_writel(&ltq_asc_regs->whbstate, LTQ_ASC_WHBSTATE_SETREN);
7487 +
7488 + return 0;
7489 +}
7490 +
7491 +/*
7492 + * fdv asc_clk
7493 + * Baudrate = ----- * -------------
7494 + * 512 16 * (bg + 1)
7495 + */
7496 +static void ltq_serial_calc_br_fdv(unsigned long asc_clk,
7497 + unsigned long baudrate, u16 *fdv,
7498 + u16 *bg)
7499 +{
7500 + const u32 c = asc_clk / (16 * 512);
7501 + u32 diff1, diff2;
7502 + u32 bg_calc, br_calc, i;
7503 +
7504 + diff1 = baudrate;
7505 + for (i = 512; i > 0; i--) {
7506 + /* Calc bg for current fdv value */
7507 + bg_calc = i * c / baudrate;
7508 +
7509 + /* Impossible baudrate */
7510 + if (!bg_calc)
7511 + return;
7512 +
7513 + /*
7514 + * Calc diff to target baudrate dependent on current
7515 + * bg and fdv values
7516 + */
7517 + br_calc = i * c / bg_calc;
7518 + if (br_calc > baudrate)
7519 + diff2 = br_calc - baudrate;
7520 + else
7521 + diff2 = baudrate - br_calc;
7522 +
7523 + /* Perfect values found */
7524 + if (diff2 == 0) {
7525 + *fdv = i;
7526 + *bg = bg_calc - 1;
7527 + return;
7528 + }
7529 +
7530 + if (diff2 < diff1) {
7531 + *fdv = i;
7532 + *bg = bg_calc - 1;
7533 + diff1 = diff2;
7534 + }
7535 + }
7536 +}
7537 +
7538 +static void ltq_serial_setbrg(void)
7539 +{
7540 + unsigned long asc_clk, baudrate;
7541 + u16 bg = 0;
7542 + u16 fdv = 511;
7543 +
7544 + /* ASC clock is same as FPI clock with CLC.RMS = 1 */
7545 + asc_clk = ltq_get_bus_clock();
7546 + baudrate = gd->baudrate;
7547 +
7548 + /* Calculate FDV and BG values */
7549 + ltq_serial_calc_br_fdv(asc_clk, baudrate, &fdv, &bg);
7550 +
7551 + /* Disable baudrate generator */
7552 + ltq_clrbits(&ltq_asc_regs->mcon, LTQ_ASC_MCON_R);
7553 +
7554 + /* Enable fractional divider */
7555 + ltq_setbits(&ltq_asc_regs->mcon, LTQ_ASC_MCON_FDE);
7556 +
7557 + /* Set fdv and bg values */
7558 + ltq_writel(&ltq_asc_regs->fdv, fdv);
7559 + ltq_writel(&ltq_asc_regs->bg, bg);
7560 +
7561 + /* Enable baudrate generator */
7562 + ltq_setbits(&ltq_asc_regs->mcon, LTQ_ASC_MCON_R);
7563 +}
7564 +
7565 +static unsigned int ltq_serial_tx_free(void)
7566 +{
7567 + unsigned int txfree;
7568 +
7569 + txfree = (ltq_readl(&ltq_asc_regs->fstat) &
7570 + LTQ_ASC_FSTAT_TXFREE_MASK) >>
7571 + LTQ_ASC_FSTAT_TXFREE_SHIFT;
7572 +
7573 + return txfree;
7574 +}
7575 +
7576 +static unsigned int ltq_serial_rx_fill(void)
7577 +{
7578 + unsigned int rxffl;
7579 +
7580 + rxffl = ltq_readl(&ltq_asc_regs->fstat) & LTQ_ASC_FSTAT_RXFFL_MASK;
7581 +
7582 + return rxffl;
7583 +}
7584 +
7585 +static void ltq_serial_tx(const char c)
7586 +{
7587 + ltq_writeb(&ltq_asc_regs->tbuf[LTQ_ASC_TBUF_OFFSET], c);
7588 +}
7589 +
7590 +static u8 ltq_serial_rx(void)
7591 +{
7592 + return ltq_readb(&ltq_asc_regs->rbuf[LTQ_ASC_RBUF_OFFSET]);
7593 +}
7594 +
7595 +static void ltq_serial_putc(const char c)
7596 +{
7597 + if (c == '\n')
7598 + ltq_serial_putc('\r');
7599 +
7600 + while (!ltq_serial_tx_free())
7601 + ;
7602 +
7603 + ltq_serial_tx(c);
7604 +}
7605 +
7606 +static int ltq_serial_getc(void)
7607 +{
7608 + while (!ltq_serial_rx_fill())
7609 + ;
7610 +
7611 + return ltq_serial_rx();
7612 +}
7613 +
7614 +static int ltq_serial_tstc(void)
7615 +{
7616 + return (0 != ltq_serial_rx_fill());
7617 +}
7618 +
7619 +static struct serial_device ltq_serial_drv = {
7620 + .name = "ltq_serial",
7621 + .start = ltq_serial_init,
7622 + .stop = NULL,
7623 + .setbrg = ltq_serial_setbrg,
7624 + .putc = ltq_serial_putc,
7625 + .puts = default_serial_puts,
7626 + .getc = ltq_serial_getc,
7627 + .tstc = ltq_serial_tstc,
7628 +};
7629 +
7630 +void ltq_serial_initialize(void)
7631 +{
7632 + serial_register(&ltq_serial_drv);
7633 +}
7634 +
7635 +__weak struct serial_device *default_serial_console(void)
7636 +{
7637 + return &ltq_serial_drv;
7638 +}
7639 --- a/drivers/spi/Makefile
7640 +++ b/drivers/spi/Makefile
7641 @@ -25,6 +25,7 @@ COBJS-$(CONFIG_DAVINCI_SPI) += davinci_s
7642 COBJS-$(CONFIG_EXYNOS_SPI) += exynos_spi.o
7643 COBJS-$(CONFIG_ICH_SPI) += ich.o
7644 COBJS-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o
7645 +COBJS-$(CONFIG_LANTIQ_SPI) += lantiq_spi.o
7646 COBJS-$(CONFIG_MPC52XX_SPI) += mpc52xx_spi.o
7647 COBJS-$(CONFIG_MPC8XXX_SPI) += mpc8xxx_spi.o
7648 COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o
7649 --- /dev/null
7650 +++ b/drivers/spi/lantiq_spi.c
7651 @@ -0,0 +1,666 @@
7652 +/*
7653 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
7654 + *
7655 + * SPDX-License-Identifier: GPL-2.0+
7656 + */
7657 +
7658 +#include <common.h>
7659 +#include <spi.h>
7660 +#include <malloc.h>
7661 +#include <watchdog.h>
7662 +#include <asm/gpio.h>
7663 +#include <asm/lantiq/io.h>
7664 +#include <asm/lantiq/clk.h>
7665 +#include <asm/lantiq/pm.h>
7666 +#include <asm/arch/soc.h>
7667 +
7668 +#define LTQ_SPI_CLC_RMC_SHIFT 8
7669 +#define LTQ_SPI_CLC_RMC_MASK (0xFF << LTQ_SPI_CLC_RMC_SHIFT)
7670 +#define LTQ_SPI_CLC_DISS (1 << 1)
7671 +#define LTQ_SPI_CLC_DISR 1
7672 +
7673 +#define LTQ_SPI_ID_TXFS_SHIFT 24
7674 +#define LTQ_SPI_ID_TXFS_MASK (0x3F << LTQ_SPI_ID_TXFS_SHIFT)
7675 +#define LTQ_SPI_ID_RXFS_SHIFT 16
7676 +#define LTQ_SPI_ID_RXFS_MASK (0x3F << LTQ_SPI_ID_RXFS_SHIFT)
7677 +
7678 +#define LTQ_SPI_CON_ENBV (1 << 22)
7679 +#define LTQ_SPI_CON_BM_SHIFT 16
7680 +#define LTQ_SPI_CON_BM_MASK (0x1F << LTQ_SPI_CON_BM_SHIFT)
7681 +#define LTQ_SPI_CON_IDLE (1 << 23)
7682 +#define LTQ_SPI_CON_RUEN (1 << 12)
7683 +#define LTQ_SPI_CON_AEN (1 << 10)
7684 +#define LTQ_SPI_CON_REN (1 << 9)
7685 +#define LTQ_SPI_CON_TEN (1 << 8)
7686 +#define LTQ_SPI_CON_LB (1 << 7)
7687 +#define LTQ_SPI_CON_PO (1 << 6)
7688 +#define LTQ_SPI_CON_PH (1 << 5)
7689 +#define LTQ_SPI_CON_HB (1 << 4)
7690 +#define LTQ_SPI_CON_RXOFF (1 << 1)
7691 +#define LTQ_SPI_CON_TXOFF 1
7692 +
7693 +#define LTQ_SPI_STAT_RXBV_SHIFT 28
7694 +#define LTQ_SPI_STAT_RXBV_MASK (0x7 << LTQ_SPI_STAT_RXBV_SHIFT)
7695 +#define LTQ_SPI_STAT_BSY (1 << 13)
7696 +
7697 +#define LTQ_SPI_WHBSTATE_SETMS (1 << 3)
7698 +#define LTQ_SPI_WHBSTATE_CLRMS (1 << 2)
7699 +#define LTQ_SPI_WHBSTATE_SETEN (1 << 1)
7700 +#define LTQ_SPI_WHBSTATE_CLREN 1
7701 +#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50
7702 +
7703 +#define LTQ_SPI_TXFCON_TXFLU (1 << 1)
7704 +#define LTQ_SPI_TXFCON_TXFEN 1
7705 +
7706 +#define LTQ_SPI_RXFCON_RXFLU (1 << 1)
7707 +#define LTQ_SPI_RXFCON_RXFEN 1
7708 +
7709 +#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f
7710 +#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8
7711 +#define LTQ_SPI_FSTAT_TXFFL_MASK (0x3f << LTQ_SPI_FSTAT_TXFFL_SHIFT)
7712 +
7713 +#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF
7714 +#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF
7715 +
7716 +#define LTQ_SPI_GPIO_DIN 16
7717 +#define LTQ_SPI_GPIO_DOUT 17
7718 +#define LTQ_SPI_GPIO_CLK 18
7719 +
7720 +struct ltq_spi_regs {
7721 + __be32 clc; /* Clock control */
7722 + __be32 pisel; /* Port input select */
7723 + __be32 id; /* Identification */
7724 + __be32 rsvd0;
7725 + __be32 con; /* Control */
7726 + __be32 stat; /* Status */
7727 + __be32 whbstate; /* Write HW modified state */
7728 + __be32 rsvd1;
7729 + __be32 tb; /* Transmit buffer */
7730 + __be32 rb; /* Receive buffer */
7731 + __be32 rsvd2[2];
7732 + __be32 rxfcon; /* Recevie FIFO control */
7733 + __be32 txfcon; /* Transmit FIFO control */
7734 + __be32 fstat; /* FIFO status */
7735 + __be32 rsvd3;
7736 + __be32 brt; /* Baudrate timer */
7737 + __be32 brstat; /* Baudrate timer status */
7738 + __be32 rsvd4[6];
7739 + __be32 sfcon; /* Serial frame control */
7740 + __be32 sfstat; /* Serial frame status */
7741 + __be32 rsvd5[2];
7742 + __be32 gpocon; /* General purpose output control */
7743 + __be32 gpostat; /* General purpose output status */
7744 + __be32 fgpo; /* Force general purpose output */
7745 + __be32 rsvd6;
7746 + __be32 rxreq; /* Receive request */
7747 + __be32 rxcnt; /* Receive count */
7748 + __be32 rsvd7[25];
7749 + __be32 dmacon; /* DMA control */
7750 + __be32 rsvd8;
7751 + __be32 irnen; /* Interrupt node enable */
7752 + __be32 irnicr; /* Interrupt node interrupt capture */
7753 + __be32 irncr; /* Interrupt node control */
7754 +};
7755 +
7756 +struct ltq_spi_drv_data {
7757 + struct ltq_spi_regs __iomem *regs;
7758 +
7759 + struct spi_slave slave;
7760 + unsigned int max_hz;
7761 + unsigned int mode;
7762 + unsigned int tx_todo;
7763 + unsigned int rx_todo;
7764 + unsigned int rx_req;
7765 + unsigned int bits_per_word;
7766 + unsigned int speed_hz;
7767 + const u8 *tx;
7768 + u8 *rx;
7769 + int status;
7770 +};
7771 +
7772 +static struct ltq_spi_drv_data *to_ltq_spi_slave(struct spi_slave *slave)
7773 +{
7774 + return container_of(slave, struct ltq_spi_drv_data, slave);
7775 +}
7776 +
7777 +#ifdef CONFIG_SPL_BUILD
7778 +/*
7779 + * We do not have or want malloc in a SPI flash SPL.
7780 + * Neither we have to support multiple SPI slaves. Thus we put the
7781 + * SPI slave context in BSS for SPL builds.
7782 + */
7783 +static struct ltq_spi_drv_data ltq_spi_slave;
7784 +
7785 +static struct ltq_spi_drv_data *ltq_spi_slave_alloc(unsigned int bus,
7786 + unsigned int cs)
7787 +{
7788 + ltq_spi_slave.slave.bus = bus;
7789 + ltq_spi_slave.slave.cs = cs;
7790 +
7791 + return &ltq_spi_slave;
7792 +}
7793 +
7794 +static void ltq_spi_slave_free(struct spi_slave *slave)
7795 +{
7796 +}
7797 +#else
7798 +static struct ltq_spi_drv_data *ltq_spi_slave_alloc(unsigned int bus,
7799 + unsigned int cs)
7800 +{
7801 + return spi_alloc_slave(struct ltq_spi_drv_data, bus, cs);
7802 +}
7803 +
7804 +static void ltq_spi_slave_free(struct spi_slave *slave)
7805 +{
7806 + struct ltq_spi_drv_data *drv;
7807 +
7808 + if (slave) {
7809 + drv = to_ltq_spi_slave(slave);
7810 + free(drv);
7811 + }
7812 +}
7813 +#endif
7814 +
7815 +static unsigned int tx_fifo_size(struct ltq_spi_drv_data *drv)
7816 +{
7817 + u32 id = ltq_readl(&drv->regs->id);
7818 +
7819 + return (id & LTQ_SPI_ID_TXFS_MASK) >> LTQ_SPI_ID_TXFS_SHIFT;
7820 +}
7821 +
7822 +static unsigned int rx_fifo_size(struct ltq_spi_drv_data *drv)
7823 +{
7824 + u32 id = ltq_readl(&drv->regs->id);
7825 +
7826 + return (id & LTQ_SPI_ID_RXFS_MASK) >> LTQ_SPI_ID_RXFS_SHIFT;
7827 +}
7828 +
7829 +static unsigned int tx_fifo_level(struct ltq_spi_drv_data *drv)
7830 +{
7831 + u32 fstat = ltq_readl(&drv->regs->fstat);
7832 +
7833 + return (fstat & LTQ_SPI_FSTAT_TXFFL_MASK) >> LTQ_SPI_FSTAT_TXFFL_SHIFT;
7834 +}
7835 +
7836 +static unsigned int rx_fifo_level(struct ltq_spi_drv_data *drv)
7837 +{
7838 + u32 fstat = ltq_readl(&drv->regs->fstat);
7839 +
7840 + return fstat & LTQ_SPI_FSTAT_RXFFL_MASK;
7841 +}
7842 +
7843 +static unsigned int tx_fifo_free(struct ltq_spi_drv_data *drv)
7844 +{
7845 + return tx_fifo_size(drv) - tx_fifo_level(drv);
7846 +}
7847 +
7848 +static void hw_power_on(struct ltq_spi_drv_data *drv)
7849 +{
7850 + u32 clc;
7851 +
7852 + /* Power-up mdule */
7853 + ltq_pm_enable(LTQ_PM_SPI);
7854 +
7855 + /*
7856 + * Set clock divider for run mode to 1 to
7857 + * run at same frequency as FPI bus
7858 + */
7859 + clc = (1 << LTQ_SPI_CLC_RMC_SHIFT);
7860 + ltq_writel(&drv->regs->clc, clc);
7861 +}
7862 +
7863 +static void hw_reset_fifos(struct ltq_spi_drv_data *drv)
7864 +{
7865 + u32 val;
7866 +
7867 + val = LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU;
7868 + ltq_writel(&drv->regs->txfcon, val);
7869 +
7870 + val = LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU;
7871 + ltq_writel(&drv->regs->rxfcon, val);
7872 +}
7873 +
7874 +static int hw_is_busy(struct ltq_spi_drv_data *drv)
7875 +{
7876 + u32 stat = ltq_readl(&drv->regs->stat);
7877 +
7878 + return stat & LTQ_SPI_STAT_BSY;
7879 +}
7880 +
7881 +static void hw_enter_config_mode(struct ltq_spi_drv_data *drv)
7882 +{
7883 + ltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_CLREN);
7884 +}
7885 +
7886 +static void hw_enter_active_mode(struct ltq_spi_drv_data *drv)
7887 +{
7888 + ltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_SETEN);
7889 +}
7890 +
7891 +static void hw_setup_speed_hz(struct ltq_spi_drv_data *drv,
7892 + unsigned int max_speed_hz)
7893 +{
7894 + unsigned int spi_hz, speed_hz, brt;
7895 +
7896 + /*
7897 + * SPI module clock is derived from FPI bus clock dependent on
7898 + * divider value in CLC.RMS which is always set to 1.
7899 + *
7900 + * f_SPI
7901 + * baudrate = --------------
7902 + * 2 * (BR + 1)
7903 + */
7904 + spi_hz = ltq_get_bus_clock() / 2;
7905 +
7906 + /* TODO: optimize baudrate calculation */
7907 + for (brt = 0; brt < 0xFFFF; brt++) {
7908 + speed_hz = spi_hz / (brt + 1);
7909 + if (speed_hz <= max_speed_hz)
7910 + break;
7911 + }
7912 +
7913 + ltq_writel(&drv->regs->brt, brt);
7914 +}
7915 +
7916 +static void hw_setup_bits_per_word(struct ltq_spi_drv_data *drv,
7917 + unsigned int bits_per_word)
7918 +{
7919 + u32 bm;
7920 +
7921 + /* CON.BM value = bits_per_word - 1 */
7922 + bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT;
7923 +
7924 + ltq_clrsetbits(&drv->regs->con, LTQ_SPI_CON_BM_MASK, bm);
7925 +}
7926 +
7927 +static void hw_setup_clock_mode(struct ltq_spi_drv_data *drv, unsigned int mode)
7928 +{
7929 + u32 con_set = 0, con_clr = 0;
7930 +
7931 + /*
7932 + * SPI mode mapping in CON register:
7933 + * Mode CPOL CPHA CON.PO CON.PH
7934 + * 0 0 0 0 1
7935 + * 1 0 1 0 0
7936 + * 2 1 0 1 1
7937 + * 3 1 1 1 0
7938 + */
7939 + if (mode & SPI_CPHA)
7940 + con_clr |= LTQ_SPI_CON_PH;
7941 + else
7942 + con_set |= LTQ_SPI_CON_PH;
7943 +
7944 + if (mode & SPI_CPOL)
7945 + con_set |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
7946 + else
7947 + con_clr |= LTQ_SPI_CON_PO | LTQ_SPI_CON_IDLE;
7948 +
7949 + /* Set heading control */
7950 + if (mode & SPI_LSB_FIRST)
7951 + con_clr |= LTQ_SPI_CON_HB;
7952 + else
7953 + con_set |= LTQ_SPI_CON_HB;
7954 +
7955 + /* Set loopback mode */
7956 + if (mode & SPI_LOOP)
7957 + con_set |= LTQ_SPI_CON_LB;
7958 + else
7959 + con_clr |= LTQ_SPI_CON_LB;
7960 +
7961 + ltq_clrsetbits(&drv->regs->con, con_clr, con_set);
7962 +}
7963 +
7964 +static void hw_set_rxtx(struct ltq_spi_drv_data *drv)
7965 +{
7966 + u32 con;
7967 +
7968 + /* Configure transmitter and receiver */
7969 + con = ltq_readl(&drv->regs->con);
7970 + if (drv->tx)
7971 + con &= ~LTQ_SPI_CON_TXOFF;
7972 + else
7973 + con |= LTQ_SPI_CON_TXOFF;
7974 +
7975 + if (drv->rx)
7976 + con &= ~LTQ_SPI_CON_RXOFF;
7977 + else
7978 + con |= LTQ_SPI_CON_RXOFF;
7979 +
7980 + ltq_writel(&drv->regs->con, con);
7981 +}
7982 +
7983 +static void hw_init(struct ltq_spi_drv_data *drv)
7984 +{
7985 + hw_power_on(drv);
7986 +
7987 + /* Put controller into config mode */
7988 + hw_enter_config_mode(drv);
7989 +
7990 + /* Disable all interrupts */
7991 + ltq_writel(&drv->regs->irnen, 0);
7992 +
7993 + /* Clear error flags */
7994 + ltq_clrsetbits(&drv->regs->whbstate, 0, LTQ_SPI_WHBSTATE_CLR_ERRORS);
7995 +
7996 + /* Enable error checking, disable TX/RX */
7997 + ltq_writel(&drv->regs->con, LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN |
7998 + LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | LTQ_SPI_CON_TXOFF |
7999 + LTQ_SPI_CON_RXOFF);
8000 +
8001 + /* Setup default SPI mode */
8002 + drv->bits_per_word = 8;
8003 + drv->speed_hz = 0;
8004 + hw_setup_bits_per_word(drv, drv->bits_per_word);
8005 + hw_setup_clock_mode(drv, SPI_MODE_0);
8006 +
8007 + /* Enable master mode and clear error flags */
8008 + ltq_writel(&drv->regs->whbstate, LTQ_SPI_WHBSTATE_SETMS |
8009 + LTQ_SPI_WHBSTATE_CLR_ERRORS);
8010 +
8011 + /* Reset GPIO/CS registers */
8012 + ltq_writel(&drv->regs->gpocon, 0);
8013 + ltq_writel(&drv->regs->fgpo, 0xFF00);
8014 +
8015 + /* Enable and flush FIFOs */
8016 + hw_reset_fifos(drv);
8017 +
8018 + /* SPI/DIN input */
8019 + gpio_set_altfunc(16, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
8020 + /* SPI/DOUT output */
8021 + gpio_set_altfunc(17, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
8022 + /* SPI/CLK output */
8023 + gpio_set_altfunc(18, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
8024 +}
8025 +
8026 +static void tx_fifo_write(struct ltq_spi_drv_data *drv)
8027 +{
8028 + const u8 *tx8;
8029 + const u16 *tx16;
8030 + const u32 *tx32;
8031 + u32 data;
8032 + unsigned int tx_free = tx_fifo_free(drv);
8033 +
8034 + while (drv->tx_todo && tx_free) {
8035 + switch (drv->bits_per_word) {
8036 + case 8:
8037 + tx8 = drv->tx;
8038 + data = *tx8;
8039 + drv->tx_todo--;
8040 + drv->tx++;
8041 + break;
8042 + case 16:
8043 + tx16 = (u16 *) drv->tx;
8044 + data = *tx16;
8045 + drv->tx_todo -= 2;
8046 + drv->tx += 2;
8047 + break;
8048 + case 32:
8049 + tx32 = (u32 *) drv->tx;
8050 + data = *tx32;
8051 + drv->tx_todo -= 4;
8052 + drv->tx += 4;
8053 + break;
8054 + default:
8055 + return;
8056 + }
8057 +
8058 + ltq_writel(&drv->regs->tb, data);
8059 + tx_free--;
8060 + }
8061 +}
8062 +
8063 +static void rx_fifo_read_full_duplex(struct ltq_spi_drv_data *drv)
8064 +{
8065 + u8 *rx8;
8066 + u16 *rx16;
8067 + u32 *rx32;
8068 + u32 data;
8069 + unsigned int rx_fill = rx_fifo_level(drv);
8070 +
8071 + while (rx_fill) {
8072 + data = ltq_readl(&drv->regs->rb);
8073 +
8074 + switch (drv->bits_per_word) {
8075 + case 8:
8076 + rx8 = drv->rx;
8077 + *rx8 = data;
8078 + drv->rx_todo--;
8079 + drv->rx++;
8080 + break;
8081 + case 16:
8082 + rx16 = (u16 *) drv->rx;
8083 + *rx16 = data;
8084 + drv->rx_todo -= 2;
8085 + drv->rx += 2;
8086 + break;
8087 + case 32:
8088 + rx32 = (u32 *) drv->rx;
8089 + *rx32 = data;
8090 + drv->rx_todo -= 4;
8091 + drv->rx += 4;
8092 + break;
8093 + default:
8094 + return;
8095 + }
8096 +
8097 + rx_fill--;
8098 + }
8099 +}
8100 +
8101 +static void rx_fifo_read_half_duplex(struct ltq_spi_drv_data *drv)
8102 +{
8103 + u32 data, *rx32;
8104 + u8 *rx8;
8105 + unsigned int rxbv, shift;
8106 + unsigned int rx_fill = rx_fifo_level(drv);
8107 +
8108 + /*
8109 + * In RX-only mode the bits per word value is ignored by HW. A value
8110 + * of 32 is used instead. Thus all 4 bytes per FIFO must be read.
8111 + * If remaining RX bytes are less than 4, the FIFO must be read
8112 + * differently. The amount of received and valid bytes is indicated
8113 + * by STAT.RXBV register value.
8114 + */
8115 + while (rx_fill) {
8116 + if (drv->rx_todo < 4) {
8117 + rxbv = (ltq_readl(&drv->regs->stat) &
8118 + LTQ_SPI_STAT_RXBV_MASK) >>
8119 + LTQ_SPI_STAT_RXBV_SHIFT;
8120 + data = ltq_readl(&drv->regs->rb);
8121 +
8122 + shift = (rxbv - 1) * 8;
8123 + rx8 = drv->rx;
8124 +
8125 + while (rxbv) {
8126 + *rx8++ = (data >> shift) & 0xFF;
8127 + rxbv--;
8128 + shift -= 8;
8129 + drv->rx_todo--;
8130 + drv->rx++;
8131 +
8132 + if (drv->rx_req)
8133 + drv->rx_req --;
8134 + }
8135 + } else {
8136 + data = ltq_readl(&drv->regs->rb);
8137 + rx32 = (u32 *) drv->rx;
8138 +
8139 + *rx32++ = data;
8140 + drv->rx_todo -= 4;
8141 + drv->rx += 4;
8142 +
8143 + if (drv->rx_req >= 4)
8144 + drv->rx_req -= 4;
8145 + }
8146 + rx_fill--;
8147 + }
8148 +}
8149 +
8150 +static void rx_request(struct ltq_spi_drv_data *drv)
8151 +{
8152 + unsigned int rxreq, rxreq_max;
8153 +
8154 + if (drv->rx_req)
8155 + return;
8156 +
8157 + /*
8158 + * To avoid receive overflows at high clocks it is better to request
8159 + * only the amount of bytes that fits into all FIFOs. This value
8160 + * depends on the FIFO size implemented in hardware.
8161 + */
8162 + rxreq = drv->rx_todo;
8163 + rxreq_max = rx_fifo_size(drv) * 4;
8164 + if (rxreq > rxreq_max)
8165 + rxreq = rxreq_max;
8166 +
8167 + drv->rx_req = rxreq;
8168 + ltq_writel(&drv->regs->rxreq, rxreq);
8169 +}
8170 +
8171 +void spi_init(void)
8172 +{
8173 +}
8174 +
8175 +struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
8176 + unsigned int max_hz, unsigned int mode)
8177 +{
8178 + struct ltq_spi_drv_data *drv;
8179 +
8180 + if (!spi_cs_is_valid(bus, cs))
8181 + return NULL;
8182 +
8183 + drv = ltq_spi_slave_alloc(bus, cs);
8184 + if (!drv)
8185 + return NULL;
8186 +
8187 + drv->regs = (struct ltq_spi_regs *) CKSEG1ADDR(LTQ_SPI_BASE);
8188 +
8189 + hw_init(drv);
8190 +
8191 + drv->max_hz = max_hz;
8192 + drv->mode = mode;
8193 +
8194 + return &drv->slave;
8195 +}
8196 +
8197 +void spi_free_slave(struct spi_slave *slave)
8198 +{
8199 + ltq_spi_slave_free(slave);
8200 +}
8201 +
8202 +static int ltq_spi_wait_ready(struct ltq_spi_drv_data *drv)
8203 +{
8204 + const unsigned long timeout = 20000;
8205 + unsigned long timebase;
8206 +
8207 + timebase = get_timer(0);
8208 +
8209 + do {
8210 + WATCHDOG_RESET();
8211 +
8212 + if (!hw_is_busy(drv))
8213 + return 0;
8214 + } while (get_timer(timebase) < timeout);
8215 +
8216 + return 1;
8217 +}
8218 +
8219 +int spi_claim_bus(struct spi_slave *slave)
8220 +{
8221 + struct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave);
8222 + int ret;
8223 +
8224 + ret = ltq_spi_wait_ready(drv);
8225 + if (ret) {
8226 + debug("cannot claim bus\n");
8227 + return ret;
8228 + }
8229 +
8230 + hw_enter_config_mode(drv);
8231 + hw_setup_clock_mode(drv, drv->mode);
8232 + hw_setup_speed_hz(drv, drv->max_hz);
8233 + hw_setup_bits_per_word(drv, drv->bits_per_word);
8234 + hw_enter_active_mode(drv);
8235 +
8236 + return 0;
8237 +}
8238 +
8239 +void spi_release_bus(struct spi_slave *slave)
8240 +{
8241 + struct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave);
8242 +
8243 + hw_enter_config_mode(drv);
8244 +}
8245 +
8246 +int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
8247 + const void *dout, void *din, unsigned long flags)
8248 +{
8249 +
8250 + struct ltq_spi_drv_data *drv = to_ltq_spi_slave(slave);
8251 + int ret = 0;
8252 +
8253 + if (bitlen % 8)
8254 + return 1;
8255 +
8256 + if (!bitlen) {
8257 + ret = 0;
8258 + goto done;
8259 + }
8260 +
8261 + if (flags & SPI_XFER_BEGIN)
8262 + spi_cs_activate(slave);
8263 +
8264 + drv->tx = dout;
8265 + drv->tx_todo = 0;
8266 + drv->rx = din;
8267 + drv->rx_todo = 0;
8268 + hw_set_rxtx(drv);
8269 +
8270 + if (drv->tx) {
8271 + drv->tx_todo = bitlen / 8;
8272 +
8273 + tx_fifo_write(drv);
8274 + }
8275 +
8276 + if (drv->rx) {
8277 + drv->rx_todo = bitlen / 8;
8278 +
8279 + if (!drv->tx)
8280 + rx_request(drv);
8281 + }
8282 +
8283 + for (;;) {
8284 + if (drv->tx) {
8285 + if (drv->rx && drv->rx_todo)
8286 + rx_fifo_read_full_duplex(drv);
8287 +
8288 + if (drv->tx_todo)
8289 + tx_fifo_write(drv);
8290 + else
8291 + goto done;
8292 + } else if (drv->rx) {
8293 + if (drv->rx_todo) {
8294 + rx_fifo_read_half_duplex(drv);
8295 +
8296 + if (drv->rx_todo)
8297 + rx_request(drv);
8298 + else
8299 + goto done;
8300 + } else {
8301 + goto done;
8302 + }
8303 + }
8304 + }
8305 +
8306 +done:
8307 + ret = ltq_spi_wait_ready(drv);
8308 +
8309 + drv->rx = NULL;
8310 + drv->tx = NULL;
8311 + hw_set_rxtx(drv);
8312 +
8313 + if (flags & SPI_XFER_END)
8314 + spi_cs_deactivate(slave);
8315 +
8316 + return ret;
8317 +}
8318 --- a/include/phy.h
8319 +++ b/include/phy.h
8320 @@ -214,6 +214,7 @@ int phy_atheros_init(void);
8321 int phy_broadcom_init(void);
8322 int phy_davicom_init(void);
8323 int phy_et1011c_init(void);
8324 +int phy_lantiq_init(void);
8325 int phy_lxt_init(void);
8326 int phy_marvell_init(void);
8327 int phy_micrel_init(void);
8328 --- a/spl/Makefile
8329 +++ b/spl/Makefile
8330 @@ -100,6 +100,8 @@ LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += dri
8331 LIBS-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += drivers/usb/musb-new/libusb_musb-new.o
8332 LIBS-$(CONFIG_SPL_USBETH_SUPPORT) += drivers/usb/gadget/libusb_gadget.o
8333 LIBS-$(CONFIG_SPL_WATCHDOG_SUPPORT) += drivers/watchdog/libwatchdog.o
8334 +LIBS-$(CONFIG_SPL_LZMA_SUPPORT) += lib/lzma/liblzma.o
8335 +LIBS-$(CONFIG_SPL_LZO_SUPPORT) += lib/lzo/liblzo.o
8336
8337 ifneq ($(CONFIG_OMAP_COMMON),)
8338 LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
8339 --- a/tools/.gitignore
8340 +++ b/tools/.gitignore
8341 @@ -2,6 +2,7 @@
8342 /envcrc
8343 /gen_eth_addr
8344 /img2srec
8345 +/ltq-boot-image
8346 /kwboot
8347 /mkenvimage
8348 /mkimage
8349 --- a/tools/Makefile
8350 +++ b/tools/Makefile
8351 @@ -49,6 +49,7 @@ BIN_FILES-$(CONFIG_VIDEO_LOGO) += bmp_lo
8352 BIN_FILES-$(CONFIG_BUILD_ENVCRC) += envcrc$(SFX)
8353 BIN_FILES-$(CONFIG_CMD_NET) += gen_eth_addr$(SFX)
8354 BIN_FILES-$(CONFIG_CMD_LOADS) += img2srec$(SFX)
8355 +BIN_FILES-$(CONFIG_SOC_LANTIQ) += ltq-boot-image$(SFX)
8356 BIN_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes$(SFX)
8357 BIN_FILES-y += mkenvimage$(SFX)
8358 BIN_FILES-y += mkimage$(SFX)
8359 @@ -95,6 +96,7 @@ OBJ_FILES-$(CONFIG_MX28) += mxsboot.o
8360 OBJ_FILES-$(CONFIG_NETCONSOLE) += ncb.o
8361 OBJ_FILES-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1.o
8362 OBJ_FILES-$(CONFIG_SMDK5250) += mkexynosspl.o
8363 +OBJ_FILES-$(CONFIG_SOC_LANTIQ) += ltq-boot-image.o
8364 OBJ_FILES-$(CONFIG_VIDEO_LOGO) += bmp_logo.o
8365 OBJ_FILES-$(CONFIG_XWAY_SWAP_BYTES) += xway-swap-bytes.o
8366
8367 @@ -195,6 +197,10 @@ $(obj)img2srec$(SFX): $(obj)img2srec.o
8368 $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
8369 $(HOSTSTRIP) $@
8370
8371 +$(obj)ltq-boot-image$(SFX): $(obj)ltq-boot-image.o
8372 + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
8373 + $(HOSTSTRIP) $@
8374 +
8375 $(obj)xway-swap-bytes$(SFX): $(obj)xway-swap-bytes.o
8376 $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $^
8377 $(HOSTSTRIP) $@
8378 --- /dev/null
8379 +++ b/tools/ltq-boot-image.c
8380 @@ -0,0 +1,315 @@
8381 +/*
8382 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
8383 + *
8384 + * SPDX-License-Identifier: GPL-2.0+
8385 + */
8386 +
8387 +#include <stdio.h>
8388 +#include <stdlib.h>
8389 +#include <string.h>
8390 +#include <unistd.h>
8391 +#include <getopt.h>
8392 +#include <compiler.h>
8393 +#include <sys/stat.h>
8394 +
8395 +enum image_types {
8396 + IMAGE_NONE,
8397 + IMAGE_SFSPL
8398 +};
8399 +
8400 +/* Lantiq non-volatile bootstrap command IDs */
8401 +enum nvb_cmd_ids {
8402 + NVB_CMD_DEBUG = 0x11,
8403 + NVB_CMD_REGCFG = 0x22,
8404 + NVB_CMD_IDWNLD = 0x33,
8405 + NVB_CMD_CDWNLD = 0x44,
8406 + NVB_CMD_DWNLD = 0x55,
8407 + NVB_CMD_IFCFG = 0x66,
8408 + NVB_CMD_START = 0x77
8409 +};
8410 +
8411 +/* Lantiq non-volatile bootstrap command flags */
8412 +enum nvb_cmd_flags {
8413 + NVB_FLAG_START = 1,
8414 + NVB_FLAG_DEC = (1 << 1),
8415 + NVB_FLAG_DBG = (1 << 2),
8416 + NVB_FLAG_SDBG = (1 << 3),
8417 + NVB_FLAG_CFG0 = (1 << 4),
8418 + NVB_FLAG_CFG1 = (1 << 5),
8419 + NVB_FLAG_CFG2 = (1 << 6),
8420 + NVB_FLAG_RST = (1 << 7)
8421 +};
8422 +
8423 +struct args {
8424 + enum image_types type;
8425 + __u32 entry_addr;
8426 + const char *uboot_bin;
8427 + const char *spl_bin;
8428 + const char *out_bin;
8429 +};
8430 +
8431 +static void usage_msg(const char *name)
8432 +{
8433 + fprintf(stderr, "%s: [-h] -t type -e entry-addr -u uboot-bin [-s spl-bin] -o out-bin\n",
8434 + name);
8435 + fprintf(stderr, " Image types:\n"
8436 + " sfspl - SPL + [compressed] U-Boot for SPI flash\n");
8437 +}
8438 +
8439 +static enum image_types parse_image_type(const char *type)
8440 +{
8441 + if (!type)
8442 + return IMAGE_NONE;
8443 +
8444 + if (!strncmp(type, "sfspl", 6))
8445 + return IMAGE_SFSPL;
8446 +
8447 + return IMAGE_NONE;
8448 +}
8449 +
8450 +static int parse_args(int argc, char *argv[], struct args *arg)
8451 +{
8452 + int opt;
8453 +
8454 + memset(arg, 0, sizeof(*arg));
8455 +
8456 + while ((opt = getopt(argc, argv, "ht:e:u:s:o:")) != -1) {
8457 + switch (opt) {
8458 + case 'h':
8459 + usage_msg(argv[0]);
8460 + return 1;
8461 + case 't':
8462 + arg->type = parse_image_type(optarg);
8463 + break;
8464 + case 'e':
8465 + arg->entry_addr = strtoul(optarg, NULL, 16);
8466 + break;
8467 + case 'u':
8468 + arg->uboot_bin = optarg;
8469 + break;
8470 + case 's':
8471 + arg->spl_bin = optarg;
8472 + break;
8473 + case 'o':
8474 + arg->out_bin = optarg;
8475 + break;
8476 + default:
8477 + fprintf(stderr, "Invalid option -%c\n", opt);
8478 + goto parse_error;
8479 + }
8480 + }
8481 +
8482 + if (arg->type == IMAGE_NONE) {
8483 + fprintf(stderr, "Invalid image type\n");
8484 + goto parse_error;
8485 + }
8486 +
8487 + if (!arg->uboot_bin) {
8488 + fprintf(stderr, "Missing U-Boot binary\n");
8489 + goto parse_error;
8490 + }
8491 +
8492 + if (!arg->out_bin) {
8493 + fprintf(stderr, "Missing output binary\n");
8494 + goto parse_error;
8495 + }
8496 +
8497 + if (arg->type == IMAGE_SFSPL && !arg->spl_bin) {
8498 + fprintf(stderr, "Missing SPL binary\n");
8499 + goto parse_error;
8500 + }
8501 +
8502 + return 0;
8503 +
8504 +parse_error:
8505 + usage_msg(argv[0]);
8506 + return -1;
8507 +}
8508 +
8509 +static __u32 build_nvb_command(unsigned cmdid, unsigned cmdflags)
8510 +{
8511 + __u32 cmd;
8512 + __u16 tag;
8513 +
8514 + tag = (cmdid << 8) | cmdflags;
8515 + cmd = (tag << 16) | (0xFFFF - tag);
8516 +
8517 + return cpu_to_be32(cmd);
8518 +}
8519 +
8520 +static int write_header(int fd, const void *hdr, size_t size)
8521 +{
8522 + ssize_t n;
8523 +
8524 + n = write(fd, hdr, size);
8525 + if (n != size) {
8526 + fprintf(stderr, "Cannot write header: %s\n",
8527 + strerror(errno));
8528 + return -1;
8529 + }
8530 +
8531 + return 0;
8532 +}
8533 +
8534 +static int write_nvb_dwnld_header(int fd, size_t size, __u32 addr)
8535 +{
8536 + __u32 hdr[3];
8537 +
8538 + hdr[0] = build_nvb_command(NVB_CMD_DWNLD, NVB_FLAG_START |
8539 + NVB_FLAG_SDBG);
8540 + hdr[1] = cpu_to_be32(size + 4);
8541 + hdr[2] = cpu_to_be32(addr);
8542 +
8543 + return write_header(fd, hdr, sizeof(hdr));
8544 +}
8545 +
8546 +static int write_nvb_start_header(int fd, __u32 addr)
8547 +{
8548 + __u32 hdr[3];
8549 +
8550 + hdr[0] = build_nvb_command(NVB_CMD_START, NVB_FLAG_SDBG);
8551 + hdr[1] = cpu_to_be32(4);
8552 + hdr[2] = cpu_to_be32(addr);
8553 +
8554 + return write_header(fd, hdr, sizeof(hdr));
8555 +}
8556 +
8557 +static int open_input_bin(const char *name, void **ptr, size_t *size)
8558 +{
8559 + struct stat sbuf;
8560 + int ret, fd;
8561 +
8562 + fd = open(name, O_RDONLY | O_BINARY);
8563 + if (0 > fd) {
8564 + fprintf(stderr, "Cannot open %s: %s\n", name,
8565 + strerror(errno));
8566 + return -1;
8567 + }
8568 +
8569 + ret = fstat(fd, &sbuf);
8570 + if (0 > ret) {
8571 + fprintf(stderr, "Cannot fstat %s: %s\n", name,
8572 + strerror(errno));
8573 + return -1;
8574 + }
8575 +
8576 + *ptr = mmap(0, sbuf.st_size, PROT_READ, MAP_SHARED, fd, 0);
8577 + if (*ptr == MAP_FAILED) {
8578 + fprintf(stderr, "Cannot mmap %s: %s\n", name,
8579 + strerror(errno));
8580 + return -1;
8581 + }
8582 +
8583 + *size = sbuf.st_size;
8584 +
8585 + return fd;
8586 +}
8587 +
8588 +static void close_input_bin(int fd, void *ptr, size_t size)
8589 +{
8590 + munmap(ptr, size);
8591 + close(fd);
8592 +}
8593 +
8594 +static int copy_bin(int fd, void *ptr, size_t size)
8595 +{
8596 + ssize_t n;
8597 +
8598 + n = write(fd, ptr, size);
8599 + if (n != size) {
8600 + fprintf(stderr, "Cannot copy binary: %s\n", strerror(errno));
8601 + return -1;
8602 + }
8603 +
8604 + return 0;
8605 +}
8606 +
8607 +static int open_output_bin(const char *name)
8608 +{
8609 + int fd;
8610 +
8611 + fd = open(name, O_RDWR | O_CREAT | O_TRUNC | O_BINARY, 0666);
8612 + if (0 > fd) {
8613 + fprintf(stderr, "Cannot open %s: %s\n", name,
8614 + strerror(errno));
8615 + return -1;
8616 + }
8617 +
8618 + return fd;
8619 +}
8620 +
8621 +static int create_sfspl(const struct args *arg)
8622 +{
8623 + int out_fd, uboot_fd, spl_fd, ret;
8624 + void *uboot_ptr, *spl_ptr;
8625 + size_t uboot_size, spl_size;
8626 +
8627 + out_fd = open_output_bin(arg->out_bin);
8628 + if (0 > out_fd)
8629 + goto err;
8630 +
8631 + spl_fd = open_input_bin(arg->spl_bin, &spl_ptr, &spl_size);
8632 + if (0 > spl_fd)
8633 + goto err_spl;
8634 +
8635 + uboot_fd = open_input_bin(arg->uboot_bin, &uboot_ptr, &uboot_size);
8636 + if (0 > uboot_fd)
8637 + goto err_uboot;
8638 +
8639 + ret = write_nvb_dwnld_header(out_fd, spl_size, arg->entry_addr);
8640 + if (ret)
8641 + goto err_write;
8642 +
8643 + ret = copy_bin(out_fd, spl_ptr, spl_size);
8644 + if (ret)
8645 + goto err_write;
8646 +
8647 + ret = write_nvb_start_header(out_fd, arg->entry_addr);
8648 + if (ret)
8649 + goto err_write;
8650 +
8651 + ret = copy_bin(out_fd, uboot_ptr, uboot_size);
8652 + if (ret)
8653 + goto err_write;
8654 +
8655 + close_input_bin(uboot_fd, uboot_ptr, uboot_size);
8656 + close_input_bin(spl_fd, spl_ptr, spl_size);
8657 + close(out_fd);
8658 +
8659 + return 0;
8660 +
8661 +err_write:
8662 + close_input_bin(uboot_fd, uboot_ptr, uboot_size);
8663 +err_uboot:
8664 + close_input_bin(spl_fd, spl_ptr, spl_size);
8665 +err_spl:
8666 + close(out_fd);
8667 +err:
8668 + return -1;
8669 +}
8670 +
8671 +int main(int argc, char *argv[])
8672 +{
8673 + int ret;
8674 + struct args arg;
8675 +
8676 + ret = parse_args(argc, argv, &arg);
8677 + if (ret)
8678 + goto done;
8679 +
8680 + switch (arg.type) {
8681 + case IMAGE_SFSPL:
8682 + ret = create_sfspl(&arg);
8683 + break;
8684 + default:
8685 + fprintf(stderr, "Image type not implemented\n");
8686 + ret = -1;
8687 + break;
8688 + }
8689 +
8690 +done:
8691 + if (ret >= 0)
8692 + return EXIT_SUCCESS;
8693 +
8694 + return EXIT_FAILURE;
8695 +}
OpenWrt Source Repository