package/boot/uboot-lantiq/patches/0032-MIPS-add-board-support-for-ZTE-ZXV10-H201L.patch

   1 From 2473526cf879ead429c6aa1fb7fb77ed3407baaa Mon Sep 17 00:00:00 2001
   2 From: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   3 Date: Sun, 9 Dec 2012 17:35:09 +0100
   4 Subject: MIPS: add board support for ZTE ZXV10 H201L
   5
   6 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   7
   8 --- /dev/null
   9 +++ b/board/zte/zxv10h201l/Makefile
  10 @@ -0,0 +1,27 @@
  11 +#
  12 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  13 +#
  14 +# SPDX-License-Identifier:     GPL-2.0+
  15 +#
  16 +
  17 +include $(TOPDIR)/config.mk
  18 +
  19 +LIB    = $(obj)lib$(BOARD).o
  20 +
  21 +COBJS  = $(BOARD).o
  22 +
  23 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  24 +OBJS   := $(addprefix $(obj),$(COBJS))
  25 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  26 +
  27 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  28 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  29 +
  30 +#########################################################################
  31 +
  32 +# defines $(obj).depend target
  33 +include $(SRCTREE)/rules.mk
  34 +
  35 +sinclude $(obj).depend
  36 +
  37 +#########################################################################
  38 --- /dev/null
  39 +++ b/board/zte/zxv10h201l/config.mk
  40 @@ -0,0 +1,7 @@
  41 +#
  42 +# Copyright (C) 2012-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
  43 +#
  44 +# SPDX-License-Identifier:     GPL-2.0+
  45 +#
  46 +
  47 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
  48 --- /dev/null
  49 +++ b/board/zte/zxv10h201l/ddr_settings.h
  50 @@ -0,0 +1,55 @@
  51 +/*
  52 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
  53 + *
  54 + * The values have been extracted from original ZTE U-Boot.
  55 + *
  56 + * SPDX-License-Identifier:    GPL-2.0+
  57 + */
  58 +
  59 +#define MC_DC00_VALUE  0x1B1B
  60 +#define MC_DC01_VALUE  0x0
  61 +#define MC_DC02_VALUE  0x0
  62 +#define MC_DC03_VALUE  0x0
  63 +#define MC_DC04_VALUE  0x0
  64 +#define MC_DC05_VALUE  0x200
  65 +#define MC_DC06_VALUE  0x307
  66 +#define MC_DC07_VALUE  0x303
  67 +#define MC_DC08_VALUE  0x103
  68 +#define MC_DC09_VALUE  0x80B
  69 +#define MC_DC10_VALUE  0x203
  70 +#define MC_DC11_VALUE  0xE02
  71 +#define MC_DC12_VALUE  0x2C8
  72 +#define MC_DC13_VALUE  0x1
  73 +#define MC_DC14_VALUE  0x0
  74 +#define MC_DC15_VALUE  0x100
  75 +#define MC_DC16_VALUE  0xC800
  76 +#define MC_DC17_VALUE  0xF
  77 +#define MC_DC18_VALUE  0x301
  78 +#define MC_DC19_VALUE  0x200
  79 +#define MC_DC20_VALUE  0xA04
  80 +#define MC_DC21_VALUE  0x1600
  81 +#define MC_DC22_VALUE  0x1616
  82 +#define MC_DC23_VALUE  0x0
  83 +#define MC_DC24_VALUE  0x5D
  84 +#define MC_DC25_VALUE  0x0
  85 +#define MC_DC26_VALUE  0x0
  86 +#define MC_DC27_VALUE  0x0
  87 +#define MC_DC28_VALUE  0x5FB
  88 +#define MC_DC29_VALUE  0x35DF
  89 +#define MC_DC30_VALUE  0x99E9
  90 +#define MC_DC31_VALUE  0x0
  91 +#define MC_DC32_VALUE  0x0
  92 +#define MC_DC33_VALUE  0x0
  93 +#define MC_DC34_VALUE  0x0
  94 +#define MC_DC35_VALUE  0x0
  95 +#define MC_DC36_VALUE  0x0
  96 +#define MC_DC37_VALUE  0x0
  97 +#define MC_DC38_VALUE  0x0
  98 +#define MC_DC39_VALUE  0x0
  99 +#define MC_DC40_VALUE  0x0
 100 +#define MC_DC41_VALUE  0x0
 101 +#define MC_DC42_VALUE  0x0
 102 +#define MC_DC43_VALUE  0x0
 103 +#define MC_DC44_VALUE  0x0
 104 +#define MC_DC45_VALUE  0x600
 105 +#define MC_DC46_VALUE  0x0
 106 --- /dev/null
 107 +++ b/board/zte/zxv10h201l/zxv10h201l.c
 108 @@ -0,0 +1,51 @@
 109 +/*
 110 + * Copyright (C) 2012 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
 111 + *
 112 + * SPDX-License-Identifier:    GPL-2.0+
 113 + */
 114 +
 115 +#include <common.h>
 116 +#include <switch.h>
 117 +#include <asm/gpio.h>
 118 +#include <asm/lantiq/eth.h>
 119 +#include <asm/lantiq/reset.h>
 120 +#include <asm/lantiq/chipid.h>
 121 +
 122 +int board_early_init_f(void)
 123 +{
 124 +       return 0;
 125 +}
 126 +
 127 +int checkboard(void)
 128 +{
 129 +       puts("Board: " CONFIG_BOARD_NAME "\n");
 130 +       ltq_chip_print_info();
 131 +
 132 +       return 0;
 133 +}
 134 +
 135 +static const struct ltq_eth_port_config eth_port_config[] = {
 136 +       /* MAC0: REALTEK RTL8306 switch */
 137 +       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
 138 +};
 139 +
 140 +static const struct ltq_eth_board_config eth_board_config = {
 141 +       .ports = eth_port_config,
 142 +       .num_ports = ARRAY_SIZE(eth_port_config),
 143 +};
 144 +
 145 +int board_eth_init(bd_t *bis)
 146 +{
 147 +       return ltq_eth_initialize(&eth_board_config);
 148 +}
 149 +
 150 +static struct switch_device rtl8306_dev = {
 151 +       .name = "rtl8306",
 152 +       .cpu_port = 5,
 153 +       .port_mask = 0xF,
 154 +};
 155 +
 156 +int board_switch_init(void)
 157 +{
 158 +       return switch_device_register(&rtl8306_dev);
 159 +}
 160 --- a/boards.cfg
 161 +++ b/boards.cfg
 162 @@ -496,6 +496,9 @@ Active  mips        mips32         -
 163  Active  mips        mips32         -           micronas        vct                 vct_premium_onenand                  vct:VCT_PREMIUM,VCT_ONENAND                                                                                                       -
 164  Active  mips        mips32         -           micronas        vct                 vct_premium_onenand_small            vct:VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE                                                                                       -
 165  Active  mips        mips32         -           micronas        vct                 vct_premium_small                    vct:VCT_PREMIUM,VCT_SMALL_IMAGE                                                                                                   -
 166 +Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_nor                       zxv10h201l:SYS_BOOT_NOR                                                                                                           Luka Perkov <luka@openwrt.org>
 167 +Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_ram                       zxv10h201l:SYS_BOOT_RAM                                                                                                           Luka Perkov <luka@openwrt.org>
 168 +Active  mips        mips32         arx100      zte             zxv10h201l          zxv10h201l_zte                       zxv10h201l:SYS_BOOT_ZTE                                                                                                           Luka Perkov <luka@openwrt.org>
 169  Active  mips        mips32         au1x00      -               dbau1x00            dbau1000                             dbau1x00:DBAU1000                                                                                                                 Thomas Lange <thomas@corelatus.se>
 170  Active  mips        mips32         au1x00      -               dbau1x00            dbau1100                             dbau1x00:DBAU1100                                                                                                                 Thomas Lange <thomas@corelatus.se>
 171  Active  mips        mips32         au1x00      -               dbau1x00            dbau1500                             dbau1x00:DBAU1500                                                                                                                 Thomas Lange <thomas@corelatus.se>
 172 --- /dev/null
 173 +++ b/include/configs/zxv10h201l.h
 174 @@ -0,0 +1,77 @@
 175 +/*
 176 + * Copyright (C) 2011 Daniel Schwierzeck, daniel.schwierzeck@googlemail.com
 177 + *
 178 + * SPDX-License-Identifier:    GPL-2.0+
 179 + */
 180 +
 181 +#ifndef __CONFIG_H
 182 +#define __CONFIG_H
 183 +
 184 +#define CONFIG_MACH_TYPE       "ZXV10 H201L"
 185 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 186 +#define CONFIG_BOARD_NAME      "ZTE ZXV10 H201L"
 187 +
 188 +/* Configure SoC */
 189 +#define CONFIG_LTQ_SUPPORT_UART                        /* Enable ASC and UART */
 190 +
 191 +#define CONFIG_LTQ_SUPPORT_ETHERNET            /* Enable ethernet */
 192 +
 193 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH           /* Have a parallel NOR flash */
 194 +
 195 +#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH       /* Build NOR flash SPL */
 196 +#define CONFIG_LTQ_SPL_COMP_LZO                        /* Compress SPL with LZO */
 197 +#define CONFIG_LTQ_SPL_CONSOLE                 /* Enable SPL console */
 198 +
 199 +/* Switch devices */
 200 +#define CONFIG_SWITCH_MULTI
 201 +#define CONFIG_SWITCH_RTL8306
 202 +
 203 +/* Environment */
 204 +#if defined(CONFIG_SYS_BOOT_NOR)
 205 +#define CONFIG_ENV_IS_IN_FLASH
 206 +#define CONFIG_ENV_OVERWRITE
 207 +#define CONFIG_ENV_OFFSET              (256 * 1024)
 208 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 209 +#elif defined(CONFIG_SYS_BOOT_NORSPL)
 210 +#define CONFIG_ENV_IS_IN_FLASH
 211 +#define CONFIG_ENV_OVERWRITE
 212 +#define CONFIG_ENV_OFFSET              (128 * 1024)
 213 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 214 +#else
 215 +#define CONFIG_ENV_IS_NOWHERE
 216 +#endif
 217 +
 218 +#define CONFIG_ENV_SIZE                        (8 * 1024)
 219 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 220 +
 221 +#if defined(CONFIG_SYS_BOOT_ZTE)
 222 +#define CONFIG_SYS_TEXT_BASE           0x80800000
 223 +#define CONFIG_SKIP_LOWLEVEL_INIT
 224 +#endif
 225 +
 226 +/* Console */
 227 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 228 +#define CONFIG_BAUDRATE                        115200
 229 +#define CONFIG_CONSOLE_ASC             1
 230 +#define CONFIG_CONSOLE_DEV             "ttyLTQ1"
 231 +
 232 +/* Pull in default board configs for Lantiq XWAY Danube */
 233 +#include <asm/lantiq/config.h>
 234 +#include <asm/arch/config.h>
 235 +
 236 +#if defined(CONFIG_SYS_BOOT_ZTE)
 237 +#define CONFIG_SYS_TEXT_BASE           0x80800000
 238 +#define CONFIG_SKIP_LOWLEVEL_INIT
 239 +#endif
 240 +
 241 +/* Pull in default OpenWrt configs for Lantiq SoC */
 242 +#include "openwrt-lantiq-common.h"
 243 +
 244 +#define CONFIG_ENV_UPDATE_UBOOT_NOR \
 245 +       "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
 246 +
 247 +#define CONFIG_EXTRA_ENV_SETTINGS      \
 248 +       CONFIG_ENV_LANTIQ_DEFAULTS      \
 249 +       CONFIG_ENV_UPDATE_UBOOT_NOR
 250 +
 251 +#endif /* __CONFIG_H */