projects / openwrt / openwrt.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
uboot-lantiq: reorder and rework patches
[openwrt/openwrt.git] / package / boot / uboot-lantiq / patches / 0101-MIPS-add-board-support-for-Easy-80920.patch
1 --- /dev/null
2 +++ b/board/lantiq/easy80920/Makefile
3 @@ -0,0 +1,27 @@
4 +#
5 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
6 +#
7 +# SPDX-License-Identifier: GPL-2.0+
8 +#
9 +
10 +include $(TOPDIR)/config.mk
11 +
12 +LIB = $(obj)lib$(BOARD).o
13 +
14 +COBJS = $(BOARD).o
15 +
16 +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
17 +OBJS := $(addprefix $(obj),$(COBJS))
18 +SOBJS := $(addprefix $(obj),$(SOBJS))
19 +
20 +$(LIB): $(obj).depend $(OBJS) $(SOBJS)
21 + $(call cmd_link_o_target, $(OBJS) $(SOBJS))
22 +
23 +#########################################################################
24 +
25 +# defines $(obj).depend target
26 +include $(SRCTREE)/rules.mk
27 +
28 +sinclude $(obj).depend
29 +
30 +#########################################################################
31 --- /dev/null
32 +++ b/board/lantiq/easy80920/config.mk
33 @@ -0,0 +1,7 @@
34 +#
35 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
36 +#
37 +# SPDX-License-Identifier: GPL-2.0+
38 +#
39 +
40 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
41 --- /dev/null
42 +++ b/board/lantiq/easy80920/ddr_settings.h
43 @@ -0,0 +1,69 @@
44 +/*
45 + * Copyright (C) 2007-2010 Lantiq Deutschland GmbH
46 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
47 + *
48 + * SPDX-License-Identifier: GPL-2.0+
49 + */
50 +
51 +#define MC_CCR00_VALUE 0x101
52 +#define MC_CCR01_VALUE 0x1000100
53 +#define MC_CCR02_VALUE 0x1010000
54 +#define MC_CCR03_VALUE 0x101
55 +#define MC_CCR04_VALUE 0x1000000
56 +#define MC_CCR05_VALUE 0x1000101
57 +#define MC_CCR06_VALUE 0x1000100
58 +#define MC_CCR07_VALUE 0x1010000
59 +#define MC_CCR08_VALUE 0x1000101
60 +#define MC_CCR09_VALUE 0x0
61 +#define MC_CCR10_VALUE 0x2000100
62 +#define MC_CCR11_VALUE 0x2000300
63 +#define MC_CCR12_VALUE 0x30000
64 +#define MC_CCR13_VALUE 0x202
65 +#define MC_CCR14_VALUE 0x7080A0F
66 +#define MC_CCR15_VALUE 0x2040F
67 +#define MC_CCR16_VALUE 0x40000
68 +#define MC_CCR17_VALUE 0x70102
69 +#define MC_CCR18_VALUE 0x4020002
70 +#define MC_CCR19_VALUE 0x30302
71 +#define MC_CCR20_VALUE 0x8000700
72 +#define MC_CCR21_VALUE 0x40F020A
73 +#define MC_CCR22_VALUE 0x0
74 +#define MC_CCR23_VALUE 0xC020000
75 +#define MC_CCR24_VALUE 0x4401B04
76 +#define MC_CCR25_VALUE 0x0
77 +#define MC_CCR26_VALUE 0x0
78 +#define MC_CCR27_VALUE 0x6420000
79 +#define MC_CCR28_VALUE 0x0
80 +#define MC_CCR29_VALUE 0x0
81 +#define MC_CCR30_VALUE 0x798
82 +#define MC_CCR31_VALUE 0x0
83 +#define MC_CCR32_VALUE 0x0
84 +#define MC_CCR33_VALUE 0x650000
85 +#define MC_CCR34_VALUE 0x200C8
86 +#define MC_CCR35_VALUE 0x1D445D
87 +#define MC_CCR36_VALUE 0xC8
88 +#define MC_CCR37_VALUE 0xC351
89 +#define MC_CCR38_VALUE 0x0
90 +#define MC_CCR39_VALUE 0x141F04
91 +#define MC_CCR40_VALUE 0x142704
92 +#define MC_CCR41_VALUE 0x141b42
93 +#define MC_CCR42_VALUE 0x141b42
94 +#define MC_CCR43_VALUE 0x566504
95 +#define MC_CCR44_VALUE 0x566504
96 +#define MC_CCR45_VALUE 0x565F17
97 +#define MC_CCR46_VALUE 0x565F17
98 +#define MC_CCR47_VALUE 0x0
99 +#define MC_CCR48_VALUE 0x0
100 +#define MC_CCR49_VALUE 0x0
101 +#define MC_CCR50_VALUE 0x0
102 +#define MC_CCR51_VALUE 0x0
103 +#define MC_CCR52_VALUE 0x133
104 +#define MC_CCR53_VALUE 0xF3014B27
105 +#define MC_CCR54_VALUE 0xF3014B27
106 +#define MC_CCR55_VALUE 0xF3014B27
107 +#define MC_CCR56_VALUE 0xF3014B27
108 +#define MC_CCR57_VALUE 0x7800301
109 +#define MC_CCR58_VALUE 0x7800301
110 +#define MC_CCR59_VALUE 0x7800301
111 +#define MC_CCR60_VALUE 0x7800301
112 +#define MC_CCR61_VALUE 0x4
113 --- /dev/null
114 +++ b/board/lantiq/easy80920/easy80920.c
115 @@ -0,0 +1,138 @@
116 +/*
117 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
118 + *
119 + * SPDX-License-Identifier: GPL-2.0+
120 + */
121 +
122 +#include <common.h>
123 +#include <spi.h>
124 +#include <asm/gpio.h>
125 +#include <asm/lantiq/eth.h>
126 +#include <asm/lantiq/chipid.h>
127 +#include <asm/lantiq/cpu.h>
128 +#include <asm/arch/gphy.h>
129 +
130 +#if defined(CONFIG_SPL_BUILD)
131 +#define do_gpio_init 1
132 +#define do_pll_init 1
133 +#define do_dcdc_init 0
134 +#elif defined(CONFIG_SYS_BOOT_RAM)
135 +#define do_gpio_init 1
136 +#define do_pll_init 0
137 +#define do_dcdc_init 1
138 +#elif defined(CONFIG_SYS_BOOT_NOR)
139 +#define do_gpio_init 1
140 +#define do_pll_init 1
141 +#define do_dcdc_init 1
142 +#else
143 +#define do_gpio_init 0
144 +#define do_pll_init 0
145 +#define do_dcdc_init 1
146 +#endif
147 +
148 +static void gpio_init(void)
149 +{
150 + /* SPI CS 0.4 to serial flash */
151 + gpio_direction_output(10, 1);
152 +
153 + /* EBU.FL_CS1 as output for NAND CE */
154 + gpio_set_altfunc(23, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
155 + /* EBU.FL_A23 as output for NAND CLE */
156 + gpio_set_altfunc(24, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
157 + /* EBU.FL_A24 as output for NAND ALE */
158 + gpio_set_altfunc(13, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
159 + /* GPIO 3.0 as input for NAND Ready Busy */
160 + gpio_set_altfunc(48, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_IN);
161 + /* GPIO 3.1 as output for NAND Read */
162 + gpio_set_altfunc(49, GPIO_ALTSEL_SET, GPIO_ALTSEL_CLR, GPIO_DIR_OUT);
163 +}
164 +
165 +int board_early_init_f(void)
166 +{
167 + if (do_gpio_init)
168 + gpio_init();
169 +
170 + if (do_pll_init)
171 + ltq_pll_init();
172 +
173 + if (do_dcdc_init)
174 + ltq_dcdc_init(0x7F);
175 +
176 + return 0;
177 +}
178 +
179 +int checkboard(void)
180 +{
181 + puts("Board: " CONFIG_BOARD_NAME "\n");
182 + ltq_chip_print_info();
183 +
184 + return 0;
185 +}
186 +
187 +static const struct ltq_eth_port_config eth_port_config[] = {
188 + /* GMAC0: external Lantiq PEF7071 10/100/1000 PHY for LAN port 0 */
189 + { 0, 0x0, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
190 + /* GMAC1: external Lantiq PEF7071 10/100/1000 PHY for LAN port 1 */
191 + { 1, 0x1, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
192 + /* GMAC2: internal GPHY0 with 10/100/1000 firmware for LAN port 2 */
193 + { 2, 0x11, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
194 + /* GMAC3: unused */
195 + { 3, 0x0, LTQ_ETH_PORT_NONE, PHY_INTERFACE_MODE_NONE },
196 + /* GMAC4: internal GPHY1 with 10/100/1000 firmware for LAN port 3 */
197 + { 4, 0x13, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_GMII },
198 + /* GMAC5: external Lantiq PEF7071 10/100/1000 PHY for WANoE port */
199 + { 5, 0x5, LTQ_ETH_PORT_PHY, PHY_INTERFACE_MODE_RGMII },
200 +};
201 +
202 +static const struct ltq_eth_board_config eth_board_config = {
203 + .ports = eth_port_config,
204 + .num_ports = ARRAY_SIZE(eth_port_config),
205 +};
206 +
207 +int board_eth_init(bd_t * bis)
208 +{
209 + const enum ltq_gphy_clk clk = LTQ_GPHY_CLK_25MHZ_PLL0;
210 + const ulong fw_addr = 0x80FF0000;
211 +
212 + ltq_gphy_phy11g_a1x_load(fw_addr);
213 +
214 + ltq_cgu_gphy_clk_src(clk);
215 +
216 + ltq_rcu_gphy_boot(0, fw_addr);
217 + ltq_rcu_gphy_boot(1, fw_addr);
218 +
219 + return ltq_eth_initialize(&eth_board_config);
220 +}
221 +
222 +int spi_cs_is_valid(unsigned int bus, unsigned int cs)
223 +{
224 + if (bus)
225 + return 0;
226 +
227 + if (cs == 4)
228 + return 1;
229 +
230 + return 0;
231 +}
232 +
233 +void spi_cs_activate(struct spi_slave *slave)
234 +{
235 + switch (slave->cs) {
236 + case 4:
237 + gpio_set_value(10, 0);
238 + break;
239 + default:
240 + break;
241 + }
242 +}
243 +
244 +void spi_cs_deactivate(struct spi_slave *slave)
245 +{
246 + switch (slave->cs) {
247 + case 4:
248 + gpio_set_value(10, 1);
249 + break;
250 + default:
251 + break;
252 + }
253 +}
254 --- a/boards.cfg
255 +++ b/boards.cfg
256 @@ -509,6 +509,11 @@ Active mips mips32 incai
257 Active mips mips32 incaip - incaip incaip_100MHz incaip:CPU_CLOCK_RATE=100000000 Wolfgang Denk <wd@denx.de>
258 Active mips mips32 incaip - incaip incaip_133MHz incaip:CPU_CLOCK_RATE=133000000 Wolfgang Denk <wd@denx.de>
259 Active mips mips32 incaip - incaip incaip_150MHz incaip:CPU_CLOCK_RATE=150000000 Wolfgang Denk <wd@denx.de>
260 +Active mips mips32 vrx200 lantiq easy80920 easy80920_nandspl easy80920:SYS_BOOT_NANDSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
261 +Active mips mips32 vrx200 lantiq easy80920 easy80920_nor easy80920:SYS_BOOT_NOR Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
262 +Active mips mips32 vrx200 lantiq easy80920 easy80920_norspl easy80920:SYS_BOOT_NORSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
263 +Active mips mips32 vrx200 lantiq easy80920 easy80920_ram easy80920:SYS_BOOT_RAM Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
264 +Active mips mips32 vrx200 lantiq easy80920 easy80920_sfspl easy80920:SYS_BOOT_SFSPL Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
265 Active mips mips64 - - qemu-mips qemu_mips64 qemu-mips64:SYS_BIG_ENDIAN -
266 Active mips mips64 - - qemu-mips qemu_mips64el qemu-mips64:SYS_LITTLE_ENDIAN -
267 Active nds32 n1213 ag101 AndesTech adp-ag101 adp-ag101 - Andes <uboot@andestech.com>
268 --- /dev/null
269 +++ b/include/configs/easy80920.h
270 @@ -0,0 +1,109 @@
271 +/*
272 + * Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
273 + *
274 + * SPDX-License-Identifier: GPL-2.0+
275 + */
276 +
277 +#ifndef __CONFIG_H
278 +#define __CONFIG_H
279 +
280 +#define CONFIG_MACH_TYPE "EASY80920"
281 +#define CONFIG_IDENT_STRING " "CONFIG_MACH_TYPE
282 +#define CONFIG_BOARD_NAME "Lantiq EASY80920 VRX200 Family Board"
283 +
284 +/* Configure SoC */
285 +#define CONFIG_LTQ_SUPPORT_UART /* Enable ASC and UART */
286 +
287 +#define CONFIG_LTQ_SUPPORT_ETHERNET /* Enable ethernet */
288 +
289 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH /* Have a parallel NOR flash */
290 +
291 +#define CONFIG_LTQ_SUPPORT_SPI_FLASH
292 +#define CONFIG_SPI_FLASH_MACRONIX /* Have a MX29LV620 serial flash */
293 +
294 +#define CONFIG_LTQ_SUPPORT_NAND_FLASH
295 +
296 +#define CONFIG_LTQ_SUPPORT_SPL_SPI_FLASH /* Build SPI flash SPL */
297 +#define CONFIG_SPL_SPI_BUS 0
298 +#define CONFIG_SPL_SPI_CS 4
299 +#define CONFIG_SPL_SPI_MAX_HZ 25000000
300 +#define CONFIG_SPL_SPI_MODE 0
301 +
302 +#define CONFIG_LTQ_SUPPORT_SPL_NOR_FLASH /* Build NOR flash SPL */
303 +
304 +#define CONFIG_LTQ_SUPPORT_SPL_NAND_FLASH /* Build NAND flash SPL */
305 +#define CONFIG_SYS_NAND_PAGE_COUNT 128
306 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048
307 +#define CONFIG_SYS_NAND_OOBSIZE 64
308 +#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
309 +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
310 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x4000
311 +
312 +#define CONFIG_LTQ_SPL_COMP_LZO
313 +#define CONFIG_LTQ_SPL_CONSOLE
314 +
315 +#define CONFIG_SYS_DRAM_PROBE
316 +
317 +/* Environment */
318 +#define CONFIG_ENV_SPI_BUS CONFIG_SPL_SPI_BUS
319 +#define CONFIG_ENV_SPI_CS CONFIG_SPL_SPI_CS
320 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SPL_SPI_MAX_HZ
321 +#define CONFIG_ENV_SPI_MODE CONFIG_SPL_SPI_MODE
322 +
323 +#if defined(CONFIG_SYS_BOOT_NOR)
324 +#define CONFIG_ENV_IS_IN_FLASH
325 +#define CONFIG_ENV_OVERWRITE
326 +#define CONFIG_ENV_OFFSET (384 * 1024)
327 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
328 +#elif defined(CONFIG_SYS_BOOT_NORSPL)
329 +#define CONFIG_ENV_IS_IN_FLASH
330 +#define CONFIG_ENV_OVERWRITE
331 +#define CONFIG_ENV_OFFSET (192 * 1024)
332 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
333 +#elif defined(CONFIG_SYS_BOOT_SFSPL)
334 +#define CONFIG_ENV_IS_IN_SPI_FLASH
335 +#define CONFIG_ENV_OVERWRITE
336 +#define CONFIG_ENV_OFFSET (192 * 1024)
337 +#define CONFIG_ENV_SECT_SIZE (64 * 1024)
338 +#elif defined(CONFIG_SYS_BOOT_NANDSPL)
339 +#define CONFIG_ENV_IS_IN_NAND
340 +#define CONFIG_ENV_OVERWRITE
341 +#define CONFIG_ENV_OFFSET (256 * 1024)
342 +#define CONFIG_ENV_SECT_SIZE (256 * 1024)
343 +#else
344 +#define CONFIG_ENV_IS_NOWHERE
345 +#endif
346 +
347 +#define CONFIG_ENV_SIZE (8 * 1024)
348 +
349 +#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
350 +
351 +/* Console */
352 +#define CONFIG_LTQ_ADVANCED_CONSOLE
353 +#define CONFIG_BAUDRATE 115200
354 +#define CONFIG_CONSOLE_ASC 1
355 +#define CONFIG_CONSOLE_DEV "ttyLTQ1"
356 +
357 +/* Pull in default board configs for Lantiq XWAY VRX200 */
358 +#include <asm/lantiq/config.h>
359 +#include <asm/arch/config.h>
360 +
361 +/* Pull in default OpenWrt configs for Lantiq SoC */
362 +#include "openwrt-lantiq-common.h"
363 +
364 +#define CONFIG_ENV_UPDATE_UBOOT_NOR \
365 + "update-uboot-nor=run load-uboot-norspl-lzo write-uboot-nor\0"
366 +
367 +#define CONFIG_ENV_UPDATE_UBOOT_SF \
368 + "update-uboot-sf=run load-uboot-sfspl-lzo write-uboot-sf\0"
369 +
370 +#define CONFIG_ENV_UPDATE_UBOOT_NAND \
371 + "update-uboot-nand=run load-uboot-nandspl-lzo write-uboot-nand\0"
372 +
373 +#define CONFIG_EXTRA_ENV_SETTINGS \
374 + CONFIG_ENV_LANTIQ_DEFAULTS \
375 + CONFIG_ENV_UPDATE_UBOOT_NOR \
376 + CONFIG_ENV_UPDATE_UBOOT_SF \
377 + CONFIG_ENV_UPDATE_UBOOT_NAND
378 +
379 +#endif /* __CONFIG_H */
OpenWrt Source Repository