package/boot/uboot-mediatek/patches/001-mtk-0008-clk-mtmips-add-clock-driver-for-MediaTek-MT7621-SoC.patch

   1 From c2e579662748cb5d3bf3e31f58d99c4db4d102c1 Mon Sep 17 00:00:00 2001
   2 From: Weijie Gao <weijie.gao@mediatek.com>
   3 Date: Fri, 20 May 2022 11:22:36 +0800
   4 Subject: [PATCH 08/25] clk: mtmips: add clock driver for MediaTek MT7621 SoC
   5
   6 This patch adds a clock driver for MediaTek MT7621 SoC.
   7 This driver provides clock gate control as well as getting clock frequency
   8 for CPU/SYS/XTAL and some peripherals.
   9
  10 Reviewed-by: Sean Anderson <seanga2@gmail.com>
  11 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
  12 ---
  13  drivers/clk/mtmips/Makefile            |   1 +
  14  drivers/clk/mtmips/clk-mt7621.c        | 288 +++++++++++++++++++++++++
  15  include/dt-bindings/clock/mt7621-clk.h |  46 ++++
  16  3 files changed, 335 insertions(+)
  17  create mode 100644 drivers/clk/mtmips/clk-mt7621.c
  18  create mode 100644 include/dt-bindings/clock/mt7621-clk.h
  19
  20 --- a/drivers/clk/mtmips/Makefile
  21 +++ b/drivers/clk/mtmips/Makefile
  22 @@ -1,4 +1,5 @@
  23  # SPDX-License-Identifier: GPL-2.0
  24
  25  obj-$(CONFIG_SOC_MT7620) += clk-mt7620.o
  26 +obj-$(CONFIG_SOC_MT7621) += clk-mt7621.o
  27  obj-$(CONFIG_SOC_MT7628) += clk-mt7628.o
  28 --- /dev/null
  29 +++ b/drivers/clk/mtmips/clk-mt7621.c
  30 @@ -0,0 +1,288 @@
  31 +// SPDX-License-Identifier: GPL-2.0
  32 +/*
  33 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
  34 + *
  35 + * Author: Weijie Gao <weijie.gao@mediatek.com>
  36 + */
  37 +
  38 +#include <clk-uclass.h>
  39 +#include <dm.h>
  40 +#include <dm/device_compat.h>
  41 +#include <regmap.h>
  42 +#include <syscon.h>
  43 +#include <dt-bindings/clock/mt7621-clk.h>
  44 +#include <linux/io.h>
  45 +#include <linux/bitops.h>
  46 +#include <linux/bitfield.h>
  47 +
  48 +#define SYSC_MAP_SIZE                  0x100
  49 +#define MEMC_MAP_SIZE                  0x1000
  50 +
  51 +/* SYSC */
  52 +#define SYSCFG0_REG                    0x10
  53 +#define XTAL_MODE_SEL                  GENMASK(8, 6)
  54 +
  55 +#define CLKCFG0_REG                    0x2c
  56 +#define CPU_CLK_SEL                    GENMASK(31, 30)
  57 +#define PERI_CLK_SEL                   BIT(4)
  58 +
  59 +#define CLKCFG1_REG                    0x30
  60 +
  61 +#define CUR_CLK_STS_REG                        0x44
  62 +#define CUR_CPU_FDIV                   GENMASK(12, 8)
  63 +#define CUR_CPU_FFRAC                  GENMASK(4, 0)
  64 +
  65 +/* MEMC */
  66 +#define MEMPLL1_REG                    0x0604
  67 +#define RG_MEPL_DIV2_SEL               GENMASK(2, 1)
  68 +
  69 +#define MEMPLL6_REG                    0x0618
  70 +#define MEMPLL18_REG                   0x0648
  71 +#define RG_MEPL_PREDIV                 GENMASK(13, 12)
  72 +#define RG_MEPL_FBDIV                  GENMASK(10, 4)
  73 +
  74 +/* Fixed 500M clock */
  75 +#define GMPLL_CLK                      500000000
  76 +
  77 +struct mt7621_clk_priv {
  78 +       void __iomem *sysc_base;
  79 +       int cpu_clk;
  80 +       int ddr_clk;
  81 +       int sys_clk;
  82 +       int xtal_clk;
  83 +};
  84 +
  85 +enum mt7621_clk_src {
  86 +       CLK_SRC_CPU,
  87 +       CLK_SRC_DDR,
  88 +       CLK_SRC_SYS,
  89 +       CLK_SRC_XTAL,
  90 +       CLK_SRC_PERI,
  91 +       CLK_SRC_125M,
  92 +       CLK_SRC_150M,
  93 +       CLK_SRC_250M,
  94 +       CLK_SRC_270M,
  95 +
  96 +       __CLK_SRC_MAX
  97 +};
  98 +
  99 +struct mt7621_clk_map {
 100 +       u32 cgbit;
 101 +       enum mt7621_clk_src clksrc;
 102 +};
 103 +
 104 +#define CLK_MAP(_id, _cg, _src) \
 105 +       [_id] = { .cgbit = (_cg), .clksrc = (_src) }
 106 +
 107 +#define CLK_MAP_SRC(_id, _src) \
 108 +       [_id] = { .cgbit = UINT32_MAX, .clksrc = (_src) }
 109 +
 110 +static const struct mt7621_clk_map mt7621_clk_mappings[] = {
 111 +       CLK_MAP_SRC(MT7621_CLK_XTAL, CLK_SRC_XTAL),
 112 +       CLK_MAP_SRC(MT7621_CLK_CPU, CLK_SRC_CPU),
 113 +       CLK_MAP_SRC(MT7621_CLK_BUS, CLK_SRC_SYS),
 114 +       CLK_MAP_SRC(MT7621_CLK_50M, CLK_SRC_PERI),
 115 +       CLK_MAP_SRC(MT7621_CLK_125M, CLK_SRC_125M),
 116 +       CLK_MAP_SRC(MT7621_CLK_150M, CLK_SRC_150M),
 117 +       CLK_MAP_SRC(MT7621_CLK_250M, CLK_SRC_250M),
 118 +       CLK_MAP_SRC(MT7621_CLK_270M, CLK_SRC_270M),
 119 +
 120 +       CLK_MAP(MT7621_CLK_HSDMA, 5, CLK_SRC_150M),
 121 +       CLK_MAP(MT7621_CLK_FE, 6, CLK_SRC_250M),
 122 +       CLK_MAP(MT7621_CLK_SP_DIVTX, 7, CLK_SRC_270M),
 123 +       CLK_MAP(MT7621_CLK_TIMER, 8, CLK_SRC_PERI),
 124 +       CLK_MAP(MT7621_CLK_PCM, 11, CLK_SRC_270M),
 125 +       CLK_MAP(MT7621_CLK_PIO, 13, CLK_SRC_PERI),
 126 +       CLK_MAP(MT7621_CLK_GDMA, 14, CLK_SRC_SYS),
 127 +       CLK_MAP(MT7621_CLK_NAND, 15, CLK_SRC_125M),
 128 +       CLK_MAP(MT7621_CLK_I2C, 16, CLK_SRC_PERI),
 129 +       CLK_MAP(MT7621_CLK_I2S, 17, CLK_SRC_270M),
 130 +       CLK_MAP(MT7621_CLK_SPI, 18, CLK_SRC_SYS),
 131 +       CLK_MAP(MT7621_CLK_UART1, 19, CLK_SRC_PERI),
 132 +       CLK_MAP(MT7621_CLK_UART2, 20, CLK_SRC_PERI),
 133 +       CLK_MAP(MT7621_CLK_UART3, 21, CLK_SRC_PERI),
 134 +       CLK_MAP(MT7621_CLK_ETH, 23, CLK_SRC_PERI),
 135 +       CLK_MAP(MT7621_CLK_PCIE0, 24, CLK_SRC_125M),
 136 +       CLK_MAP(MT7621_CLK_PCIE1, 25, CLK_SRC_125M),
 137 +       CLK_MAP(MT7621_CLK_PCIE2, 26, CLK_SRC_125M),
 138 +       CLK_MAP(MT7621_CLK_CRYPTO, 29, CLK_SRC_250M),
 139 +       CLK_MAP(MT7621_CLK_SHXC, 30, CLK_SRC_PERI),
 140 +
 141 +       CLK_MAP_SRC(MT7621_CLK_MAX, __CLK_SRC_MAX),
 142 +
 143 +       CLK_MAP_SRC(MT7621_CLK_DDR, CLK_SRC_DDR),
 144 +};
 145 +
 146 +static ulong mt7621_clk_get_rate(struct clk *clk)
 147 +{
 148 +       struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
 149 +       u32 val;
 150 +
 151 +       switch (mt7621_clk_mappings[clk->id].clksrc) {
 152 +       case CLK_SRC_CPU:
 153 +               return priv->cpu_clk;
 154 +       case CLK_SRC_DDR:
 155 +               return priv->ddr_clk;
 156 +       case CLK_SRC_SYS:
 157 +               return priv->sys_clk;
 158 +       case CLK_SRC_XTAL:
 159 +               return priv->xtal_clk;
 160 +       case CLK_SRC_PERI:
 161 +               val = readl(priv->sysc_base + CLKCFG0_REG);
 162 +               if (val & PERI_CLK_SEL)
 163 +                       return priv->xtal_clk;
 164 +               else
 165 +                       return GMPLL_CLK / 10;
 166 +       case CLK_SRC_125M:
 167 +               return 125000000;
 168 +       case CLK_SRC_150M:
 169 +               return 150000000;
 170 +       case CLK_SRC_250M:
 171 +               return 250000000;
 172 +       case CLK_SRC_270M:
 173 +               return 270000000;
 174 +       default:
 175 +               return 0;
 176 +       }
 177 +}
 178 +
 179 +static int mt7621_clk_enable(struct clk *clk)
 180 +{
 181 +       struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
 182 +       u32 cgbit;
 183 +
 184 +       cgbit = mt7621_clk_mappings[clk->id].cgbit;
 185 +       if (cgbit == UINT32_MAX)
 186 +               return -ENOSYS;
 187 +
 188 +       setbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
 189 +
 190 +       return 0;
 191 +}
 192 +
 193 +static int mt7621_clk_disable(struct clk *clk)
 194 +{
 195 +       struct mt7621_clk_priv *priv = dev_get_priv(clk->dev);
 196 +       u32 cgbit;
 197 +
 198 +       cgbit = mt7621_clk_mappings[clk->id].cgbit;
 199 +       if (cgbit == UINT32_MAX)
 200 +               return -ENOSYS;
 201 +
 202 +       clrbits_32(priv->sysc_base + CLKCFG1_REG, BIT(cgbit));
 203 +
 204 +       return 0;
 205 +}
 206 +
 207 +static int mt7621_clk_request(struct clk *clk)
 208 +{
 209 +       if (clk->id >= ARRAY_SIZE(mt7621_clk_mappings))
 210 +               return -EINVAL;
 211 +       return 0;
 212 +}
 213 +
 214 +const struct clk_ops mt7621_clk_ops = {
 215 +       .request = mt7621_clk_request,
 216 +       .enable = mt7621_clk_enable,
 217 +       .disable = mt7621_clk_disable,
 218 +       .get_rate = mt7621_clk_get_rate,
 219 +};
 220 +
 221 +static void mt7621_get_clocks(struct mt7621_clk_priv *priv, struct regmap *memc)
 222 +{
 223 +       u32 bs, xtal_sel, clkcfg0, cur_clk, mempll, dividx, fb;
 224 +       u32 xtal_clk, xtal_div, ffiv, ffrac, cpu_clk, ddr_clk;
 225 +       static const u32 xtal_div_tbl[] = {0, 1, 2, 2};
 226 +
 227 +       bs = readl(priv->sysc_base + SYSCFG0_REG);
 228 +       clkcfg0 = readl(priv->sysc_base + CLKCFG0_REG);
 229 +       cur_clk = readl(priv->sysc_base + CUR_CLK_STS_REG);
 230 +
 231 +       xtal_sel = FIELD_GET(XTAL_MODE_SEL, bs);
 232 +
 233 +       if (xtal_sel <= 2)
 234 +               xtal_clk = 20 * 1000 * 1000;
 235 +       else if (xtal_sel <= 5)
 236 +               xtal_clk = 40 * 1000 * 1000;
 237 +       else
 238 +               xtal_clk = 25 * 1000 * 1000;
 239 +
 240 +       switch (FIELD_GET(CPU_CLK_SEL, clkcfg0)) {
 241 +       case 0:
 242 +               cpu_clk = GMPLL_CLK;
 243 +               break;
 244 +       case 1:
 245 +               regmap_read(memc, MEMPLL18_REG, &mempll);
 246 +               dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
 247 +               fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
 248 +               xtal_div = 1 << xtal_div_tbl[dividx];
 249 +               cpu_clk = (fb + 1) * xtal_clk / xtal_div;
 250 +               break;
 251 +       default:
 252 +               cpu_clk = xtal_clk;
 253 +       }
 254 +
 255 +       ffiv = FIELD_GET(CUR_CPU_FDIV, cur_clk);
 256 +       ffrac = FIELD_GET(CUR_CPU_FFRAC, cur_clk);
 257 +       cpu_clk = cpu_clk / ffiv * ffrac;
 258 +
 259 +       regmap_read(memc, MEMPLL6_REG, &mempll);
 260 +       dividx = FIELD_GET(RG_MEPL_PREDIV, mempll);
 261 +       fb = FIELD_GET(RG_MEPL_FBDIV, mempll);
 262 +       xtal_div = 1 << xtal_div_tbl[dividx];
 263 +       ddr_clk = fb * xtal_clk / xtal_div;
 264 +
 265 +       regmap_read(memc, MEMPLL1_REG, &bs);
 266 +       if (!FIELD_GET(RG_MEPL_DIV2_SEL, bs))
 267 +               ddr_clk *= 2;
 268 +
 269 +       priv->cpu_clk = cpu_clk;
 270 +       priv->sys_clk = cpu_clk / 4;
 271 +       priv->ddr_clk = ddr_clk;
 272 +       priv->xtal_clk = xtal_clk;
 273 +}
 274 +
 275 +static int mt7621_clk_probe(struct udevice *dev)
 276 +{
 277 +       struct mt7621_clk_priv *priv = dev_get_priv(dev);
 278 +       struct ofnode_phandle_args args;
 279 +       struct udevice *pdev;
 280 +       struct regmap *memc;
 281 +       int ret;
 282 +
 283 +       pdev = dev_get_parent(dev);
 284 +       if (!pdev)
 285 +               return -ENODEV;
 286 +
 287 +       priv->sysc_base = dev_remap_addr(pdev);
 288 +       if (!priv->sysc_base)
 289 +               return -EINVAL;
 290 +
 291 +       /* get corresponding memc phandle */
 292 +       ret = dev_read_phandle_with_args(dev, "mediatek,memc", NULL, 0, 0,
 293 +                                        &args);
 294 +       if (ret)
 295 +               return ret;
 296 +
 297 +       memc = syscon_node_to_regmap(args.node);
 298 +       if (IS_ERR(memc))
 299 +               return PTR_ERR(memc);
 300 +
 301 +       mt7621_get_clocks(priv, memc);
 302 +
 303 +       return 0;
 304 +}
 305 +
 306 +static const struct udevice_id mt7621_clk_ids[] = {
 307 +       { .compatible = "mediatek,mt7621-clk" },
 308 +       { }
 309 +};
 310 +
 311 +U_BOOT_DRIVER(mt7621_clk) = {
 312 +       .name = "mt7621-clk",
 313 +       .id = UCLASS_CLK,
 314 +       .of_match = mt7621_clk_ids,
 315 +       .probe = mt7621_clk_probe,
 316 +       .priv_auto = sizeof(struct mt7621_clk_priv),
 317 +       .ops = &mt7621_clk_ops,
 318 +};
 319 --- /dev/null
 320 +++ b/include/dt-bindings/clock/mt7621-clk.h
 321 @@ -0,0 +1,46 @@
 322 +/* SPDX-License-Identifier: GPL-2.0 */
 323 +/*
 324 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
 325 + *
 326 + * Author: Weijie Gao <weijie.gao@mediatek.com>
 327 + */
 328 +
 329 +#ifndef _DT_BINDINGS_MT7621_CLK_H_
 330 +#define _DT_BINDINGS_MT7621_CLK_H_
 331 +
 332 +#define MT7621_CLK_XTAL                0
 333 +#define MT7621_CLK_CPU         1
 334 +#define MT7621_CLK_BUS         2
 335 +#define MT7621_CLK_50M         3
 336 +#define MT7621_CLK_125M                4
 337 +#define MT7621_CLK_150M                5
 338 +#define MT7621_CLK_250M                6
 339 +#define MT7621_CLK_270M                7
 340 +
 341 +#define MT7621_CLK_HSDMA       8
 342 +#define MT7621_CLK_FE          9
 343 +#define MT7621_CLK_SP_DIVTX    10
 344 +#define MT7621_CLK_TIMER       11
 345 +#define MT7621_CLK_PCM         12
 346 +#define MT7621_CLK_PIO         13
 347 +#define MT7621_CLK_GDMA                14
 348 +#define MT7621_CLK_NAND                15
 349 +#define MT7621_CLK_I2C         16
 350 +#define MT7621_CLK_I2S         17
 351 +#define MT7621_CLK_SPI         18
 352 +#define MT7621_CLK_UART1       19
 353 +#define MT7621_CLK_UART2       20
 354 +#define MT7621_CLK_UART3       21
 355 +#define MT7621_CLK_ETH         22
 356 +#define MT7621_CLK_PCIE0       23
 357 +#define MT7621_CLK_PCIE1       24
 358 +#define MT7621_CLK_PCIE2       25
 359 +#define MT7621_CLK_CRYPTO      26
 360 +#define MT7621_CLK_SHXC                27
 361 +
 362 +#define MT7621_CLK_MAX         28
 363 +
 364 +/* for u-boot only */
 365 +#define MT7621_CLK_DDR         29
 366 +
 367 +#endif /* _DT_BINDINGS_MT7621_CLK_H_ */